 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| W83768 I/O COUPLER GENERAL DESCRIPTION The W83768 is an I/O-coupler chip that includes six line drivers (1488), ten line receivers (1489), two timers (556), and one 244-type buffer block for game port signals. It also supports a power-down control circuit to reduce power consumption. This chip is intended for use with an I/O controller, and it is specifically designed to match the pin assignments of the Winbond Power I/O series. With this chip, engineers can easily design an all-in-one I/O circuit for personal computer systems without using any other TTL ICs. FEATURES * Six line drivers (1488), ten line receivers (1489), two timers (556), one buffer block for game port signals * Supports two RS232 serial ports and one game port control logic circuit * Power-down control function available * Four power supplies needed: 0V, +5V, +12V, and -12V * 48-pin QFP package PIN CONFIGURATION / R V GO NP D3 / R V O P 2 / R V O P 1 P D C I N R V I N 9 R V I N 6 / D R O P 5 R V I N 7 R V I N 8 G B O 0 G B O 1 36 35 34 33 32 31 30 29 28 27 26 25 RVOP4 DRIN1 DRIN2 DRIN3 RVOP5 GMRD GMWR DRIN4 DRIN5 DRIN6 RVOP6 +5V 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 -12V RVIN10 DROP4 DROP6 RVIN1 RVIN4 DROP2 RVIN3 RVIN2 RVIN5 DROP3 DROP1 / R V O P 7 / R V O P 8 / R V O P 9 / MSSSS GG RR DDDD PP V 01 45 OO O 10 P 1 0 + 1 2 V -1- Publication Release Date: October 1994 Revision A1 W83768 PIN DESCRIPTION Power Pins PIN NO. 36 48 12 24 SYMBOL GND VCC VDD VSS I/O Ground +5V Power +12V Power -12V Power DESCRIPTION Line Drivers PIN NO. 38 39 40 44 45 46 13 18 14 22 27 21 SYMBOL DRIN1 DRIN2 DRIN3 DRIN4 DRIN5 DRIN6 DROP1 DROP2 DROP3 DROP4 DROP5 DROP6 I/O I I I I I I O O O O O O Driver input 1 Driver input 2 Driver input 3 Driver input 4 Driver input 5 Driver input 6 Driver output 1 Driver output 2 Driver output 3 Driver output 4 Driver output 5 Driver output 6 DESCRIPTION Line Receivers PIN NO. 20 16 17 19 15 28 26 25 29 SYMBOL RVIN1 RVIN2 RVIN3 RVIN4 RVIN5 RVIN6 RVIN7 RVIN8 RVIN9 I/O I I I I I I I I I Receiver input 1 Receiver input 2 Receiver input 3 Receiver input 4 Receiver input 5 Receiver input 6 Receiver input 7 Receiver input 8 Receiver input 9 DESCRIPTION -2- W83768 Line Receivers, continued PIN NO. 23 33 SYMBOL RVIN10 RVOP1 I/O I I/O Receiver input 10 DESCRIPTION During normal operations, this pin works as receiver output #1. During power-on reset, this pin is used to select powerdown control (PDC) mode enable level. When RVOP1 is set to high at power-on, PDC is high active. When RVOP1 is set to low at power-on, PDC is low active. 34 35 37 41 47 1 2 3 4 RVOP2 RVOP3 RVOP4 RVOP5 RVOP6 RVOP7 RVOP8 RVOP9 RVOP10 O O O O O O O O O Receiver output 2 Receiver output 3 Receiver output 4 Receiver output 5 Receiver output 6 Receiver output 7 Receiver output 8 Receiver output 9 Receiver output 10 Game Port PIN NO. 11 10 31 30 42 43 SYMBOL GPO0 GPO1 GBO0 GBO1 GMRD GMWR I/O I/O I/O I I I I DESCRIPTION Game port RC constant (open drain) Game port RC constant (open drain) Game port button input Game port button input Game port read. This pin is internally pulled-up to make it convenient to disable the game port. Game port write Control Signals PIN NO. 5 32 SYMBOL MR PDCIN I/O I I DESCRIPTION Master reset signal input This pin is used to enable/disable the power-down function. The active level of this pin depends on how pin RVOP1 is programmed at power-on. If RVOP1 is set high at poweron, for example, then setting PDCIN to high will cause the W83768 to enter power-down mode. Publication Release Date: October 1994 Revision A1 -3- W83768 Data Bus PIN NO. 6 7 8 9 SYMBOL SD0 SD1 SD4 SD5 I/O O O O O System data bit 0 System data bit 1 System data bit 4 System data bit 5 DESCRIPTION BLOCK DIAGRAM GBO0 GBO1 GPO0 GPO1 GPO0' GPO1' SD0, SD1 SD4, SD5 74244 556 GMRD GMWR LINE DRIVER 1488 DRIN1-6 DROP1-6 RVOP1-10 LINE RECEIVER 1489 RVIN1-10 FUNCTIONAL DESCRIPTION Block 74244 This 244-type block functions as a buffer for reading game port buttons GBO0 and GBO1 and the status of block 556 output signals GPO0' and GPO1' on data bits 4, 5, 0, and 1, respectively. Block 556 This block contains two independent 555-type timing circuits that are used to generate two separate one-shot signals. With these two one-shot pulses, the RC inputs of the game port can easily be measured. The GMWR signal is the trigger signal of block 556. -4- W83768 Line Driver Block 1488 This block contains six line drivers that are designed to serve as an interface between data terminal equipment and data communications equipment in conformance with the specifications of EIA standard RS-232C. The power requirements are +12V, 0V, and -12V. Line Receiver Block 1489 This block contains ten line receivers that are designed to serve as an interface between data terminal equipment and data communications equipment in conformance with the specifications of EIA standard RS-232C. The power requirements are +12V, 0V, and -12V. Power-Down Control Mode When pin PDCIN is set active (active high or low determined by RVOP1 at power-on reset), the W83768 enters power-down mode, and all output buffers (SD0, SD1, SD4, SD5, RVOP1 - 10 , DROP1 - 6 ) will enter tri-state to reduce power consumption. ABSOLUTE MAXIMUM RATINGS PARAMETER Power Supply Voltage Input Voltage Operating Temperature Storage Temperature GND, VCC VSS, VDD Low Voltage High Voltage RATING 0 to 5.5 -13 to 13 -0.5 to 7.0 -12 to 12 0 to 70 -55 to 150 C C V UNIT V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC CHARACTERISTICS Ta = 0 C to +70 C, VCC = 5V, VDD = 12V, VSS = -12V, GND = 0V PARAMETER Input low voltage Input high voltage Input low voltage SYMBOL VIL (TTL) VIH (TTL) VIL (CMOS) MIN. -0.3V +2.4V -0.3V MAX. +0.6V VCC +0.3V 0.2 VCC NOTES MR, GMRD, GMWR MR, GMRD, GMWR DRIN1-6, GBO0-1, GPO0-1, PDCIN -5- Publication Release Date: October 1994 Revision A1 W83768 DC Characteristics, continued PARAMETER Input high voltage Input low voltage Input high voltage Output low voltage Output high voltage Output low voltage Output high voltage SYMBOL VIH (CMOS) VIL (HI-V) VIH (HI-V) VOL VOH VOL (HI-V) VOH (HI-V) MIN. +3.9V VSS 2V +2.4V VSS +2V MAX. VCC +0.3V GND VDD 0.4V -2V VDD NOTES DRIN1-6, GBO0-1, GPO0-1, PDCIN RVIN1-10 RVIN1-10 RVOP1 - 10 , SD0, SD1, SD4, SD5 RVOP1 - 10 , SD0, SD1, SD4, SD5 DROP1 - 6 DROP1 - 6 CURRENT LEVEL SYMBOL IIL MR PDCIN GMRD , GMWR MAX. IIH 3 A 3 A 3 A 3 A 3 A IOL 1.5 mA 5.5 mA 2 mA 10 mA -20 A -20 A -20 A -20 A -1 mA - MIN. IOH 4 mA 2 mA 10 mA IOL 2 mA 8 mA 3 mA 14 mA TYP. IOH 6 mA 3 mA 16 mA GBO0, GBO1 RVIN1-10 GPO0, GPO1 SD0, SD1, SD4, SD5 RVOP1 - 10 DROP1 - 6 AC CHARACTERISTICS PARAMETER 1488 tpLH 1488 tpHL 1489 tpLH 1489 tpHL tD SYMBOL DRIN1-6 DROP1 - 6 MIN. - TYP. 60 60 60 60 90 MAX. 90 90 90 90 120 UNIT nS nS nS nS nS RVIN1-10 RVOP1 - 10 SD0, SD1, SD4, SD5 -6- W83768 TIMING WAVEFORMS Driver Timing +5V IN DRIN1-6 tpLH DROP1-6 OUT tpHL +12V 0V -12V Receiver Timing +12V IN RVIN1-10 tpLH RVOP1-10 OUT tpHL +5V 0V -12V Timer Timing GMWR CV= 3.3V GPO0 GPO1 GPO0' GPO1' T= RC GMRD tD SD0, SD1 SD4, SD5 Floating Data Valid Floating -7- Publication Release Date: October 1994 Revision A1 W83768 PACKAGE DIMENSIONS 48-lead QFP HD D 48 37 Symbol Dimension in inch Min. --0.004 0.052 0.011 0.004 0.389 0.389 0.024 0.618 0.618 0.067 0.110 --0 0.630 0.630 0.075 0.118 ----- Dimension in mm Min. --0.10 1.32 0.28 0.10 9.87 9.87 0.60 15.70 15.70 1.70 2.79 --0 Nom. ----0.057 0.013 0.006 0.394 0.394 Max. 0.070 --0.062 0.017 0.010 0.399 0.399 0.036 0.642 0.642 0.083 0.126 0.006 15 Nom. ----1.45 0.33 0.15 10.00 10.00 0.75 16.00 16.00 1.90 3.00 ----- Max. 1.78 --1.58 0.43 0.25 10.13 10.13 0.90 16.30 16.30 2.10 3.20 0.15 15 1 36 E HE 12 25 13 e b 24 A A1 A2 b c D E e HD HE L L1 y 0 c Notes: 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec. A2 A1 y A Seating Plane See Detail F L L1 Detail F Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792646 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006 Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27516023 FAX: 852-27552064 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. -8- |
Price & Availability of W83768
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |