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| 8BIT 40MSPS ADC GENERAL DESCRIPTION The BW1223X is a CMOS 8-bit A/D converter for video applications. It is a two-step ping-pong A/D converter which consists of reference resistor-matrix, 4-bit coarse and fine A/D converters. The maximum conversion rate of BW1223X is 30MSPS and supply voltage is 3.3V single. BW1223X FEATURES * * * * * * * * * TYPICAL APPLICATIONS * * * * * * * Multi-media Applications Frame-grabber Scanner Camcorder Digital Video (TV/VCR) Broadcasting and Studio Equipments. Medical Electronics (ultra-sound and imaging) High Speed Instruments (digital scope, radar) Process : CMOS Resolution : 8Bit Maximum Conversion Rate : 40MSPS Power Supply : 3.3V Single Power Consumption : 60mW Differential Linearity Error : 0.3 LSB (Typ) Integral Linearity Error : 0.5 LSB (Typ) On-Chip Reference Bias Resistors Reference Bias Adjustable Externally FUNCTIONAL BLOCK DIAGRAM VDDA VSSA VBBA VDDD VSSD VBBD Coarse Sampling Amplifier COUT Latch FREF Reference Matrix Latch Encoder DO[0] (LSB) DO[1] Data Latches and 3-state Output Buffer DO[2] DO[3] DO[4] DO[5] Encoder DO[6] DO[7] (MSB) AIN Fine Sampling Amplifier Analog Mux Fine Sampling Amplifier Latch Error Correction Circuit FOUT Timing Generator CLK VRT VRB VRTS VRBS Ver 1.1 (Feb. 2000) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. 8BIT 40MSPS ADC CORE PIN DESCRIPTION NAME VRTS VRT VRBS VRB VDDA VBBA VSSA AIN CLK DO[7:0] VBBD VSSD VDDD BW1223X I/O TYPE AB AB AB AB AP AG AG AI DI DO DG DG DP I/O PAD poa_bb poa_bb poa_bb poa_bb vdda vbba vssa piar10_bb picc_bb pot2_bb vbba vsstd vddd PIN DESCRIPTION Internal Reference Top Bias (Short to VRTS for Self-Bias) 2.6V External Reference Top Bias Internal Reference Bottom Bias (Short to VRBS for Self-Bias) 0.6V External Reference Bottom Bias +3.3V Analog Power. Analog Sub Bias. Analog Ground. Analog Input Input Span : VRB ~ VRT Clock Input Digital Output Digital Sub Bias. Digital Ground. Digital Power. I/O TYPE ABBR. * * * * * * * * * * AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AB : Analog Bidirectional DB : Digital Bidirectional AP DP AG DG : : : : Analog Power Digital Power Analog Ground Digital Ground CORE CONFIGURATION VDDA VSSA VBBA VDDD VSSD VBBD DO[0] (LSB) DO[1] DO[2] AIN BW1223X VRTS VRT VRBS VRB DO[3] DO[4] DO[5] CLK DO[6] DO[7] (MSB) SEC ASIC 2 / 11 ANALOG 8BIT 40MSPS ADC ABSOLUTE MAXIMUM RATINGS Characteristics Supply Voltage Analog Input Voltage Digital Input Voltage Digital Output Voltage Reference Voltage Storage Temperature Range NOTES BW1223X Symbol VDD AIN CLK VOH, VOL VRT/VRB Tstg Value -0.3 to 4.5 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -45 to 125 Unit V V V V V C 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5k resistor (Human body model) RECOMMENDED OPERATING CONDITIONS Characteristics Supply Voltage Supply Voltage Difference Reference Input Voltage Analog Input Voltage Clock High Time Clock Low Time Digital Input 'L' Voltage Digital Input 'H' Voltage Operating Temperature Symbol VDDA - VSSA VDDD - VSSD VDDA - VDDD VRT VRB AIN Tpwh Tpwl VIL VIH Topr Min 3.15 -0.1 VRB 3.0 0 Typ 3.3 0.0 2.6 0.6 16.6 16.6 - Max 3.45 0.1 VRT 0.3 70 Unit V V V V ns V C NOTES 1. It is strongly recommended that all the supply pins (VDDA, VDDD, VDDP) be powered from the same source to avoid power latch-up. SEC ASIC 3 / 11 ANALOG 8BIT 40MSPS ADC DC ELECTRICAL CHARACTERISTICS Characteristics Resolution Reference Current BW1223X Symbol IREF Min - Typ 8 6.25 Max - Unit Bits mA - Conditions VRT : 2.6V VRB : 0.6V AIN : 0.6 ~ 2.6V (Ramp Input) Fs : 1MHz 20MHz EOB = AIN(0,1) - VRB EOT = VRT - AIN(254,255) Differential Linearity Error DLE - 0.3 0.5 6.3 5.4 0.5 0.8 6.5 5.6 LSB Integral Linearity Error Bottom Offset Voltage Error Top Offset Voltage Error ILE EOB EOT - LSB LSB LSB NOTES 1. Converter Specifications (unless otherwise specified) VDDA=3.3V VDDD=3.3V VSSA=GND VSSD=GND VRT=2.6V VRB=0.6V Ta=25C 2. TBD : To Be Determined AC ELECTRICAL CHARACTERISTICS Characteristics Clock High Time Clock Low Time Conversion Rate Symbol Tpwh Tpwl Fs Is (IREF) Min 40 Typ 16.6 16.6 20 (6.25) Max - Unit ns ns MSPS - Conditions Dynamic Supply Current - - mA Is = I(VDDA) + I(VDDD) + IREF Fs : 40MHz See "DELAY TIMING DIAGRAM" AIN : 1, 2, 4MHz respectively (Sine Input) Fs : 40MHz Digital Output Data Delay Signal to Noise Distortion Ratio (SNDR) td SNR1 SNR2 SNR3 - 10 42 42 42 20 ns 38 - dB SEC ASIC 4 / 11 ANALOG 8BIT 40MSPS ADC DELAY TIMING DIAGRAM BW1223X AIN(0) AIN(1) AIN(2) AIN(3) AIN(4) AIN CLK td DO DO (-2) DO (-1) DO (0) DO (1) DO (2) 2.5 CLK PIPELINE DELAY SEC ASIC 5 / 11 ANALOG 8BIT 40MSPS ADC FUNCTIONAL DESCRIPTION 1. BW1223X is a two-step ping-pong A/D converter with subranging reference resistor matrix. It consists of 4-bit coarse A/D converter and fine A/D converter of which the accuracy is 4.459 bits. The latching comparators in coarse and fine A/D converters have offset cancellation features built in such as auto-zero and averaging, and the number of comparators are 15 in the coarse converter and 42 in the fine one. The sampling operation of fine A/D converter is performed, through 21 analog MUXs, in a ping-pong manner between the two sampling amplifier banks each of which consists of 21 latching comparators. BW1223X converter output 'FOUT' and 'COUT', and from which the final digital output 'DO' is generated. The overall pipeline delay, measured from the sampling instance to the time that the 'DO' comes to be available, is 2.5 clock cycles. 4. BW1223X implements the error correction scheme to correct the error which stems from the mismatch between the offset of coarse A/D converter and that of the fine A/D converter. This scheme can handle coarse comparator offset error up to 3 LSBs and helps reducing the differential linearity error consequently. 2. The reference resistor matrix switch one of the 16 different sets of reference voltages, according to the states of the coarse comparator digital outputs, to the fine sampling amplifier banks. This fact and the use of a CMOS auto-zero comparator surely eliminate the extra pain for implementing high accuracy D/A converter of 8 bits or more, and thus a low-power, high-performance and high speed A/D converter results. 3. The operation of BW1223X can be stated as follows. (refer to the 'TIMING DIAGRAM' that follows) During the first cycle of external clock, the analog input 'AIN' is traced by each converter, and at the falling edge of CLK the 'AIN' is sampled and held to be compared with the 16-level coarse reference voltages. The result of comparison in coarse comparator, 'COUT', is latched and used to select a set of fine reference voltage 'FREF' which, to be compared with the sampled analog input, is fed to the fine sampling amplifier banks. The result of the comparison is reproduced by successive comparators with sufficiently large gain and then multiplexed to the latching digital logic in a ping-pong manner. Latching logic in coarse and fine converters refine the results of comparison to generate A/D SEC ASIC 6 / 11 ANALOG 8BIT 40MSPS ADC TIMING DIAGRAM BW1223X A1 AIN A2 A3 A4 A5 Coarse Sample Coarse Compare FREF A0 A1 A2 A3 A4 COUT A0 A1 A2 A3 Fine 1 Sample Fine 1 Compare Fine 2 Sample Fine 2 Compare MUX OUT FComp1 FComp2 FComp1 FComp2 FComp1 FOUT A0 A1 A2 A3 DO A0 2.5 CLOCK PIPELINE DELEY A1 A2 SEC ASIC 7 / 11 ANALOG BW1223X 1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP back-end circuit. 2. The reference voltages may be biased externally through VRT and VRB pins, otherwise these voltages are internally generated with VRT and VRB shorted to VRTS and VRBS respectively. +3.3V Analog Power GND GND +3.3V Digital Power NOTES : 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 0.1uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED VDDA VSSA VBBA VBBD VSSD VDDD DO[0] (LSB) DO[1] DO[2] DO[4] DO[5] HOST DO[6] CLK VRTS VRT VRBS VRB DSP DO[7] (MSB) CORE EVALUATION GUIDE CORE BIDIRECTIONAL PAD 2.6V Top Reference GND 0.6V Bottom Reference 8BIT 40MSPS ADC GND ADC Function Measuring & Digital Input Forcing SEC ASIC 8 / 11 AIN BW1223X DO[3] MUX ANALOG 8BIT 40MSPS ADC PACKAGE CONFIGURATION BW1223X +2.6V +0.6V Reference Reference Top Bottom +3.3V Digital Power GND 48 47 46 45 4 VRB NC VDDA VDDA VBBA VSSA VSSA AIN NC NC NC NC NC NC VDDP VSSP CLK NC 21 3 VRBS 2 VRTS 1 VRT VDDD VDDD VSSD VSSD 5 +3.3V Analog Power 6 7 8 9 GND Analog Input (Input Span =VRB~VRT) 10 11 12 13 14 15 16 +3.3V PAD Power 17 18 19 20 Clock Signal VBBD NC NC NC NC NC NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Digital Output Bits 2 Through 7 BW1223X NC NC NC DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[0] 27 DO[1] 28 NC 22 NC 23 NC 24 NC 25 NC 26 NOTES : 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 0.1uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED Digital Output Bits 0 and 1 NOTES 1. You can test ADC function by checking external bidirectional pad connected to internal signal path. 2. ESD (ElectroStatic Discharge) sensitive device. Although the digital control inputs are diode protected, permanent damage may occur on devices subjected to high electrostatic discharges. It is recommended that unused devices be stored in conductive foam or shunts to avoid performance degradation or loss of functionality. The protective foam should be discharged to the destination socket before devices are inserted. 3. NC denotes "No Connection". SEC ASIC 9 / 11 ANALOG 8BIT 40MSPS ADC PACKAGE PIN DESCRIPTION NAME VRT VRTS BW1223X PIN NO. 1 2 I/O TYPE AB AB PIN DESCRIPTION +2.6V External Reference Top Bias. Internal Reference Top Bias. (Short to VRTS for Self-Bias.) Internal Reference Bottom Bias. (Short to VRBS for Self-Bias.) +0.6V External Reference Bottom Bias. No Connection +3.3V Analog Power. Analog Sub Bias. Analog Ground. Analog Input. Input Span = VRT ~ VRB. No Connection PAD Power PAD Ground Clock Input. No Connection Digital Output. No Connection Digital Sub Bias. Digital Ground. Digital Power. I/O TYPE ABBR. * * * * * * * * * * AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AB : Analog Bidirectional DB : Digital Bidirectional AP DP AG DG : : : : Analog Power Digital Power Analog Ground Digital Ground VRBS 3 AB VRB NC VDDA VBBA VSSA AIN NC VDDP VSSP CLK NC DO[7:0] NC VBBD VSSD VDDD 4 5 6, 7 8 9, 10 11 12~17 18 19 20 21~26 34~27 35~43 44 45, 46 47, 48 AB AP AG AG AI DP DG DI DO DG DG DP SEC ASIC 10 / 11 ANALOG 8BIT 40MSPS ADC FEEDBACK REQUEST BW1223X It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the following characteristic checking table and fill out the additional questions. We appreciate your interest in our products. Thank you very much. Characteristics Analog Power Supply Voltage Digital Power Supply Voltage Bit Resolution Reference Input Voltage Analog Input Voltage Operating Temperature Integral Non-linearity Error Differential Non-linearity Error Bottom Offset Voltage Error Top Offset Voltage Error Maximum Conversion Rate Dynamic Supply Current Power Dissipation Signal-to-noise+distortion Ratio Pipeline Delay Min Typ Max Unit V V Bit V Vpp C LSB LSB LSB LSB MSPS mA mW dB CLK Remarks Digital Output Format (Provide detailed description & timing diagram) 1. Between single input-output and differential input-output configurations, which one is suitable for your system and why? 2. Please comment on the internal/external pin configurations you want our ADC to have, if you have any reason to prefer some type of configuration. 3. Freely list those functions you want to be implemented in our ADC, if you have any. SEC ASIC 11 / 11 ANALOG |
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