View DS-BD-3SXLC-PQ208_453037.PDF datasheet online --- IC-ON-LINE

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A
B
3SxLC REV2
A
B
C
C
D
D
BOARD NAME : SPARTAN 3 EVALUATION BOARD BOARD PART NUMBER : DS-BD-3SXLC-PQ208 BOARD REVISION : 2
E E
BOARD TITLE PAGE TITLE LAST MODIFIED
MemecBoard
Calgary, Alberta Canada
SPARTAN 3Sx EVALUATION BOARD
2
TITLE PAGE
3
Monday, April 12, 2004
4
SIZE
C
DESIGNER
JBE
5
REVISION
2
SHEET
6
1
of
8
1
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VOLTAGE INPUT JACK
JP1 1 2
9
REGULATION
8
7
6
5
LED
4
3
2
GROUND TEST LOOPS
1
VINJACK VINUSB SW1 VINJACK 1 JP32 1 2 1X2 INSTALL SHUNT TO POWER THE BOARD FROM USB 5V 5V 2 3 SPDT Slide 6A 2 + C56 330u 5V
H
Barrel Jack SMT
TP5
H
VIN (5V)
TP6 1
FEET
NE1 Little Rubber Feet -Thick MOUNT TO BOTTOM AS PER SSB
G
5V 3V3ENABLE R98 10k 1% 1 2 3 4 5
G
U2
TPS78633KTT 3.3V GND 6 R115 100
NE2 Little Rubber Feet -Thick MOUNT TO BOTTOM AS PER SSB NE3 Little Rubber Feet -Thick MOUNT TO BOTTOM AS PER SSB NE4 Little Rubber Feet -Thick MOUNT TO BOTTOM AS PER SSB
TP8
+ 1 2
F
3.3V
C162 330u
C3 2.2u
C163 2.2u 3.3V DISABLE
C175 .01u 6 0402
ENABLE IN GND OUT BYPASS/FB
1
Q5 2
Si2333 3 C183 47n 6 0402 3.3V 100
JP22 1X2 3.3V 2
DS6 GREEN LABEL = 3.3V
MOUNTING HOLES
F
NE6 NE7 NE8 NE9 Mounting Hole (.125) Mounting Hole (.125) Mounting Hole (.125) Mounting Hole (.125)
C182 .1u 6 0603
1
R129
R130 210k 1%
SOFTSTART CIRCUIT
E
5V 2V5ENABLE 1 2 3 + C159 330u C1 2.2u C160 2.2u C161 .1u 6 0603 4 5
U1 EN IN GND OUT BYPASS/FB TPS79525DCQ R1 100 Q6 2 C184 .1u 6 0603 Si2333 3 C185 47n 6 0402 2.5V 100 R132 121k 1% SOFTSTART CIRCUIT DS1 GREEN LABEL = 2.5V GND 6 2.5V
E
D
2.5V
D
1
R131
TP7 1 2
5V 11 12 13 14 15 16 17 18 19 20
U3 PGND PGND PGND VIN VIN VIN VBIAS SS/ENA SYNC RT PH PH PH PH PH BOOT PWRGD COMP VSENSE AGND 10 9 8 7 6 5 4 3 2 1
L1 6.2uH C105 47n 6 0402
5V
C
SUPERVISOR
C103 10u 6.3 1206 1.2V C195 330u R2 330 1% 5V 5V
C
1.2V
2.5V C191 1u 6 0603 C192 10u 6.3 1206 C193 10u 6.3 1206 C100 10u 6.3 1206
+
1.2V
B
2.5V R13 10k 1%
C104 .1u 0603 6 R3 73.2k 1%
3V3ENABLE
TPS54110PWP R24 30.1k 1% C186 2.7n 6 0603 1V2ENABLE C190 470p 16 0603 R134 1.91k 1% 1 R1 Q3 R2 R127 10k 1% 2 BCR108 R12 3.3k 1% DS2 GREEN C187 27p 6 0603 U5 LABEL = 1.2V C194 22u 6 1206 1.2V 8 7 6 5 VDD CONTROL SENSE RESIN RESET CT RESET GND TLC7733IPW 1 2 3 4
R133 3.3k 1%
3
2V5ENABLE
C188 4.7u 6 0603
B
1
1.2V DISABLE
JP34
C189 1u 6 0603
1X2 2
R135 28.7k 1%
2.5V DISABLE
JP33
1X2 2
A
MemecBoard
Calgary, Alberta Canada
1
A
BOARD TITLE PAGE TITLE LAST MODIFIED
SPARTAN 3Sx EVALUATION BOARD
9 8 7
POWER
6
Monday, April 12, 2004
5
SIZE
4
C
DESIGNER
JBE
3
REVISION
2
2
SHEET
2
1
of
8
10
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BANK 0 - P160 LEFT & CLOCK
9
8
BANK 1 - P160 LEFT
7
6
5
BANK 2 - P160 LEFT
4
3
BANK 3 - P160 RIGHT
2
1
3.3V
3.3V
3.3V
3.3V
H
188 201 177 164
H
110 127 U4C XC3S400 143 144 138 139 140 141 137 135 133 132
VCCO_0 VCCO_0
VCCO_1 VCCO_1
VCCO_2 VCCO_2
LIO_B39 LIO_B38 LIO_B37 LIO_B36 LIO_B35 LIO_B34
205 204 203 200 199 198 184 183
IO/VREF_0 IO_L01N_0/VRP_0 IO_L01P_0/VRN_0 IO/VREF_0,nc IO_L25N_0 IO_L25P_0 IO_L32N_0/GCLK7 IO_L32P_0/GCLK6
G
CLK_50M CLK_SOCKET
IO IO IO_L30P_0 IO_L30N_0 IO_L27P_0 IO_L27N_0 IO_L31P_0/VREF_0 IO_L31N_0
197 189 190 191 194 196 185 187
LIO_B33 LIO_B28 LIO_B29 LIO_B30 LIO_B31 LIO_B32 LIO_A39 LIO_B27
LIO_A9 LIO_A11 LIO_A17 LIO_A19 LIO_A21 LIO_A15 LIO_A13
161 162 165 166 167 181 180
IO_L01P_1/VRN_1 IO_L01N_1/VRP_1 IO_L10P_1 IO_L10N_1/VREF_1 IO IO_L32N_1/GCLK5 IO_L32P_1/GCLK4
IO_L27P_1 IO_L27N_1 IO_L28P_1 IO_L28N_1 IO IO_L31P_1 IO_L31N_1/VREF_1 IO
168 169 171 172 175 176 178 182
LIO_A23 LIO_A25 LIO_A27 LIO_A29 LIO_A31 LIO_A33 LIO_A35 LIO_A37
LIO_B26 LIO_B25 LIO_B24 LIO_B23 LIO_B22 LIO_B21 LIO_B20 LIO_B19 LIO_B18
156 155 154 152 150 149 148 147 146
IO_L01N_2/VRP_2 IO_L01P_2/VRN_2 IO/VREF_2,nc IO_L19N_2 IO_L19P_2 IO_L20N_2 IO_L20P_2 IO_L21N_2 IO_L21P_2
IO_L22P_2 IO_L22N_2 IO_L24P_2 IO_L24N_2 IO_L23P_2 IO_L23N_2/VREF_2 IO_L39N_2,nc IO_L39P_2,nc IO_L40N_2 IO_L40P_2/VREF_2
LIO_B16 LIO_B17 LIO_B12 LIO_B13 LIO_B14 LIO_B15 LIO_B11 LIO_B10 LIO_B9 LIO_B8
RIO_A19 RIO_A20 RIO_A17 RIO_A18 RIO_A15 RIO_A16 RIO_A13 RIO_A14 RIO_A11 RIO_A12
107 106 109 108 113 111 115 114 117 116
VCCO_3 VCCO_3
U4A XC3S400
U4B XC3S400
153 136
U4D XC3S400
IO_L01N_3/VRP_3 IO_L40P_3 IO_L01P_3/VRN_3 IO_L40N_3/VREF_3 IO_L17N_3,nc IO_L39P_3,nc IO_L17P_3/VREF_3,nc IO_L39N_3,nc IO_L19N_3 IO_L24P_3 IO_L19P_3 IO_L24N_3 IO_L20N_3 IO_L23P_3/VREF_3 IO_L20P_3 IO_L23N_3 IO_L21N_3 IO_L22P_3 IO_L21P_3 IO_L22N_3
130 131 126 128 124 125 122 123 119 120
RIO_A2 RIO_A1 RIO_A4 RIO_A3 RIO_A6 RIO_A5 RIO_A8 RIO_A7 RIO_A10 RIO_A9
G
16
14 P160 LEFT 2 CLOCK
15
15 P160 LEFT
19
19 P160 LEFT
20
20 P160 RIGHT
F
BANK 4 - P160 RIGHT
3.3V
BANK 5 - P160 RIGHT
3.3V
BANK 6 - P160 RIGHT & DISPLAY & DIP
3.3V
BANK 7 - RS232 & USB & DIP & PUSH & & LED & P160 LEFT
3.3V
F
98 84
60 73
49 32
VCCO_4 VCCO_4
VCCO_5 VCCO_5
VCCO_6 VCCO_6
E
INITn
RIO_B18 RIO_B20 RIO_B22 RIO_B24 RIO_B26 RIO_B28 RIO_B30
90 87 86 85 83 81 80 79
IO_L27P_4/D1 IO IO_L30N_4/D2 IO_L27N_4/DIN/D0 IO_L30P_4/D3 IO_L25P_4 IO/VREF_4 IO_L25N_4 IO_L31N_4/INIT_B IO/VREF_4,nc IO_L31P_4/DOUT/BUSY IO,nc IO_L01P_4/VRN_4 IO_L32N_4/GCLK1 IO_L01N_4/VRP_4 IO_L32P_4/GCLK0 IO/VREF_4
93 92 94 95 96 97 100 101 102
RIO_B16 RIO_B14 RIO_B12 RIO_B10 RIO_B8 RIO_B6 RIO_B4 RIO_B2 D0 RIO_A29 RIO_A30 RIO_A27 RIO_A28 RIO_A26 RIO_B34 RIO_B36
58 57 62 61 63 77 76
IO_L01N_5/RDWR_B IO_L27P_5 IO_L01P_5/CS_B IO_L27N_5/VREF_5 IO_L10N_5/VRP_5 IO_L28N_5/D6 IO_L10P_5/VRN_5 IO_L28P_5/D7 IO IO IO_L31P_5/D5 IO_L32N_5/GCLK3 IO_L31N_5/D4 IO_L32P_5/GCLK2 IO/VREF_5
64 65 68 67 71 72 74 78
RIO_A25 RIO_A24 RIO_A22 RIO_A23 RIO_A21 RIO_B40 RIO_B38 RIO_B32
RIO_A31 RIO_A32 RIO_A33 RIO_A34 RIO_A35 RIO_A36 RIO_A37 RIO_A38 RIO_A39
52 51 50 48 46 45 44 43 42
IO_L01N_6/VRP_6 IO_L01P_6/VRN_6 IO/VREF_6,nc IO_L19N_6 IO_L19P_6 IO_L20N_6 IO_L20P_6 IO_L21N_6 IO_L21P_6
IO_L22N_6 IO_L22P_6 IO_L23N_6 IO_L23P_6 IO_L24N_6/VREF_6 IO_L24P_6 IO_L39N_6,nc IO_L39P_6,nc IO_L40N_6 IO_L40P_6/VREF_6
40 39 37 36 35 34 33 31 29 28
FPGA OUT
RIO_A40 DISPLAY.1C DISPLAY.1B DISPLAY.1A DISPLAY.1G DISPLAY.1F DISPLAY.1D DISPLAY.1E DIP4 DIP3
FPGA IN
RXD LIO_B40 USB_RI TXD USB_DTR USB_DCD USB_SOUT USB_DSR USB_RTS USB_SIN
3 2 5 4 9 7 11 10 13 12
VCCO_7 VCCO_7
U4E XC3S400
U4F XC3S400
U4G XC3S400
6 23
U4H XC3S400 15 16 18 19 20 21 22 24 26 27
IO_L01N_7/VRP_7 IO_L22P_7 IO_L01P_7/VRN_7 IO_L22N_7 IO_L16N_7,nc IO_L23P_7 IO_L16P_7/VREF_7,nc IO_L23N_7 IO_L19N_7/VREF_7 IO_L24P_7 IO_L19P_7 IO_L24N_7 IO_L20N_7 IO_L39P_7,nc IO_L20P_7 IO_L39N_7,nc IO_L21N_7 IO_L21P_7 IO_L40P_7 IO_L40N_7/VREF_7
USB_CTS USB_RESETn LED3 LED4 LED1 LED2 PUSH1 PUSH2 DIP1 DIP2
E
D
15 2 CONFIG 15 P160 RIGHT 15 15 P160 RIGHT 19 7 DISPLAY 10 P160 RIGHT 2 DIP 20
4 1 2 2 2 9
LED P160 LEFT DIP PUSH RS232 USB
D
CONFIGURATION BLOCK
2.5V
POWER BLOCK
3.3V 2.5V R5 3.3k R6 3.3k R7 3.3k R8 3.3k 1% R140 3.3k 1% DEPOPULATED = Y
R143 1 33 1%
J12 2 1X2 RA USB_CTS
1.2V
2.5V
C
C
192 174 88 70 193 173 142 121 89 69 38 17
Mode
Master-serial Slave Serial Master SelectMAP Slave SelectMAP Boundary-scan
Pull-ups No No Yes No No
0
1
2
3
PROGRAMn FPGA.CCLK DONE M0 M1 M2 TCK TDI.FPGA TMS MHS
207 104 103 55 54 56 159 208 158 160 206
PROG_B CCLK DONE M0 M1 M2 TCK TDI TDO TMS HSWAP_EN
U4I XC3S400
B
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX
VCCINT VCCINT VCCINT VCCINT
U4J XC3S400
0123
Indicates jumper installed ('0') Indicates jumper removed ('1')
2X4 NE10 SHUNT-LO-CL INSTALL ON J1[1-2] NE11 SHUNT-LO-CL INSTALL ON J1[3-4] NE12 SHUNT-LO-CL INSTALL ON J1[5-6]
A
MemecBoard
Calgary, Alberta Canada
2 4 6 8
25 112 186 66 163 47 157 99 59 41 202 105 14 195 151 145 1 30 118 179 129 8 170 75 82 134 53 91
Pull-ups ON Pull-ups OFF
TDO.FPGA.to.TDO.PORT J1
B
1 3 5 7
A
BOARD TITLE PAGE TITLE LAST MODIFIED
SPARTAN 3Sx EVALUATION BOARD
9 8 7
FPGA
6
Monday, April 12, 2004
5
SIZE
4
C
DESIGNER
JBE
3
REVISION
2
2
SHEET
3
1
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PROM (PLATFORM FLASH)
9
8
7
PROGRAM PUSHBUTTON
6
5
DONE LED
4
3
PROM JTAG BYPASS
2.5V
2
1
H
2.5V
R9 100
H
NE17 SHUNT-LO-CL INSTALL ON J11
R10 3.3k 2.5V 3.3V 3.3V R114 3.3k 1% 18 20 19 R128 100k 1% DEPOPULATED = Y U10 TDO.PROM TDI.PORT.to.TDI.PROM TMS TCK INITn DONE FPGA.CCLK 17 4 5 6 3 8 13 10 TDO TDI TMS TCK 4 1 16 2 15 7 14 9 12 D0 3 2.5V 1 2 SW2 TL1105SP LABEL = PROGRAM DONE 1 PROGRAMn 2.5V
DS5 GREEN LABEL = DONE 3 TDO.PROM 1 1X2 RA J11 2 33 1% R141 TDI.FPGA
R1
Q2 BCR108 SEE DIAGRAM BELOW FOR CONFIGURATION
G
R2
G
VCCJ
D0/DATA DNC DNC DNC CF XCF02SVO20C CLK DNC OE/RESET DNC CEO DNC CE 11 GND
VCCOO
VCC
PROGRAMn
2
CLOCKs
JTAG PORT
3.3V 3.3V
F
2.5V 2.5V 3.3V Y2
F
R136 CLK_SOCKET 33 1% PLACE CLOSE TO Y2 ACTUAL VALUE SET ON BOM Y3 1 3 5 7 9 11 13 3.3V 3.3V Parallel IV RA C180 .1u C181 .01u 6 0402 3.3V J2 GND GND GND GND GND GND GND R142 JTAG SSer 2 4 6 8 10 12 14 33 1% R11 TCK TDO.FPGA.to.TDO.PORT TDI.PORT.to.TDI.PROM 33 1% TMS
8 R105
VCC
OUT
5
1 C8 .1u C61 .1u C62 .1u 2
EN GND 50MHz
VCC OUT
4 3 33 1%
CLK_50M
3.3V
3.3V C164 .01u 6 0402
GND
PLACE CLOSE TO Y2 ACTUAL VALUE SET ON BOM
CAN
VREF VREF TMS PROG TCK CCLK TDO DONE TDI DIN NC NC NC INIT
ENABLE
1
E
4
PLACE CLOSE TO J2 ACTUAL VALUE SET ON BOM
C179 .1u
E
JTAG CONNECTION DIAGRAM
JTAG CABLE CONNECTIONS
D
FPGA ONLY IN CHAIN PROM ONLY IN CHAIN PROM & FPGA IN CHAIN J2/SAM R11 TCK TMS TCK TMS TDI TDO TCK TMS TDI TDO TCK TMS TDI TDO TCK TMS
D
C
C
TCK TMS TDI.PORT.to.TDI.PROM TDO.PROM TDI TDO TDO.FPGA.to.TDO.PORT
TCK TMS TDI TDO
PROM
FPGA
B
TDO TDI
1 J11
B
2 JP11 JUMPER OUT JP11 JUMPER OUT JP11 JUMPER IN TDI.FPGA
A
MemecBoard
Calgary, Alberta Canada
A
BOARD TITLE PAGE TITLE LAST MODIFIED
SPARTAN 3Sx EVALUATION BOARD
9 8 7
FPGA PERIPHERALS
6
Monday, April 12, 2004
5
SIZE
4
C
DESIGNER
JBE
3
REVISION
2
2
SHEET
4
1
of
8
10
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FPGA CORE DECOUPLING (4 pins)
9
8
7
6
5
4
3
2
1
FPGA BANK DECOUPLING (16 pins)
FPGA AUX DECOUPLING (8 pins)
H
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
3.3V
3.3V
3.3V
3.3V
2.5V
2.5V
2.5V
2.5V
H
C168 .01u 6 0402
C27 .01u 6 0402
C29 .01u 6 0402
C30 .01u 6 0402
C31 .01u 6 0402
C32 .01u 6 0402
C33 .01u 6 0402
C85 .01u 6 0402
C86 .01u 6 0402
C87 .01u 6 0402
C88 .01u 6 0402
C165 .01u 6 0402
C166 .01u 6 0402
C167 .01u 6 0402
DEPOPULATED = Y DEPOPULATED = Y DEPOPULATED = Y DEPOPULATED = Y
G
1.2V
1.2V
1.2V
3.3V
3.3V
3.3V
3.3V
2.5V
2.5V
G
C170 .1u 6 0603
C35 .1u 6 0603
C36 .1u 6 0603
C37 .1u 6 0603
C94 .01u 6 0402
C95 .01u 6 0402
C96 .01u 6 0402
C97 .01u 6 0402
C169 .1u 6 0603
DEPOPULATED = Y DEPOPULATED = Y
1.2V
1.2V
3.3V
3.3V
3.3V
3.3V
2.5V
2.5V
F
C39 1u 6 0603 C40 1u 6 0603 C89 .1u 6 0603 C90 .1u 6 0603 C98 .1u 6 0603 C99 .1u 6 0603 C171 1u 6 0603 C172 1u 6 0603
F
DEPOPULATED = Y
1.2V
3.3V
3.3V
3.3V
2.5V
E
C41 10u 6.3 1206
C92 1u 6 0603
C101 1u 6 0603
C110 1u 6 0603
C173 10u 6.3 1206
E
1.2V
1.2V
3.3V
2.5V
D
+ C79 330u 6.3
+ C80 330u 6.3
C93 10u 6.3 1206
+ C174 330u 6.3
D
3.3V
3.3V
C
+ C102 330u 6.3
+ C111 330u 6.3
C
B
B
AS PER XILINX APP NOTE UPDATE
A
MemecBoard
Calgary, Alberta Canada
A
BOARD TITLE PAGE TITLE LAST MODIFIED
SPARTAN 3Sx EVALUATION BOARD
9 8 7
DECOUPLING
6
Monday, April 12, 2004
5
SIZE
4
C
DESIGNER
JBE
3
REVISION
2
2
SHEET
5
1
of
8
10
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SEVEN SEGMENT DISPLAYs
3.3V
9
8
7
DIP SWITCH
6
5
4
3
2
1
H
3 A B C D 8 E F G DP DD1 RED CA DIP1 DIP2 DIP3 DIP4
PULL-UPS MUST BE IMPLEMENTED IN FPGA SW3 8 7 6 5 SWDIP04 7 6 4 2 1 10 9 5 a 1 2 3 4
H
f
b g
G
PUSHBUTTONS
PULL-UPS MUST BE IMPLEMENTED IN FPGA 1 2 SW4 TL1105SP LABEL = PUSH1 4 3 4 3 1 2 SW5 TL1105SP LABEL = PUSH2
LEDs
R18 1.15k 1% R14 1.15k 1% R15 1.15k 1% R16 1.15k 1%
R19 1.15k 1% R17 1.15k 1%
R20 1.15k 1%
G
3.3V 3.3V 3.3V 3.3V
e
c
d
R21 100 1%
R80 100 1%
R137 100 1%
R138 100 1%
DISPLAY.1A DISPLAY.1B DISPLAY.1C DISPLAY.1D DISPLAY.1E DISPLAY.1F DISPLAY.1G
DS3 GREEN LABEL = LED1
DS4 GREEN LABEL = LED2
DS7 RED LABEL = LED3
DS8 RED LABEL = LED4
F
PUSH1 PUSH2
LED1 LED2 LED3 LED4
F
USB
SERIAL PORT
3.3V
NE5 SHUNT-LO-CL INSTALL ON JP3[2-3]
E
5V JP3 1 2 VUSB VUSB VUSB C176 1u 0603 6 C177 .1u 0402 6.3 7 U11 6 C178 10u 1206 6.3 VUSB CP2101 J3 VBUS D+ DSUSPEND SUSPEND RESET NC NC NC NC NC NC NC NC NC NC NC GND GND GND 8 4 5 12 11 9 10 13 14 15 16 17 18 19 20 21 22 USB_RESETn VINUSB 4 3 2 1 GND D+ DVCC USB-B BOARD POWERED USB POWERED 1X3 3 VINUSB
C13 .1u
U8 1 2 3 4 5 6 7 8 C15 .47u 6 0603 EN C1+ V+ C1C2+ C2VRIN MAX3221 C16 .47u 6 0603 FORCEOFF VCC GND DOUT FORCEON DIN INVALID ROUT 16 15 14 13 12 11 10 9
E
C14 .47u 6 0603
3.3V JD1 C12 .1u 1 6 2 7 3 8 4
DCD DSR RD RTS TD CTS DTR RI GND USE STANDARD STRAIGHT-THRU CABLE WHEN CONNECTING TO A PC
VUSB
D
D
REGIN
VDD
Shield Shield
9 TXD FPGA SERIAL IN FPGA SERIAL OUT RXD 5
C
USB_DTR USB_RTS USB_SOUT USB_SIN USB_RI USB_DCD USB_DSR USB_CTS
28 24 26 25 2 1 27 23
DTR RTS SOUT SIN RI DCD DSR CTS
6 5
DB9F RA
C
R139 330 1%
30 29
DS9 GREEN LABEL = USB POWER
B
3
B
A
MemecBoard
Calgary, Alberta Canada
A
BOARD TITLE PAGE TITLE LAST MODIFIED
SPARTAN 3Sx EVALUATION BOARD
9 8 7
USER IO
6
Monday, April 12, 2004
5
SIZE
4
C
DESIGNER
JBE
3
REVISION
2
2
SHEET
6
1
of
8
10
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10
P160
5V 3.3V 2.5V
9
8
7
6
5
4
3
2
1
2.5V JX2 P160 Right Header MB
3.3V
5V
H
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40
JX1
P160 Left Header MB
H
LIO_A9 LIO_A11
CLK
LIO_A13 LIO_A15 LIO_A17 LIO_A19 LIO_A21 LIO_A23 LIO_A25 LIO_A27 LIO_A29 LIO_A31
G
CLK
F
LIO_A33 LIO_A35 LIO_A37 LIO_A39
TCK GND TMS VIN TDI GND TDO 3.3V IOA9 GND IOA11 2.5V IOA13 GND IOA15 VIN IOA17 GND IOA19 3.3V IOA21 GND IOA23 2.5V IOA25 GND IOA27 VIN IOA29 GND IOA31 3.3V IOA33 GND IOA35 2.5V IOA37 GND IOA39 VIN
DIN DOUT CCLK DONE INITn PROGRAMn NC IOB8 IOB9 IOB10 IOB11 IOB12 IOB13 IOB14 IOB15 IOB16 IOB17 IOB18 IOB19 IOB20 IOB21 IOB22 IOB23 IOB24 IOB25 IOB26 IOB27 IOB28 IOB29 IOB30 IOB31 IOB32 IOB33 IOB34 IOB35 IOB36 IOB37 IOB38 IOB39 IOB40
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40
LIO_B8 LIO_B9 LIO_B10 LIO_B11 LIO_B12 LIO_B13 LIO_B14 LIO_B15 LIO_B16 LIO_B17 LIO_B18 LIO_B19 LIO_B20 LIO_B21 LIO_B22 LIO_B23 LIO_B24 LIO_B25 LIO_B26 LIO_B27 LIO_B28 LIO_B29 LIO_B30 LIO_B31 LIO_B32 LIO_B33 LIO_B34 LIO_B35 LIO_B36 LIO_B37 LIO_B38 LIO_B39 LIO_B40
RIO_A1 RIO_A2 RIO_A3 RIO_A4 RIO_A5 RIO_A6 RIO_A7 RIO_A8 RIO_A9 RIO_A10 RIO_A11 RIO_A12 RIO_A13 RIO_A14 RIO_A15 RIO_A16 RIO_A17 RIO_A18 RIO_A19 RIO_A20 RIO_A21 RIO_A22 RIO_A23 RIO_A24 RIO_A25 RIO_A26 RIO_A27 RIO_A28 RIO_A29 RIO_A30 RIO_A31 RIO_A32 RIO_A33 RIO_A34 RIO_A35 RIO_A36 RIO_A37 RIO_A38 RIO_A39 RIO_A40
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40
IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 IOA8 IOA9 IOA10 IOA11 IOA12 IOA13 IOA14 IOA15 IOA16 IOA17 IOA18 IOA19 IOA20 IOA21 IOA22 IOA23 IOA24 IOA25 IOA26 IOA27 IOA28 IOA29 IOA30 IOA31 IOA32 IOA33 IOA34 IOA35 IOA36 IOA37 IOA38 IOA39 IOA40
GND IOB2 VIN IOB4 GND IOB6 3.3V IOB8 GND IOB10 2.5V IOB12 GND IOB14 VIN IOB16 GND IOB18 3.3V IOB20 GND IOB22 2.5V IOB24 GND IOB26 VIN IOB28 GND IOB30 3.3V IOB32 GND IOB34 2.5V IOB36 GND IOB38 VIN IOB40
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40
RIO_B2 RIO_B4 RIO_B6 RIO_B8 RIO_B10 RIO_B12 RIO_B14 RIO_B16 RIO_B18 RIO_B20 RIO_B22 RIO_B24 RIO_B26 RIO_B28 RIO_B30 RIO_B32 RIO_B34 RIO_B36 RIO_B38 RIO_B40
G
F
E
SYSTEM ACE MODULE
PLACEMENT
E
19 P156 P157
FPGA IO TO SAM CLOCK
20 P131 P132 P105 P104
JX2 60
JP30 USB_DSR 1 1X2 2 NE18 SHUNT-LO-CL INSTALL ON JP30[1-2]
13 CLK PINS 2 BANK 1 15 P182 P183
BANK 2 19
BANK 3 20
15
BANK 4 15 P79 P78
2.5V
3.3V
3.3V 2.5V 15 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
BANK 0 16
BANK 5 15
15
C
TDO.FPGA.to.TDO.PORT TMS TDI.PORT.to.TDI.PROM PROGRAMn RIO_A19 RIO_B32 RIO_A35 RIO_A10 RIO_B10 RIO_A15 RIO_A16 RIO_A11 RIO_A14 RIO_B14 RIO_A21 RIO_A33 RIO_A37 LIO_B20 LIO_B37 DONE FPGA.CCLK
SAM
JX1 49
D
D
JP29 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 3.3V 3.3V TDO GND TMS CLOCK TDI GND PROGRAMn TCK GND GND OEn INITn A00 WEn A02 A01 2.5V A03 D00 2.5V D02 D01 D04 D03 D06 D05 D08 D07 D10 D09 D12 D11 D14 D13 A04 D15 A06 A05 IRQ GND RESETn CEn DONE BRDY CCLK BITSTREAM GND GND SAM Header CUT PIN 50
BANK 7 20
BANK 6 19
10
C
TCK INITn RIO_A40 RIO_A34 RIO_B36 RIO_B12 RIO_A12 RIO_B16 RIO_B18 RIO_A9 RIO_A13 RIO_A17 RIO_A18 RIO_A36 LIO_B18 RIO_A39 D0 1 1 USB CLK CAN
P208 P1
P27 P28
P53 P52
2
7
4
6
7
2
RS232 USB
B
EEPROM DIP(2) DISPLAY DIP(2) PUSHs(2) LED(2) AVAILABLE
B
USED DISPLAY EEPROM RS232 DIP PUSH LEDs JX1 JX2 CLOCK USB TOTAL : 7 4 2 4 2 2 49 60 2 7 139
BANK BANK BANK BANK BANK BANK BANK BANK
0 1 2 3 4 5 6 7
16 15 19 20 15 15 19 20 139
TOTAL :
A
MemecBoard
Calgary, Alberta Canada
A
BOARD TITLE PAGE TITLE LAST MODIFIED
SPARTAN 3Sx EVALUATION BOARD
9 8 7
P160 & SAM
6
Monday, April 12, 2004
5
SIZE
4
C
DESIGNER
JBE
3
REVISION
2
2
SHEET
7
1
of
8
10
www..com
10
9
8
7
6
5
4
3
2
1
H
H
REV A
REV 1
REV 2
G
CHANGED USB FROM TI TO CYGNAL ADDED ASSEMBLY NOTES ADDED CLOCK SOCKET REMOVED EEPROM CHANGED U5 SUPERVISOR CHANGED 1.2V CONVERTER TO SWIFT REDESIGNED POWER SEQUENCING ADDED SOFTSTART CIRCUITS TO 2.5V AND 3.3V CHANGED DONE LED DRIVE TRANSISTOR TO BCR108 ADDED TWO USER LEDs REDUCED CURRENT THROUGH 1.2V LED (100 TO 330 OHM) ADDED JUMPER BLOCK TO USB UART SIGNALS
ADDED CCLK JUMPER CHANGED SAM CLOCK JUMPER CONNECTIONS CHANGED SSD TO 0750 CHANGED SSD RESISTOR VALUES TO 1.15k MODIFIED JTAG CHAIN FOR 3.3V OPERATION ADDED OPTIONAL PULL-UP ON FPGA's TDO ADDED ALTERNATE PART NUMBER FOR INDUCTOR (L1) REMOVED REDUNDANT PULL-UP FROM DONE LINE
G
F
F
E
E
D
D
C
C
B
B
A
MemecBoard
Calgary, Alberta Canada
A
BOARD TITLE PAGE TITLE LAST MODIFIED
SPARTAN 3Sx EVALUATION BOARD
9 8 7
HISTORY
6
Monday, April 12, 2004
5
SIZE
4
C
DESIGNER
JBE
3
REVISION
2
2
SHEET
8
1
of
8
10

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