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| HM5117800 Series 16 M FP DRAM (2-Mword x 8-bit) 2 k Refresh ADE-203-632E (Z) Rev. 5.0 Nov. 1997 Description The Hitachi HM5117800 is a CMOS dynamic RAM organized 2,097,152-word x 8-bit. It employs the most advanced CMOS technology for high performance and low power. The HM5117800 offers Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM5117800 to be packaged in standard 28-pin plastic SOJ and 28-pin TSOP. Features * * * * Single 5 V (10%) High speed Access time: 60 ns/70 ns (max) Power dissipation Active mode: 550mW/495 mW (max) Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) Fast page mode capability Long refresh period 2048 refresh cycles : 32 ms : 128 ms (L-version) 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) Battery backup operation (L-version) * * * * Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Ordering Information Type No. HM5117800J-6 HM5117800J-7 HM5117800LJ -6 HM5117800LJ -7 HM5117800S-6 HM5117800S-7 HM5117800LS-6 HM5117800LS-7 HM5117800TT-6 HM5117800TT-7 HM5117800LTT-6 HM5117800LTT-7 HM5117800TS-6 HM5117800TS-7 HM5117800LTS-6 HM5117800LTS-7 Access time 60 ns 70 ns 60 ns 70 ns 60 ns 70 ns 60 ns 70 ns 60 ns 70 ns 60 ns 70 ns 60 ns 70 ns 60 ns 70 ns 300-mil 28-pin plastic TSOP II (TTP-28DB) 400-mil 28-pin plastic TSOP II (TTP-28DA) 300-mil 28-pin plastic SOJ (CP-28DNA) Package 400-mil 28-pin plastic SOJ (CP-28DA) 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Pin Arrangement HM5117800J/LJ Series HM5117800S/LS Series VCC I/O0 I/O1 I/O2 I/O3 WE RAS NC A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS I/O7 I/O6 I/O5 I/O4 CAS OE A9 A8 A7 A6 A5 A4 VSS HM5117800TT/LTT Series HM5117800TS/LTS Series VCC I/O0 I/O1 I/O2 I/O3 WE RAS NC A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top view) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS I/O7 I/O6 I/O5 I/O4 CAS OE A9 A8 A7 A6 A5 A4 VSS (Top view) Pin Description Pin name A0 to A10 Function Address input * * I/O0 to I/O7 RAS CAS WE OE VCC VSS NC Row/Refresh address A0 to A10 Column address A0 to A9 Data input/data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground No connection 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Block Diagram RAS CAS WE OE Timing and control A0 A1 to A9 Row decoder * * * Column address buffers Column decoder 2M array 2M array 2M array 2M array 2M array 2M array 2M array 2M array I/O buffers I/O0 to I/O7 * * * Row address buffers A10 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Input high voltage Input low voltage Note: 1. All voltage referred to VSS . Symbol VCC VIH VIL Min 4.5 2.4 -1.0 Typ 5.0 -- -- Max 5.5 6.5 0.8 Unit V V V Note 1 1 1 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM5117800 -6 Parameter Operating current* , * 2 1 -7 Max 100 2 Min -- -- Max 90 2 Unit mA mA Test conditions t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2V Dout = High-Z CMOS interface RAS, CAS VCC - 0.2V Dout = High-Z t RC = min RAS = VIH CAS = VIL Dout = enable t RC = min t PC = min CMOS interface Dout = High-Z CBR refresh: tRC = 62.5 s t RAS 0.3 s CMOS interface RAS, CAS 0.2V Dout = High-Z 0 V Vin 7 V 0 V Vout 7 V Dout = disable High Iout = -5 mA Low Iout = 4.2 mA Symbol I CC1 I CC2 Min -- -- Standby current -- 1 -- 1 mA Standby current (L-version) RAS-only refresh current*2 Standby current* 1 I CC2 -- 150 -- 150 A I CC3 I CC5 -- -- 100 5 -- -- 90 5 mA mA CAS-before-RAS refresh current Fast page mode current*1, * 3 Battery backup current (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage I CC6 I CC7 I CC10 -- -- -- 100 90 500 -- -- -- 90 85 500 mA mA A I CC11 -- 300 -- 300 A I LI I LO VOH VOL -10 -10 2.4 0 10 10 VCC 0.4 -10 -10 2.4 0 10 10 VCC 0.4 A A V V Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L ( 0.2 V) while RAS = L ( 0.2 V). 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Capacitance (Ta = 25C, VCC = 5 V 10%) Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *2, *18 Test Conditions * Input rise and fall time: 5 ns * Input timing reference levels: 0.8 V, 2.4 V * Output load: 2 TTL gate + C L (100 pF) (Including scope and jig) 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5117800 -6 Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Symbol t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT Min 110 40 10 60 15 0 10 0 10 20 15 15 60 5 15 0 0 3 Max -- -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- -- -- -- 50 -7 Min 130 50 10 70 18 0 10 0 15 20 15 18 70 5 18 0 0 3 Max -- -- -- 10000 10000 -- -- -- -- 52 35 -- -- -- -- -- -- 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 3 4 Notes 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Read Cycle HM5117800 -6 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Symbol t RAC t CAC t AA t OEA t RCS t RCH t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD Min -- -- -- -- 0 0 0 30 30 0 3 3 -- -- 15 Max 60 15 30 15 -- -- -- -- -- -- -- -- 15 15 -- -7 Min -- -- -- -- 0 0 0 35 35 0 3 3 -- -- 18 Max 70 18 35 18 -- -- -- -- -- -- -- -- 15 15 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 13 5 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9 Write Cycle HM5117800 -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol t WCS t WCH t WP t RWL t CWL t DS t DH Min 0 10 10 15 15 0 10 Max -- -- -- -- -- -- -- -7 Min 0 15 10 18 18 0 15 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 15 15 Notes 14 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Read-Modify-Write Cycle HM5117800 -6 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol t RWC t RWD t CWD t AWD t OEH Min 155 85 40 55 15 Max -- -- -- -- -- -7 Min 181 98 46 63 18 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes Refresh Cycle HM5117800 -6 Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol t CSR t CHR t WRP t WRH t RPC Min 5 10 0 10 5 Max -- -- -- -- -- -7 Min 5 10 0 10 5 Max -- -- -- -- -- Unit ns ns ns ns ns Notes Fast Page Mode Cycle HM5117800 -6 Parameter Fast page mode cycle time Fast page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Symbol t PC t RASP t CPA t CPRH Min 40 -- -- 35 Max -- -7 Min 45 Max -- Unit ns 16 9, 17 Notes 100000 -- 35 -- -- 40 100000 ns 40 -- ns ns 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Fast Page Mode Read-Modify-Write Cycle HM5117800 -6 Parameter Fast page mode read-modify-write cycle time WE delay time from CAS precharge Symbol t PRWC t CPW Min 85 60 Max -- -- -7 Min 96 68 Max -- -- Unit ns ns 14 Notes Refresh Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 32 128 Unit ms ms Note 2048 cycles 2048 cycles Self Refresh Mode (L-version) HM5117800L -6 Parameter RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Symbol t RASS t RPS t CHS Min 100 110 -50 Max -- -- -- -7 Min 100 130 -50 Max -- -- -- Unit s ns ns Notes 19, 20, 21, 22 Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in Fast page mode cycles. 17. Access time is determined by the longest among tAA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS 100 s, then RAS precharge time should use tRPS instaed of tRP. 20. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycles, 2048 cycles of distributed CBR refresh with 15.6 s interval should be executed within 32 ms immediately after exiting from and before entering into the self refresh mode. 21. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 22. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 23. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 12 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Timing Waveforms*23 Read Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t RAD t ASR t ASC t RAL t CAL t CAH t RAH Address Row Column t RRH t RCS t RCH WE t DZC t CDD Din High-Z t DZO t OEA t OED OE t OEZ t CAC t AA t RAC t CLZ Dout t OFF t OH Dout t OHO 13 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Early Write Cycle tRC tRAS tRP RAS tCSH tRCD tT CAS tRSH tCAS tCRP tASR tRAH tASC tCAH Address Row Column tWCS tWCH WE tDS tDH Din Din Dout High-Z* * t WCS t WCS (min) Delayed Write Cycle*18 14 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH Address Row Column t CWL t RCS t RWL t WP WE t DZC t DS t DH Din High-Z Din t OEH t OED t DZO t OEZ t CLZ Dout High-Z Invalid Dout OE Read-Modify-Write Cycle*18 15 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series t RWC t RAS t RP RAS tT t RCD t CAS t CRP CAS t RAD t ASR tRAH t ASC t CAH Address Row t RCS Column t CWD t AWD t RWD tCWL t RWL t WP WE t DZC t DS Din High-Z Din t DH t DZO t OED t OEA t OEH OE t CAC t AA t RAC t OEZ t OHO High-Z Dout t CLZ Dout 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series RAS-Only Refresh Cycle t RC t RAS RAS tT t CRP CAS t RPC t CRP t RP t ASR t RAH Address Row t OFF Dout High-Z CAS-Before-RAS Refresh Cycle 17 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series t RC t RP t RAS t RP t RAS t RC t RP RAS t RPC t CP tT t CSR t CHR t RPC t CP t CRP t CSR t CHR CAS t WRP t WRH t WRP t WRH WE Address t OFF High-Z Dout Hidden Refresh Cycle 18 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series t RC t RAS t RP t RC t RAS t RC t RP t RAS t RP RAS tT t RSH t RCD CAS t RAD t ASR t RAH Address Row t ASC t RAL t CAH t CHR t CRP Column t WRP t RCS t RRH t WRH WE t DZC High-Z Din t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout Powered by ICminer.com Electronic-Library Service CopyRight 2003 t WRP t WRH t CDD t OED t OEZ t OHO t OFF t OH 19 HM5117800 Series Fast Page Mode Read Cycle t RASP t CPRH t RP RAS tT t CSH t RCD CAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH Column 1 t CAL t ASC t CAH Column 2 t CAL t ASC t CAH Column N t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t RCS t RCS WE t DZC t CDD Din t DZO High-Z t OED t DZC t CDD High-Z t DZO t OED t RCH t RCH t RCS t RRH t RCH t DZC t CDD High-Z t DZO t OED OE t RAC t AA t OEA t CAC t CLZ Dout Dout 1 t OH t CPA t AA t OHO t OEA t CPA t AA t OHO t OFF t OEZ Dout 2 t OEA t CAC t CLZ Dout N t OFF t OEZ t OH t OH t OHO t OFF t CAC t OEZ t CLZ Fast Page Mode Early Write Cycle 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series t RASP t RP RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address ROW Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS t DH t DS t DH t DS t DH Din Din 1 Din 2 Din N Dout High-Z* * t WCS t WCS (min) Fast Page Mode Delayed Write Cycle*18 21 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series t RASP t RP RAS tT t CSH t RCD CAS t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z Invalid Dout Invalid Dout Invalid Dout Fast Page Mode Read-Modify-Write Cycle*18 22 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series t RASP t RP RAS tT t CP t RCD CAS t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DS t DZC t DH Din t DZO t OED t OEH OE Din 1 t DZO t OED t OEH t WP t DS t DZC t DH Din 2 t DZO t OED t OEH t WP t DS t DZC t DH Din N t RCS t CWL t ASC t CAH Column 2 t CPW t AWD t CWD t RCS t CWL t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL t CAS t CAS t PRWC t CP t RSH t CAS t CRP Address t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ High-Z Dout Dout 1 Dout 2 Dout N Self Refresh Cycle (L-version)* 19, 20, 21, 22 23 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series t RP t RASS t RPS RAS t RPC t CP CAS t WRP t WRH tT t CRP t CSR t CHS WE t OFF Dout High-Z Package Dimensions HM5117800J/LJ Series (CP-28DA) 24 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Unit: mm 18.17 18.54 Max 28 15 10.16 0.13 11.18 0.13 1 3.50 0.26 0.74 14 2.85 0.12 1.30 Max 0.80 +0.25 -0.17 0.43 0.10 0.41 0.08 1.27 9.40 0.25 Hitachi Code JEDEC EIAJ Weight (reference value) CP-28DA Conforms Conforms 1.16 g 0.10 Dimension including the plating thickness Base material dimension HM5117800S/LS Series (CP-28DNA) 25 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Unit: mm 18.41 18.84 Max 28 15 1 0.74 14 3.50 0.26 7.62 0.12 8.51 0.12 1.165 Max 0.90 0.26 0.43 0.10 0.41 0.08 6.79 0.18 1.27 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) CP-28DNA -- -- 0.95 g Dimension including the plating thickness Base material dimension 26 Powered by ICminer.com Electronic-Library Service CopyRight 2003 0.25 2.45 + 0.36 - HM5117800 Series HM5117800TT/LTT Series (TTP-28DA) Unit: mm 18.41 18.81 Max 28 15 1 0.42 0.08 0.40 0.06 1.27 0.21 1.15 Max M 14 0.80 11.76 0.20 0 - 5 0.68 27 0.50 0.10 10.16 0.10 0.145 0.05 0.125 0.04 0.13 0.05 1.20 Max Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) TTP-28DA Conforms -- 0.43 g Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series HM5117800TS/LTS Series (TTP-28DB) Unit: mm 18.41 18.81 Max 28 15 1 0.42 0.08 0.40 0.06 1.27 0.21 M 1.15 Max 14 0.80 9.22 0.2 0.50 0.10 0.63 0 - 5 0.145 0.05 0.125 0.04 0.13 0.05 1.20 Max 0.10 7.62 Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) TTP-28DB -- -- 0.35 g 28 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA. 94005-1897 USA Tel: 800-285-1601 Fax:303-297-0447 Hitachi Europe GmbH Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright (c) Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 29 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Revision Record Rev. 1.0 2.0 Date Sep. 30, 1996 Dec. 5, 1996 Contents of Modification Initial issue Addition of HM5117800-5 Series Addition of HM5117800S/LS Series (CP-28DNA) Addition of HM5117800TS/LTS Series (TTP-28DB) Power dissipation (active) 660/605 mW(max) to 605/550/495 mW (max) DC Characteristics I CC1 max: I CC3 max: I CC6 max: I CC7 max: 120/110 mA to 110/100/90 mA 120/110 mA to 110/100/90 mA 120/110 mA to 110/100/90 mA 100/90 mA to 100/90/85 mA Drawn by Y. Kasama Y. Kasama Approved by M. Mishima M. Mishima AC Characteristics t RRH min: 0/0 ns to 5/5/5 ns t RPC min: 0/0 ns to 5/5/5 ns 3.0 4.0 Feb. 24, 1997 Jun. 20, 1997 AC Characteristics t RRH min: 5/5/5 ns to 0/0/0 ns Deletion of HM5117800-5 Series AC Characteristics Notes 10: tRCD tRCD (max) and tRAD tRAD (max) to t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max) Notes 11: tRCD tRCD (max) and tRAD tRAD (max) to t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 5.0 Nov. 1997 Change of Subtitle Y. Kasama Y. Kasama Y. Matsuno Y. Matsuno 30 Powered by ICminer.com Electronic-Library Service CopyRight 2003 |
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