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| HY638256 Series 32Kx8bit CMOS FAST SRAM DESCRIPTION The HY638256 is a high-speed 32,768 x 8-bits CMOS static RAM fabricated using Hyundai's high performance twin tub CMOS process technology. This high reliability process coupled with high-speed circuit design techniques, yields maximum access time of 15ns. The HY638256 has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 2.0 volt. It is suitable for use in high-density high-speed system applications. FEATURES * Single 5V10% Power Supply * High speed - 15/20/25ns(max.) * Low power consumption(Max.) Mode Conditions Current Units Operating 15ns 100 mA 20/25ns 90 mA Standby TTL 30 mA CMOS 2 mA L 100 uA * Battery backup(L-part) - 2.0V(min) data retention * Fully static operation and Tri-state outputs - No clock or refresh required * TTL compatible inputs and outputs * Standard pin configuration - 28pin 300mil SOJ - 28pin 8 x 13.4 mm TSOP-I BLOCK DIAGRMM A0 ADD INPUT BUFFER COLUMN DECODER SENSE AMP ROW DECODER I/O1 OUTPUT BUFFER I/O8 A14 CONTROL LOGIC /CS /OE /WE PIN CONNECTION A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc /WE /OE A13 A11 A8 A9 A9 A8 A11 A13 /OE /WE A10 Vcc /CS1 A14 I/O8 A12 A7 I/O7 A6 I/O6 A5 I/O5 A4 I/O4 A3 PIN DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2 SOJ TSOP-I(Standard) Pin Name /CS /WE /OE A0~A14 I/O1~I/O8 Vcc Vss Pin Function Chip Select Write Enable Output Enable Adderss Input Data Input/Output Power(+5.0V) Ground ORDERING INFORMATION Part No. HY638256J HY638256LJ HY638256T1 HY638256LT1 Speed 15/20/25 15/20/25 15/20/25 15/20/25 Power L-part L-part Package SOJ SOJ TSOP-I Standard TSOP-I Standard This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.01 / Jul.96 Hyundai Semiconductor WRITE DRIVER MEMORY ARRAY 256x1024 HY638256 Series ABSOLUTE MAXIMUM RATINGS(1) Symbol Vcc, VIN, VOUT TA TSTG PD IOUT TSOLDER Parameter Power Supply, Input/Output Voltage Operating Temperature Storage Temperature Power Dissipation Data Output Current Lead Soldering Temperature & Time Rating -0.5 to 7.0 0 to 70 -65 to 150 1.0 50 260 * 10 Unit V C C W MA C * sec Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. RECOMMENDED DC OPERATING CONDITIONS TA=0C to 70C Symbol Parameter Vcc Supply Voltage Vss Ground VIH Input High Voltage VIL Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0 Max. 5.5 0 Vcc+0.5 0.8 Unit V V V V Note 1. VIL = -3.0V for pulse width less than 10ns TRUTH TABLE /CS H L L L /WE X H H L /OE X H L X Mode Standby Output Disabled Read Write I/O Operation Hi-Z Hi-Z DOUT DIN Note: 1. H=VIH, L=VIL, X=Don't care Rev.01 / Jul.96 2 HY638256 Series DC ELECTRICAL CHARACTERISTICS Vcc = 5.0V10%, TA = 0C to 70C, unless otherwise specified. Symbol Parameter Test Conditions ILI Input Leakage Current VSS < VIN < VCC ILO Output Leakage Current VSS < VOUT AC CHARACTERISTICS Vcc = 5.0V10%, TA = 0C to 70C, unless otherwise specified. -15 Parameter # Symbol Min Max READ CYCLE 1 tRC Read Cycle Time 15 2 tAA Address Access Time 15 3 tACS Chip Select Access Time 15 4 tOE Output Enable to Output Valid 8 5 tCLZ Chip Select to Output in Low Z 3 6 tOLZ Output Enable to Output in Low Z 3 7 tCHZ Chip Deselecting to Output in High Z 0 8 8 tOHZ Out Disable to Output in High Z 0 8 9 tOH Output Hold from Address Change 3 WRITE CYCLE 10 tWC Write Cycle Time 15 11 tCW Chip Select to End of Write 12 12 tAW Address Valid to End of Write 12 13 tAS Address Set-up Time 0 14 tWP Write Pulse Width 12 15 tWR Write Recovery Time 0 16 tWHZ Write to Output in High Z 0 7 17 tDW Data to Write Time Overlap 8 18 tDH Data Hold from Write Time 0 19 tOW Output Active from End of Write 3 -20 Min Max 20 3 3 0 0 3 20 13 13 0 13 0 0 9 0 3 20 20 10 10 8 9 -25 Min Max 25 3 3 0 0 3 25 15 15 0 15 0 10 0 3 25 25 12 10 8 10 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rev.01 / Jul.96 3 HY638256 Series AC TEST CONDITIONS Vcc = 5.0V10%, TA = 0C to 70C, unless otherwise specified. Parameter Value Input Pulse Level 0V to 3V Input Rise and Fall Time 3ns Input and Output Timing Reference Level 1.5V Output Load See below AC TEST LOADS Output Load (A) Output Load (B) (for tCHZ, tCLZ, tOHZ, tOLZ, tWHZ & tOW) +5V +5V 480 Ohm DOUT 255 Ohm CL=30pF(1) DOUT 255 Ohm 480 Ohm CL=5pF(1) Note : Including jig and scope capacitance CAPACITANCE (TA = 25C, f= 1.0MHz) Symbol Parameter CIN Input Capacitance CI/O Input/Output Capacitance Condition VIN = 0V VI/O = 0V Max. 6 8 Unit pF pF Note : This parameter is sampled and not 100% tested Rev.01 / Jul.96 4 HY638256 Series TIMING DIAGRAM READ CYCLE 1 tRC ADDR tAA OE tOE tOLZ CS tACS tCLZ Data Out High-Z Data Valid tOHZ tCHZ tOH Note (Read Cycle) 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device and from device to device. 3. /WE is high for read cycle. READ CYCLE 2 tRC ADDR tAA tOH Data Out Previous Data Data Valid tOH Note (Read Cycle) 1. /WE is high for read cycle. 2. Device is continuously selected /CS=VIL. 3. /OE=VIL. Rev.01 / Jul.96 5 HY638256 Series WRITE CYCLE 1(/OE Low Clocked) tWC ADDR OE tAW tCW CS tAS WE tDW Data In tOHZ Data Out tWP tWR tDH Data Valid WRITE CYCLE 2(/OE Low Fixed) tWC ADDR tAW tCW CS tAS WE tDW Data In tWHZ Data Out tDH Data Valid tOW (7) (8) tWP tWR Rev.01 / Jul.96 6 HY638256 Series Notes: 1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition among /CS going low, and /WE going low : A write ends at the earliest transition among /CS going high and /WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. If /OE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state, inputs of opposite phase of the output must not be applied because bus contention can occur. 6. If /CS goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high impedance state. 7. DOUT is the same phase of latest written data in the write cycle. 8. DOUT is the read data of the new address. DATA RETENTION ELECTRIC CHARACTERISTIC(L Version) TA=0C to 70C Symbol Parameter VDR Vcc for Data Retention ICCDR tCDR tR Data Retention Current Chip Deselect to Data Retention Time Operating Recovery Time Test Condition Power /CS > VCC - 0.2V VSS < VIN < VCC VCC = 3V, /CS > VCC-0.2V L Vin > Vcc - 0.2V or < 2.0V See Data Retention Timing Diagram Min 2.0 0 tRC(2) Typ 2 - Max 50 - Unit V uA ns ns Notes 1. Typical values are at the condition of TA=25C 2. tRC is read cycle time DATA RETENTION WAVEFORM VCC 4.5V tCDR DATA RETENTION MODE tR 2.2V VDR CS>VCC-0.2V CS VSS RELIABILITY SPEC. TEST MODE ESD HBM MM LATCH - UP TEST SPEC. > 2000V > 250V < -100mA > 100mA Rev.01 / Jul.96 7 HY638256 Series PACKAGE INFORMATION 28pin 300mil Small Outline J-Form Package (J) MAX. UNIT : INCH(mm) MIN. 0.296(7.5184) 0.305(7.747) 0.7210(18.3134) 0.7290(18.5166) 0.332(8.4328) 0.3390(8.6106) 0.138(3.505) 0.148(3.789) 0.260(6.604) 0.274(6.9596) 0.03(0.762) 0.04(1.016) 0.016(0.4064) 0.020(0.5080) 0.050(1.27)BSC 28pin 8x13.4mm Thin Small Outline Package Standard(T1) UNIT : INCH(mm) MAX. MIN. 0.468(11.9) 0.460(11.7) 0.536(13.6) 0.520(13.2) 0.319(8.1) 0.311(7.9) 0.040(1.02) 0.036(0.91) 0.008(0.20) 0.002(0.05) 0.027(0.7) 0.012(0.3) 0.008(0.2) 0.004(0.1) 0.022(0.55 BSC) Rev.01 / Jul.96 8 |
Price & Availability of HY638256LJ-20
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