View LC6527NFL_506179.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ordering number: EN 4363C
LC6527N/F/L, LC6528N/F/L
CMOS IC
LC6527N/F/L, 6528N/F/L Single-chip 4-bit Microcomputer for Small-scale Control-oriented Applications
Overview
The LC6527N/F/L, LC6528N/F/L belong to our single-chip 4-bit microcomputer LC6500 series fabicated using CMOS process technology and are suited for use in small-scale control-oriented applications. Their basic architecture and instruction set are the same. Application areas include the standard logic circuits and applications where the number of controls is small. The LC6527N/F/L, LC6528N/F/L have relation to the LC6527C/H, LC6528C/H. The C version can be replaced by N version, and the H version by F version (a part of the function is different). The L version is added as a low voltage version. The following show the careful difference of C and N version when you replace C version with N version.
Package Dimensions
unit : mm
3007A-DIP18
[LC6527N/F/L, 6528N/F/L]
Item Operating Temperature 1-pin C oscillation CF oscillation constant 400 kHz MURATA 800 kHz MURATA
C version -30C to +70C exist
N version -40C to +85C not exist
SANYO : DIP18 unit : mm
3095-MFP18
[LC6527N/F/L, 6528N/F/L]
C1 = C2 = 330 pF C1 = C2 = 220 pF R=0 R = 2.2 k C1 = C2 = 220 pF C1 = C2 = 100 pF R=0 R = 2.2 K
KYOCERA C1 = C2 = 220 pF C1 = C2 = 100 pF R=0 R=0 1MHz MURATA C1 = C2 = 220 pF C1 = C2 = 100 pF R=0 R = 2.2 k
(Note) The suffix of recommend oscillation is changed C version and N version, but the characteristics are no change. SANYO : MFP18 (Note) The package is the reference figure without the description of the rank. Please inquire us for the formal package.
SANYOSANYO Electric Co., Ltd. Semiconductor LSI Div. Microcomputer Development Dep. Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
93098HA (II) No. 4363-1/43
LC6527N/F/L, LC6528N/F/L
Features
1) 2) CMOS technology for a low-power operation (with instruction-controlled standby function) ROM/RAM LC6527N/F/L ROM : 1 K x 8 bits, RAM : 64 x 4 bits LC6528N/F/L ROM : 0.5 K x 8 bits, RAM : 32 x 4 bits Instruction set : 51 kinds selectable from 80 instructions common to the LC6500 series Wide operationg voltage range form 2.2 V to 6.0 V (L version) Instruction cycle time of 0.92s (F version) Flexible I/O port * Number of ports : 4 ports/13 pins max. * All ports : Input/output common Input/output voltage 15V max. (open drain type) Output current 20mA max. (sink current) (LED direct drivable) * Option selectable for your intended system A. Open drain output, pull-up resistor : Single-bit select for all ports B. Output level at the reset mode : 4-bit select of H/L level for port C/D Stack level : 4 levels Timer : 4-bit prescaler + 8-bit programmable timer Clock oscillation option selectable for your intended system * Oscillator option : 2-pin RC oscillaion (N, L version) 2-pin ceramic resonator oscillation, 1-pin external clock input (N, F, L version) * Predivider option : No predivider, 1/3 predivider, 1/4 predivider (N, L version)
3) 4) 5) 6)
7) 8) 9)
Function Table
Item ROM Memory RAM Instruction set Timer On-chip function Stack level Standby function Number of ports I/O voltage Output current I/O circuit configuration Output level at reset mode Minimum cycle time Supply voltage Current dissipation Resonator LC6527N/28N 1024 x 8 bits (27N) 512 x 8 bits (28N) 64 x 4 bits (27N) 32 x 4 bits (28N) 51 4-bit prescaler + 8-bit timer 4 Standby available by HALT instruction I/O 13 max. 15V max. 10mA typ. 20mA max. LC6527F/28F 1024 x 8 bits (27F) 512 x 8 bits (28F) 64 x 4 bits (27F) 32 x 4 bits (28F) 51 4-bit prescaler + 8-bit timer 4 Standby available by HALT instruction I/O 13 max. 15V max. 10mA typ. 20mA max. LC6527L/28L 1024 x 8 bits (27L) 512 x 8 bits (28L) 64 x 4 bits (27L) 32 x 4 bits (28L) 51 4-bit prescaler + 8-bit timer 4 Standby available by HALT instruction I/O 13 max. 15V max. 10mA typ. 20mA max.
Input/output port
Instruction
Open drain (N channel) or pull-up resistor-provided output selectable bit by bit. "H" or "L" level selectable port by port (port C, D only) 2.77s (VDD 4V) 6.0s (VDD3V) 3 to 6V 2.5mA typ. RC (850kHz,400kHz typ.) ceramic (400k,800k,1MHz, 4MHz) 1/1 ,1/3, 1/4 DIP18, MFP18 0.92s (VDD4.5V) 4.5 to 6V 4mA typ. ceramic 4MHz 1/1 DIP18, MFP18 3.84s (VDD 2.2V) 2.2 to 6V 2.5mA typ. RC (400kHz typ.) ceramic (400k, 800k, 1MHz, 4MHz) 1/1, 1/3, 1/4 DIP18, MFP18
Oscillation
Characteristic
predivider option Package
Other
(Note) Information on the resonator and oscillation circuit constants will be presented as soon as the recommended circuit is determined.
No. 4363-2/43
LC6527N/F/L, LC6528N/F/L
Pin Assignment
LC6527N/F/L LC6528N/F/L
Common to DIP * MFP
Top view
Pin Name
OSC1, OSC2 : RES: PA 0 to 3: PC 0 to 3: PD 0 to 3: C, R or ceramic resonator for OSC Reset Input/output common port A 0 to 3 Input/output common port C 0 to 3 Input/output common port D 0 to 3 PH 0 : Input/output common port H 0 TEST : Test
System Block Diagram
LC6527N/F/L, LC6528N/F/L
Note 1. The PH0 pin or OSC2 pin is selected by the mask option. Note 2. LC6527N/F/L ROM : 1024 bytes RAM : 64 words LC6528N/F/L ROM : 512 bytes RAM : 32 words
No. 4363-3/43
LC6527N/F/L, LC6528N/F/L
Development Support Tools
The following are available to support the program development for the LC6527, LC6528. (1) User's Manual "LC6527, LC6528 User's Manual" No. 24-6016 ('86.10.1.) Note : Do not use "LC6523 Series User's Manual" No. 16A-7015 and No. 16-9064. (2) Development Tool Manual For the EVA-800 or the EVA-850 system, refer to "EVA-800-LC6527, LC6528 Development Tool Manual". (3) Development Tools A. For program evaluation 1. Piggy back (LC65PG23/26) 2. 23T27 ; The pin-to-pin conversion socket for the piggy back LC65PG23/26. B. EVA-86000 system for program development. C. For program evaluation microcomputer built-in EPROM (LC65E29) + conversion substrate (29T027)
Note.
For notes for program evaluation, do not fail to refer to '4-3. Notes when evaluating programs' in "LC6527, LC6528 User's Manual".
Figure 1 Evaluation kit target board (EVA-TB6523C/26C/27C/28C)
Figure 2 Program evaluation
No. 4363-4/43
LC6527N/F/L, LC6528N/F/L
D. For program development (EVA-800 or EVA-850 system) 1. MS-DOS for host system (Note 1) 2. Cross assembler......MS-DOS base cross assembler : 3. Host control program 4. Evaluation chip: LC6596 5. Emulator: EVA-800 or EVA-850 emulator and evaluation boards EVA800-TB6527/28
Appearance of Development Support System
(Note 1) MS-DOS : Tradmark of Microsoft Corporation (Note 2) The EVA-800, EVA-850 are general term for emulator. A suffix (A, B,...) is added at the end of EVA-800 and EVA-850 as they are improved to be a newer version. Do not use the EVA-800 and EVA-850 with no suffix added.
No. 4363-5/43
LC6527N/F/L, LC6528N/F/L
Pin Description
Pin Name VDD VSS OSC1 Pins 1 1 1 I/O -- -- Input Power supply * Pin for externally connecting RC,ceramic resonator for system clock generation. * For 1-pin external clock input, the PH0/OSC2 pin is used as I/O port PH0. * For 2-pin RC OSC, 2-pin ceramic resonator OSC, the PH0/OSC2 pin is used as OSC pin OSC2. Function Option -- 1) 1-pin external clock input 2) 2-pin RC OSC 3) 2-pin ceramic resonator OSC 4) Predivider option 1. No predivider 2. 1/3 predivider 3. 1/4 predivider 1) Open drain type output 2) With pull-up resistor 1), 2) : Specified bit by bit Reset Mode -- --
PA 0 to PA 3
4
Input/output * I/O port A0 to A3 4-bit input (IP instruction) 4-bit output (OP instruction) Single-bit decision (BP, BNP instruction) Single-bit set/reset (SPB, RPB instruction) * Standby is controlled by PA3. * The PA3 pin must be free from chattering during the HALT instruction execution cycle. Input/output * I/O port C0 to C3 Same as for PA0 to PA3 (Note) * Option permits output at thereset mode to be "H" or "L". (Note) No standby control function is provided.
* "H"output (Out put Nch transistor : OFF)
PC 0 to PC 3
4
1) Open drain type output 2) With pull-up resistor 3) Output at reset mode:"H" 4) Output at reset mode:"L" * 1), 2): Specified bit by bit * 3), 4): Specified in a group of 4 bits Same as for PC0 to PC3 Same as for PA0 to PA3
* "H" output * "L" output (Optionselectable)
PD 0 to PD 3 PH 0 / OSC2
4 1
Input/output * I/O port D0 to D3 Same as for PC0 to PC3 Input/output * I/O port H0 Same as for PA0 to PA3 (Note) * Single-bit configuration * For 2-pin OSC, this pin is used as the OSC2 pin, providing no function as I/O port. (Note) No standby control function is provided. Input * Systen reset input * For power-up reset, C is connected externally. * For reset restart, "L" level is applied for 4 clock cycles or more. * LSI test pin Normally connected to VSS
Same as for PC0 to PC3 Same as for PA0 to PA3
RES
1
TEST
1
Input
No. 4363-6/43
LC6527N/F/L, LC6528N/F/L
Oscillator circuit option
Option Name 1. External clock 2. 2-pin RC OSC Circuit Conditions , etc. The PH 0 / OSC2 pin is used as port PH0. The PH 0 / OSC2 pin is used as OSC pin OSC2, providing no function as port.
3. Ceramic resonator OSC
The PH 0 / OSC2 pin is used as OSC pin OSC2, providing no function as port.
Predivider Option
Option Name 1. No predivider (1/1) Circuit Conditions , etc. * Applicable to all of 3 OSC options. * The OSC frequency, external clock do not exceed 1444 kHz. (LC6527N, 6528N) * The OSC frequency, external clock do not exceed 4330 kHz. (LC6527F, 6528F) * The OSC frequency, external clock do not exceed 1040 kHz. (LC6527L, 6528L) * Applicatable to only 2 OSC options of external clock, ceramic resonator OSC. * The OSC frequency, external clock do not exceed 4330 kHz. * Applicatable to only 2 OSC options of external clock, ceramic resonator OSC. * The OSC frequency, external clock do not exceed 4330 kHz.
2. 1/3 predivider
3. 1/4 predivider
Note : The OSC option and predivider option are summarized below. Full care must be exercised.
No. 4363-7/43
LC6527N/F/L, LC6528N/F/L
Table of OSC, predivider Option of LC6527N/28N, 27F/28F and 27L/28L LC6527N, LC6528N
Circuit configuration Ceramic resonator OSC Frequency 400 kHz 800 kHz Predivide option (Cycle time) 1/1 (10 s) 1/1 (5 s) 1/3 (15 s) 1/4 (20 s) 1/1 (4 s) 1/3 (12 s) 1/4 (16 s) 1/3 (3 s) 1/4 (4 s) 1/1 (20 to 6 s) 1/3 (20 to 6 s) 1/4 (20 to 6 s) 1/1 (20 to 2.77 s) 1/3 (20 to 2.77 s) 1/4 (20 to 3.70 s) VDD range 3 to 6 V 4 to 6 V 4 to 6 V 4 to 6 V 4 to 6 V 4 to 6 V 4 to 6 V 4 to 6 V 4 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 4 to 6 V 4 to 6 V 4 to 6 V Unusable with 1/1 predivider Remarks Unusable with 1/3, 1/4 predivider
1 MHz
4 MHz 1-pin external clock 200 k to 667 kHz 600 k to 2000 kHz 800 k to 2667 kHz 200 k to 1444 kHz 600 k to 4330 kHz 800 k to 4330 kHz Same as above
External clock by 2-pin RC OSC circuit 2-pin RC
Used with 1/1predivider,recommended constants. If used with other than recommended constants, the frequency, predivider option, VDD range must be the same as for 1pin external clock.
3 to 6 V 4 to 6 V
External clock input to the ceramic oscillation circuit
The ceramic oscillation circuit cannot be driven by external clock. To drive the circuit with external clock, select the external clock option or the 2-pin RC option.
LC6527F, LC6528F
Circuit configuration Ceramic resonator OSC 1-pin external clock External clock input to the ceramic oscillation circuit Frequency 4 MHz 200 k to 4330 kHz Predivider option 1/1 (1 s) 1/1 (20 to 0.92 s) VDD Range (Cycle time) 4.5 to 6 V 4.5 to 6 V Remarks
The ceramic oscillation circuit cannot be driven by external clock. To drive the circuit with external clock, select the external clock option.
No. 4363-8/43
LC6527N/F/L, LC6528N/F/L
LC6527L, LC6528L
Circuit configuration Ceramic resonator OSC Frequency 400 kHz 800 kHz Predivider option (Cycle Time) 1/1 (10 s) 1/1 (5 s) 1/3 (15 s) 1/4 (20 s) 1/1 (4 s) 1/3 (12 s) 1/4 (16 s) 1/4 (4 s) 1/1 (20 to 3.84 s) 1/3 (20 to 3.84 s) 1/4 (20 to 3.84 s) VDD range 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V Unusable with 1/1, 1/3 predivider Remarks Unusable with 1/3, 1/4 predivider
1 MHz
4 MHz 1-pin external clock 200 k to 1040 kHz 600 k to 3120 kHz 800 k to 4160 kHz Same as above
External clock by 2-pin RC OSC circuit 2-pin RC
Used with 1/1predivider, recommended constants. If used with other than recommended constants, the frequency, predivider option, VDD range must be the same as for 1-pin external clock.
2.2 to 6 V
External clock input to the ceramic oscillation circuit
The ceramic oscillation circuit cannot be driven by external clock. To drive the circuit with external clock, select the external clock option or the 2-pin RC option.
Option of ports C, D Output Level at the Reset Mode
For input/output common ports C, D either of the following two output levels may be selected in a group of 4 bits during reset by option.
Option Name 1. Output at the reset mode : "H" level 2. Output at the reset mode : "L" level Conditions , etc. All of 4 bits of ports C, D All of 4 bits of ports C, D
Option of Port Output Configuration
For each input/output common port, either of the following two output configurations may be selected by option.
Option Name 1. Open drain output Circuit Conditions , etc. * Unapplicable to port PH0/OSC2 when 2-pin RC OSC or ceramic resonator OSC is selected.
2. Output with pull-up resistor
No. 4363-9/43
LC6527N/F/L, LC6528N/F/L
Specifications
LC6527N, LC6528N
1. Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Output voltage Input voltage Symbol VDD max VO VI(1) VI(2) Input/output voltage Peak output current Average output current VIO(1) VIO(2) I OP I OA IOA(1) IOA(2) Allowable power dissipation Operating temperature Storage temperature Pd max (1) Pd max (2) Topr Tstg Per pin over the period of 100 ms Total current of PA0 to PA3, (*2) Conditions VDD OSC2 OSC1 (*1) TEST, RES Port of OD type Port of PU type I/O port I/O Port PA0 to PA3 PC0 to PC3 PH0 PD0 to PD3 Pins Ratings -0.3 to +7.0 Allowable up to voltage generated -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to +15 -0.3 to VDD+0.3 -2 to +20 -2 to +20 -6 to +40 -14 to +90 250 150 -40 to +85 -55 to +125 Unit V V V V V V mA mA mA mA mW mW C C
Total current of PC0 to PC3, PD0 to PD3, PH0 (*2) Ta = -40 to +85C (DIP package) Ta = -40 to +85C (MFP package)
2. Allowable Operating Conditions at Ta = -40 to +85C, VSS = 0 V, V DD = 3.0 to 6.0 V
Parameter Symbol Conditions VDD [V] Operating supply voltage Standby supply voltage "H"-level input voltage VDD VST VIH(1) VIH(2) VIH(3) VIH(4) VIH(5) VIH(6) "L"-level input voltage VIL(1) VIL(2) VIL(3) External clock mode Output Nch transistor OFF Output Nch transistor OFF External clock mode VDD = 4 to 6 VDD = 3 to 6 VDD = 4 to 6 RAM, register hold (*3) Output Nch transistor OFF Output Nch transistor OFF Output Nch transistor OFF Output Nch transistor OFF VDD VDD Port of ODtype (except H0) Port of PU type (except H0) H0 of OD type H0 of PU type RES OSC1 Port Port OSC1 Pins min 3.0 1.8 0.7VDD 0.7VDD 0.8VDD 0.8VDD 0.8VDD 0.8VDD VSS VSS VSS Ratings typ max 6.0 6.0 13.5 VDD 13.5 VDD VDD VDD 0.3VDD 0.25VDD 0.25VDD V V V V V V V V V V V Unit
No. 4363-10/43
LC6527N/F/L, LC6528N/F/L
Parameter Symbol Conditions VDD [V] "L"-level input voltage VIL(4) VIL(5) VIL(6) VIL(7) VIL(8) Operating frequency (cycle time) fop (tCYC) When the 1/3 or 1/4 predivider option is selected, clock must not exceed 4.33 MHz. External clock mode VDD = 3 to 6 VDD = 4 to 6 VDD = 3 to 6 VDD = 4 to 6 VDD = 3 to 6 VDD = 4 to 6 OSC1 TEST TEST RES RES Pins min VSS VSS VSS VSS VSS 200 (20) 200 (20) Ratings typ max 0.2VDD 0.3VDD 0.25VDD 0.25VDD 0.2VDD 1444 (2.77) 667 (6.0) V V V V V kHz (s) kHz (s) Unit
External clock conditions Frequency Pulse width Rise/Fall time Oscillation guaranty constants 2-pin RC oscillation
text textH, textL textR, textF
Figure 1. When clock exceeds 1.444 MHz, the 1/3 or 1/4 pre-divider option is selected.
VDD = 4 to 6 3 to 6 VDD = 4 to 6 3 to 6 VDD = 4 to 6 3 to 6
OSC1 OSC1 OSC1
200 200 69 180
4330 2667
kHz kHz ns ns ns ns
50 100
Cext Cext Rext Rext
Figure 2 Figure 2 Figure 2 Figure 2 Figure 3
VDD = 3 to 6 VDD = 4 to 6 VDD = 3 to 6 VDD = 4 to 6
OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 OSC1, OSC2
220 5% 220 5% 12 1% 4.7 1% Table 1
pF pF k k
Ceramic resonator OSC
3. Electrical Characteristics at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 V to 6.0 V
Parameter Symbol Conditions Pins min "H"-level input current IIH (1) Output Nch transistor OFF (including OFF leak current of Nch transistor) VIN = +13.5 V External clock mode, VIN = VDD Output Nch transistor OFF VIN = VSS Output Nch transistor OFF VIN = VSS VIN = VSS External clock mode, VIN = VSS I OH = -50 A VDD = 4.0 to 6.0 V I OH = -10 A Port of OD type Ratings typ max +5.0 A Unit
I IH(2) "L"-level input current I IL (1) I IL (2) I IL (3) I IL (4) "H"-level output voltage VOH(1) VOH(2)
OSC1 Port of OD type Port of PU type RES OSC1 Port of PU type Port of PU type -1.0 -1.3 -45 -1.0 VDD -1.2 VDD -0.5 -0.35 -10
+1.0
A A mA A A V V
No. 4363-11/43
LC6527N/F/L, LC6528N/F/L
Parameter Symbol Conditions Pins min "L"-level output voltage VOL(1) VOL(2) VHIS Output Nch transistor OFF at operating, Port = VDD Figure 2 fosc = 850 kHz (typ) VDD = 4 to 6 V Figure 2 fosc = 400 kHz (typ) Figure 3 4 MHz, 1/3 predivider VDD = 4 to 6 V Figure 3 4 MHz, 1/4 predivider VDD = 4 to 6 V Figure 3 400 kHz Figure 3 800 kHz VDD = 4 to 6 V IOL = 10 mA, VDD = 4.0 to 6.0 V IOL = 1.8 mA, IOL of each port: 1mA or less Port Port RES, OSC1 of schmitt type (*4) 0.1VDD Ratings typ max 1.5 0.4 V V V Unit
Hysteresis voltage Current drain 2-pin RC oscillation Ceramic resonator oscillation
IDDOP(1) IDDOP(2) IDDOP(3) IDDOP(4) IDDOP(5) IDDOP(6)
VDD VDD VDD VDD VDD VDD VDD
1.0 0.8 1.2 1.2 0.5 1.0 1.0
2.5 2.5 3 2.5 2 2.5 2.5
mA mA mA mA mA mA mA
External clock
IDDOP(7)
200 kHz to 667 kHz, 1/1 predivider 600 kHz to 2000 kHz, 1/3 predivider 800kHz to 2667kHz, 1/4 predivider 200 kHz to 1444 kHz, 1/1 predivider 600 kHz to 4330 kHz, 1/3 predivider 800 kHz to 4330 kHz, 1/4 predivider, VDD = 4 to 6 V Output Nch transistor OFF VDD = 6 V Port = VDD VDD = 3 V Figure 3 fo = 400 kHz Figure 3 fo = 800 kHz, VDD = 4 to 6 V Figure 3 fo = 1 MHz VDD = 4 to 6 V Figure 3 fo = 4 MHz, 1/3 predivider 1/4 predivider VDD = 4 to 6 V Figure 4 fo = 400 kHz Figure 4 fo = 800 kHz, 1 MHz, 4 MHz, 1/3 predivider, 1/4 predivider VDD = 4 to 6 V Figure 2 Cext = 220 pF 5% Figure 2 Rext = 4.7 k 1% VDD = 4 to 6 V Figure 2 Cext = 220 pF 5% Figure 2 Rext = 12 k 1% VDD = 3 to 6 V
IDDOP(8)
VDD
1.2
3
mA
Standby mode Oscillation characteristics Ceramic OSC Frequency Stable time
IDDst fCFOSC (*5)
VDD VDD OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 384 768 960 3840
0.05 0.025 400 800 1000 4000
10 5 416 832 1040 4160 10 10
A kHz kHz kHz kHz ms ms
tCFS
2-pin RC oscillation Frequency
fMOSC
OSC1, OSC2
646
850
1117
kHz
OSC1, OSC2
304
400
580
kHz
No. 4363-12/43
LC6527N/F/L, LC6528N/F/L
Parameter Symbol Conditions Pins min Pull-up resistance I/O port pull-up resistance External reset characteristics Reset time Pin capacitance RPP tRST VDD=5V Port of PU type Ratings typ 14 See Figure 5. f = 1 MHz Other than pins to be tested, VIN = VSS 10 pF max k Unit
Cp
(*1) When oscillated internally under the oscillating conditions in Figure 3, up to the oscillation amplitude generated is allowable. (*2) Average over the period of 100 ms. (*3) Operating supply voltage VDD must be held until the standby mode is entered after the execution of the HALT instruction. The PA3 pin must be free from chattering during the HALT instruction execution cycle. (*4) The OSC1 pin can be schmitt-triggered when the 2-pin RC oscillation option or external clock oscillation option has been selected. (*5) fCFOSC: oscillation frequency. There is a tolerance of approximately 1% between the center frequency at the ceramic resonator mode and the nominal value presented by the ceramic resonator supplier. For details, refer to the specification for the ceramic resonator.
No. 4363-13/43
LC6527N/F/L, LC6528N/F/L
VDD 0.8 VDD
0.2 VDD (VDD = 3-4 V) 0.25 VDD (VDD = 4-6 V) VSS
Figure 1 External Clock Input Waveform * External clock can be used at selecting 2-pin RC option or 1-pin external clock option, and cannot be used at ceramic resonator oscillation.
OSC1
OSC2
OSC1
OSC2 R
Cext
Rext C1
Ceramic resonator
C2
Figure 2 2-pin RC Oscillation Circuit
Figure 3 Ceramic Resonator Oscillation Circuit
VDD VDD Lower limit of VDD operating VDD 0V OSC
Unstabilized OSC period tCFS
Stabilized OSC
Figure 4 Oscillation Stabilizing Period
No. 4363-14/43
LC6527N/F/L, LC6528N/F/L
Table 1
Constants Guaranteed for Ceramic Resonator OSC
C1 C2 R C1 C2 R C1 C2 R 33 pF 10% 33 pF 10% 0 33 pF 10 % 33 pF 10% 0 100 pF10% 100pF10% 2.2 k 100 pF 10% 100 pF 10% 0 100 pF 10% 100 pF 10% 2.2 k 100 pF10% 100 pF10% 0 220 pF 10% 220 pF 10% 2.2 k 330 pF 10% 330 pF 10% 0
4MHz (Murata) CSA4.00MG CST4.00MGW (built-in C) 4 MHz (Kyocera) KBR4.0MSA KBR4.0MKS (built-in C) 1 MHz (Murata) CSB1000J
RES
CRES(=0.1 F)
Figure 5 Reset Circuit
1 MHz (Kyocera) KBR1000F
C1 C2 R
800 kHz (Murata) CSB800J
C1 C2 R
(Note) When the rise time of the power supply is 0, the reset time becomes 10 ms to 100 ms at C RES = 0.1 F. If the rise time of the power supply is long, the value of C RES must be increased so that the reset time becomes 10 ms or more.
800 kHz (Kyocera) KBR800F
C1 C2 R
400 kHz (Murata) CSB400P
C1 C2 R
400 kHz (Kyocera) KBR400BK
C1 C2 R
No. 4363-15/43
LC6527N/F/L, LC6528N/F/L
RC Oscillation Characteristics of the LC6527N, LC6528N
Figure 6 shows the RC oscillation characteristics of the LC6527N, 6528N. For the variation range of RC OSC frequency of the LC6527N, LC6528N, the following are guaranteed at the external constants only shown below. 1) VDD = 3.0 V to 6.0 V, Ta = -40C to +85C External constants Cext = 220 pF Rext = 12 k 304 kHz fMOSC 580 kHz 2) VDD = 4.0 V to 6.0 V, Ta = -40C to +85C Cext = 220 pF Rext = 4.7 k 646 kHz fMOSC 1117 kHz If any other constants than specified above are used, the range of Rext = 3 k to 20 k, Cext = 150 pF to 390 pF must be observed. (See Figure 6.)
(*6) : The oscillation frequency at VDD = 5.0 V, Ta = +25C must be in the range of 350 kHz to 750 kHz. (*7) : The oscillation frequency at VDD = 4.0 to 6.0 V, Ta = -40C to +85C and VDD = 3.0 V to 6.0 V, Ta = -40C to 85C must be within the operation clock frequency range.
fMOSC -- Rext
fMOSC [kHz]
Rext [k] Figure 6 RC Oscillation Frequency Data (typ)
No. 4363-16/43
LC6527N/F/L, LC6528N/F/L
LC6527F, LC6528F
1. Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Output voltage Input voltage Symbol VDD max VO VI (1) VI (2) Input/output voltage VIO (1) VIO (2) Peak output current Average output current IOP IOA IOA (1) IOA (2) Allowable power dissipation Operating temperature Storage temperature Pd max (1) Pd max (2) Topr Tstg Per pin over the period of 100 ms Total current of PA0 to PA3, (*2) Total current of PC0 to PC3, PD0 to PD3, PH0 (*2) Ta = -40 to +85C (DIP package) Ta = -40 to +85C (MFP package) Conditions VDD OSC2 OSC1 (*1) TEST, RES Port of OD type Port of PU type I/O Port I/O Port PA0 to PA3 PC0 to PC3 PH0 PD0 to PD3 Pin Ratings -0.3 to +7.0 Allowable up to voltage generated -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to +15 -0.3 to VDD+0.3 -2 to +20 -2 to +20 -6 to +40 -14 to +90 250 150 -40 to +85 -55 to +125 Unit V V V V V V mA mA mA mA mW mW C C
2. Allowable Operating Conditions at Ta = -40 to +85C, VSS = 0 V, VDD = 4.5 to 6.0 V
Parameter Symbol Conditions Pin min Operating supply voltage Standby supply voltage "H"-level input voltage VDD VST VIH(1) VIH(2) VIH(3) VIH(4) VIH(5) VIH(6) External clock mode RAM, register hold (*3) Output Nch transistor OFF Output Nch transistor OFF Output Nch transistor OFF Output Nch transistor OFF VDD VDD Port of OD type (except H0) Port of PU type (except H0) H0 of OD type H0 of PU type RES OSC1 4.5 1.8 0.7V DD 0.7V DD 0.8V DD 0.8V DD 0.8V DD 0.8V DD Ratings typ max 6.0 6.0 13.5 VDD 13.5 VDD VDD VDD V V V V V V V V Unit
No. 4363-17/43
LC6527N/F/L, LC6528N/F/L
Parameter Symbol Conditions Pin min "L"-level input voltage VIL(1) VIL(2) VIL(3) VIL(4) Operating frequency (Cycle time) External clock conditions Frequency Pulse width Rise/fall time Oscillation guaranteed constants Ceramic resonator OSC fOP (tCYC) Output Nch transistor OFF External clock mode Port OSC1 TEST RES VSS VSS VSS VSS 200 (20) Ratings typ max 0.3VDD 0.25VDD 0.3VDD 0.25VDD 4330 (0.92) V V V V kHz (s) Unit
text textH, textL textR, textF
Figure 1 Figure 2
OSC1 OSC1 OSC1
200 69 See Table 1.
4330 50
kHz ns ns
3. Electrical Characteristics at Ta = -40C to +85C, VSS = 0 V, VDD = 4.5 to 6.0 V
Parameter Symbol Conditions Pin min "H"-level input current IIH(1) Output Nch transistorOFF (including OFF leak current of Nch transistor) VIN = +13.5 V External clock mode, V IN = V DD Output Nch transistor OFF VIN = VSS Output Nch transistor OFF VIN = VSS VIN = VSS External clock mode, V IN = VSS IOH = -50 A IOH = -10 A IOL = 10 mA IOL = 1.8 mA, IOL of each port : 1 mA or less Port of OD type Ratings typ max +5.0 A Unit
IIH(2) "L"-level input current IIL(1) IIL(2) IIL(3) IIL(4) "H"-level output voltage "L"-level output voltage VOH(1) VOH(2) VOL(1) VOL(2) VHIS
OSC1 Port of OD type Port of PU type RES OSC1 Port of PU type Port of PU type Port Port RES, OSC1 of schmitt type (*4) 0.1VDD -1.0 -1.3 -45 -1.0 VDD-1.2 VDD-0.5 -0.35 -10
+1.0
A A mA A A V V
1.5 0.4
V V V
Hysteresis voltage
No. 4363-18/43
LC6527N/F/L, LC6528N/F/L
Parameter Symbol Conditions Pin min Current drain Ceramic resonator OSC External clock Ratings typ max Unit
IDDOP(1) IDDOP(2)
Figure 2
4 MHz
*1
VDD VDD
1.5 1.5
3.5 3.5
mA mA
200 kHz to 4330 kHz *1 Output Nch transistor OFF at Operating mode Port = VDD Output Nch transistor OFF Port = VDD VDD = 6 V VDD = 3 V
Standby mode
IDDst
VDD VDD
0.05 0.025
10 5
A A
Oscillation characteristics Ceramic resonator OSC Frequency Stable time Pull-up resistance I/O port pull-up resistance External reset characteristics Reset time Pin capacitance
fCFOSC tCFS RPP
Figure 2 fo = 4 MHz (*5) Figure 3 fo = 4 MHz VDD = 5 V
OSC1, OSC2
3840
4000
4160 10
kHz ms k
Port of PU type
14
tRST Cp f = 1 MHz, other than pins to be tested, VIN = V SS
See Figure 4 10 pF
(*1) When oscillated internally under the oscillating conditions in Fig.2, up to the oscillation amplitude generated is allowable. (*2) Average over the period of 100 ms. (*3) Operating supply voltage VDD must be held until the standby mode is entered after the execution of the HALT instruction. The PA3 pin must be free from chattering during the HALT instruction execution cycle. (*4) The OSC1 pin can be schmitt-triggered when the external clock oscillation option has been selected. (*5) fCFOSC : Oscillatable frequency.
No. 4363-19/43
LC6527N/F/L, LC6528N/F/L
OSC1
(OSC2) OPEN
VDD VDD 0.8 VDD VDD
External clock
0.25VDD VDD
VSS VSS textF textL textR text textH
Figure 1 External Clock Input Waveform VDD VDD Lower limit of operating VDD VDD 0V C1
Ceramic resonator
OSC1
OSC2 R
C2
OSC
Unstabilized OSC period tCFS Figure 2 Ceramic resonator OSC circuit
Stabilized OSC
Figure 3 OSC Stabilizing Period
Table 1 Constants Guaranteed for Ceramic Resonator OSC
4MHz (Murata) CSA4.00MG CST4.00MGW (built-in C) 4MHz (Kyocera) KBR4.0MSA KBR4.0MKS (built-in C) C1 C2 R C1 C2 R 33 pF 10% 33 pF 10% 0 33 pF 10% 33 pF 10% 0
RES
CRES(=0.1 F)
Figure 4 Reset Circuit (Note) When the rise time of the power supply is 0, the reset time becomes 10ms to 100ms at CRES = 0.1 F. If the rise time of the power supply is long, the value of CRES must be increased so that the reset time becomes 10ms or more. No. 4363-20/43
LC6527N/F/L, LC6528N/F/L
LC6527L, LC6528L
1. Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum VDD max supply voltage Output voltage Input voltage Symbol VDD max VO VI(1) VI(2) Input/output voltage VIO(1) VIO(2) Peak output current Average output current IOP IOA IOA(1) IOA(2) Allowable power dissipation Operating temperature Storage temperature Pd max(1) Pd max(2) Topr Tstg Per pin over the period of 100 ms Total current of PA0 to PA3, (*2) Total current of PC0 to PC3, PD0 to PD3, PH0 (*2) Ta = -40 to +85C (DIP package) Ta = -40 to +85C (MFP package) Conditions VDD OSC2 OSC1 (*1) TEST, RES Port of OD type Port of PU type I/O Port I/O Port PA0 to PA3 PC0 to PC3 PH0 PD0 to PD3 Pin Ratings -0.3 to +7.0 Allowable up to voltage generated -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to +15 -0.3 to VDD+0.3 -2 to +20 -2 to +20 -6 to +40 -14 to +90 250 150 -40 to +85 -55 to +125 Unit V V V V V V mA mA mA mA mW mW C C
2. Allowable Operating Conditions at Ta = -40C to 85C, VSS = 0 V, VDD = 2.2 to 6.0 V
Parameter Symbol Conditions Pin min Operating supply voltage Standby supply voltage "H"-level input voltage VDD VST VIH (1) VIH (2) VIH (3) VIH (4) VIH (5) VIH (6) "L"-level input voltage VIL (1) VIL (2) VIL (3) VIL (4) External clock Output Nch transistor OFF External clock RAM, register hold (*3) Output Nch transistor OFF Output Nch transistor OFF Output Nch transistor OFF Output Nch transistor OFF VDD VDD Port of OD type (except H0) Port of PU type (except H0) H0 of OD type H0 of PU type RES OSC1 Port OSC1 TEST RES 2.2 1.8 0.7VDD 0.7VDD 0.8VDD 0.8VDD 0.8VDD 0.8VDD VSS VSS VSS VSS Ratings typ max 6.0 6.0 13.5 VDD 13.5 VDD VDD VDD 0.2V DD 0.15V DD 0.2V DD 0.15V DD V V V V V V V V V V V V Unit
No. 4363-21/43
LC6527N/F/L, LC6528N/F/L
Parameter Symbol Conditions Pin min Operating frequency (cycle time) External Clock conditions Frequency Pulse width Rise/fall time Oscillation guaranteed constants 2-pin RC oscillation Ceramic oscillation fOP (tCYC) When the 1/3 or 1/4 predivider option is selected, clock must not exceed 4.16 MHz. 200 (20) Ratings typ max 1040 (3.84) kHz (s) Unit
text textH, textL textR, textF
Figure 1 When clock exceeds 1.040 MHz, the 1/3 or 1/4 predivider option is selected.
OSC1 OSC1 OSC1
200 120
4160 100
kHz ns ns
Cext Rext
Figure 2
OSC1, OSC2
220 5% 12 1%
pF k
Figure 3
See Table 1.
3. Electrical Characteristics at Ta = -40C to +85C, VSS = 0 V, VDD = 2.2 to 6.0 V
Parameter Symbol Conditions Pin min "H"-level input current IIH(1) Output Nch transistor OFF (including OFF leak current of Nch transistor) VIN = +13.5 V External clock mode, VIN = VDD Output Nch transistor OFF VIN = VSS Output Nch transistor OFF VIN = VSS VIN = VSS External clock mode, V IN = VSS I OH = -10 A I OL = 3 mA I OL = 1 mA, IOL of each port: 1 mA or less Port of OD type Ratings typ max +5.0 A Unit
IIH(2) "L"-level input current IIL(1) IIL(2) IIL(3) IIL(4) "H"-level output voltage "L"-level output voltage VOH VOL(1) VOL(2) VHIS
OSC1 Port of OD type Port of PU type RES OSC1 Port of PU type Port Port RES, OSC1 of Schmitt type (*4) 0.1VDD -1.0 -1.3 -45 -1.0 VDD-0.5 -0.35 -10
+1.0
A A mA A A V
1.5 0.4
V V V
Hysteresis voltage
No. 4363-22/43
LC6527N/F/L, LC6528N/F/L
Parameter Symbol Conditions Pin min Current drain 2-pin RC OSC IDDOP(1) Ceramic OSC IDDOP(2) IDDOP(3) IDDOP(4) IDDOP(5) External clock IDDOP(6) Output Nch transistor OFF at operating, Port = VDD Figure 2 fOSC = 400 kHz (typ) Figure 3 4 MHz, 1/4 predivider Figure 3 4 MHz, 1/4 predivider VDD = 2.2 V Figure 3 Figure 3 400 kHz 800 kHz Ratings typ max Unit
VDD VDD VDD VDD VDD VDD
0.8 1.2 0.5 0.5 1.0 1.0
2.5 2.5 1 2 2.5 2.5
mA mA mA mA mA mA
200 kHz to 667 kHz, 1/1 predivider 600 kHz to 2000 kHz, 1/3 predivider 800 kHz to 2667 kHz, 1/4 predivider Output Nch transistor OFF Port = V DD VDD = 6 V VDD = 2.2 V
Standby mode
IDDst
VDD VDD
0.05 0.025
10 5
A A
Oscillation characteristics Ceramic OSC Frequency
fCFOSC (*5) Figure 3 fo = 400 kHz Figure 3 fo = 800 kHz Figure 3 fo = 1 MHz Figure 3 fo = 4 MHz, 1/4 predivider tCFS Figure 4 fo = 400 kHz Figure 4 fo = 800 kHz, 1 MHz, 4 MHz, 1/4 predivider Figure 2 Cext = 220 pF 5% Figure 2 Rext = 12 k 1% VDD = 5 V
OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 OSC1, OSC2
384 768 960 3840
400 800 1000 4000
416 832 1040 4160 10 10
kHz kHz kHz kHz ms ms kHz
Stable time
2-pin RC OSC Frequency Pull-up resistance I/O port pull-up resistance External reset characteristics Reset time Pin capacitance
fMOSC
OSC1, OSC2
281
400
580
RPP tRST
Port of PU type
14 See Figure 5.
k
Cp
f = 1 MHz, Other than pins to be tested, VIN = VSS
10
pF
(*1) When oscillated internally under the oscillating conditions in Fig.3, up to the oscillation amplitude generated is allowable. (*2) Average over the period of 100ms. (*3) Operating supply voltage VDD must be held until the standby mode is entered after the execution of the HALT instruction. The PA3 pin must be free from chattering during the HALT instruction execution cycle. (*4) The OSC1 pin can be schmitt-triggered when the 2-pin RC oscillation option, or external clock oscillation option has been selected. (*5) fCFOSC : Oscillatable frequency. There is a tolerance of approximately 1% between the center frequency at the ceramic resonator mode and the nominal value presented by the ceramic resonator supplier. For details, refer to the specification for the ceramic resonator.
No. 4363-23/43
LC6527N/F/L, LC6528N/F/L
OSC1
(OSC2) OPEN
VDD VDD 0.8 V 0.8 VDD DD
External clock
0.15VDD 0.15 VDD
VSS VSS
textF textL textR text textH
Figure 1 External Clock Input Waveform * External clock can be used at selecting 2-pin RC option or 1-pin external clock option, and cannot be used at ceramic resonator oscillation.
OSC1
OSC2
OSC1
OSC2 R
Cext
Rext
C1
Ceramic resonator
C2
Figure 2 2-pin RC Oscillation Circuit
Figure 3 Ceramic Resonator Oscillation Circuit
VDD VDD Lower limit of Lower limit of operating VDD operating VDD 0V OSC
Unstabilized OSC period tCFS
Stabilized OSC
Figure 4 Oscillation Stabilizing Period
No. 4363-24/43
LC6527N/F/L, LC6528N/F/L
Table 1 Constants Guaranteed for Ceramic Resonator OSC
C1 C2 R C1 C2 R 1MHz (Kyocera) KBR1000F C1 C2 R 800kHz (Murata) CSB800J C1 C2 R 800kHz (Kyocera) KBR800F C1 C2 R 400kHz (Murata) CSB400P C1 C2 R 400kHz (Kyocera) KBR400BK C1 C2 R 33 pF10% 33 pF10% 0 100 pF10% 100 pF10% 2.2 k 100 pF 10% 100 pF 10% 0 100 pF10% 100 pF10% 2.2 k 100 pF10% 100 pF10% 0 220 pF10% 220 pF10% 2.2 k 330 pF10% 330 pF10% 0
4MHz (Murata) CSA4.00MGU CST4.00MGWU (built-in C) 1MHz (Murata) CSB1000J
RES
CRES(=0.1 F)
Figure 5 Reset Circuit
(Note)
When the rise time of the power supply is 0, the reset time becomes 10 ms to 100 ms at CRES = 0.1 F. If the rise time of the power supply is long, the value of CRES must be increased so that the reset time becomes 10ms or more.
No. 4363-25/43
LC6527N/F/L, LC6528N/F/L
RC Oscillation Characteristic of the LC6527L, 6528L
Fig. 6 shows the RC oscillation characteristic of the LC6527L, 6528L. For the variation range of RC OSC frequency of the LC6527L, 6528L, the following are guaranteed at the external constants only shown below. VDD = 2.2 V to 6.0 V, Ta = -40C to +85C External constants Cext = 220 pF Rext = 12 k 281 kHz fMOSC 580 kHz If any other constants than specified above are used, the range of Rext = 3 k to 20 k, Cext = 150 pF to 390 pF must be observed. (See Figure 6.) (*6) : The oscillation frequency at VDD = 5.0 V, Ta = +25C must be in the range of 350 kHz to 500 kHz. (*7) : The oscillation frequency at VDD = 2.2 to 6.0 V and Ta = -40C to +85C must be within the operation clock frequency range.
fMOSC - Rext
fMOSC [kHz]
Rext [k] Figure 6 RC Oscillation Frequency Data (typ.)
No. 4363-26/43
LC6527N/F/L, LC6528N/F/L
Notes for Program Evaluation * When evaluating the LC6527/28 with the evaluation chip (LC6596, LC65PG23/26), the following must be observed.
Classification Function Mass-production chip 2-pin OSC PH 0 and OSC2 share one pin (PH0 /OSC2). Either of them is selected exclusively by user option. When 2-pin OSC is selected, PH 0/OSC2 pin provides OSC2 and performs no function as PH0 port. Data input to PH 0/OSC2 by mistake is always read as "0". 3 selections (1/1, 1/3, 1/4) by option. Ports C, D can be brought to "H" or "L" in a group of 4 bits. Evaluation chip Evaluation chip has PH0 and OSC2 separately. Pin required for option is selected as required. Even when OSC2 pin is selected by option, PH0 circuit is present and functions as complete port PH 0. Since input/output at PH0 on evaluation chip results in difference between evaluation chip operation and massproduction chip operation, input/output at PH0 is prohibited.
Item
Notes for evaluation
OSC predivider Notes for option Ports C, D output level at reset mode
3 selections (1/1, 1/3, 1/4) available by 2 pins of DIV pin, 3OR4 pin. Port C and port D can be brought to "H" and "L" by CHL pin and DHL pin respectively.
DIV pin, 3OR4 pin must be set according to option specified for massproduction chip. CHL pin and DHL in must be set according to option specified for massproduction chip.
Port output PU or OD can be selected configuration bitwise. PU/OD
Only OD without PU.
[LC6596-applied evaluation] External resistor (15k) on evaluation board must be connected to necessary port. [Piggyback-applied evalutaion] Resistor must be connected to necessary port on application board. For mass-production chip, leakage current only flows in Pch Tr at "L" output mode; for evaluation chip, current continues flowing in PU resistor at "L" output mode. [2-pin RC OSC] Frequency must be adjusted to OSC frequency of mass-production chip by adjusting variable rest iro. [2-pin ceramic resonator OSC] External constants must be fineadjusted according to service conditions.
PU resistor PU resistor brought to Hi-Z (Pch configuration Tr to turn OFF) at "L" output mode.
PU resistor, being external resistor, whose impedance remains unchanged at "L" output mode. [2-pin RC OSC] Different from mass-production chip in circuit design and characteristic. [2-pin ceramic resonator OSC] Different from mass-production chip in circuit design and characteristic. Wiring capacitance may provide unstable OSC.
OSC constants-1
[2-pin RC OSC] Catalog-guaranteed constants provide OSC at frequency specified in catalog. [2-pin ceramic resonator OSC] Catalog-guaranteed constants provide OSC at frequency specified in catalog.
Notes for OSC
OSC [2-pin ceramic resonator OSC] constants-2 Feedback resistor is contained. (Note)
[2-pin ceramic resonator OSC] [2-pin ceramic resonator OSC] No feedback resistor is contained. For evaluation chip, feedback resistor of 1M must be connected externally.
Continued on next page.
No. 4363-27/43
LC6527N/F/L, LC6528N/F/L
Continued from preceding page.
Classification Function Mass-production chip OSC frequency OSC frequency characteristic as indicated in catalog. Evaluation chip Different from mass-production chip in circuit design, and characteristic. ES, CS must be used to evaluate characteristic in detail.
Item
Notes for evaluation
Notes for electrical characteristics
Operating current, standby current Type No. setting
Current characteristic as indicated Different from mass-production chip in circuit design, characterisin catalog. tic. LC6527/28 differ in ROM, RAM. ROM, RAM to be used according to Type No. are set by INSTC, MEMC. Input pin RSTC, which is not provided in mass-production chip, is provided. INSTC, MEMC are set according to Type No. of mass-production chip.
Other notes
Evaluation chip pin setting
SW4 on evaluation board must remain turned OFF.
Note)
When the evaluation chip is used in the 2-pin ceramic resonator OSC mode, no feedback resistor is contained unlike the mass-production chip. Connect a feedback resistor of 1 M externally as shown below. Since constants R, C also differ from those for the mass-production chip, refer to Table 1 and adjust the capacitor value according to the stray capacitance of the circuit.
Figure 1 2-Pin Ceramic Resonator OSC Circuit for Evaluation Chip and Mass-production Chip
No. 4363-28/43
LC6527N/F/L, LC6528N/F/L
Evaluation chip (*) Ceramic resonator Mass-production chip C1 = C2 Including capacitance of Including no capacitance of standard cable (FAS-20-03B) standard cable (FAS-20-03B) C1 = C2 4 MHz CSA4.00MG (Murata) KBR4.0MS (Kyocera) 1 MHz CSB1000K (Murata) KBR1000H (Kyocera) 800 kHz CSB800K (Murata) KBR800H (Kyocera) 400 kHz CSB400P (Murata) KBR400B, KBR400H (Kyocera) 30 pF 33 pF (Using CSB1000D) 100 pF 100 pF (Using CSB800D) 100 pF 100 pF 330 pF 150 pF 8 pF 8 pF 82 pF 82 pF 120 pF 120 pF 220 pF 330 pF R 0 0 2.2 k 2.2 k 2.2 k 2.2 k 3.3 k 1.0 k C1 = C2 33 pF 33 pF 100 pF 100 pF 150 pF 150 pF 270 pF 330 pF R 0 0 2.2 k 2.2 k 2.2 k 2.2 k 3.3 k 1.0 k
Table 1 Reference Values of Constants R, C
(*) Standard cable (FAS-20-03B) is a cable attached to target board EVA-TB6523C/26C/27C/28C. Table 1 shows two cases where the capacitance of the cable is included and no capacitance of the cable is included. * Example where the capacitance of the cable is included The capacitance of the cable is included when the resonator is connected to the user's applciation board through the cable from the EVA-TB6523C/26C/27C/28C. * Example where no capacitance of the cable is included No capacitance of the cable is included when the resonator is placed near the evaluation chip (on the EVA-TB6523C/26C / 27C/28C). When using any other cable than the attached cable, adjust the capacitor value according to the stray capacitance.
No. 4363-29/43
LC6527N/F/L, LC6528N/F/L
LC6527, 6528 Instruction Set (by function)
Symbol AC ACt CF DP E M M (DP) Description : Accumulator : Accumulator bit t : Carry flag : Data pointer : E register : Memory : Memory addressed by DP P(DPL) PC STACK TM TMF ZF
Instruction code D7 D6 D5 D4 D3 D2 D1 D0 CLA Accumulator manipulation instructions CLC STC CMA INC DEC TAE XAE INM DEM SMB bit RMB bit AD Clear AC Clear CF Set CF Complement AC Increment AC Decrement AC Transfer AC to E Exchange AC with E Increment M Decrement M Set M data bit Reset M data bit Add M to AC 1100 1110 1111 1110 0000 0000 0000 0000 0010 0010 0000 0010 0110 0000 0001 0001 1011 1110 1111 0011 1101 1110 1111
: Input/output port addressed by DP L : Program counter : Stack register : Timer : Timer (internal) interrupt request flag : Zero flag
Bytes Cycles
( ), [ ] + - Y
: Contents : Transfer and direction : Addition : Subtraction : Exclusive OR
Instruction group
Mnemonic
Function
Description
Status flag affected
Remarks
1 1 AC 0 1 1 CF 0 1 1 CF 1 1 1 AC (AC) 1 1 AC (AC) + 1 1 1 AC (AC) - 1 1 1 E (AC) 1 1 (AC) (E) 1 1 M(DP) [M (DP)] + 1 1 1 M(DP) [M(DP)] - 1
The AC contents are cleared. The CF contents are cleared. The CF is set. The AC contents are complemented. The AC contents are incremented +1. The AC contents are decremented -1. The AC contents are transferred to the E. The AC contents and the E contents are exchanged. The M(DP) contents are incremented +1. The M(DP) contents are decremented -1. A single bit of the M(DP) specified with B1B0 is set. A single bit of the M(DP) specified with B1B0 is reset.
ZF CF CF ZF ZF CF ZF CF
*1
Memory manipulation instructions
ZF CF ZF CF
1 0 B1 B0 1 1 M(DP, B1B0) 1 1 0 B1 B0 1 1 M(DP, B1B0) 0 0000
ZF ZF CF
1 1 AC = (AC) + [M(DP)] Binary addition of the AC contents and the M(DP) contents is performed and the result is stored in the AC. 1 1 AC (AC) + [M(DP)] +(CF) Binary addition of the AC, CF contents and the M(DP) contents is performed and the result is stored in the AC. 6 is added to the AC contents. 10 is added to the AC contents. The AC contents and the M(DP) contents are exclusive OR ad and the result is stored in the AC. The AC contents and the M(DP) contents are compared and the CF and ZF are set/ reset. Comparison result CF [M(DP)] > (AC) [M(DP)] = (AC) [M(DP)] < (AC) 0 1 1 ZF 0 1 0
ADC Arithmetic operation/comparison instructions
Add M to AC with CF
0010
0000
ZF CF
DAA DAS EXL
Decimal adjust AC in addition Decimal adjust AC in subtraction Exclusive or M to AC
1110 1110 1111
0110 1010 0101
1 1 AC (AC) + 6 1 1 AC (AC) + 10 1 1 AC (AC) Y [M(DP)]
ZF ZF ZF
CM
Compare AC with M
1111
1011
1 1 [M(DP)] + (AC) + 1
ZF CF
No. 4363-30/43
LC6527N/F/L, LC6528N/F/L
Instruction group Instruction code D7 D6 D5 D4 D3 D2 D1 D0 CI data Compare AC with immediate data 0010 0100 1100 I3 I2 I1 I0 Bytes Cycles Status flag affected The AC contents and the immediate data I3 I2I1I0 are compared and the ZF and CF are set/reset. Comparison result CF I3I2 I1 I0 > (AC) I3I2 I1 I0 = (AC) I3I2 I1 I0 < (AC) LI data Load/store instructions S L Load AC with immediate data Store AC to M Load AC from M 1100 0000 0010 1000 I3 I2 I1 I0 1 1 AC I3I2I1I0 0010 0001 1 1 M(DP) (AC) 1 1 AC [M(DP)] 0 1 1 ZF 0 1 0 ZF *1 ZF CF
Mnemonic
Function
Description
Remarks
2 2 I3I2I1I0 + (AC) + 1
The immediate data I3I2I1 I0 is loaded in the AC. The AC contents are stored in the M(DP). The M(DP) contents are loaded in the AC. The DPH and DPL are loaded with 0 and the immediate data I3I2I1I0 respectively. The DPH is loaded with the immediate data I1 I0 . The DPL contents are incremented + 1. The DPL contents are decremented - 1. The AC contents are transferred to the DPL . The DPL contents are transferred to the AC. A jump to the address specified with immediate data P9P8P7P6P5P4P3P2P1P0 occurs. A subroutine is page 0 is called. A subroutine is called.
ZF
Data pointer manipulation instructions
LDZ data Load DPH with Zero and DPL with immediate data respectively LHI data IND DED TAL TLA Load DPH with immediate data Increment DPL Decrement DPL Transfer AC to DPL Transfer DPL to AC
I3 I2 I1 I0 1 1 DPH 0 DPL I3I2I1I0
0100 1110 1110 1111 1110 0110 P7 P6 P5 P4 1011
0 0 I1 I0 1 1 DPH I1I0 1110 1111 0111 1001 1 1 DPL (DPL) + 1 1 1 DPL (DPL) - 1 1 1 DPL (AC) 1 1 AC (DPL)
ZF ZF
ZF
JMP addr Jump Jump/subroutine instructions
1 0 P9 P8 2 2 PC P9P8P7P6P5 P3 P2 P1 P0 P4P3P2P1P0 P3 P2 P1 P0 1 1 STACK (PC) + 1 PC9--6 PC1--0 0 PC5--2 P3P2P1P0 1 0 P9 P8 2 2 STACK (PC) + 2 P3 P2 P1 P0 PC9--0 P6P5P4P3P2P1P0 0010 1 1 PC (STACK)
CZP addr Call subroutine in the zero page CAL addr Call subroutine
1010 P7 P6 P5 P4 0110
RT
Return from subroutine Branch on AC bit
A return from a subroutine occurs. If a single bit of the AC specified with the immediate data t1t0 is 1, a branch to the address specified with the immediate data P7P6P5P4P3P2P1P0 within the same page occurs. If a single bit of the AC specified with the immediate data t1t0 is 0, a branch to the address specified with the immediate data P7P6P5P4P3P2P1P0 within the same page occurs. If a single bit of the M(DP) specified with the immediate data t1t0 is 1, a branch to the address specified with the immediate data P7P6P5P4P3P2P1P0 within the same page occurs. Mnemonic is BA0 to BA3 according to the value of t. Mnemonic is BNA0 to BNA3 according to the value of t. Mnemonic is BM0 to BM3 according to the value of t.
BAt addr
0111 P7 P6 P5 P4
0 0 t1 t0 2 2 PC7--0 P7P6P5P4 P3 P2 P1 P0 P3P2P1P0 if ACt = 1
Branch instructions
BNAt addr Branch on no AC bit
0011 P7 P6 P5 P4
0 0 t1 t0 2 2 PC7--0 P7P6P5P4 P3 P2 P1 P0 P3P2P1P0 if ACt = 0
BMt addr Branch on M bit
0111 P7 P6 P5 P4
0 1 t1 t0 2 2 PC7--0 P7P6P5P4 P3 P2 P1 P0 P3P2P1P0 if [M(DP, t1t0)] = 1
No. 4363-31/43
LC6527N/F/L, LC6528N/F/L
Instruction group Bytes Cycles Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 BNMt addr Branch on no M bit 0011 P7 P6 P5 P4 Function Description Status flag affected Remarks
0 1 t1 t0 2 2 PC7--0 P7P6P5P4 P3 P2 P1 P0 P3P2P1P0 if [M(DP, t1t0)] = 0
If a single bit of the M(DP) specified with the immediate data t1t0 is 0, a branch to the address specified with the immediate data P7P6P5P4P3P2P1P0 within the same page occurs. If a single bit of port P(DPL) specified with the immediate data t1t0 is 1, a branch to the address specified with the immediate data P7P6P5P4P3P2P1P0 within the same page occurs. If a single bit of port P(DPL) specified with the immediate data t1t0 is 0, a branch to the address specified with the immediate data P7P6P5P4P3P2P1P0 within the same page occurs. If the TMF is 1, a branch to the address specified with the immediate data P7P6P5P4P3P2P1P0 within the same page occurs. The TMF is reset. If the TMF is 0, a branch to the address specified with the immediate data P7P6P5P4P3P2P1P0 within the same page occurs. The TMF is reset. If the CF is 1, a branch to the address specified with the immediate data P7P6P5P4P3P2P1P0 within the same page occurs. If the CF is 0, a branch to the address specified with the immediate data P7P6P5P4P3P2P1P0 within the same page occurs. If the ZF is 1, a branch to the address specified with the immediate data P7P6P5P4P3P2P1P0 within the same page occurs. If the ZF is 0 a branch to the addressd specified with the immediate data P7P6P5P4P3P2P1P0 within the same page occurs. Port P(DPL) contents are loaded in the AC. The AC contents are outputted to port P(DPL). A single bit in prot P(DPL) specified with the immediate data B1B0 is set. ZF TMF
Mnemonic is BNM0 to BNM3 according to the value of t. Mnemonic is BP0 to BP3 according to the value of t.
BPt addr
Branch on Port bit
0111 P7 P6 P5 P4
1 0 t1 t0 2 2 PC7--0 P7P6P5P4 P3 P2 P1 P0 P3P2P1P0 if [P(DPL t1t0)] = 1
BNPt addr Branch on no Port bit
0011 P7 P6 P5 P4
1 0 t1 t0 2 2 PC7--0 P7P6P5P4 P3 P2 P1 P0 P3P2P1P0 if [P(DPL, t1t0)] = 0
Mnemonic is BNP0 to BNP3 according to the value of t.
BTM addr Branch on timer
0111 P7 P6 P5 P4
1 1 0 0 2 2 PC7--0 P7P6P5P4 P3 P2 P1 P0 P3P2P1P0 if TMF = 1 then TMF 0
BNTM addr Branch on no timer
0011 P7 P6 P5 P4
1 1 0 0 2 2 PC7--0 P7P6P5P4 P3 P2 P1 P0 P3P2P1P0 if TMF = 0 then TMF 0
TMF
BC addr
Branch on CF
0111 P7 P6 P5 P4
1 1 1 1 2 2 PC7-0 P7P6P5P4 P3 P2 P1 P0 P3P2P1P0 if CF = 1
BNC addr Branch on no CF
0011 P7 P6 P5 P4
1 1 1 1 2 2 PC7-0 P7P6P5P4 P3 P2 P1 P0 P3P2P1P0 if CF = 0
BZ addr
Branch on ZF
0111 P7 P6 P5 P4
1 1 1 0 2 2 PC7-0 P7P6P5P4 P3 P2 P1 P0 P3P2P1P0 if ZF = 1
BNZ addr Branch on no ZF
0011 P7 P6 P5 P4
1 1 1 0 2 2 PC7-0 P7P6P5P4 P3 P2 P1 P0 P3P2P1P0 if ZF = 0
IP OP Input/output instructions SPB bit
Input port to AC Output AC to port Set port bit
0000 0110 0000
1100 0001
1 1 AC [P(DPL)] 1 1 P(DPL) (AC)
0 1 B1B0 1 2 P(DPL, B1B0) 1
When this instruction is executed, the E contents are destroyed. ZF When this instruction is executed, the E contents are destroyed.
RPB bit
Reset port bit
0010
0 1 B1B0 1 2 P(DPL, B1B0) 0
A single bit in port P(DPL) specified with the immediate data B1B0 is reset.
No. 4363-32/43
LC6527N/F/L, LC6528N/F/L
Instruction group Bytes Cycles Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 WTTM Other instructions Write timer 1111 Function Description Status flag affected TMF Remarks
1 0 0 1 1 1 TM (E), (AC) TMF 0 0 1 1 0 1 1 Halt
The E and AC contents are loaded in the timer. The TMF is reset. All operations stop.
HALT
Halt
1111
Only when all pins of port PA are set at L stop.
NOP
No operation
0000
0 0 0 0 1 1 No operation
No operation is performed, but 1 machine cycle is consumed.
*1 If the CLA instruction is used continuously in such a manner as CLA, CLA, ---, the first CLA instruction only is effective and the following CLA instructions are changed to the NOP instructions. This is also true of the LI instruction.
The following instructions, which are included in the instruction set of the LC6523, 6526, are excluded. AND, BFn, BI, BNFn, BNI, CLI, JPEA, OR RAL, RCTL, RFB, RTI, RTBL, SCTL, SFB, X, XAH, XA0, XA1, XA2, XA3, XD, XH0, XH1, XI, XL0, XL1, XM
No. 4363-33/43
LC6527N/F/L, LC6528N/F/L
LC6527N/F/L, 6528N/F/L Option Code Specifying Method General Description
It is requested that you should submit to us various mask options of the LC6527N/F/L, LC6528N/F/L together with the program code which are stored in an EPROM. By using our cross assembler for the LC6527, 6528, the option code can be specified interactively and stored in the EPROM. If our cross assembler is not used, specify the option code as shown below. (This is the same as the method where the cross assembler is creasted automatically.) The Type No. of the EPROM to be submitted is 2732 or 2764.
No. 4363-34/43
LC6527N/F/L, LC6528N/F/L
LC6527N/L, LC6528N/L Option Code Specifying Method
Always write '0' in the area of 0.
Note: When the 2-pin OSC mode is selected, always write '0'. No. 4363-35/43
LC6527N/F/L, LC6528N/F/L
LC6527F, LC6528F Option Code Specifying Method
Always write '0' in the area of 0.
Note: When the 2-pin OSC mode is selected, always write '0'. No. 4363-36/43
LC6527N/F/L, LC6528N/F/L
Notes for Standby Function Application
The LC6527N/F/L, 6528N/F/L provide the standby function called HALT mode to minimize the current dissipation when the program is in the wait state. The standby function is controlled by the HALT instruction, PA pin, RES pin. A peripheral circuit and program must be so designed as to provide precise control of the standby function. In most applications where the standby function is performed, voltage regulation, instantaneous break of power, and external noise are not negligible. When designing an application circuit and program, whether or not to take some measures must be considered according to the extent to which these factors are allowed. This section mainly describes power failure backup for which the standby function is mostly used. A sample application circuit where the standby function is performed precisely is shown below and notes for circuit design and program design are also given below. When using the standby function, the application circuit shown below must be used and the notes must be also fully observed. If any other method than shown in this section is applied, it is necessary to fully check the environmental conditions such as power failure and the actual operation of application equipment. 1. HALT mode release conditions The HALT mode setting, release conditions are shown in Table 1. Table 1 HALT mode setting, release conditions
HALT mode setting conditions HALT instruction Provided that PA3 is at high level. HALT mode release conditions 1 Reset (Low level is applied to RES.) 2 Low level is applied to PA3.
Note)
HALT mode release condition 2 is available only when the RC mode is used for system clock generation; and unavailable when the ceramic resonator mode is used because the OSC circuit may not operate normally.
2.
Proper cares in using standby function When using the standby function, an application circuit and program must be designed with the following in mind. (1) The supply voltage at the standby state must not be less than specified. (2) Input timing and conditions of each control signal (RES, PA 3) must be observed at the standby initiate/release state. (3) Release operation must not be overlapped at the time of execution of the HALT instruction. A sample applicastion where the standby function is used for power failure backup is shown below as a concrete method to observe these notes. A sample application circuit, its operation, and notes for program design are given below. Sample application where the standby function is used for power failure backup. Power failure backup is an application where power failure of the main power source is detected and the HALT instruction is executed to cause the standby state to be entered. The power dissipation is minimized and a backup capacitor is used to retain the contents of the internal registers for a certain period of time. After power is restored, a reset occurs automatically and the execution of the program starts at address 000H of the program counter (PC). Shown below are sample applications where the program selects or not between power-ON reset and reset after power is restored, notes, measures for instantaneous break of AC power.
No. 4363-37/43
LC6527N/F/L, LC6528N/F/L
2-1. Sample application 1 where the standby function is used for power failure backup Shown below is a sample application where the program does not select between power-ON reset and reset after power is restored. 2-1-1. Sample application circuit - (1) Fig. 2-1 shows a sample application where the standby function is used for power failure backup.
(Note) Normal input ports other than PA3 . Fig. 2-1. Sample Application - (1) where the Standby Function is Used for Power Failure Backup 2-1-2. Operating waveform in sample application circuit - (1) The operating waveform in the sample application circuit in Fig. 2-1 is shown in Fig. 2-2. The mode is roughly divided as follows: (a) Power-ON reset (b) Instantaneous break of main power source (c) Return from power failure backup
Fig. 2-2 Operating Waveform in Sample Application Circuit - (1) No. 4363-38/43
LC6527N/F/L, LC6528N/F/L
2-1-3. Operation of sample application circuit - (1) (a) At the time of power-ON reset After power rises, a reset occurs automatically and the execution of the program starts at address 000H of the program counter (PC). - Note - This sample application circuit provides an indeterminate region where no reset occurs before the operating VDD range is entered. (b) At the time of instantaneous break (i) When the PXX input voltage does not meet VIL (the PXX input level does not get lower than input threshold level VIL) and the RES input voltage only meets VIL: A reset occurs in the normal mode, providing the same operation as power-ON reset. (ii) When both of the PXX input voltage and RES input voltage do not meet VIL: The program continues running in the normal mode. (iii) When both of the PXX input voltage and RES input voltage meet VIL: When two pollings do not regard the PXX input voltage as "L" level, the HALT mode is not entered and reset occurs. When two pollings regard the PXX input voltage as "L" level, the HALT mode is entered and after power is restored a reset occurs, releasing the standby mode. (c) At the time of return from power failure backup After power is restored, a reset occurs, releasing the standby mode. 2-1-4. Notes for design of sample application circuit - (1) * V+ rise time and C2 Make the time constant (C2, R) of the reset circuit 10 times as long as the V+ rise time. (R: ON-chip resistor, 200kohms typ.) Make the V+ rise time shorter (up to 20ms). * R1 and C1 Make the R1 value as small as possible. Make the C1 value as large as possible according to the backup time calculated. (Fix the R1 value so that the C1 charging current does not exceed the power source capacity.) * R2 and R3 Make the "H"-level input voltage applied to the PXX pin equal to VDD. * R4 Fix the time constant of C2 and C4 so that C2 can discharge during the period of time from when V+ gets lower than V+TRON (TR OFF) at the time of instantaneous break until the PXX input voltage gets lower than VIL (because release by reset is not available after the HALT mode is entered by instantaneous break). * R5 and R6 Make V+ (VBE = 0.6V is obtained by R5 and R6) when the reset circuit works (Tr ON) more than (operating VDD min + VF of diode D1). Observing this note, make V+ as low as possible to provide a reset early enough after power-ON. * Backup time The normal operastion continues with a relatively high current dissipation from when power failure is detected by the PXX until the HALT instruction is executed. Fix the C1 value so that the standby supply voltage is held during backup time of set + above-mentioned time. 2-1-5. Notes for software design * Design the program so that port A3 is brought to "H" level at the standby mode. * Check a standby request by polling the input port twice. (Example)
BP1 BP1 HALT
AAA AAA
; 1st polling ; 2nd polling ; Standby
AAA:
No. 4363-39/43
LC6527N/F/L, LC6528N/F/L
2-2. Sample application 2 where the standby function is used for power failure backup Shown below is a sample application where the program selects between power-ON reset and reset after power is restored. 2-2-1. Sample application circuit - (2) (No instantaneous break in power source) Fig. 2-3 shows a sample application where the standby function is used for power failure backup.
(Note) Normal input ports other than PA 3 Fig. 2-3 Sample Application - (2) where the Standby Function is Used for Power Failure Backup 2-2-2. Operating waveform in sample application circuit - (2) The operating waveform in the sample applicatioin circuit in Fig. 2-3 is shown in Fig. 2-4. The mode is roughly divided as follows: (1) Power-ON reset (2) Return from power failure backup
Fig. 2-4 Operating Waveform in Sample Application Circuit - (2) No. 4363-40/43
LC6527N/F/L, LC6528N/F/L
2-2-3. Operating of sample application circuit - (2) (a) At the time of power-ON reset The operation and notes are the same as for sample application circuit - (1), except that after reset release PXX="L" is program-detected to decide program start after initial reset. (b) Standby initiation When one polling regrds the PXX input voltage as "L" level, the HALT mode is entered. (c) At the time of return from power failure backup After power is restored, a reset occurs, releasing the standby mode. After standby release PXX="H" is program-detected, deciding program start after power is restored. - Note - If power is restored after VDD during power failure backup gets lower than VIH on the PXX, PXX ="L" may be programdetected, deciding program start after initial reset. 2-2-4. Notes for design of sample application circuit - (2) * R2 and R3 Fix the R2 value so that R2 R1 is yielded and fix the R3 value so that IB of TR2 is limited. * R4 There is no severe restriction on the R4 value, but fix it so that C2 can discharge quickly. Other notes are the same as for sample application circuit - (1). 2-2-5. Notes for software design * Design the program so that port A3 is brought to "H" level at the standby mode. * Check a standby request by polling the input port once. (Example)
BP1 HALT
AAA
; Polling ; Standby
AAA:
No. 4363-41/43
LC6527N/F/L, LC6528N/F/L
2-3. Sample application 3 where the standby function is used for power failure backup 2-3-1. Sample application circuit - (30) (There is an instantaneous break in power source.) Fig. 2-5 shows a sample application where the standby function is used for power failure backup.
(Note) Normal input ports other than PA 3. Fig. 2-5 Sample Application - (3) where the Standby Function is Used for Power Failure Backup 2-3-2. Operating waveform in sample application circuit - (3) The operating waveform in the sample application circuit in Fig. 2-5 is shown in Fig. 2-6. The mode is roughly divided as follows: (1) Power-ON reset (2) Instantaneous break of main power source (3) Return from power failure backup
Fig. 2-6 Operating Waveform in Sample Application Circuit - (3) No. 4363-42/43
LC6527N/F/L, LC6528N/F/L
2-3-3. Operation of sample application circuit - (3) (a) At the time of power-ON reset The operation and notes are the same as for sample application circuit - (2) (b) At the time of instantaneous break (i) When the PXX input voltage does not meet VIL (the PXX input level does not get lower than input threshold level VIL) and the RES input voltage only meets VIL: A reset occurs in the normal mode. After reset release PXX ="H" is program-detected, deciding program start after instantaneous break. (ii) When both of the PXX input voltage and RES input voltage do not meet VIL: The program continues running in the normal mode. (iii) When both of the PXX input voltage and RES input voltage meet VIL: When two pollings do not regard the PXX input voltage as "L" level, the HALT mode is not entered and a reset occurs. When two pollings regard the PXX input voltage as "L" level, the HALT mode is entered and after power is restored a reset occurs, releasing the standby mode. After standby release PXX="H" is program-detected, deciding program start after instantaneous break. (c) At the time of return from power failure backup The operation and notes are the same as for sample application circuit - (2) 2-3-4. Notes for design of sample application circuit - (3) * R3 Bias resistance of TR2 * R7 and R8 Fix the R7 and R8 values so that TR3 is turned ON/OFF at approximately 1.5V of V+. Other notes are the same as for sample application circuit - (1). 2-3-5. Notes for software design Same as for sample application circuit - (1).
This catalog provides information as of September, 1998. Specifications and information herein are subject to change without notice.
PS No. 4363-43/43

▲Up To Search▲

Price & Availability of LC6527NFL

	To Download LC6527NFL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .