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Data Sheet
OXU210HP USB2.0 High-Speed Host, Peripheral and OTG Controller
Features
Highperformance,highspeedUSBdualrole(host/peripheral) controller CompatiblewiththeUniversalSerialBusSpecification,Revision2.0 forhighspeed(480Mb/s),fullspeed(12Mb/s),andlowspeed (1.5Mb/s)operations Highspeedoptimizedhostcontrollerwithtransactiontranslator forcompletebackwardcompatibilitywithfullspeedand lowspeedproducts TwohighspeedUSBports;oneportremainshostwhiletheother canbeconfiguredasperipheral,host,orOTG(dualrole) Simultaneousoperationofbothports Processorinterfaceiseither16bits(BGA)orconfigurable16or32 bits(LQFP) Fastmicroprocessoraccesscycleanddouble/multibuffering supportforUSBtransfers HostinterfacecontainssupportforcommonSoCDMAmodes includingburstingandslaverequest/acknowledgeprotocols Completehost,peripheralandOTGsoftwaresolutionsfor popularmicroprocessorsusingmanyofthemostpopular operatingsystems AdvancedpowermanagementcontrolschipclockingandPHY functionforverylowpowerconsumption IntegratedonchipVBUSvoltagecomparatorand100mAcharge pump 72KbytesofsingleportSRAMprovidesspacefordatastructures andbufferspacefortransferdata Truetransferleveloperation,withtransactionschedulingand handling(datasequencetoggle,errorretry,etc.),implementedin hardware IntegratedPLLrunsfromasingle12MHzcrystaloranexternal 12MHzclocksource
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Packaging 7x7mmBGA,84ball,RoHScompliant 14x14mmLQFP,128pin,RoHScompliant Operatingtemperaturerange:40to85C
Device Overview
TheOxfordSemiconductorOXU210HPisasinglechip,highspeedUSB hostandhighspeedUSBperipheralcontrollerwithintegrated transceivers.Itisthefourthcontrollerinthefamilyofintegrated lowcost,highperformance,OTGcontrollersthathavebeenspecifically designedforembeddedsystems. TheOXU210HPoperatesatupto480Mb/s,usingacompatible EHCIbasedcore.Italsoincludesanintegratedtransactiontranslator thatsupportsfullspeed(12Mb/s)andlowspeed(1.5Mb/s)USB peripherals. Theselectable16and32bitprocessorinterfaceiscompatiblewitha varietyofCPUs.Alarge72Kbytebufferhasalsobeenintegratedto reduceinterruptsandminimizeCPUoverhead. TheOXU210HPsupportsallUSBtransfermodes(control,interrupt, bulkandisochronous)andissupportedwithUSBdevicedriversandthe OxfordSemiconductorUSBLinkproductsuite.TheUSBLinkhost, peripheralandOTGstackshavebeenportedtoawidevarietyofreal timeoperatingsystemsincludingVxWorks(R),ThreadX(R),andNucleus(R). Inaddition,OxfordSemiconductoralsomakesavailablelowlevel controllerdriversforothernativeUSBstackssuchasthoseincludedwith Windows(R)CEandLinux(R)2.6.x.
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OXU210HP Data Sheet
Figure1showstheOXU210HPblockdiagram.
Figure 1 OXU210HP Block Diagram
Superior Performance
Large internal RAM allows for multibuffering simultaneous streams. Retries due to USB NAKs are done in hardware decreasing interrupts and lowering CPU and bus utilization. XSCI XSCO PLL/ Clock 72 KB Buffer Memory Test Control
TEST
ACK DRQ
DMA Interface
Transaction Translator Host Controller HS OTG Xcvr
Power Management Transaction Translator Host Controller Peripheral Controller OTG Controller
2 Ports
allow multiple usage models: 2 Hosts Host + Peripheral, or Host + OTG
Low Power Design
Multiple power and ADDR clock regions are available with DATA software-controlled power saving modes. PLL and oscillator can be disabled for CNTRL deep-sleep state. Clock control block INT produces the lowest of four primary clock frequencies that meet the application's operational requirements. 16/32-bit Microprocessor Interface
HS OTG Xcvr
System Configuration & Control Registers
Simultaneous Operation OTG Logic
Integrated hardware or software HNP options allow for more control of software development. Full host controller and peripheral controller implementations allow both to operate at the same time.
Sample Applications
Digitaltelevisions Homemediacenters Portablemediacenters Digitalvideocameras Digitalstillcameras Printers MP3players Externalstorageproducts SetTopBoxes(STB) PersonalVideoRecorders(PVR) PersonalDigitalAssistants(PDA) 3Gmobilephones DVDrecorders
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Development Support
TheOXU210HPproductsuiteincludestheUSBcontrolleraswellasthe protocolstacksandthedriversoftwarethatenableawidevarietyofUSB applications.Thisuniqueabilitytodeliveratotalhardwareandsoftware solutionsetsOxfordSemiconductorapartfromothersemiconductor companiesandbenefitscustomersby: Shorteningtimetomarket Reducingrisk Offeringasinglesourceforhardwareandsoftware,thereby reducingthenumberofsuppliersthecustomerhastodealwith OxfordSemiconductorisaMicrosoft(R)Windows(R)EmbeddedPartner andhasdevelopedhostandperipheralcontrollerdriversforWindows CE5.0.SimilarsoftwaresupportisalsoavailableforLinux(R)2.6.x. ForcustomersusinganRTOSsuchasVxWorks(R),ThreadX(R),Nucleus(R), OSE,LynxOS(R),andAMXTM,amongothers,OxfordSemiconductor offersitsUSBLinkTMhost,peripheralandOnTheGosoftwaresolutions. TheUSBLinkProductSuiteisamodularizedapproachtoprovidingUSB connectivityforawidevarietyofembeddedproducts.Duetoitsflexible architectureandbroadbasedsupportforUSBhost,peripheralandOTG applications,OxfordSemiconductorcantailortheUSBLinksoftware deliverablestomeeteachcustomer'sUSBrequirements. TheUSBLinksolutionsareconfigurableandcansupportsystemswith: Bigorlittleendianprocessors DMAornonDMAUSBcontrollers AwidevarietyofUSBcontrollers,includingtheOXU210HP Complextosimpleoperatingsystems OxfordSemiconductorhasovereightyearsofexperiencedeveloping embeddedUSBtechnology.ItsUSBLinksoftwarehasbeenportedto twentydifferentoperatingsystemsandawidevarietyofembedded architectures.USBLinkisshippinginmanymillionsofunits.
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OXU210HP Data Sheet
Electrical Characteristics
Symbol VPWM3, VDD3IO VDD3.3A VDD1.8 VIO VI TS
Note:
Table1toTable10detailtherequiredoperatingconditionsforthe deviceandtheDCandACelectricalcharacteristics.
Table 1 Absolute Maximum Device Ratings Parameter 3.3 V digital power supply 3.3 V analog power supply 1.8 V power supply 1.65 V to 3.3 V power supply DC input voltage Storage temperature
1
Condition
Min -0.3 -0.3 -0.3 -0.3 -0.3 -40
Max 4.0 4.0 2.16 4.0 4.0 +150
Unit V V V V V C
Permanentdevicedamagemayoccurifabsolutemaximumratingsareexceeded. Functionaloperationshouldberestrictedtothenormaloperatingconditions specifiedinthefollowingsection.Exposuretoabsolutemaximumratingconditions forextendedperiodsmayaffectdevicereliability.
Table 2 Recommended Operating Conditions Symbol VPWM3, VDD3IO VDD3.3A VDD1.8 VIO VI3.3 VIW TO Parameter 3.3 V digital power supply 3.3 V analog power supply 1.8 V power supply 1.65 - 3.3 V wide-range I/O power supply DC input voltage of 3.3 V pins DC input voltage of wide-range pins Operating temperature Condition Min 3.0 3.0 1.62 1.65 0 0 -40 Max 3.6 3.6 1.98 3.6 3.6 VIO + 0.3 +85 Unit V V V V V V C
Table 3 DC Characteristics, Full-Speed USB I/O Signals: DP_HOST, DM_HOST, DP_OTG, DM_OTG Symbol VDI VCM VOL VOH VCRS CIN Parameter Diff. input sensitivity Diff. comm. mode range Static output low Static output high Output signal crossover Input capacitance Condition |VI(DP) - VI(DM)| Min 0.2 0.8 -2.8 1.3 Max -2.5 0.3 3.6 2.0 20 Unit V V V V V pF
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Table 4 DC Characteristics, High-Speed USB I/O Signals: DP_HOST, DM_HOST, DP_OTG, DM_OTG Symbol VHSDIFF VHSCM VHSSQ VHSOI VHSOL VHSOH VCHIRPJ VCHIRPK Parameter High-speed differential input sensitivity High-speed data signaling common mode range High-speed squelch detection threshold High-speed idle output voltage (differential) High speed low level output voltage (differential) High speed high level output voltage (differential) Chirp-J output voltage (differential) Chirp-K output voltage (differential) Squelch detected No squelch detected Condition |VI(DP) - VI(DM)| Min 300 -50 -150 -10 -10 -360 700 -900 Max -500 100 -10 10 400 1100 -500 Unit mV mV mV mV mV mV mV mV mV
Table 5 DC Characteristics, Logic Signals Symbol VOL VOH Parameter Low level output voltage High level output voltage VIO = 3.3 V VIO = 2.5 V VIO = 1.8 V VIL Low level input voltage VIO = 3.3 V VIO = 2.5 V VIO = 1.8 V VIH High level input voltage VIO = 3.3 V VIO = 2.5 V VIO = 1.8 V CIN COUT CBI IIN
Note:
Condition
Min -2.4 1.85 0.75 * VIO --0.3 * VIO 2.0 0.625 * VIO 0.7 * VIO
Max 0.4 --0.8 0.25 * VIO -----
Unit V V V V V V V pF pF pF A
Input capacitance Output capacitance Bi-directional capacitance Input leakage current
1
2.2 (typical) 2.2 (typical) 2.2 (typical) No pull up or pull down -10 10
ThechargepumpsupplyVCPSUPPLYsuppliestheexternalcomponentsofthechargepump circuit.Thisisnotapinonthechip.
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OXU210HP Data Sheet
Table 6 DC Characteristics, ID Resistance Symbol RB-PLUG-ID RA-PLUG-ID Parameter Resistance to ground on Mini-B plug Resistance to ground on Mini-B plug Condition Min 100 K -Max -10 Unit
Table 7 DC Characteristics, Charge Pump Symbol CVout CIdrive Ctst Parameter Output voltage Driving current Start-up time when enabled Condition Driving current <= 100 mA VCPSUPPLY = 3.3 V Output voltage = 5 V VCPSUPPLY = 3.3 V RVout = 4.5 V (90%) Table 8 AC Characteristics, DP_HOST, DM_HOST, DP_OTG, DM_OTG Driver Characteristics (High Speed) Symbol tHSRt tHSF RDRV Parameter High speed differential rise time High speed differential fall time Driver output impedance Equivalent resistance used as internal chip Condition Min 500 500 40.5 Max --49.5 Unit ps ps 400 (typical) s Min 4.75 -Max 5.07 100 Unit V mA
Table 9 AC Characteristics, DP_HOST, DM_HOST, DP_OTG, DM_OTG Driver Characteristics (Full Speed) Symbol tFR tFF tFRFM ZDRV Parameter Rise time Fall time TR/TF matching Driver output resistance Steady state drive with external 33 series resistor CL = 50 pF CL = 50 pF Condition Min 4 4 90 3 Max 20 20 110 9 Unit ns ns %
Table 10 AC Characteristics, DP_HOST, DM_HOST, DP_OTG, DM_OTG Driver Characteristics (Low Speed) Symbol tLR tFF tFRFM Parameter Rise time Fall time TR/TF matching Condition CL = 200 - 600 pF CL = 200 - 600 pF Min 75 75 80 Max 300 300 125 Unit ns ns %
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Power Consumption
Table11givesthepowerconsumptionfiguresfortheOXU210HP.
Table 11 OXU210HP Power Consumption Mode Full-power down Power down, remote wakeup enabled (PHY PLL enabled during power down) Idle but clocking @ 120 MHz (port suspend) FS bulk in/out transfers @ OTG port, peak current (120 MHz), SPH idle FS transmit of test packet, both ports (60 MHz) HS bulk in/out transfers @ OTG port, peak current (120 MHz), SPH idle HS transmit of test packet, OTG port only (120 MHz) HS transmit of test packet, both ports (120 MHz) 3.3 V (mA) 0.06 0.66 23 33 25 61 56 91 1.8 V (mA) 0.2 0.24 56 60 35 70 59 59 Power (mW) 0.56 2.61 177 217 146 327 291 407
Theabovemeasurementsareattypicalprocesscornerandroom temperatureanddonotaccountforprocessandtemperaturevariations. Bulktransfercurrentmeasurementsaremadeatthepeakofeach transfer.Actualaveragecurrentincustomerapplicationwillbelower. Transmitoftestpacketmeasurementsaretakenintestmodeand representmaximumswitchingonthebus.
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OXU210HP Data Sheet
Pin Layout
Thedeviceissuppliedasa128pinLQFPpackageandasan84ballBGA package.Figure2showsthechiplayoutofthe128pinLQFPpackage. Figure3showsthechiplayoutofthe84ballBGApackage.
Figure 2 OXU210HP 128-Pin LQFP Package (Top View)
GPIO 0 PD_PMOS VSSA VPWM3 DEBUG3 DEBUG2 DEBUG1 DEBUG0 /OC /EXVBO /RESET ACK 1 VSS VDD1.8 VSSA VDD3.3A DRQ 0 DRQ 1 TEST VDD3IO ACK 0
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 GPIO 1 GPIO 2 GPIO 3 DEBUG 4 DEBUG 5 DEBUG 6 DEBUG 7 VIO VSS A1 A2 A3 A4 A5 A6 A7 A8 V DD1.8 VSS A9 A 10 A 11 A 12 A 13 VIO VSS A 14 A 15 A 16 /CS /WR VSS 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1
/RD
VIO
VOUT
VBUS
EXT VSSA
/INT
VSS
/PO ID
VSS
VIO
64 V DD3.3A 63 DP_OTG 62 DM_OTG 61 REF_OTG 60 VSSA 59 V DD3.3A 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2
D 24
XSCO XSCI VSS VSS V DD1.8 V DD1.8 V DD3.3A VSSA REF_HOST DM_HOST DP_HOST V DD3.3A VSSA BE 3 BE 2 BE 1 BE 0 D 23 D 22 D 21 D 20 D 19 D 18 D 17 D 16 D 15
LQBG
3
D 25
4
D 26
5
D 27
6
VIO
7
VSS
8
D 28
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
V DD1.8 VSS VSS D 29 D 30 D 31 D 10 D 11 VSS D0 D2 D3 D4 D5 D6 D7 D8 D9 D 12 D 13 D 14 VIO D1 VIO
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Table 12liststheLQFPpinallocations.
Table 12 OXU210HP 128-Pin LQFP Pin Allocations (Sheet 1 of 2) Pin No. Bits 16 Type(1) Name Description
Processor Interface (61 pins) 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 30, 31, 32, 33 2, 3, 4, 5, 8, 9, 10, 11, 34, 35, 36, 37, 38, 39, 40, 41 106, 107, 108, 109, 110, 111, 112, 113, 116, 117, 118, 119, 120, 123, 124, 125 127 1 126 83 MSBCT D0 - D15 16-bit data bus
16
MSBCT
D16 - D31
Additional 16-bits of data bus for optional 32-bit mode. In 16-bit mode, these signals have an internal pull down Address bus for direct address space of 72 Kbytes plus memory mapped registers
16
MSI
A1 - A16
1 1 1 1
MSIU MSIU MSIU MOCT
/WR /RD /CS /INT
Write strobe Read strobe Chip select Interrupt to the MCU.This pin can be software configured as a driven output or WO. WO is the default Hardware reset DMA request outputs to support two channels DMA acknowledge Byte enables Byte enables. These signals have an internal pull down. General purpose I/O Digital ground
84 90, 91 92, 93 42, 43 44, 45
1 2 2 2 2
I MOCT SI MSI MSID
/RESET DRQ1, DRQ0 ACK1, ACK0 BE0, BE1 BE2, BE3
General Purpose I/O (4 pins) 96, 97, 98, 99 7, 13, 28, 29, 55, 56, 79, 82, 95, 105, 115, 122, 128 46, 51, 60, 65, 68, 73 18, 53, 54, 81, 114 47, 52, 59, 64, 72 6, 12, 27, 80, 94, 104, 121 74 4 13 BC GPIO0 - GPIO3 VSS Power and Ground (38 pins)
6 5 5 7 1
VSSA VDD1.8 VDD3.3A VIO VDD3IO
Analog ground 1.8 V core power. VREGOUT may be used for the supplies Analog +3.3 V power Wide-range I/O voltage. If using +1.8 V, VREGOUT may be used for the supplies Digital +3.3 V power
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OXU210HP Data Sheet
Table 12 OXU210HP 128-Pin LQFP Pin Allocations (Sheet 2 of 2) Pin 67 No. Bits 1 Type(1) VPWM3 Name Description Analog 3.3 V power for the charge pump Pulse Width Modulator (PWM) Data lines for host port. If not used, these pins should be left floating Data lines for OTG port. If not used, these pins should be left floating VBUS input used by the voltage comparators of the OTG port for connection. This pin should be left floating in a host-only application Turn on/off the external VBUS (5 V) for OTG operation (1:VBUS off, 0: VBUS on) when using the external VBUS source Over current condition indicator for powered host ports Connected to the ID pin of the mini-AB connector for OTG applications. With the help of an internal pull-up resistor, this pin determines the chip's responsibility in an OTG application (0: A-device, 1:B-device) Turn on/off gang power for all host ports Input. A 12 MHz passive crystal should be connected across the two pins (XSCI and XSCO). Optionally, a 12 MHz oscillator can be sourced through XSCI while keeping XSCO unconnected Output Internal charge pump output for P-MOSFET (optional switch on the VOUT) Internal charge pump output for N-MOSFET Internal charge pump output voltage feedback pin Debug outputs
USB Interface (9 pins) 48, 49 62, 63 71 2 2 1 B B 5I DP_HOST, DM_HOST DP_OTG, DM_OTG VBUS
75
1
P5O
/EXVBO
76 77
1 1
P5IU P5IU
/OC ID
78 57
1 1
P5OT I
/PO XSCI
Clock Interface (2 pins)
58 69 66 70 Test (9 pins) 85, 86, 87, 88, 100, 101, 102, 103 89
1 1 1 1 8
O O O I OC
XSCO PD_PMOS EXT VOUT DEBUG0 - DEBUG7
Internal VBUS Charge Pump (3 pins)
1
I
TEST
Factory test mode. This pin should be grounded or left floating (has an internal pull-down) for normal operation Connect external reference resistor (12 KW+/ 1%) to VSSA. One per port
Miscellaneous (2 pins) 50 61 1 1 B B REF_HOST REF_OTG
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NotetoTable12: 1
Oxford Semiconductor, Inc. Typekey:formatis[(L)(W_)X(Y)(_Z(T))]wherethefollowingconventionsapply:
L--Logic Level P
(2)
W--Tolerance 5 5V 3.3 V I O
X--Type Input Output U D
Y--Pull Pull up Pull down
Z--Drive C
(4)
T--Tristate T Tristate Normal
OD 3.3 CMOS Multi-voltage: 3.3 V CMOS 2.5 V CMOS 1.8 V CMOS Schmitt Trigger
M(3)
S
B
2 3 4
Bidirectional
None
ProgramtoODor3.3VCMOSviatheASOregister(0x0068). Programto3.3,2.5,or1.8VbysettingtheVIOvoltagelevel. Programto2mA,4mA,6mA,or8mAviatheI/OControlregister(0x006C).
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OXU210HP Data Sheet
Figure 3 OXU210HP 84-Ball BGA Package (Top View)
1 A B C D E F G H J K
/CS
2
A 15
3
A 13
4
A 11
5
A 10
6
A7
7
A6
8
A4
9
A2
10
ACK0
/RD
/WR
A 14
A 12
A9
A8
A5
A3
GPIO0
DRQ0
D0
A16
VSS
VIO
VSS
VDD1.8
VSS
VDD1.8
A1
TEST
D1
D2
VSS
VIO
/INT
/RESET
D3
D4
VDD1.8
VSS
ID
/PO
D6
D5
D7
OXU210HP-TBBG
VSSA
/EXVBO
/OC
D8
D9
VSS
VDD3.3A
VBUS
VOUT
D 11
D 10
VSSA
VDD3.3A
VDD3.3A
VDD3.3A
VSSA
VSSA
VPWM3
PD_PMOS
D 13
D 12
BE 1
BE 0
VSSA
VDD3IO
VIO
VDD3.3A
VSSA
EXT
D 15
D 14
DM_HOST
DP_HOST
REF_HOST
XSCI
XSCO
DM_OTG
DP_OTG
REF_OTG
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Table 13liststheBGApinallocations.
Table 13 OXU210HP 84-Ball BGA Pin Allocations (Sheet 1 of 2) Pin No. Bits Type(1) Name Description
Processor Interface (41 pins) C1, D1, D2, E1, E2, 16 F2, F1, F3, G1, G2, H2, H1, J2, J1, K2, K1 C9, A9, B8, A8, B7, A7, A6, B6, B5, A5, A4, B4, A3, B3, A2, C2 B2 B1 A1 D9 D10 B10 A10 J4, J3 B9 C3, C5, C7, D3, E8, G3 C6, C8, E3 G8, H4, H5, H6, J8 C4, D8, J7 J6 H9 USB Interface (9 pins) K4, K3 K8, K9 G9 2 2 1 B B 5I DP_HOST, DM_HOST Data lines for host port. If not used, these pins should be left floating DM_OTG, DP_OTG VBUS Data lines for OTG port. If not used, these pins should be left floating. VBUS input used by the voltage comparators of the OTG port for connection. This pin should be left floating in a host only application 16 MSBCT D0 - D15 16-bit data bus
MSI
A1 - A16
Address bus for direct address space of 72 Kbytes plus memory mapped registers
1 1 1 1 1 1 1 2 1 6
MSIU MSIU MSIU MOCT I MOT SI MSI B
/WR /RD /CS /INT /RESET DRQ0 ACK0 BE0, BE1 GPIO0 VSS VSSA VDD1.8 VDD3.3A VIO VDD3IO VPWM3
Write strobe Read strobe Chip select Interrupt to the MCU.This pin can be software configured as a driven output or WO. WO is the default Hardware reset DMA request outputs to support two channels DMA acknowledge Byte enables General purpose I/O Digital ground Analog ground 1.8 V core power. VREGOUT may be used for the supplies Analog +3.3 V power Wide-range I/O voltage. If using +1.8 V, VREGOUT may be used for the supplies Digital +3.3 V power Analog 3.3 V power for the charge pump Pulse Width Modulator (PWM)
General Purpose I/O (1 pin) Power and Ground (25 pins)
F8, H3, H7, H8, J5, J9 6 3 5 3 1 1
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OXU210HP Data Sheet
Table 13 OXU210HP 84-Ball BGA Pin Allocations (Sheet 2 of 2) Pin F9 No. Bits 1 Type(1) P5O /EXVBO Name Description Turn on/off the external VBUS (5 V) for OTG operation (1:VBUS off, 0:VBUS on) when using the external charge pump Over current condition indicator for powered host ports Connected to the ID pin of the mini-AB connector for OTG applications. With the help of an internal pull-up resistor, this pin determines the chip's responsibility in an OTG application (0: A-peripheral, 1:B-peripheral) Turn on/off the gang power for all host ports Input. A 12 MHz passive crystal should be connected across the two pins (XSCI and XSCO). Optionally, a 12 MHz oscillator can be connected to XSCI while keeping XSCO unconnected Output Internal charge pump output for P-MOSFET (optional switch on the VOUT) Internal charge pump output for N-MOSFET Internal charge pump output voltage feedback pin Factory test mode. This pin should be grounded or left floating (has an internal pull-down) for normal operation Connect external reference resistor (12 K +/- 1%) to VSSA. One per port
F10 E9
1 1
P5IU P5IU
/OC ID
E10 Clock Interface (2 pins) K6
1 1
P5O I
/PO XSCI
K7 H10 J10 G10 Test (1 pin) C10 Miscellaneous (2 pins) K5 K10
Note to Table 13:
1 1 1 1 1
O O O I SIUC
XSCO PD_PMOS EXT VOUT TEST
Internal VBUS Charge Pump (3 pins)
1 1
1
B B
REF_HOST REF_OTG
Typekey:formatis[(L)(W_)X(Y)(_Z(T))]wherethefollowingconventionsapply:
L--Logic Level P(2) M(3) OD 3.3 CMOS Multi-voltage: 3.3 V CMOS 2.5 V CMOS 1.8 V CMOS Schmitt Trigger
W--Tolerance 5 5V 3.3 V I O
X--Type Input Output U D
Y--Pull Pull up Pull down
Z--Drive C(4)
T--Tristate T Tristate Normal
S
B
2 3 4
Bidirectional
None
ProgramtoODor3.3VCMOSviatheASOregister(0x0068). Programto3.3,2.5,or1.8VbysettingtheVIOvoltagelevel. Programto2mA,4mA,6mA,or8mAviatheI/OControlregister(0x006C).
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Package Layout
Figure 4 128-Pin LQFP
Figure4showsthepackagelayoutforthe128pinLQFPpackage. Figure5onpage17showsthelayoutforthe84ballTFBGA.
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OXU210HP Data Sheet
Figure 5 84-Ball TFBGA Package
Ordering Information
ThefollowingconventionsareusedtoidentifyOxfordSemiconductor products:
OXU210HP - LQBG Green (RoHS compliant) Revision Package Type: LQ Part Number 128-Pin LQFP
OXU210HP - TBBG Green (RoHS compliant) Revision Package Type: TB Part Number 84-Ball TF-BGA
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Contacting Oxford Semiconductor Revision Information
SeetheOxfordSemiconductorwebsite(http://www.oxsemi.com)for furtherdetailaboutOxfordSemiconductordevices,oremail sales@oxsemi.com.
Table14documentstherevisionsofthisdatasheet.
Table 14 Revision Information Revision Jun 06 Dec 06 First publication Miscellaneous editorial changes Modification
USBLinkisatrademarkofOxfordSemiconductor,Inc. VxWorksisaregisteredtrademarkofWindRiverSystems. ThreadXisaregisteredtrademarkofExpressLogic,Inc. NucleusisaregisteredtrademarkofMentorGraphicsCorporation. WindowsisatrademarkofMicrosoft,Inc.,registeredintheUSandothercountries. LynxOSisaregisteredtrademarkofLynuxWorks,Inc. AMXisatrademarkofKADAKProductsLTD. LinuxisaregisteredtrademarkofLinusTorvalds. Allothertrademarksarethepropertyoftheirrespectiveowners.
(c) Oxford Semiconductor, Inc. 2006 The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Oxford Semiconductor, Inc. Oxford Semiconductor, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in this document.
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