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PRISM1KIT-EVAL DSSS PC Card Wireless LAN Description
Application Note August 1999
AN9624.6
Authors: Carl Andren, Mike Paljug, and Doug Schultz (Integrated RF Solutions, Inc.)
Introduction
The PRISM1KIT-EVAL wireless LAN PC card is a complete wireless high speed modem utilizing the Intersil PRISMTM Direct Sequence Spread Spectrum (DSSS) wireless transceiver chip set. The card is packaged in an open frame PCMCIA Type II extended coverset for evaluation access and a connector output for use in the laboratory. Evaluation kits include two cards, Microsoft(R) Windows(R) 95 software and documentation to get your WLAN evaluation started quickly. The PRISM1KIT-EVAL is not FCC approved as an intentional radiator and is intended for use with cabled connections only (30dB antenna port to antenna port attenuation recommended). An FCC experimental license is required while transmitting over the air with unapproved equipment. Please refer to the WLANKITPR1-KIT for an FCC-approved radio kit for wireless LAN evaluations. This application note details the RF and analog design of these cards. The physical layer (PHY) sections of these PC Cards are described in detail. The medium access control (MAC) section of the PC Cards will be described in detail in the pending AMD application note titled "Wireless LAN DSSS PC Card Reference Design" [1].
TM
* Operating Voltage. . . . . . . . . . . . . . . . . . 4.5VDC - 5.5VDC * Standby Current . . . . . . .190mA at 1s Recovery (Note 4) 70mA at 25s Recovery (Note 4) 60mA at 2ms Recovery (Note 4) 30mA at 15ms Recovery (Note 4) * Operating Temperature Range . . . . . 0oC to 70oC (Note 2) * Storage Temperature Range . . . . . . . . . . -55oC to 125oC * Mechanical . . . . . . . . . . . . . . . . . . . . . Type II PCMCIA Card, with Antenna Extension * Antenna Interface . . . . . . . . . . . . . . . . . . . . . . . SMA, 50
Receive Specifications
* Sensitivity . . . . .-91dBm (Typ), 1Mbps, 8E-2 FER (Note 3) -88dBm (Typ), 2Mbps, 8E-2 FER (Note 3) * Input Third Order Intercept Point . . . . . . . . . -20dBm (Typ) * Image Rejection . . . . . . . . . . . . . . . . . . . . . . . . 65dB (Typ) * IF Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . 80dB (Typ) * Adjacent Channel Rejection . . . . . . . . . . . . . . . 63dB (Typ) at 25MHz Offset * Supply Current . . . 287mA (Typ), 2Mbps, 100% Duty Cycle
Figure 1 shows a block diagram of the reference radio design. This radio has been designed to conform to the draft IEEE 802.11 specification but does not include the antenna diversity selection. The specifications of the PC Card Wireless LAN are as follows:
Transmit Specifications
* Output Power . . . . . . . . . . . . . . . . . . . . . . +17.5dBm (Typ) * Transmit Spectral Mask. . . .-32dBc (Typ) at First Side-Lobe * Supply Current . . . . 488mA (Typ), 2Mbps, 100% Duty Cycle
Ordering Information
PART NUMBER PRISM1KIT-EVAL DESCRIPTION Evaluation Kit CARDS PER KIT 2
NOTES: 1. Using M/A-COM AND-C-107 omnidirectional antenna. 2. AM79C930 limited to 0oC to 70oC. 3. FER = Frame Error Rate or Packet Error Rate. 4. Recovery times do not include MAC recovery.
General Specifications
* Targeted Standard . . . . . . . . . . . . . . . IEEE 802.11 (Draft) * Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . .1Mbps DBPSK 2Mbps DQPSK * Range . . . . . . . . . . . . . . . . . . . 400ft Indoor (Typ) (Note 1) 3700ft Outdoor (Typ) (Note 1) * Frequency Range . . . . . . . . . . . . . .2412MHz to 2484MHz * Step Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1MHz * IF Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280MHz * IF Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17MHz * RX/TX Switching Speed . . . . . . . . . . . . . . . . . . . 2s (Typ)
Receive Processing
Referring to the block diagram in Figure 1, the schematic on our web site [2], and the bill of materials in Appendix A, a single antenna is used. Up to two antennas are supported in the HFA3824A [3] Baseband Processor to implement diversity, countering the adverse effects of multipath fading. As space is at a premium in a PC Card environment, only one antenna is used. In an actual system implementation, if one can achieve diversity in at least one end of a link, such as at the access point where it is possible to achieve physical separation between diversity antennas, multipath performance will be improved.
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http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 PRISM and PRISM logo are trademarks of Intersil Corporation. Microsoft(R) and Windows(R) are registered trademarks of Microsoft Corporation.
TX/RX SELECT FL6 FL3 LNA HFA3424 U7
LC FILTER
FILTER CUTOFF SELECT
FL1
HFA3724 Q MODEM QUADRATURE DEMOD
RSSI
ADC
CCA
128K FLASH DEMOD TX/RCV DATA IO
32K SRAM
2
RXI
I ADC DESPREAD Q ADC
RXQ HFA3624 RF/IF CONVERTER LIMITING IF /RSSI I/Q LO 5TH ORDER BUTTERWORTH LOW PASS FILTERS
HFA3824A BASEBAND PROCESSOR TXI MOD/ ENCODE
DATA AM79C930 PCnetTM MOBILE WIRELESS LAN MAC
Application Note 9624
HFA3925 RF POWER AMP AND TX/RX SWITCH
FL4
U5 HFA3424 BUFFER FL2 TXQ QUADRATURE MODULATOR
VCO
SPREAD
CONTROL TEST I/O
CTRL
TO HOST COMPUTER
VCO
CLK
OSC OSC
22MHz HFA3524A DUAL SYNTHESIZER
22MHz
FIGURE 1. PRISM PC CARD BLOCK DIAGRAM
PCnetTM is a trademark of Advanced Micro Devices, Inc.
Application Note 9624
From the antenna, the received input is applied to FL3 and FL6, a Toko TDF2A-2450T-10 two pole dielectric bandpass filters, which are used to provide image rejection for the receiver. The IF frequency is 280MHz, and low-side injection is used, thereby placing the received image 560MHz below the tuned channel. FL3 and FL6 also provide protection for the RF front-end from out of band interfering signals. The T/R switch is integrated in the HFA3925 [4] RF Power Amplifier (RFPA). The HFA3925 RFPA operates from the unregulated 5V PC Card supply. Following the T/R switch, the HFA3424 [5] Low Noise Amplifier (LNA) is used to set the receiver noise figure. The HFA3424 LNA operates from a regulated 3.5V supply. A logic-level PMOS switch, RF1K49093 [9], is used to control the drain supply voltage to the HFA3424 LNA, and implement a power down mode when transmitting. A trade-off between noise figure and input intercept point exists in any receiver, to balance these conflicting requirements in the PRISM radio, an attenuator follows the HFA3424 LNA, and it may be mounted. To improve input intercept point, this attenuation may be increased. The cascaded front-end noise figure, input intercept point, and gain distribution analysis are shown in Table 1. Next, the signal enters the HFA3624 [6] RF/IF Converter LNA section, which aids in setting receiver NF. FL1 is used to suppress image noise generated in both the HFA3424 LNA and the HFA3624 LNA, and is a Murata LFJ3003B2442B084 two pole monolithic LC bandpass filter. Only modest attenuation at the image frequency is required. The insertion loss is not critical, since at this point in the receiver, component loss or NF is offset by the preceding gain stages. All sections of the HFA3624 RF/IF Converter operate from a regulated 3.5V supply. Down-conversion from the 2.4GHz - 2.5GHz band is performed in the HFA3624 RF/IF Converter mixer section. As previously mentioned, the IF center frequency is 280MHz, and low-side local oscillator (LO) injection is used. A discrete LC matching network is used at the mixer output to differentially combine the IF outputs, as well as match impedance to a 50 environment. A trimmer capacitor is used as part of the narrow-band matching network. An alternative, broadband matching network is described in the HFA3624 RF/IF Converter application note, and does not require any tunable elements. A direct impedance match to the IF filter, U7 could be implemented if desired. The 50 environment was chosen to allow ease in measurement of portions of the radio with external test equipment. An analysis of the mixer spurious responses is shown in Appendix B. There are no crossing spurious responses, therefore only tuned responses are shown. The IF receive filter, U7, is a Toyocom TQS-432 SAW bandpass filter. The center frequency is 280MHz, the 3dB bandwidth is 17MHz, and the differential group delay is less than 100ns. Insertion loss is typically 6dB, making it ideal for single-conversion systems. The impedance of the SAW is 270, in parallel with 5pF, and a series 33nH inductor is used to match the filter input to 50. The SAW output is matched directly to the IF input of the HFA3724 Quadrature IF Modulator/Demodulator, using a shunt 33nH inductor and 261 resistor. This presents a 250 source impedance to the limiter input, thereby optimizing the limiter's NF. Measured performance of the SAW filter is shown in Appendix C. In the receive mode, the HFA3724 Quadrature IF Modulator/Demodulator provides two limiting amplifiers, a quadrature baseband demodulator, and two baseband low pass filters. All sections of the HFA3724 operate from a regulated 3.5V supply. The first limiting amplifier establishes the NF of the IF strip at approximately 7dB. A discrete one pole LC differential filter is placed between the two limiters to restrict the noise bandwidth of the first limiter. As both limiters exhibit a broadband response, with over 400MHz bandwidth, a noise bandwidth reduction filter is appropriate to ensure that the second limiter is fully limiting on the frontend noise within the signal bandwidth, as opposed to the broadband noise generated by the first limiter. This filter has a center frequency of 280MHz, and a 3dB bandwidth of 50MHz. It consists of a fixed 10nH inductor and a fixed 20pF capacitor, as described in the HFA3724 data sheet.
TABLE 1. PRISM CASCADED FRONT-END ANALYSIS STAGE FL6 RF Filter FL3 RF Filter HFA3925 T/R Switch HFA3424 LNA HFA3624 LNA FL1 RF Filter HFA3624 Mixer U7 IF Filter HFA3724 [7] IF Strip Cascaded Gain = 13.4dB G -2.0 -2.0 -1.2 13.0 15.6 -3.0 3.0 -10.0 0.0 Cascaded NF = 7.7dB GC -2.0 -4.0 -5.2 7.8 23.4 20.4 23.4 13.4 13.4 F 2.0 2.0 1.2 2.0 3.8 3.0 12.0 10.0 7.0 FC 2.0 4.0 5.2 7.2 7.4 7.4 7.5 7.5 7.7 IP30 100.0 100.0 34.0 11.1 15.0 100.0 4.0 100.0 100.0 IP30C 100.0 95.9 34.0 11.0 14.7 11.7 3.6 -6.4 -6.4 IP3IC 102.0 99.9 39.2 3.3 -8.7 -8.7 -19.8 -19.8 -19.8
Cascaded Input IP3 = -19.8dBm
NOTE: G (individual stage gain, dB), GC (cumulative gain, dB), F (NF, dB), FC (cumulative NF, dB), IP3O (individual stage output IP3, dBm), IP3OC (cumulative output IP3, dBm), IP3IC (cumulative input IP3, dBm).
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Application Note 9624
The gain distribution/limiter noise analysis is shown in Appendix F. If the alternative HFA3624 broadband matching network is used, the HFA3624 mixer conversion gain will be higher, which will help ensure that the second limiter is fully limited on front-end noise. At the output of the limiters, a 200mVP-P differential signal level is maintained under all input conditions. This limited signal is then mixed in quadrature to baseband in the HFA3724 Quadrature IF Modulator/Demodulator. The LO needed for the quadrature mixing is applied at twice the IF frequency, or 560MHz. A divide by two circuit then provides an accurate quadrature LO for the mixers. The baseband outputs of the quadrature mixers are AC coupled off-chip to the integrated fifth order Butterworth filters. The output levels of the low pass filters are nominally 500mVP-P single-ended, and are intended to be AC coupled to the HFA3824A Baseband Processor. The AC coupling time constant is approximately 25 times longer than the symbol period, and is implemented with 0.01F series capacitors. These coupling capacitors must be taken into account, however, when estimating the time it takes to power up or awaken from sleep mode. At the input to the HFA3824A Baseband Processor, the quadrature signals are analog to digital converted in wideband 3 bit converters. The sample rate is 22MSPS, which results in two samples per chip. A 22MHz Fox F4106 crystal oscillator is used to provide the main clock for the HFA3824A. The signals are spread spectrum with no DC term, so it is feasible to AC couple the signals to the ADCs and avoid DC bias offsets. The signal at this point has been limited to a constant IF amplitude and then passed through two separate mixer and low pass filter paths. The component variations in these two paths can introduce offsets in amplitude and phase and can also use up some of the headroom in the ADCs. The maximum amplitude variation is 2dB and the maximum phase balance variation is 4 degrees. Since the signal is limited, the IF signals will have low peak to average ratios even with noise as an input. The I and Q signals will have sinusoidal properties with PSK modulation imposed. It is their combined vector magnitude that is limited, not their individual amplitudes. To optimize the demodulator's performance, the ADCs are operated at the point where they are at full scale on either I or Q one third of the time. To maintain this operating point in the face of component variations, there is an optional active adjustment of the ADC reference voltage by feedback. This avoids the necessity of allowing extra headroom for the variation. The adjustment circuit is very slow and averages the energy from the two channels over both packet and noise conditions. The HFA3824A Baseband Processor correlates the PN spreading to remove it and to uncover the differential BPSK or QPSK data. The processor initially uses differential detection to identify and lock onto the signal. It then makes measurements of the carrier and symbol timing phase and frequency and uses these to initialize tracking loops for fast acquisition. Once demodulating and tracking, the processor uses coherent demodulation for best performance. Since this radio uses a spread spectrum signal with 10.4dB of processing gain (10 log 11), the signal to noise ratio (SNR) in the chip rate bandwidth is approximately 0dB when the demodulator is at the desired bit error rate in BPSK. The radio operates with about 2.5dB of implementation loss relative to theoretical performance and achieves a sensitivity of -91dBm in the BPSK mode of operation. The HFA3824A Baseband Processor provides differential decoding and descrambling of the data to prepare it for the Media Access Controller (MAC). The MAC is an AMD AM79C930 PCnet - Mobile controller. All packet signals have a preamble followed by a header containing a start frame delimiter (SFD), other signal related data and a cyclic redundancy check (CRC). The MAC processes the header data to locate the SFD, determine the mode and length of the incoming message and to check the CRC. The MAC then processes the packet data and sends it on through the PC Card interface to the host computer. The MAC checks the packet data CRC to determine the data purity. If corrupted data is received, a retransmission is requested by the MAC which handles the physical layer link protocols.
Transmit Processing
Data from the host computer is sent to the MAC via the PC Card interface. Prior to any communications, however, the MAC sends a Request to Send (RTS) packet to the other end of the link and receives a Clear to Send (CTS) packet. The MAC then formats the payload data packet (MPDU) by appending it to a preamble and header and sends it on to the HFA3824A Baseband Processor which clocks it in. The HFA3824A Baseband Processor scrambles the packet and differentially encodes it before applying the spread spectrum modulation. The data can be either DBPSK or DQPSK modulated at 1MSPS and is a baseband quadrature signal with I and Q components. The BPSK spreading is an 11 chip Barker sequence that is clocked at 11MHz and is modulated with the I and Q data components. These are then output to the HFA3724 as CMOS logic signals. Following the RTS/CTS/MPDU is an acknowledge (ACK) packet by the receiving side of the link. Transmit quadrature single-bit digital inputs are applied to the HFA3724 Quadrature IF Modulator/Demodulator from the HFA3824A Baseband Processor. These inputs are attenuated by 1/7 and DC coupled to the fifth order Butterworth low pass filters, which are used to provide shaping of the phase shift keyed (PSK) signal. The required transmit spectral mask, at the antenna, is -30dBc at the first side-lobe relative to the mainlobe. An unfiltered PSK waveform would have the first side-lobe suppressed only -13dBc. The fifth-order filters are tuned to an approximate 7.7MHz cutoff, using a 909 fixed tuning resistor external to the HFA3724.
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Application Note 9624
In the PC Card wireless LAN, the goal is to control the regrowth of the sidelobes, with the HFA3925 RFPA dominating the regrowth. This will result in maximum transmitted power available. To achieve this goal, once the PSK waveform is filtered at baseband, all remaining transmit elements are operated at a 6dB back-off from compression, except for the HFA3925 RFPA, which is operated at less back-off. The low pass filters provide initial shaping of the PSK waveform. Final shaping is provided by a transmit IF filter, U5, a Toyocom TQS-432 SAW bandpass filter. The low pass filter outputs are off-chip AC coupled to the quadrature upconverter in the HFA3724. As in the receive mode, the baseband AC coupling time constant is approximately 25 times longer than the symbol period, and is implemented with 0.01F series capacitors. The same twice IF frequency LO used previously is also used in this up-conversion. The IF output of the HFA3724 is reactively matched to U5, with a 250 resistive load presented to the HFA3724. A shunt 33nH inductor, in parallel with a 316 resistor, is used to provide this match, negate the effects of board and component capacitance, and provide a DC return to VCC to prevent saturation in the IF output stage of the HFA3724. The output of U5 is terminated in a 200 potentiometer that is used for transmit gain control. A shunt 27nH inductor is used to negate the effects of parasitic board and component shunt capacitance, as well as match the SAW output to the potentiometer. This potentiometer has it's center wiper connected to the HFA3624 RF/IF Converter transmit IF input, which has an input resistance of approximately 3k. By varying the potentiometer, the gain of the transmit chain is controlled, allowing for precise control of the signal back-off at the HFA3925 RFPA. Therefore, this potentiometer is adjusted to achieve the desired compromise between transmit output power and the mainlobe to sidelobe ratio of the output PSK waveform, typically -32dBc to -35dBc, at an output power of +17.5dBm. Upconversion to the 2.4GHz - 2.5GHz band is performed in the HFA3624 RF/IF Converter transmit mixer. The mixer output is filtered with FL2, a Murata LFJ30-03B2442B084 two pole monolithic LC bandpass filter. This filter suppresses the LO feedthrough from the mixer, and selects the upper sideband. The transmit buffer in the HFA3624 RF/IF Converter amplifies the selected sideband, easing the requirement for HFA3925 RFPA gain. FL4, a Toko TDF2A-2450T-10 two pole dielectric bandpass filter, is used to further suppress both the transmit LO leakage and the undesired sideband. The HFA3925 RFPA amplifies the transmit signal to a level of approximately +21.5dBm, as measured at the T/R switch output. This represents a back-off from 1dB compression of approximately 3dB. Transmit side-lobe performance is approximately -32dBc to -35dBc with this level of back-off. Allowing for approximately 4dB of loss between the T/R switch output and the antenna connector results in a final output power of +17.5dBm. The HFA3925 RFPA is the only physical layer component that operates directly from the 5V PC Card supply. To supply the needed negative gate bias to the HFA3925 RFPA, a ICL7660SIBA [8] charge pump is used. A second potentiometer is used to adjust the drain current on the third stage of the HFA3925 to a quiescent operating current of 90mA, as measured through a one ohm sense resistor. A base-emitter junction is used as part of the gate bias network to provide temperature compensation, and all three gates are driven from one source to reduce the impact of process variation on pinch-off voltage. The nominal quiescent drain bias currents are 20mA for stage one, 53mA for stage two, and 90mA for stage three. A second logic-level PMOS switch, RF1K49093, is used to control the drain supply voltage to the HFA3925 RFPA, and implement a power down mode when receiving. A 2N2222 NPN transistor is used to level shift the 3.5V logic level from the AM79C30 MAC to drive the 5V PMOS switch gates, as well as the 5V HFA3925 RFPA T/R control gate. The T/R VDD pin is connected to the three PA VDD pins, and is powered down in the receive mode by the PMOS switch. In this manner the T/R control pin transfer characteristic is less dependent on its voltage, with the receive state being valid for T/R control voltages as low as 3V. If the T/R VDD pin was connected to a supply in both transmit and receive modes, the T/R control voltage would have to be within a few hundred millivolts of the supply to obtain similar performance. Following the T/R switch, FL3 and FL6 are reused in the transmit mode to attenuate harmonics generated in the HFA3925 RFPA, as well as provide additional suppression of the LO. As the loss of FL3 and FL6 is approximately 4dB, the amount of transmit power available at the antenna is approximately +17.5dBm. As the transmit chain is operated linearly, any gain flatness from the HFA3624 and HFA3925, as well as from FL2, FL3, FL4, and FL6, will result in the transmit output power varying across the operating channels. To reduce the amount of variability, three 1pF capacitors are used as coupling elements to provide a form of simple equalization. Care must be exercised to ensure that the filter rejection is still acceptable in meeting the requirements of FCC 15.247. If desired, more complicated equalization could be used to maintain an improved 50 environment for all passband frequencies. Using the simple equalization, the transmit output varies approximately 2.5dB across the band.
Synthesizer Section
The dual frequency synthesizer section uses the HFA3524A [10] Synthesizer and two voltage controlled oscillators to provide a tunable 2132MHz to 2204MHz first LO, and a fixed 560MHz second LO. Both feedback loops
5
Application Note 9624
use a 1MHz reference frequency that is derived from a second 22MHz Fox F4106 crystal oscillator. Two separate crystal oscillators were used for the HFA3824A and HFA3524A to maintain a high quality, low spurious reference for the synthesizer. Sharing a common 22MHz oscillator is possible if care is taken to isolate the HFA3824A from the HFA3524A. Both feedback loops are third order and were designed to have loop bandwidths of 10kHz, and phase margins of 50 degrees. The feedback loop analysis is included for both loops in Appendix D. Measured phase noise performance and calculated RMS phase jitter is included in Appendix E. All components in the synthesizer section operate from a regulated 3.5V supply. The tunable 2132MHz to 2204MHz first LO oscillator is a MotorolaTM KXN1332A VCO. To ensure operation at low tuning voltages, a start-up circuit was added to force the tuning voltage from the HFA3524A Synthesizer RF charge pump to a high state for a short period (~1ms) following HFA3524A programming. A 2N2907 PNP transistor was used to implement this function, and the AM79C930 MAC device provides the control signal. The output level of the first LO to the HFA3624 RF/IF Converter is attenuated to approximately -3dBm. An active buffer using an additional HFA3424 is used to provide additional isolation between the VCO and the HFA3624 LO input. The fixed 560MHz second LO oscillator is a discrete design, using a Phillips BFR505 transistor and a Siemens BBY51 varactor, as described in the HFA3524A Synthesizer evaluation board documentation. The output level of the second LO to the HFA3724 Quadrature IF Modulator/Demodulator is attenuated to approximately -6dBm and a three pole low pass filter is included to preserve the duty cycle of the output. High even order components in the second LO can result in offsets from a 50% duty cycle, and will degrade the quadrature phase accuracy of the HFA3724. A transconductance network is used at the HFA3724 LO input to convert the second LO voltage into a current, as recommended in the HFA3724 data sheet. As the HFA3524A Synthesizer auxiliary IF input covers the 560MHz range, the internal divide-by-two LO buffer output of the HFA3724 is disabled, as recommended in the HFA3724 data sheet. The only components operating directly from the 5V supply are the HFA3925 RFPA, in order to maximize RF output power, and the PC Card interface sections of the AM79C930 MAC controller. A total of three regulators, 3.5V Toko TK11235MTL, are used in the PC Card wireless LAN. One regulator supplies voltage to the HFA3824A Baseband Processor and portions of the AM79C930, as well as the HFA3424 LNA and HFA3624 RF/IF Converter. A second regulator supplies voltage to the synthesizer. The third regulator supplies voltage to the HFA3724 Quadrature IF Modulator/Demodulator.
PCB Layout Guidelines
Although the actual PCB layout is proprietary, some of the techniques utilized are worthy of discussion [11]. As there are many RF, IF, analog, and digital circuits in close proximity, isolation is of prime concern. All RF and IF circuits utilize coplanar waveguide with ground transmission line techniques to allow for easy integration of varied line widths and component pin widths, and to provide a low dispersion, high isolation environment. A Radio Schematic is available on the internet at http://www.intersil.com/prism/lanref.htm. The outside two planes of each side of the PCB are dedicated to RF and IF signal processing, and form two pairs of coplanar waveguide with ground circuits. As the two sides of the PCB contain circuitry that must be isolated from each other, blind via techniques are used, and the only places that the two sides share common ground or signal connections are when signals are passed between them - mainly when LO1 and LO2 need to pass from the synthesizer side to the RF/IF transceiver side. In general, the RF and IF circuit layouts need to be as short and direct as possible to avoid costly shielding. This is especially critical in the receive IF stages where spurious signal coupling can easily occur, resulting in poor sensitivity or high packet error rates.
Regulator Section
Linear voltage regulators are used to provide filtering and isolation from the 5V PC Card input supply. An additional advantage of using voltage regulators is a savings in overall supply current, as all of the components that are regulated consume less current at a 3.5V operating point, as opposed to a 5V operating point. The 3.5V operating point was chosen specifically to support the AM79C930 MAC controller. At the time of publication 3.5V was the lowest nominal operating voltage approved by AMD for 40MHz AM79C930 operation.
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MotorolaTM is a trademark of Motorola, Inc.
Appendix A Reference Radio Bill Of Materials
TABLE 2. REFERENCE RADIO BILL OF MATERIALS (Rev. A1, 3-26-98) LINE ITEM 1 PART #/CUST. # 00000003206C VENDOR VENDOR P/N COMMODITY Capacitor TYPE Ceramic MECH. DES. MOIST. SMT0603 REFERENCE DESCRIPTION C21, C26, C27, C34, C36, C37, C38, C40, C41, C42, C45, C46, C53, C55, C57, C58, C66, C70, C71, C74, C79, C80, C82, C99, C101, C102, C106, C119, C120, C121, C124-C130, C132, C136 Q4 L7, L9, L14, L23 C97 N U12 CR3 DS2 DS3 Y-6 U1 DS1 N U4 Q2 N U13, U16, U21 U3 L2, L4-L5 C78, C122 C93 C32, C154 QTY 39 COMMENTS
Murata, AVX, GRM39X7R104K016AD Kemet, TDK 0603YC104KAT2A C0603C104K5RAC C1608X7R1C104KT
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2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 00000003209C 00000004945C 00000006661C 00000009762C 00000009897C 00000009898C 00000009899C 00000009900C 00000009901C 00000009902C 00000009903C 00000009904C 00000009907C 00000009935C 00000009936C 00000009937C 00000009938C Motorola, Siemens Toko Rohm Intersil Siemens Dialight Dialight Intersil Dialight Intersil Philips Toko AMD Toko AVX, TDK AVX, TDK AVX, TDK MMBT2907ALT1 SMBT2907A LL1608-F15NK MCH212C683KP ICL7660SIBA-T BBY51-E6327 597-3401-407 597-3111-407 HFA3724IN 597-3311-407 HFA3624IA96 BFR 505 TK11235AMTL AM79C930 LL1608-F33NK 04025A5R6CAT2A C1005C0G1H5R6CT 04025A4R7CAT2A C1005COG1H4R7CT 04025C501JAT2A C1005X7R1H501JT Transistor Inductor Capacitor Linear Diode-Rect Optic Optic Wireless/RF Optic Wireless/RF Transistor Linear Controller Inductor Capacitor Capacitor Capacitor Power Ceramic Ceramic Ceramic BJT-PNP Power Ceramic Converter Varactor LED Single LED Single Mod/Demod LED Single Prescalar BJT-NPN Volt Reg SMTSOT23 SMT SMT0805 SMTSOIC SMTSOT23 SMT SMT TQFP SMT SMTSSOP SMTSOT23 SMTSOT23 TQFP SMT0805 SMT0402 SMT0402 SMT0402 Y-4
1 4 1 1 1 1 1 1 1 1 1 3 1 3 2 1 2 Super Voltage Converter CT = 5.3PF at 1V, CT = 3.1PF at 4V SMT, 7" Reel, 2500 Pieces/Reel SMT, 7" Reel, 2500 Pieces/Reel 400MHz Quadrature IF Modulator/Demod. SMT, 7" Reel, 2500 Pieces/Reel 2.4GHz RF to IF Converter 9GHz Wideband Transistor, High Gain 3.5V Voltage Regulator with On/Off Switch IC LAN Media Access Controller Chip Inductor, DCR = 0.65
Application Note 9624
TABLE 2. REFERENCE RADIO BILL OF MATERIALS (Rev. A1, 3-26-98) (Continued) LINE ITEM 19 20 21 PART #/CUST. # 00000009943C 00000009944C 00000009945C VENDOR AVX, TDK AVX, TDK AVX, TDK VENDOR P/N 04025A470JAT2A C1005COG1H470JT 04025A100CAT2A C1005COG1H100CT 04025A101JAT2A C1005COG1H101JT COMMODITY Capacitor Capacitor Capacitor TYPE Ceramic Ceramic Ceramic MECH. DES. MOIST. SMT0402 SMT0402 SMT0402 REFERENCE DESCRIPTION C13, C18, C28, C60 C31 C6, C9, C11, C12, C14, C15, C22, C30, C43, C47, C48, C65, C69, C72, C90, C92, C100, C104, C109, C110, C118 C1, C2, C3, C4, C5, C7, C8, C10, C16, C29, C35, C76, C94, C96, C147, C153 C23, C24, C52, C67, C98, C143 C17, C19, C25, C33, C39, C50, C63, C64, C75, C95, C113, C138, C140, C141 C139 R31 R63, R64 R2, R33 FL3-FL4, FL6 R5 R9 R23, R87 R38, R76 R46, R77 R99-R104 R27 QTY 4 1 21 COMMENTS
8
22 00000009947C AVX, TDK 0402YC103KAT*A C1005X7R1C103KT 04025A220JAT2A C1005COG1H220JT 04023C102KAT2A C1005X7R1C102KT JZ060 ERJ2GEJ911X MCR01MZSJ911 ERJ2GEJ432X MCR01MZ5J432 ERJ2GEJ221X MCR01MZ5J221 TDF2A-2450T-10 ERJ2RKF2610X MCR01MZSF2610 ERJ2GEJ561X MCR01MZSJ561 ERJ2GEJ560X MCR01MZSJ560 ERJ2GEJ472X MCR01MZSJ472 ERJ2GEJ153X MCR01MZSJ153 ERJ2GEJ104X MCR01M2SJ104 Capacitor Ceramic SMT0402 23 24 00000009948C 00000009949C AVX, TDK AVX, TDK Capacitor Capacitor Ceramic Ceramic SMT0402 SMT0402 25 26 27 28 29 30 31 32 33 34 35 36 00000009950C 00000009974C 00000009975C 00000009976C 00000009977C 00000009978C 00000009979C 00000009981C 00000009982C 00000009983C 00000009983C 00000009984C Voltronics Panasonic, Rohm Panasonic, Rohm Panasonic, Rohm Toko Panasonic, Rohm Panasonic, Rohm Panasonic, Rohm Panasonic, Rohm Panasonic Rohm Panasonic, Rohm Capacitor Resistor Resistor Resistor Filter Resistor Resistor Resistor Resistor Resistor Resistor Resistor Trim Film Film Film Dielectric Film Film Film Film Film Film Film SMT SMT0402 SMT0402 SMT0402 SMT SMT0402 SMT0402 SMT0402 SMT0402 SMT0402 SMT0402 SMT0402
16
* = 1, 2, M or N
6
Application Note 9624
14
1 1 2 2 3 1 1 2 2 2 6 1
TABLE 2. REFERENCE RADIO BILL OF MATERIALS (Rev. A1, 3-26-98) (Continued) LINE ITEM 37 38 39 40 PART #/CUST. # 00000009986C 00000009989C 00000009990C 00000009991C VENDOR Panasonic, Rohm Panasonic, Rohm Panasonic, Rohm Panasonic, Rohm, K0A Panasonic, Rohm Panasonic, Rohm Panasonic, Rohm Panasonic, Rohm Panasonic, Rohm Panasonic, Rohm Panasonic, Rohm Panasonic, Rohm Panasonic, Rohm VENDOR P/N ERJ2GEJ152X MCR01MZSJ152 ERJ2GEJ100X MCR01M2SJ100 ERJ2GEJ101X MCR01M2SJ101 ERJ2GEJ103X MCR01MZSJ103 RM73B1ET103J ERJ2GEJ750X MCR01MZSJ750 ERJ2GEJ681X MCR01MZSJ681 ERJ2GEJ392X MCR01MZSJ392 ERJ2GEJ822X MCR01MZSJ822 ERJ2GEJ912X MCR01MZSJ912 ERJ2GEJ331X MCR01MZSJ331 ERJ2GEJ102X MCR01MZSJ102 ERJ2GE0R00X MCR01MZSJ0R00 ERJ3GSYJ681V MCR03EZHMJ681 COMMODITY Resistor Resistor Resistor Resistor TYPE Film Film Film Film MECH. DES. MOIST. SMT0402 SMT0402 SMT0402 SMT0402 REFERENCE DESCRIPTION R35, R50 R39, R85 R45, R78 R41 QTY 2 2 2 1 COMMENTS
9
41 42 43 44 45 46 47 48
00000009992C 00000009994C 00000010004C 00000010005C 00000010006C 00000010007C 00000010008C 00000010009C
Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor
Film Film Film Film Film Film Film Film
SMT0402 SMT0402 SMT0402 SMT0402 SMT0402 SMT0402 SMT0402 SMT0402
R51 R42 R13 R22 R1 R21, R24 R4 R7, R20, R48, R49, R55, R56, R59, R60, R61, R62, R66, R69, R97 R58, R65 R17
1 1
Application Note 9624
1 1 1 2 1 13
Resistor 3.9K 5% 0402 1/16W Resistor 8.2K 5% 1/16W 0402 Resistor 5% 9.1K 1/16W 0402 Resistor 330 5% 0402 1/16W Resistor 1K 5% 1/16W 0402 Resistor 0 Jumper 0402
49 50
00000010010C 00000010011C
Resistor Resistor
Film Film
SMT0603 SMT0603
2 1
Panasonic, ERJ3EKF3160V Rohm, KO, Q MCR03EZHMF3160 Dale RK73H1JTF3160 CRCW06033160FRT1 Rohm, Panasonic Philips Intersil Intersil MCR10EZHMJW331 ERJGEYJ331V 9C06031A1R0F HFA3524AIA96 HFA3824AVI
51 52 53 54
00000010012C 00000010013C 00000010014C 00000010021C
Resistor Resistor Wireless/RF Wireless/RF
Film Film Synth BBP
SMT0805 SMT0603 TSOP II TQFP N Y-2
R32 R3 U22 U6
1 1 1 1 This was changed from the SMT0505 2.5GHz/600MHz Dual Freq Synth. Baseband processor
TABLE 2. REFERENCE RADIO BILL OF MATERIALS (Rev. A1, 3-26-98) (Continued) LINE ITEM 55 56 57 PART #/CUST. # 00000010085C 00000010169C 00000010170C 00000010171C 00000010172C 00000010214C 00000011540C 00000011729C 00000011734C 00000011758C None 00000011759C None 00000011760C None 00000011762C None VENDOR NIC Intersil Intersil Murata Panasonic, Rohm Statek Intersil Panasonic, Rohm Panasonic AVX, TDK AVX, NIC AVX, TDK AVX, TDK, NIC VENDOR P/N NCB1206B320TR HFA3424IB96 HFA3925IA96 LFJ30-03B2442B084 ERJ2RKF4990X MCR01MZSF4990 CX-6V-SM2-32.768KRF1K4909396 ERJ2GEJ751X MCR01MZSJ751 EVM1SSW50B22 04025C222JAT2A C1005X7R1H222JT 04023A101FAT2A NMC0402NPO101F025T 04023A200FAT*A C1005COG1E200CT COMMODITY Inductor Wireless/RF Wireless/RF Filter Resistor Freq Control Transistor Resistor Resistor Capacitor Capacitor Capacitor TYPE Ferr Chip LNA PA EMI Film Crystal FET P-CH Film Pots Ceramic Ceramic Ceramic Ceramic MECH. DES. MOIST. SMT SMTSOIC SMTSSOP SMT SMT0402 SMT SMTSO8 SMT0402 SMT SMT0402 SMT0402 SMT0402 SMT0402 N N REFERENCE DESCRIPTION L1, L8, L12, L19, L21, L22, L24 U19, U24 AR1 FL1-FL2 R10 U11 U9, U25 R26, R52 R19 C142 C44, C49, C54, C61, C111, C155 C62 C73, C77 QTY 7 2 1 2 1 1 2 2 1 1 6 1 2 * = 1, 2, M or N for AVX P/N RF component, 2.5GHz Low Noise Amplifier 2.4-2.5GHz 25MW RF Power Amplifier Tape and Reel 2.442GHz, BW = 84MHz Resistor, 499 1% 1/16W 0402 Nickel tin plated termination Dual MOSFET, 8 Pin DIL SMT package Resistor, 750 5% 0402 1/16W COMMENTS
10
58 59 60 61 62 63 64 65 66 67
Application Note 9624
04023A150FAT2A Capacitor C1005COG1E150FT NMC0402NPO150F25TR L0603100GFWTR L0603120GFWTR ERJ3GSYK106V MCR03EZHUK106 ERJ2GEJ430X MCR01MZSJ430 ERJ2GEJ240X MCR01MZSJ240 KM62256CLTG-5L M5M5256CVP-55LL Inductor Inductor Resistor Resistor Resistor Memory
68 69 70 71 72 73
00000011836C N/A AVX 00000011837C N/A AVX 00000011866C 00000011869C 00000011870C 00000012189C Panasonic, Rohm Panasonic, Rohm Panasonic, Rohm Samsung, Mitsubishi
Power Power Film Film Film SRAM
SMT0603 SMT0603 SMT0603 SMT0402 SMT0402 TSOP I Y-3
L3 L17 R57 R36 R47, R53 U8
1 1 1 1 2 1
RF IND. L at 450, DCR = 0.13 RF IND. L at 450, DCR = 0.20
Resistor, 24 5% 0402
TABLE 2. REFERENCE RADIO BILL OF MATERIALS (Rev. A1, 3-26-98) (Continued) LINE ITEM 74 75 76 PART #/CUST. # 00000012987C 00000012990C 00000012992C 00000013250C 00000013251C 00000013303C 00000013319C None 00000013325C None 00000013326C None 00000013327C 00000013329C 00000013330C 00000013345C 00000013875C AVX, TDK AVX, TDK AVX AVX, Kemet AVX AVX Panasonic, Rohm AVX, Kemet, Murata AVX, Murata Statek Fox Panasonic, Rohm Murata, TDK AVX Murata TDK AVX 04025A5R0CAT*A C1005COG1H5R0CT 0402YC562JAT*A C1005X7R1C562JT 0805YC563JAT*A TAJS475K6R3R T491S475K006AS TAJT475K010R TAJT106K010R ERJ2GEJ394X MCR01MZSJ394 06035C682KAT*A C0603C682K5RAC GRM39X7R682K050%# VENDOR Fox, Statek Panasonic, Rohm Panasonic, Rohm Panasonic, Rohm Panasonic, Rohm VENDOR P/N F4106-22.000M CXOM10N22M(25PPM) ERJ2RKF9090X MCR01MZSF9090 ERJ2RKF3011X MCR01MZSF3011 ERJ2RKF7150X MCR01MZSF7150 ERJ2GEJ511X MCR01MZSJ511 COMMODITY Freq Control Oscillator Resistor Resistor Resistor Resistor Sheet Metal Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Resistor Capacitor Film Film Film Film Bottom Shield Ceramic Ceramic Ceramic Tantalum Tantalum Tantalum Film Ceramic SMT0402 SMT0402 SMT0805 SMTS SMTT SMTT SMT0402 SMT0603 TYPE MECH. DES. MOIST. SMT SMT0402 SMT0402 SMT0402 SMT0402 REFERENCE DESCRIPTION U20, U23 R34 R14, R25 R43, R84 R82 Bottom Shield C123, C144, C151 C91 C115 C51, C56, C83, C85, C133, C134 C84, C135 C81 R79 C89 QTY 2 1 2 2 1 1 3 1 1 6 2 1 1 1 * = 1 or 2 or M: % = A or B: # = D or L * = 1 or 2 or M, % = A or B, # = D or L 3528L - Low Profile * = 1 or 2 Resistor, 909 1% 0402 1/16W Resistor, 3.01K 1% 1/16W Resistor, 715 1% 1/16W 0402 COMMENTS
11
77 78 79 80 81 82 83 84 85 86 87
Application Note 9624
* = 1 or 2 * = 1 or 2 Low Profile - 3216L
88 89 90 91
00000014977C 00000015327C 00000016302C 00000016708C
04025A1R0CAT*A Capacitor GRM36COG1R0C050%# CXO-M-10N-40MHz (100PPM) F3355-40MHz ERJ2GEJ680X MCR01MZSJ680 GRM39COG2R0C050A# C1608COG1H020CT 06035A2R0CAT*A GRM36COG8R0C050A# C1005COG1H080CT 04025A8R0CAT*A Freq Control Oscillator Resistor Capacitor
Ceramic
SMT0402 SMT
C59, C131, C137 U10 R86 C116
3 1 1 1
Film Ceramic
SMT0402 SMT0603
* = 1, 2, M or N; # = D or L
92
00000016709C
Capacitor
Ceramic
SMT0402
C68
1
* = 1, 2, M or N; # = D or L
TABLE 2. REFERENCE RADIO BILL OF MATERIALS (Rev. A1, 3-26-98) (Continued) LINE ITEM 93 94 95 96 PART #/CUST. # 00000016710C 00000016812C 00000017117C 00000017587C 00000018647C 00000018864C 00000019393C 00000019584C 00000019598C 00000019599C 00000025454C Panasonic, Rohm, KOA KOA, Rohm AVX, Murata TDK AMD AMD ITT-Cannon ERJ2GEJ202X MCR01MZSJ202 RM73B1ET202J RM73B1ET132J MCR01MZSJ132 04023C122JAT*A GRM36X7R122J025A# C1005X7R1E122JT Device Driver Firmware Version 1.6 or later Connector 68-pin PC card side LL1608-F12NK MMBT2222ALT1 AM29F010-55EC Inductor Transistor Memory CTS KXN1332A ITT-Cannon VENDOR Toko Panasonic Toyocom VENDOR P/N LL2012-F27NK EVM1SSX50B53 TQS-432E-7R COMMODITY Inductor Resistor Filter Label Outline Drawing Coverset (top and bottom) Sheet Metal Freq Control PCB Coppertape top cut out Coppertape bottom cut out Resistor Film SMT0402 R37 1 Top Shield Oscillator SMT Top shield U18 PRISM1BRD 1 1 1 Voltage Controlled, 2132-2204MHz range Raw PC Board TYPE Fixed Poteniometer Saw General MECH. DES. MOIST. SMT0805 SMT SMT L6 R75 U5, U7 REFERENCE DESCRIPTION QTY 1 1 2 COMMENTS Chip Inductor, DCR = 0.55 5K SMP Pot, Type X 2000 per Reel Tape and Reel
12
97 98 99 100 101 102 103
Application Note 9624
104 105
00000027262C 00000027369C
Resistor Capacitor
Film Ceramic
SMT0402 SMT0402
R44 C86
1 1 * = 1, 2, M or N; # = D or L
106 107 108
00000032228C 00000032227C 000000932607C
Device Driver
Software Firmware Terminal
April '98 Software Win95 Driver Firmware Version 1.6 April '98 or later P1
1 0 1
109 110 111
0000013H9703fP 000000941687 000000943218
Toko Motorola AMD
Fixed BJT-NPN Flash
SMT0603 SMTSOT23 TSOP I Y-3
L15-L16 Q3, Q5 U2
2 2 1
(10%)
32 Pin Standard TSOP
Application Note 9624 Appendix B Receive Mixer Spurious Analysis
SystemPlus 1.0 S/N 11158 Copyright (c) 1992-1993 Webb Laboratories All Rights Reserved PRISM Reference Radio, 08/29/1996, 16:08:48 Receive Crossover Responses in Receive Band (2400MHz to 2500MHz) LO Level = +7dBm
IF FREQ No spurs recorded. LO FREQ RCV FREQ SPUR FREQ M N MXR
PRISM Reference Radio, 08/29/1996, 16:08:50 Spurious Responses in 0MHz to 5000MHz Band (-90dBC Minimum) LO Level = +7dBm Fixed Bandpass Preselector Band Edges are 2400MHz and 2500MHz 4 Section Butterworth - Corner Attenuation = 1dB Ultimate Preselector Rejection = 80dB
IF FREQ 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 LO FREQ 2120.0000 2120.0000 2120.0000 2120.0000 2120.0000 2130.0000 2130.0000 2130.0000 2130.0000 2140.0000 2140.0000 2140.0000 2140.0000 2140.0000 2150.0000 2150.0000 2150.0000 2150.0000 2160.0000 2160.0000 2160.0000 2160.0000 2170.0000 2170.0000 2170.0000 2170.0000 RCV FREQ 2400.0000 2400.0000 2400.0000 2400.0000 2400.0000 2410.0000 2410.0000 2410.0000 2410.0000 2420.0000 2420.0000 2420.0000 2420.0000 2420.0000 2430.0000 2430.0000 2430.0000 2430.0000 2440.0000 2440.0000 2440.0000 2440.0000 2450.0000 2450.0000 2450.0000 2450.0000 SPUR FREQ 2400.0000 1840.0000 2488.0000 2426.6667 2462.8571 2410.0000 1850.0000 2438.3333 2474.2857 2420.0000 1860.0000 2450.0000 2485.7143 2405.7143 2430.0000 1870.0000 2461.6667 2417.1429 2440.0000 1880.0000 2473.3333 2428.5714 2450.0000 1890.0000 2485.0006 2440.0000 M +1 -1 -5 -6 +7 +1 -1 -6 +7 +1 -1 -6 +7 -7 +1 -1 -6 -7 +1 -1 -6 -7 +1 -1 -6 -7 N -1 +1 +6 +7 -8 -1 +1 +7 -8 -1 +1 +7 -8 +8 -1 +1 +7 +8 -1 +1 +7 +8 -1 +1 +7 +8 MXR 0 0 90 90 90 0 0 90 90 0 0 90 90 90 0 0 90 90 0 0 90 90 0 0 90 90 FLT 1 80 0 0 0 0 80 0 0 0 80 0 0 0 0 80 0 0 0 80 0 0 0 80 0 0 TOT 1 80 90 90 90 0 80 90 90 0 80 90 90 90 0 80 90 90 0 80 90 90 0 80 90 90
13
Application Note 9624
IF FREQ 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 280.0000 LO FREQ 2180.0000 2180.0000 2180.0000 2180.0000 2190.0000 2190.0000 2190.0000 2190.0000 2200.0000 2200.0000 2200.0000 2200.0000 2210.0000 2210.0000 2210.0000 2210.0000 2220.0000 2220.0000 2220.0000 2220.0000 RCV FREQ 2460.0000 2460.0000 2460.0000 2460.0000 2470.0000 2470.0000 2470.0000 2470.0000 2480.0000 2480.0000 2480.0000 2480.0000 2490.0000 2490.0000 2490.0000 2490.0000 2500.0000 2500.0000 2500.0000 2500.0000 SPUR FREQ 2460.0000 1900.0000 2273.3333 2451.4286 2470.0000 1910.0000 2283.3333 2462.8571 2480.0000 1920.0000 2293.3333 2474.2857 2490.0000 1930.0000 2303.3333 2485.7143 2500.0000 1940.0000 2360.0000 2313.3333 M +1 -1 +3 -7 +1 -1 +3 -7 +1 -1 +3 -7 +1 -1 +3 -7 +1 -1 +2 +3 N -1 +1 -3 +8 -1 +1 -3 +8 -1 +1 -3 +8 -1 +1 -3 +8 -1 +1 -2 -3 MXR 0 0 50 90 0 0 50 90 0 0 50 90 0 0 50 90 0 0 74 50 FLT 0 80 39 0 0 80 37 0 0 80 35 0 0 80 32 0 1 79 15 30 TOT 0 80 89 90 0 80 87 90 0 80 85 90 0 80 82 90 1 79 89 80
TABLE 3. RECEIVE SPUR TABLE - LO POWER = 7dBm 15 14 13 12 11 10 9 8 (M) 7 6 5 4 3 2 1 0 99 99 90 99 90 99 90 99 90 90 90 86 67 73 24 --0 99 99 99 99 99 95 95 90 90 80 90 64 73 0 26 1 90 99 90 99 90 99 90 90 90 86 69 74 35 35 2 99 95 99 90 95 90 90 71 88 50 70 13 39 3 90 99 90 99 90 90 90 88 77 71 40 50 4 99 99 95 87 90 68 85 47 64 24 41 5 90 99 90 90 90 86 74 69 45 53 6 95 90 90 65 85 44 64 28 49 7 (N) 90 90 88 90 74 69 49 51 8 90 65 85 47 62 33 42 9 85 85 75 74 53 62 10 85 44 62 42 51 11 70 72 60 60 12 60 47 47 13 63 77 14 50 15 IF = | (M*SPUR) (N*LO) |
14
Application Note 9624 Appendix C IF SAW Filter Measured Data
Toyocom TQS-432E-7R, VHF-Range Wideband Low Loss SAW Filter
SPECIFICATIONS (TENTATIVE) Reference Frequency (fO): Passband: Maximum Insertion Loss in Passband: Attenuation: Terminating Impedance: Operating Temperature Range: Package: 280MHz fO 8.5MHz 10dB Max fO 38.8MHz at 50dB 270//-5pF -10oC to 50oC SS-752A
1.27 #2 #12 1.27 MAX 7.3 #4 MAX 5.3 #10 0.8 1.0 SS-752 MAX 1.9
IN 50 50
OUT
FIGURE 3.
FIGURE 2.
0 10 20 30 LOSS (dB) 40 50 60 70 80 90 100 180 267.5 280 FREQUENCY (MHz)
0 1 2 3 LOSS (dB) LOSS (dB) 4 5 6 7 8 9 10 380 292.5
0
50
100 230
280 FREQUENCY (MHz)
330
FIGURE 4. FREQUENCY RESPONSE
FIGURE 5. FREQUENCY RESPONSE
50ns PER DIVISION (ns) 196.7
234.01ns 282.208MHz 234.01ns 272.208MHz
243.05ns 289.632MHz 136.8ns 298.528MHz 42 -75.316 7.547pF 280MHz
42 7.5pF
260
280 FREQUENCY (MHz)
300 CENTER, 280MHz
SPAN, 50MHz
FIGURE 6. GROUP DELAY
FIGURE 7. INPUT IMPEDANCE CHARACTERISTIC
15
Application Note 9624 Appendix D Synthesizer Loop Analysis
A linear control system model of the phase feedback for a PLL in the locked state is shown in Figure 8. The open loop gain is the product of the phase detector gain (KPD), the VCO gain (KVCO/s), and the loop filter gain Z(s) divided by the gain of the feedback counter modulus (N). The passive loop filter configuration used is displayed in Figure 9. R
+
tan ( r ) * ( T1 + T3 ) c : = ------------------------------------------------------------ * 2 [ ( T1 + T3 ) + T1 * T3 ] ( T1 + T3 ) + T1 * T3 1 + ---------------------------------------------------------- - 1 2 ( tan ( r ) * ( T1 + T3 ) )
2
1 T2 : = ----------------------------------------2 c * ( T1 + T3 )
f c : = ----------2*
2
c
E
KPD
Z(s)
I
KVCO s
O
1 + ( c * T2 ) T1 * Kpd * Kvco C1 : = -------------------------------------------- * -----------------------------------------------------------------------------------------------2 2 2 N * T2 * [ [ 1 + ( c * T1 ) ] * [ 1 + ( c * T3 ) ] ] c T2 C2 : = C1 * ------ - 1 T1 T2 R2 : = ------C2
1/N
FIGURE 8. PLL LINEAR MODEL
DO R3 R2 C1 C2 C3
VCO
Loop Filter Component Values
T1 = 4.068 * 10-6 T2 = 4.472 * 10-5 T3 = 1.592 * 10-6
FIGURE 9. PASSIVE LOOP FILTER
This analysis calculates the loop filter components for the PRISM HFA3524A Dual PLL. A. Schaldenbrand and R.D. Schultz, 5/8/96 Where: LO1, 2132MHz to 2204MHz, floop is the desired bandwidth of the PLL, in Hz, fref is the reference frequency of the loop, in Hz,
fc = 1 * 104 C1 = 6.47 * 10-9 C2 = 6.47 * 10-8 R2 = 691.064 C1 : = 0.0068 * 10-6 C2 : = 0.068 * 10-6 R2 : = 680
Rules of thumb for selecting the values of the reference frequency suppression filter are: 1. Choose C3 < C1/10
C1 C3 : = ------10 R3 = 234.051 T3 R3 : = ------C3 C3 = 6.8 * 10
-9
is the desired phase margin of the PLL, in degrees,
Kvco is the VCO Tuning Voltage Constant in Hz/V, Kpd is the Phase Detector Pump Constant in A/rad, N is the divider ratio, 1.424 is a constant to account for impact of R3/C3 pole.
f loop : = 10 * 10 f ref : = 1 * 10
6 3
2. Choose R3 < 2 * R2
R3 : = 2 * R2 T3 C3 : = ------R3 k = 10..70 R3 = 1.36 * 10 C3 = 1.224 * 10
3
R3 = 1300 C3 : = 1200 * 10
- 12
-9
p : = 2 * * f loop r : = 2 * * f ref
p = 6.283 * 10 r = 6.283 * 10
4
kp ( k ) : = 10
k ----- 10
6
(k) : = 2j * * kp ( k ) 1 + ( k ) * T2 GH(k) : = Kpd * Kvco * -------------------------------------------------------------------------------------------------------( C1 * N * ( k ) * ( k ) ) * ( 1 + ( k ) * T1 )
: = 50
r : = * ------------ 180
6
Kvco : = 53 * 10 Kpd : = 0.004 N : = 2168 1 T3 : = ------------------10 * p
Kvco : = 2 * * Kvco Kpd Kpd : = ----------2*
Kvco = 3.33 * 10
-4
8
T1 1 * ------ * --------------------------------------T2 ( 1 + ( k ) * T3 ) MAGdb_GH(k) : = 20 Log ( GH ( k ) * GH ( k ) ) Im ( GH ( k ) ) PHI_GH(k) : = atan ------------------------------ Re ( GH ( k ) )
Kpd = 6.366 * 10
p : = 1.424 * p
T1 = 4.068 * 10
-6
180 * PHI_GH(k) f_GH(k) : = -------------------------------------------- - 180 MAG_GH(k) : = ( GH ( k ) * GH ( k ) ) Phim(k) : = 180 + f_GH(k)
sec ( r ) - tan ( r ) T1 : = ---------------------------------------------
p
16
Application Note 9624
Plots of the magnitude and phase of GH(k) are shown in Figures 10 and 11. N is the divider ratio, 1.424 is a constant to account for impact of R3/C3 pole.
f loop : = 10 * 10 f ref : = 1 * 10
6 3
180 150 120 90 MAGdb_GH(k) Phim(k) 60 30 0 -30 -60 -90 -120 -150 -180 10 100 1 * 103 1 * 104 1 * 105 kp(k), kp(k) 1 * 106 1 * 107
p : = 2 * * f loop r : = 2 * * f ref
p = 6.283 * 10 r = 6.283 * 10
4
6
: = 50
r : = * ------------ 180
6
Kvco : = 13 * 10 Kpd : = 0.004 N : = 560 1 T3 : = ------------------10 * p
Kvco : = 2 * * Kvco
Kvco = 8.168 * 10
-4
7
Kpd Kpd : = ----------2*
Kpd = 6.366 * 10
p : = 1.424 * p
FIGURE 10. sec ( r ) - tan ( r ) T1 : = --------------------------------------------100
p
T1 = 4.068 * 10
-6
50
tan ( r ) * ( T1 + T3 ) c : = ------------------------------------------------------------ * 2 [ ( T1 + T3 ) + T1 * T3 ]
( T1 + T3 ) + T1 * T3 1 + ---------------------------------------------------------- - 1 2 ( tan ( r ) * ( T1 + T3 ) )
2
Phim(k)
0
1 T2 : = ----------------------------------------2 c * ( T1 + T3 )
f c : = ----------2*
c
-50
1 + ( c * T2 ) T1 * Kpd * Kvco C1 : = -------------------------------------------- * ------------------------------------------------------------------------------------------2 2 N * T2 * 2 [ [ 1 + ( c * T1 ) ] * [ 1 + c ( T3 ) ] ] c
10 100 1 * 103 1 * 104 kp(k) 1 * 105 1 * 106 1 * 107
2
-100
T2 C2 : = C1 * ------ - 1 T1 T2 R2 : = ------C2
FIGURE 11.
This analysis calculates the loop filter components for the PRISM HFA3524A Dual PLL. A. Schaldenbrand and R.D. Schultz, 5/8/96 Where: LO2, 560MHz, floop is the desired bandwidth of the PLL, in Hz, fref is the reference frequency of the loop, in Hz,
Loop Filter Component Values
T1 = 4.068 * 10-6 T2 = 4.472 * 10-5 T3 = 1.592 * 10-6 fc = 1 * 104 C1 = 6.149 * 10-9 C2 = 6.146 * 10-8 R2 = 727.746 C1 : = 5600 * 10-12 C2 : = 0.056 * 10-6 R2 : = 750
is the desired phase margin of the PLL, in degrees,
Kvco is the VCO Tuning Voltage Constant in Hz/V, Kpd is the Phase Detector Pump Constant in A/rad,
17
Application Note 9624
Rules of thumb for selecting the values of the reference frequency suppression filter are: 1. Choose C3 < C1/10
C1 C3 : = ------10 R3 = 2.842 * 10
3
(k) : = 2j * * kp ( k ) 1 + ( k ) * T2 GH(k) : = Kpd * Kvco * -------------------------------------------------------------------------------------------------------( C1 * N * ( k ) * ( k ) ) * ( 1 + ( k ) * T1 )
T3 R3 : = ------C3 C3 = 5.6 * 10
- 10
T1 1 * ------ * --------------------------------------T2 ( 1 + ( k ) * T3 ) MAGdb_GH(k) : = 20 Log ( GH ( k ) * GH ( k ) ) Im ( GH ( k ) ) PHI_GH(k) : = atan ------------------------------ Re ( GH ( k ) ) 180 * PHI_GH(k) f_GH(k) : = -------------------------------------------- - 180 MAG_GH(k) : = ( GH ( k ) * GH ( k ) ) Phim(k) : = 180 + f_GH(k)
2. Choose R3 > 2 * R2
R3 : = 2 * R2 T3 C3 : = ------R3 R3 = 1.5 * 10 C3 = 1.061 * 10
3
R3 = 1500 C3 : = 1000 * 10
- 12
-9
k = 10..70
kp ( k ) : = 10
k ----- 10
Plots of the magnitude and phase of GH(k) are shown in Figures 12 and 13.
180 150 120 90 MAGdb_GH(k) Phim(k) 60
100
50
0 -30 -60 -90
Phim(k)
30
0
-50
-120 -150 -180 10 100 1 * 103 1 * 104 1 * 105 kp(k), kp(k) 1 * 106 1 * 107 -100 10 100 1 * 103 1 * 104 kp(k) 1 * 105 1 * 106 1 * 107
FIGURE 12.
FIGURE 13.
18
Application Note 9624 Appendix E Synthesizer Phase Noise/Jitter Analysis
TABLE 4. PRISM 1 LO PHASE NOISE ANALYSIS PRISM 1 LO PHASE NOISE ANALYSIS 3/22/96 RDS 2.1GHz LO MEASURED PERFORMANCE FREQ OFFSET 10K 20K 50K 200K 300K 400K 750K Total 560MHz LO MEASURED PERFORMANCE 10K 20K 50K 100K >200K Total -83.5 -90.5 -102.1 -106 -111 7.814E-05 0.506 4.051E-05 1.768E-05 3.865E-06 1.608E-05 0.365 0.241 0.113 0.230 dBc/Hz -76.6 -81.8 -92.4 -97.6 -103.7 -107.6 -111.2 4.816E-04 1.257 NOTES PHASE JITTER (RADIANS SQUARED) 2.382E-04 1.243E-04 8.781E-05 1.782E-05 5.511E-06 7.919E-06 PHASE JITTER (RMS DEGREES) 0.884 0.639 0.537 0.242 0.135 0.161
"Assume worst case, RMS measured 2.1GHz and 560MHz LO" PHASE JITTER (RADIANS SQUARED) 2.1GHz LO 560MHz LO Total 4.816E-04 7.814E-05 5.597E-04 PHASE JITTER (RMS DEGREES) 1.257 0.506 1.355
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19
Application Note 9624 Appendix F Gain Distribution/IF Limiting Analysis
The IF stage, including the limiters, is of a differential design to improve noise rejection and stability for these high gain stages. The RF front end, on the other hand, is single ended to reduce complexity. A receive chain block diagram is shown in Figure 14. The minimum limiter 1 and 2 voltage gains are 39dB at 2.7V and 400MHz. The radio design uses the part at a less extreme operating point of 3.5V and 280MHz where the minimum performance is 42dB. The limiter 1 and 2 output limiting voltage is 200mVP-P into a differential 500 load. Using 3dB loss in the limiter Bandpass Filter (BPF), the limiter chain (LIM1, BPF, LIM2) cascaded voltage gain is 81dB, with typical performance above 90dB. With a 200mVP-P output, the input limiting voltage is 17.8VP-P or -98dBm at 250 source impedance. This is calculated as follows: since the source and load impedances are different (250 vs 500) the input signal is calculated in terms of voltage. Remember that the limiter is a voltage gain device and so gain is independent of source impedance. Substitute the result of Equation 1 into Equation 2 and calculate VIN(P-P).
gain = 10
GAIN ( dB ) ----------------------------- 20
Pwr ( dBm ) = 10 log ( Pwr ( Watts ) 10 )
3
(EQ. 5)
The limiters have a noise bandwidth of over 500MHz and so the cascaded limiters will fully limit on their own noise, if no BPF is used between the stages. The thermal noise voltage delivered from the 250 source to the limiters in a 500MHz band is -87dBm, as calculated from Equation 6. This thermal noise adds to the limiter noise figure (NF) of 7dB resulting in an equivalent input noise power of -80dBm, which is significantly higher than the -98dBm required for limiting.
P ( Watts ) A = kT f (EQ. 6)
Where:
P ( Watts ) A = Available Noise Power k = 1.38042 x 10 Boltzmanns Constant T = 300 Degree Kelvin f = 500MHz
- 23
(EQ. 1) (EQ. 2)
V OUT = gain * V IN
The RF front end 3dB bandwidth is 17MHz, with an estimated noise bandwidth of 20MHz, as defined by the IF SAW filter. This makes the available thermal noise at the limiter input -101dBm and with the 7dB limiter noise figure, is an equivalent -94dBm. If the limiter BPF was also 20MHz, the front end would only need to supply 7dB of noise floor gain to overcome the limiter noise figure. This would result in a receiver that limits in a 20MHz bandwidth from front end noise with no margin. The 20MHz limiter BPF would require a second SAW filter and therefore is not cost effective or practical. The alternative chosen to be implemented is a simple one pole LC BPF with a bandwidth wide enough so that the variability of fixed components do not result in the filter being off frequency. The filter selected has a 3dB bandwidth of 50MHz, and an estimated noise bandwidth of 100MHz. Using this method, the front end gain must be increased to compensate for excess limiter bandwidth.
Calculate the input power with a 250 impedance by using Equation 3 to get VRMS and then substitute into Equation 4 with R = 250 to get power in Watts. Equation 3 assumes a sinewave crest factor for the 2 term. Power in Watts is converted to dBm with Equation 5 to get -98dBm input power at 250 source impedance.
VP - P V RMS = --------------2 2 V RMS Pwr ( Watts ) = --------------R
2
(EQ. 3)
(EQ. 4)
50 SINGLE-ENDED
250 SINGLE-ENDED
500 DIFFERENTIAL
FRONT END
LIM1
LIMITER BPF
LIM2
BWN = 20MHz NF = 7.7dB GAIN = 8.4dB
BWN = 500MHz NF = 7dB GAIN = 42dB
BWN = 100MHz NF = 3dB IL = 3dB
BWN = 500MHz NF = 7dB GAIN = 42dB
WHERE BWN = NOISE BANDWIDTH
FIGURE 14. RECEIVE CHAIN GAIN DISTRIBUTION DIAGRAM
20
Application Note 9624
It is desired that the second limiter to be fully limited on front end noise, as opposed to noise generated in the first limiter. This requires that the front end noise floor must be greater than the sum of the following; the limiter NF of 7dB, the ratio of limiter BPF noise bandwidth to front end IF SAW bandwidth (10log(100MHz/20MHz) or 7dB), and the amount of limiting margin (6dB for -1dB limiting). The front end output noise floor must therefore be greater than 20dB. The limiting margin was measured on the HFA3724 IF Mod/Demod, with good agreement to a theoretical estimate based upon the hyperbolic tangent response of a bipolar differential limiter. The measurement means that if a nondesired jamming signal, noise in this case, is 6dB below the level of the desired signal, the desired output will be reduced 1dB. The front end noise floor was previously calculated for a 20MHz bandwidth as -101dBm, if the required gain is now added, this noise floor becomes -81dBm as shown in Equation 7. Now verify that this level is larger than the minimum signal power required to limit the limiter chain and guarantee that the radio limits on front end noise (-81dBm > -98dBm).
( 20MHz kTB ) + NF LIM + BPF Noise + Lim M arg in = Front End Noise
References
For Intersil documents available on the internet, see web site http://www.intersil.com/ Intersil AnswerFAX (407) 724-7800. [1] Application Note, AMD, "Wireless LAN DSSS PC Card Reference Design", Publication Number 20575, Rev A. [2] http://www.intersil.com/ [3] HFA3824A Data Sheet, Intersil Corporation Semiconductor, AnswerFAX Doc. No. 4064. [4] HFA3925 Data Sheet, Intersil Corporation, AnswerFAX Doc. No. 4132. [5] HFA3424 Data Sheet, Intersil Corporation, AnswerFAX Doc. No. 4131. [6] HFA3624 Data Sheet, Intersil Corporation, AnswerFAX Doc. No. 4066. [7] HFA3724 Data Sheet, Intersil Corporation, AnswerFAX Doc. No. 4067. [8] ICL7660S Data Sheet, Intersil Corporation, AnswerFAX Doc. No. 3179. [9] RF1K49093 Data Sheet, Intersil Corporation, AnswerFAX Doc. No. 3969. [10] HFA3524A Data Sheet, Intersil Corporation, AnswerFAX Doc. No. 4062. [11] "Integrating RF and Digital Circuits in a PC Card Environment", Portable Design, May 1996.
(EQ. 7)
i.e.
- 101dBm + 7dB + 7dB + 6dB = - 81dBm
Where; (20MHz kTB) is Available Thermal Noise NFLIM is Noise Figure of Limiter Chain BPFNoise is Added Noise due to Limiter BPF Bandwidth wider than Front End LimMargin is Front End Margin required to guarantee limiter jammer rejection The actual front end gain is 13.4dB and NF is 7.7dB for a front end output noise floor increase of 21.1dB typical, which is better than desired 20dB. This results in limiting, when no signal is present, on mainly front end noise, but also some limiter broadband noise. This limiter output, although still fully limited, when band filtered will have a slight drop in baseband quadrature output voltage to the HFA3824A ADCs as compared to totally limiting on front end noise due to some of the limiter noise being out of band. The net impact to the system is a small reduction in sensitivity due to reduced ADC signal to full scale. If desired, additional front end gain, or a reduced bandwidth limiter BPF could be used to gain back performance.
21

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