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DATA SHEET
PD780851(A), 780852(A)
8-BIT SINGLE-CHIP MICROCONTROLLERS
MOS INTEGRATED CIRCUIT
The PD780851(A) and 780852(A) are products of the PD780852 Subseries in the 78K/0 Series. The PD780851(A) and 780852(A) include a meter controller/driver, sound generator, LCD controller/driver, 8-bit resolution A/D converter, timer, serial interface, interrupt function, and various other peripheral hardware. A flash memory version, the PD78F0852, which can operate in the same power supply voltage range as the mask ROM version, and various development tools are also available. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing.
PD780852 Subseries User's Manual:
78K/0 Series User's Manual - Instruction:
U14581E U12326E
FEATURES
Meter controller/driver: 16 PWM outputs (8-bit resolution) Sound generator: 1 channel Internal ROM and RAM
Item Program Memory (Internal ROM) Data Memory Internal High-Speed RAM 1024 bytes Internal Expansion RAM 512 bytes LCD Display RAM 20 x 4 bits
Part Number
PD780851(A) PD780852(A)
32 KB 40 KB
Minimum instruction execution time can be changed from high-speed (0.24 s) to low-speed (3.81 s) I/O ports: 56 (Including segment signal output alternate function pins) 8-bit resolution A/D converter: 5 channels Serial interface: 3 channels Timer: 6 channels Supply voltage: VDD = 4.0 to 5.5 V
APPLICATIONS
Automobile meter (dashboard) control
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U14577EJ1V0DS00 (1st edition) Date Published October 2001 NS CP(K) Printed in Japan
The mark
shows major revised points.
2000
PD780851(A), 780852(A)
ORDERING INFORMATION
Part Number Package 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) Quality Grade Special Special
PD780851GC(A)-xxx-8BT PD780852GC(A)-xxx-8BT
Remark xxx indicates ROM code suffix.
For the details of the quality grades on the devices and their applications, refer to Quality Grades on NEC Semiconductor Devices (C11531E) published by NEC Corporation.
2
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production Products under development Y subseries products are compatible with I2C bus. Control PD78075B PD78078
100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
PD78078 with reduced EMI noise PD78078Y PD78070AY PD780018AY PD780058Y PD78058FY PD78054Y PD780078Y PD780034AY PD780024AY PD78018FY PD78054 with timer added and enhanced external interface
ROMless version of PD78078
PD78070A PD780058 PD78058F PD78054 PD780065 PD780078 PD780034A PD780024A PD78014H PD78018F PD78083
Inverter control
PD78078Y with enhanced serial I/O and limited functions PD78054 with enhanced serial I/O PD78054 with reduced EMI noise PD78018F with UART and D/A added, and enhanced I/O PD780024A with expanded RAM PD780034A with timer added and enhanced serial I/O PD780024A with enhanced A/D PD78018F with enhanced serial I/O PD78018F with reduced EMI noise
Basic subseries for control On-chip UART and capable of low voltage operation (1.8 V) On-chip inverter controller and UART. Reduced EMI noise.
64-pin
PD780988
VFD drive
100-pin 80-pin 80-pin 78K/0 Series 80-pin
PD780208 PD780232 PD78044H PD78044F
LCD drive PD780338
PD78044F with enhanced I/O and VFD C/D. Display output total: 53
For panel control. On-chip VFD C/D. Display output total: 53
PD78044F with N-ch open drain I/O added. Display output total: 34
Basic subseries for driving VFD. Display output total: 34
120-pin 120-pin 120-pin 100-pin 100-pin 100-pin
PD780308 with enhanced display function and timer. Segment signal output: 40 pins max. PD780308 with enhanced display function and timer. Segment signal output: 32 pins max. PD780308 with enhanced display function and timer. Segment signal output: 24 pins max. PD780308Y PD78064Y PD78064 with enhanced SIO and expanded ROM, RAM PD78064 with reduced EMI noise
Basic subseries for driving LCD. On-chip UART.
PD780328 PD780318 PD780308 PD78064B PD78064 PD780948 PD78098B PD780702Y PD780703Y
Bus interface supported
100-pin 80-pin 80-pin 80-pin 80-pin 64-pin
On-chip DCAN controller
PD78054 with IEBusTM controller added On-chip IEBus controller
On-chip DCAN controller On-chip J1850 (CLASS2) controller Specialized for DCAN controller function
PD780816
Meter control
PD780833Y
100-pin 80-pin 80-pin
PD780958 PD780852 PD780828B
For industrial meter control On-chip controller/driver for automobile meter drive For automobile meter drive. On-chip DCAN controller
Remark VFD (Vacuum Fluorescent Display) is referred to as FIP documents, but the functions of the two are the same.
TM
(Fluorescent Indicator Panel) in some
Data Sheet U14577EJ1V0DS
3
PD780851(A), 780852(A)
The major functional differences among the subseries are listed below.
Function Subseries Name Control PD78075B ROM Capacity Timer 8-Bit 16-Bit
Watch
8-Bit WDT A/D
10-Bit A/D -
8-Bit D/A
Serial Interface
I/O
VDD MIN. Value 1.8 V
External Expansion
32 K to 40 K 48 K to 60 K - 24 K to 60 K
4 ch
1 ch
1 ch
1 ch
8 ch
2 ch
3 ch (UART: 1 ch)
88
PD78078 PD78070A PD780058 PD78058F PD78054 PD780065 PD780078
61 2 ch
3 ch (time-division UART: 1 ch)
2.7 V 1.8 V
68
48 K to 60 K 16 K to 60 K 40 K to 48 K 48 K to 60 K 8 K to 32 K 2 ch 1 ch 8 ch - - 8 ch -
3 ch (UART: 1 ch)
69
2.7 V 2.0 V
4 ch (UART: 1 ch) 3 ch (UART: 2 ch) 3 ch (UART: 1 ch)
60 52 51
2.7 V 1.8 V
PD780034A PD780024A
PD78014H PD78018F PD78083
Inverter control VFD drive
2 ch 8 K to 60 K 8 K to 16 K 16 K to 60 K 3 ch - Note - - 1 ch - 8 ch - - - 1 ch (UART: 1 ch) 3 ch (UART: 2 ch)
53
33 47 4.0 V
- -
PD780988 PD780208 PD780232 PD78044H PD78044F
32 K to 60 K 16 K to 24 K 32 K to 48 K 16 K to 40 K 48 K to 60 K 48 K to 60 K 48 K to 60 K 48 K to 60 K
2 ch 3 ch 2 ch
1 ch - 1 ch
1 ch - 1 ch
1 ch
8 ch 4 ch 8 ch
2 ch
74 40
2.7 V 4.5 V 2.7 V
1 ch 2 ch
68
LCD drive
PD780338 PD780328 PD780318 PD780308 PD78064B PD78064
3 ch
2 ch
1 ch
1 ch
-
10 ch
1 ch
2 ch (UART: 1 ch)
54 62 70
1.8 V
-
2 ch
1 ch
8 ch
-
-
3 ch (time-division UART: 1 ch)
57
2.0 V
32 K 16 K to 32 K 60 K 40 K to 60 K 32 K to 60 K 48 K to 60 K 4 ch 2 ch 2 ch 1 ch 2 ch 2 ch - 1 ch 12 ch - - - 1 ch 1 ch 8 ch - - 2 ch - - -
2 ch (UART: 1 ch)
Bus interface supported Meter control Dashboard control
PD780948 PD78098B PD780816 PD780958 PD780852 PD780828B
3 ch (UART: 1 ch)
79 69
4.0 V 2.7 V 4.0 V 2.2 V
-
2 ch (UART: 1 ch) 2 ch (UART: 1 ch)
46 69
- -
32 K to 40 K 32 K to 60 K
3 ch
1 ch
1 ch
1 ch
5 ch
3 ch (UART: 1 ch)
56 59
4.0 V
Note 16-bit timer: 2 channels 10-bit timer: 1 channel
4
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
OVERVIEW OF FUNCTIONS
Part Number Item Internal memory ROM High-speed RAM Expansion RAM LCD display RAM General-purpose registers Minimum instruction execution time 32 KB 1024 bytes 512 bytes 20 x 4 bits 8 bits x 32 registers (8 bits x 8 registers x 4 banks) On-chip minimum instruction execution time variable function 0.24 s/0.48 s/0.95 s/1.91 s/3.81 s (@ 8.38 MHz operation) Instruction set * 16-bit operation * Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) * Bit manipulation (set, reset, test, Boolean operation) * BCD adjust, etc. I/O ports (segment signal output alternate function pins included) Total: * CMOS input: * CMOS output: * CMOS I/O: A/D converter * 8-bit resolution x 5 channels * Power-fail detection function LCD controller/driver * Segment signal outputs: * Common signal outputs: * Bias: Serial interface * 3-wire serial I/O mode: * UART mode: Timers * 16-bit timer: * 8-bit timer: * 8-bit timer/event counter: * Watch timer: * Watchdog timer: Timer outputs Meter controller/driver 2 (capable of 8-bit PWM output: 2) PWM output (8-bit resolution): 16 Pulse width setting of 8 + 1-bit precision is enabled by a 1-bit addition function Sound generator Clock output Vectored interrupt sources Maskable Non-maskable Software Supply voltage Operating ambient temperature Package 1 channel 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.04 MHz, 2.09 MHz, 4.19 MHz, 8.38 MHz (@ 8.38 MHz operation with main system clock) Internal: 16, External: 3 Internal: 1 1 VDD = SMVDD = 4.0 to 5.5 V TA = -40 to + 85C 80-pin plastic QFP (14 x 14 mm) Max. 20 Max. 4 1/3 bias only 2 channels 1 channel 1 channel 1 channel 2 channels 1 channel 1 channel 56 5 16 35 40 KB
PD780851(A)
PD780852(A)
Data Sheet U14577EJ1V0DS
5
PD780851(A), 780852(A)
CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ....................................................................................................... 7 2. BLOCK DIAGRAM................................................................................................................................... 9 3. PIN FUNCTIONS.................................................................................................................................... 10
3.1 Port Pins ....................................................................................................................................................... 10 3.2 Non-Port Pins ............................................................................................................................................... 11 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................................... 12
4. MEMORY SPACE .................................................................................................................................. 15 5. PERIPHERAL HARDWARE FUNCTION FEATURES .......................................................................... 17
5.1 Ports .............................................................................................................................................................. 17 5.2 Clock Generator ........................................................................................................................................... 18 5.3 Timer/Event Counter.................................................................................................................................... 18 5.4 Clock Output Controller .............................................................................................................................. 21 5.5 A/D Converter ............................................................................................................................................... 22 5.6 Serial Interface ............................................................................................................................................. 23 5.7 LCD Controller/Driver .................................................................................................................................. 24 5.8 Sound Generator.......................................................................................................................................... 25 5.9 Meter Controller/Driver ................................................................................................................................ 25
6. INTERRUPT FUNCTION ....................................................................................................................... 26 7. STANDBY FUNCTION........................................................................................................................... 29 8. RESET FUNCTION ................................................................................................................................ 29 9. INSTRUCTION SET ............................................................................................................................... 30 10. ELECTRICAL SPECIFICATIONS ........................................................................................................ 32 11. PACKAGE DRAWING ......................................................................................................................... 43 12. RECOMMENDED SOLDERING CONDITIONS................................................................................. 44 APPENDIX A. DEVELOPMENT TOOLS ................................................................................................... 45 APPENDIX B. RELATED DOCUMENTS................................................................................................... 47
6
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
1. PIN CONFIGURATION (TOP VIEW)
* 80-pin plastic QFP (14 x 14)
PD780851GC(A)-xxx-8BT, 780852GC(A)-xxx-8BT
P85/S15 P84/S16 P83/S17 P82/S18 P81/S19 IC X1 X2 VSS1 VROUT RESET P07 P06 P05/SI2 P04/SO2 P03/SCK2 P02/INTP2 P01/INTP1 P00/INTP0 AVREF
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 11 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P86/S14 P87/S13 P90/S12 P91/S11 P92/S10 P93/S9 P94/S8 P95/S7 P96/S6 P97/S5 S4 S3 S2 S1 S0 COM3 COM2 COM1 COM0 VLCD
SMVSS SMVDD P20/SM11 P21/SM12 P22/SM13 P23/SM14 P24/SM21 P25/SM22 P26/SM23 P27/SM24 P30/SM31 P31/SM32 P32/SM33 P33/SM34 P34/SM41 P35/SM42 P36/SM43 P37/SM44 SMVDD SMVSS
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1. 2. Connect the AVSS pin to VSS0. 3. Connect the AVREF pin to VDD0. Remark When the PD780851(A) and 780852(A) are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as connecting VSS0 and VSS1 to different ground lines, is recommended.
P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVSS P50/SCK3 P51/SO3 P52/SI3 VDD0 VSS0 P53/RxD P54/TxD P40/TI00 P41/TI01 P42/TI02 P43/TIO2 P44/TIO3 P60/TPO/PCL P61/SGO
Data Sheet U14577EJ1V0DS
7
PD780851(A), 780852(A)
ANI0 to ANI4: AVREF: AVSS: COM0 to COM3: IC: INTP0 to INTP2: P00 to P07: P10 to P14: P20 to P27: P30 to P37: P40 to P44: P50 to P54: P60, P61: P81 to P87: P90 to P97: PCL: RESET: RxD: Analog Input Analog Reference Voltage Analog Ground Common Output Internally Connected External Interrupt Input Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 8 Port 9 Programmable Clock Output Reset Receive Data S0 to S19: SCK2, SCK3: SGO: SI2, SI3: SM41 to SM44: SMVDD: SMVSS: SO2, SO3: TI00 to TI02: TIO2, TIO3: TPO: TxD: VDD0: VLCD: VROUT: VSS0, VSS1: X1, X2: Segment Output Serial Clock Sound Generator Output Serial Input Meter Output Meter Controller Power Supply Meter Controller Ground Serial Output Timer Output Timer Output/Event Counter Input Prescaler Output Transmit Data Power Supply LCD Power Supply Power Supply Regulator Output Ground Crystal (Main System Clock)
SM11 to SM14, SM21 to SM24, SM31 to SM34,
8
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
2. BLOCK DIAGRAM
TI00/P40 to TI02/P42 TPO/PCL/P60 16-bit timer 0 Port 0 P00 to P07
8-bit timer 1 8-bit timer/ event counter 2 8-bit timer/ event counter 3 Watchdog timer Watch timer SCK2/P03 SO2/P04 SI2/P05 SCK3/P50 SO3/P51 SI3/P52 RxD/P53 TxD/P54 ANI0/P10 to ANI4/P14 AVSS AVREF Serial interface SIO2 Serial interface SIO3 UART Internal expansion RAM
Port 1
P10 to P14
TIO2/P43
Port 2
P20 to P27
TIO3/P44
Port 3
P30 to P37
Port 4
P40 to P44
Port 5
P50 to P54
78K/0 CPU Core
Port 6 ROM Port 8
P60, P61
P81 to P87
Port 9
P90 to P97 S0 to S4 S5/P97 to S12/P90
A/D converter Power fail detector
RAM
LCD controller/ driver
S13/P87 to S19/P81 COM0 to COM3 VLCD SM11/P20 to SM14/P23 SM21/P24 to SM24/P27
INTP0/P00 to INTP2/P02
Interrupt control Standby control Meter controller/ driver
SM31/P30 to SM34/P33 SM41/P34 to SM44/P37 SMVDD SMVSS X1 X2 RESET VROUT VSS1
PCL/TPO/P60
Clock output control Sound generator output System control Voltage regulator
SGO/P61
VDD0
VSS0
IC
Data Sheet U14577EJ1V0DS
9
PD780851(A), 780852(A)
3. PIN FUNCTIONS
3.1 Port Pins
Pin Name I/O Function After Reset Alternate Function INTP0 to INTP2 SCK2 SO2 SI2 - Input ANI0 to ANI4
P00 to P02 P03 P04 P05 P06, P07 P10 to P14
I/O
Port 0 8-bit I/O port Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by means of software.
Input
Input
Port 1 5-bit input-only port
P20 to P23 P24 to P27 P30 to P33 P34 to P37 P40 to P42 P43, P44
Output
Port 2 8-bit output-only port
Hi-Z
SM11 to SM14 SM21 to SM24
Output
Port 3 8-bit output-only port
Hi-Z
SM31 to SM34 SM41 to SM44
I/O
Port 4 5-bit I/O port Input/output can be specified in 1-bit units.
Input
TI00 to TI02 TIO2, TIO3
P50 P51 P52 P53 P54 P60 P61
I/O
Port 5 5-bit I/O port Input/output can be specified in 1-bit units.
Input
SCK3 SO3 SI3 RxD TxD
I/O
Port 6 2-bit I/O port Input/output can be specified in 1-bit units.
Input
PCL/TPO SGO
P81 to P87
I/O
Port 8 7-bit I/O port Input/output can be specified in 1-bit units. The I/O port/segment output function can be specified in 2-bit units by means of the LCD display control register (LCDC).
Input
S19 to S13
P90 to P97
I/O
Port 9 8-bit I/O port Input/output can be specified in 1-bit units. The I/O port/segment output function can be specified in 2-bit units by means of the LCD display control register (LCDC).
Input
S12 to S5
10
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
3.2 Non-Port Pins
Pin Name INTP0 to INTP2 SI2 SO2 SCK2 SI3 SO3 SCK3 RxD TxD TI00 TI01 TI02 TIO2 TIO3 TPO PCL SGO S0 to S4 S5 to S12 S13 to S19 COM0 to COM3 VLCD SM11 to SM14 SM21 to SM24 SM31 to SM34 SM41 to SM44 ANI0 to ANI4 AVREF AVSS RESET X1 X2 SMVDD SMVSS VDD0 VSS0 VROUT VSS1 IC Input Input - Input Input - - - - - - - - Meter controller/driver power supply Meter controller/driver ground potential Port block positive power supply Port block ground potential Regulator output pin for positive power supply other than port block. Connect to VSS0 or VSS1 via a 0.1 F capacitor. Ground potential (other than port block) Internally connected. Connect directly to VSS0 or VSS1. A/D converter analog input A/D converter reference voltage input (also used for analog power supply) A/D converter ground potential. Connect to VSS0. System reset input Connecting crystal resonator for main system clock oscillation Input - - - - - - - - - - - - Output - Output LCD controller/driver common signal output Power supply for LCD drive Meter control signal output Output - Hi-Z Output Output Output Output I/O I/O Input Input Output I/O Input Output I/O Input Output Input Function External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified Serial interface SIO2 serial data input Serial interface SIO2 serial data output Serial interface SIO2 serial clock input/output Serial interface SIO3 serial data input Serial interface SIO3 serial data output Serial interface SIO3 serial clock input/output Serial data input for asynchronous serial interface Serial data output for asynchronous serial interface Capture trigger signal input to capture register (CR00) Capture trigger signal input to capture register (CR01) Capture trigger signal input to capture register (CR02) 8-bit timer (TM2) I/O (also used for 8-bit PWM output) 8-bit timer (TM3) I/O (also used for 8-bit PWM output) 16-bit timer (TM0) prescaler signal output Clock output (for trimming of main system clock) Sound generator signal output LCD controller/driver segment signal output Input Input Input Output Input Input After Reset Input Input Input Input Input Input Input Input Input Input Alternate Function P00 to P02 P05 P04 P03 P52 P51 P50 P53 P54 P40 P41 P42 P43 P44 PCL/P60 TPO/P60 P61 - P97 to P90 P87 to P81 - - P20 to P23 P24 to P27 P30 to P33 P34 to P37 P10 to P14 - - - - - - - - - - - -
Data Sheet U14577EJ1V0DS
11
PD780851(A), 780852(A)
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, refer to Figure 3-1. Table 3-1. Types of Pin Input/Output Circuits
Pin Name Input/Output Circuit Type 8-A I/O Recommended Connection of Unused Pins
P00/INTP0 to P02/INTP2 P03/SCK2 P04/SO2 P05/SI2 P06, P07 P10/ANI0 to P14/ANI4 P20/SM11 to P23/SM14 P24/SM21 to P27/SM24 P30/SM31 to P33/SM34 P34/SM41 to P37/SM44 P40/TI00 to P42/TI02 P43/TIO2 P44/TIO3 P50/SCK3 P51/SO3 P52/SI3 P53/RxD P54/TxD P60/PCL/TPO P61/SGO P81/S19 to P87/S13 P90/S12 to P97/S5 S0 to S4 COM0 to COM3 VLCD RESET SMVDD SMVSS AVREF AVSS IC
I/O
Independently connect to VSS0 via a resistor.
9 4
Input Output
Independently connect to VDD0 or VSS0 via a resistor. Leave open.
8
I/O
Independently connect to VDD0 or VSS0 via a resistor.
5 8
5
17-G
17 18 - 2 -
Output
Leave open.
- Input - Connect to VDD0. Connect to VSS0. Connect to VDD0. Connect to VSS0. Connect directly to VSS0 or VSS1. -
12
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
Figure 3-1. Pin Input/Output Circuits (1/2)
Type 2 Type 8
VDD Data IN Output disable N-ch P-ch IN/OUT
Schmitt-triggered input with hysteresis characteristics
Type 4 VDD Data P-ch OUT Output disable N-ch
Type 8-A VDD
Pullup enable Data
P-ch VDD P-ch IN/OUT
Output disable Push-pull output that enables high-impedance output (both P-ch and N-ch are off)
N-ch
Type 5 VDD Data P-ch IN/OUT Output disable N-ch
Type 9
P-ch IN N-ch
+ -
Comparator
VREF (threshold voltage)
Input enable
Input enable
Data Sheet U14577EJ1V0DS
13
PD780851(A), 780852(A)
Figure 3-1. Pin Input/Output Circuits (2/2)
Type 17 VLC0 VLC1 P-ch N-ch P-ch SEG data N-ch VLC2 P-ch N-ch OUT Output disable Input enable VLC0 Type 18 VLC0 VLC1 P-ch N-ch P-ch SEG data N-ch P-ch N-ch OUT VLC2 P-ch N-ch VLC1 P-ch N-ch N-ch Data VDD P-ch IN/OUT Type 17-G
N-ch COM data VLC2 P-ch N-ch
P-ch
14
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
4. MEMORY SPACE
Figures 4-1 and 4-2 show the memory maps of the PD780851(A) and 780852(A). Figure 4-1. Memory Map (PD780851(A))
FFFFH Special function registers (SFRs) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits FB00 FAFF FA6D FA6C H H H H Reserved LCD display RAM 20 x 4 bits
FA59H FA58H Data memory space F800H F7FFH
Reserved
7FFFH Program area 1000H 0FFFH CALLF entry area
Internal expansion RAM 512 x 8 bits F600H F5FFH Reserved 8000H 7FFFH Program memory space 0000H
0800H 07FFH Program area 0080H 007FH CALLT table area 0040H
Internal ROM 32768 x 8 bits
003FH Vector table area 0000H
Data Sheet U14577EJ1V0DS
15
PD780851(A), 780852(A)
Figure 4-2. Memory Map (PD780852(A))
FFFFH Special function registers (SFRs) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits FB00 FAFF FA6D FA6C H H H H Reserved LCD display RAM 20 x 4 bits
FA59H FA58H Data memory space
Reserved
9FFFH Program area 1000H
F800H F7FFH Internal expansion RAM 512 x 8 bits F600H F5FFH Reserved A000H 9FFFH Program memory space 0000H
0FFFH CALLF entry area 0800H 07FFH Program area 0080H 007FH CALLT table area 0040H Internal ROM 40960 x 8 bits 003FH Vector table area 0000H
16
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 Ports The following three types of I/O ports are available. * CMOS input (Port 1): * CMOS output (Ports 2 and 3): * CMOS I/O (Ports 0, 4 to 6, 8, and 9): Total: 5 16 35 56 Table 5-1. Port Functions
Port Name Port 0 Pin Name P00 to P07 Function I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by means of software. Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 8 P10 to P14 P20 to P27 P30 to P37 P40 to P44 P50 to P54 P60, P61 P81 to P87 Input-only port. Output-only port. Output-only port. I/O port. Input/output can be specified in 1-bit units. I/O port. Input/output can be specified in 1-bit units. I/O port. Input/output can be specified in 1-bit units. I/O port. Input/output can be specified in 1-bit units. The I/O port/segment signal output function can be specified in 2-bit units by means of the LCD display control register (LCDC). I/O port. Input/output can be specified in 1-bit units. The I/O port/segment signal output function can be specified in 2-bit units by means of the LCD display control register (LCDC).
Port 9
P90 to P97
Data Sheet U14577EJ1V0DS
17
PD780851(A), 780852(A)
5.2 Clock Generator A main system clock generator is incorporated. The minimum instruction execution time can be changed. * 0.24 s/0.48 s/0.95 s/1.91 s/3.81 s (@ 8.38 MHz operation) Figure 5-1. Clock Generator Block Diagram
Prescaler X1 X2 Main system clock oscillator fX
Prescaler
Clock to peripheral hardware
fX/2 fX/22 fX/23 fX/24 STOP
Selector
Standby controller
CPU clock (fCPU)
5.3 Timer/Event Counter Six timer/event counter channels are incorporated. * 16-bit timer: * 8-bit timer: * 8-bit timer/event counter: * Watch timer: * Watchdog timer: 1 channel 1 channel 2 channels 1 channel 1 channel Table 5-2. Operations of Timer/Event Counters
16-Bit Timer TM0 8-Bit Timer TM1 8-Bit Timer/Event Counters TM2, TM3 Operation mode Function Interval timer External event counter Timer output PWM output Pulse width measurement Square wave output Division output Interrupt requests - - - - 3 inputs - 1 output 4 1 1 channel - - - - - - 2 2 channels 2 channels 2 outputs 2 outputs - 1 channel - - - - - - 2 1 1 channel - - - - - - Watch Timer Watchdog Timer
2 outputs -
18
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
Figure 5-2. Block Diagram of 16-Bit Timer 0 TM0
Selector
fX/8 fX/16 fX/32 fX/64
16-bit timer register (TM0)
INTOVF
TI02/P42
Noise eliminator
Prescaler 1, 1/2, 1/4, 1/8
Edge detector
16-bit capture register 02 (CR02) INTTM02
TI01/P41
Noise eliminator
Edge detector
16-bit capture register 01 (CR01) INTTM01
TI00/P40
Noise eliminator
Edge detector
16-bit capture register 00 (CR00) INTTM00
Output controller
TPO/PCL/P60
Internal bus
Figure 5-3. Block Diagram of 8-Bit Timer 1 TM1
Internal bus
8-bit compare register 1 (CR1)
Match fX/2 fX/24 fX/25 fX/27 fX/29 fX/211
3
INTTM1
Selector
8-bit counter 1 (TM1)
Clear
Internal bus
Data Sheet U14577EJ1V0DS
19
PD780851(A), 780852(A)
Figure 5-4. Block Diagram of 8-Bit Timer/Event Counter 2 TM2
Internal bus
8-bit compare register 2 (CR2)
Match Output controller TIO2/P43 fX/23 fX/25 fX/27 fX/28 fX/29 fX/211 INTTM2
Selector
8-bit counter 2 (TM2)
OVF
Output controller
TIO2/P43
Clear
Internal bus
Figure 5-5. Block Diagram of 8-Bit Timer/Event Counter 3 TM3
Internal bus
8-bit compare register 3 (CR3)
Match TIO3/P44 fX/24 fX/26 fX/27 fX/28 fX/210 fX/212 Output controller INTTM3
Selector
8-bit counter 3 (TM3)
OVF
Output controller
TIO3/P44
Clear
Internal bus
20
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
Figure 5-6. Watch Timer Block Diagram
Selector
Selector
fX/27 fX/211
5-bit counter
fW
INTWT
Prescaler fW 24 fW 25 fW 26 fW 27 fW 28 fW 29
Selector
INTWTI
Figure 5-7. Watchdog Timer Block Diagram
fX/28 fW fW fW 214
Prescaler fW 215 fW 216 fW 217 fW fW INTWDT maskable interrupt request RESET INTWDT non-maskable interrupt request
212 213
218 220
5.4 Clock Output Controller Clocks with the following frequencies can be output as clock output. * 65.5 kHz/131 kHz/262 kHz/524 kHz/1.04 MHz/2.09 MHz/4.19 MHz/8.38 MHz (@ 8.38 MHz operation with main system clock) Figure 5-8. Block Diagram of Clock Output Controller
fX fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27
Selector
Controller
Selector
Clock controller
Output controller
PCL/TPO/P60
Data Sheet U14577EJ1V0DS
21
PD780851(A), 780852(A)
5.5 A/D Converter An A/D converter consisting of five 8-bit resolution channels is incorporated. The following two types of functions are available. * 8-bit resolution A/D conversion * Power-fail detection function Figure 5-9. A/D Converter Block Diagram
Series resistor string ANI0/P10 Sample & hold circuit AVREF
Selector
ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14
Tap selector
Voltage comparator
AVSS Successive approximation register (SAR)
Controller
INTAD
A/D conversion result register (ADCR1)
Internal bus
Figure 5-10. Block Diagram of Power-Fail Detection Function
Multiplexer
ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14
Selector
INTAD
A/D converter
Comparator
Power-fail comparison threshold register (PFT)
Internal bus
22
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
5.6 Serial Interface Three serial interface channels are incorporated. * Serial interface UART * Serial interface SIO2 * Serial interface SIO3 Figure 5-11. Block Diagram of Serial Interface UART
Internal bus
Receive buffer register (RXB)
Direction controller
Direction controller
Transmit shift register (TXS)
RxD/P53
Receive shift register (RXS)
Transmit controller
INTST
TxD/P54 INTSER INTSR Baud rate generator fSCK
Selector
Receive controller
fX/2 to fX/28
Figure 5-12. Block Diagram of Serial Interface SIO2
Internal bus
Receive buffer register
SI2/P05
Serial I/O shift register (SIO2)
SO2/P04
SCK2/P03
Serial clock counter
INTCSI2
Serial clock controller
Selector
fX/29 to fX/211
Data Sheet U14577EJ1V0DS
23
PD780851(A), 780852(A)
Figure 5-13. Block Diagram of Serial Interface SIO3
Internal bus
SI3/P52
Serial I/O shift register (SIO3)
SO3/P51
SCK3/P50
Serial clock counter
INTCSI3
Selector
fX/22 to fX/24
Serial clock controller
5.7 LCD Controller/Driver An LCD controller/driver with following functions is incorporated. * Display mode: 1/4 duty (1/3 bias) * 15 of the segment signal outputs can be switched to I/O ports in 2-output units (P81/S19 to P87/S13 and P90/S12 to P97/S5). Figure 5-14. LCD Controller/Driver Block Diagram
Internal bus Prescaler Display data memory Timing controller Segment data selector Port output data LCDCL fX 217
Selector
fX 214 fX 215
fX 216
LCD drive voltage generator Segment driver Common driver
...
S0
......
COM0 COM1 COM2 COM3 VLCD
... S4 S5/P97 ...... S19/P81
24
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
5.8 Sound Generator The sound generator is a function for generating a buzzer sound by externally connecting a speaker. following signal is output from the sound generator. * Basic cycle output signal This is a buzzer output signal of variable frequency. Signals of 0.12 to 4.0 kHz (when fx = 8.38 MHz) can be output by setting bits 0 to 2 (SGCL0 to SGCL2) of the sound generator control register (SGCR). The basic cycle output signal can be used to change the amplitude of the 7-bit resolution PWM signal for variable amplitude, enabling the dynamics of the buzzer sound to be expressed. Figure 5-15. Sound Generator Block Diagram
Selector
fX
The
fX/2
Selector
5-bit counter
Basic cycle PWM generator
SGO/P61
Amplitude generator
Internal bus
5.9 Meter Controller/Driver The meter controller/driver is a function for driving an externally connected stepper motor or cross-coil for meter control. * 8-bit precision pulse width can be set * 8 + 1-bit precision pulse width can be set using a 1-bit addition function * Up to four 360-type meters can be driven Figure 5-16. Meter Controller/Driver Block Diagram
Internal bus
Compare register
fX fX/2
Selector
PWM pulse generator
Output controller
SMn1 (sin+) SMn2 (sin )
Remark
n = 1 to 4
Data Sheet U14577EJ1V0DS
25
PD780851(A), 780852(A)
6. INTERRUPT FUNCTION
A total of 21 interrupt sources are provided, divided into the following three types. * Non-maskable interrupts: 1 * Maskable interrupts: 19 * Software interrupts: 1 Table 6-1. Interrupt Source List
Interrupt Type Nonmaskable Maskable Default PriorityNote 1 - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Software - Interrupt Source Name INTWDT INTWDT INTAD INTOVF INTTM00 INTTM01 INTTM02 INTP0 INTP1 INTP2 INTCSI3 INTSER INTSR INTST INTTM1 INTTM2 INTTM3 INTCSI2 INTWTI INTWT BRK End of serial interface SIO3 transfer Occurrence of serial interface UART reception error End of serial interface UART reception End of serial interface UART transmission Generation of matching signal of 8-bit timer register and capture register (CR1) Generation of matching signal of 8-bit timer register and capture register (CR2) Generation of matching signal of 8-bit timer register and capture register (CR3) End of serial interface SIO2 transfer Watch timer overflow Reference time interval signal of watch timer Execution of BRK instruction - Internal Trigger Watchdog timer overflow (with non-maskable interrupt selected) Watchdog timer overflow (with interval timer selected) End of A/D conversion 16-bit timer overflow TI00 valid edge detection TI01 valid edge detection TI02 valid edge detection Pin input edge detection External 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H 0028H 003EH (E) (B) (D) (C) Internal/ External Internal Vector Table Address 0004H Basic ConfigurationNote 2 (A) (B)
Notes 1. Default priority is the priority order when several maskable interrupt requests are generated at the same time. 0 is the highest priority and 18 is the lowest. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1.
26
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
Figure 6-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt
Internal bus
Interrupt request
Priority controller
Vector table address generator
Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
PR
ISP
Interrupt request
IF
Priority controller
Vector table address generator
Standby release signal
(C) Internal maskable interrupt (16-bit timer capture input)
Internal bus
Prescaler mode register (PRM0)
MK
IE
PR
ISP
Interrupt request
Sampling clock
Edge detector
IF
Priority controller
Vector table address generator
Standby release signal
Data Sheet U14577EJ1V0DS
27
PD780851(A), 780852(A)
Figure 6-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except 16-bit timer capture input)
Internal bus
External interrupt edge enable register (EGP, EGN)
MK
IE
PR
ISP
Interrupt request
Edge detector
IF
Priority controller
Vector table address generator
Standby release signal
(E) Software interrupt
Internal bus
Interrupt request
Priority controller
Vector table address generator
IF: IE:
Interrupt request flag Interrupt enable flag
ISP: In-service priority flag MK: Interrupt mask flag PR: Priority specification flag
28
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
7. STANDBY FUNCTION
The following two types of standby function are available for further reduction of system current consumption. * HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be reduced by intermittent operation by combining this mode with the normal operating mode. * STOP mode: In this mode, oscillation of the main system clock is stopped. All the operations performed on the main system clock are suspended, resulting in extremely small power consumption. Figure 7-1. Standby Function
Main system clock operation HALT instruction Interrupt request
Interrupt request
STOP instruction
Main system clock oscillation stopped
STOP mode
Clock supply to CPU halted, oscillation maintained
HALT mode
8. RESET FUNCTION
The following two reset methods are available. * External reset by RESET signal input * Internal reset by watchdog timer runaway time detection
Data Sheet U14577EJ1V0DS
29
PD780851(A), 780852(A)
9. INSTRUCTION SET
(1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd Operand 1st Operand [HL+ Byte]
#byte
A
rNote
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + B] [HL + C]
$addr16
1
None
A
ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
ROR ROL RORC ROLC
r
MOV
MOV ADD ADDC SUB SUBC AND OR XOR CMP
INC DEC
B, C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW [DE] [HL] [HL + byte] [HL + B] [HL + C] X C MOV MOV MOV MOV MOV MOV MOV MOV
DBNZ DBNZ INC DEC
PUSH POP ROR4 ROL4
MULU DIVUW
Note Except r = A
30
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
(2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand # word 1st Operand AX ADDW SUBW CMPW MOVW MOVW MOVW MOVW MOVWNote MOVW MOVW MOVW MOVW MOVW XCHW MOVW MOVW MOVW MOVW AX
rpNote
sfrp
saddrp
!addr16
SP
None
rp sfrp saddrp !addr16 SP
INCW, DECW PUSH, POP
Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand A.bit 1st Operand A.bit MOV BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1 sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
CY
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
(4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand 1st Operand Basic instruction Compound instruction BR AX !addr16 CALL BR !addr11 CALLF [addr5] CALLT $addr16 BR, BC, BNC, BZ, BNZ BT, BF BTCLR DBNZ
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
Data Sheet U14577EJ1V0DS
31
PD780851(A), 780852(A)
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD AVREF AVSS SMVDD SMVSS Input voltage Output voltage VI VO1 P00 to P07, P40 to P44, P50 to P54, P60, P61, P81 to P87, P90 to P97, RESET P20 to P27, P30 to P37 P10 to P14 Analog input pin SMVDD = VDD Conditions Ratings -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to +6.5 -0.3 to +0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.5 to SMVDD + 0.7 AVSS - 0.3 to AVREF + 0.3 -10 -15 -30 -45 -135 -45 -135 20 Unit V V V V V V V
VO2 Analog input voltage Output current, high VAN IOH
V V mA
Per pin (P00 to P07, P40 to P44, P50 to P54, P60, P81 to P87, P90 to P97) Total for P00 to P07, P40 to P44, P50 to P54, P60, P81 to P87, P90 to P97 P61 Per pin (P20 to P27) Total for P20 to P27 Per pin (P30 to P37) Total for P30 to P37
mA
mA mA mA mA mA mA
Output current, low
IOL
Per pin (P00 to P07, P40 to P44, P50 to P54, P60, P81 to P87, P90 to P97) Total for P00 to P07, P40 to P44, P50 to P54, P60, P81 to P87, P90 to P97 P61 Per pin (P20 to P27) Total for P20 to P27 Per pin (P30 to P37) Total for P30 to P37
50
mA
30 45 135 45 135 -40 to +85 -65 to +150
mA mA mA mA mA C C
Operating ambient temperature Storage temperature
TA Tstg
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
32
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance Output capacitance Symbol CIN CIO COUT f = 1 MHz Unmeasured pins returned to 0 V. f = 1 MHz Unmeasured pins returned to 0 V. P00 to P07, P40 to P44, P50 to P54, P60, P81 to P87, P90 to P97 P20 to P27, P30 to P37, P61 Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
CSM
40
pF
Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 4.0 to 5.5 V)
Resonator Ceramic resonator Recommended Circuit Parameter Oscillation frequency (fX)Note 1 Conditions VDD = Oscillation voltage range OSCM = 00H OSCM = 80H MIN. 4.0 4.0 TYP. MAX. 8.38 4.19 4 Unit MHz MHz ms
X2
X1 IC
C2
C1
Oscillation stabilization timeNote 2
After VDD reaches oscillation voltage range MIN.
Crystal resonator
X2
X1 IC
Oscillation frequency (fX)Note 1
VDD = Oscillation voltage range
OSCM = 00H OSCM = 80H
4.0 4.0
8.38 4.19 10
MHz MHz ms
C2
C1
Oscillation stabilization timeNote 2
After VDD reaches oscillation voltage range MIN.
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Caution When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator.
Data Sheet U14577EJ1V0DS
33
PD780851(A), 780852(A)
Recommended Oscillator Constant Main system clock: Ceramic resonator (-40 to +85C) - 8.38 MHz oscillation mode (OSCM = 00H)
Manufacturer Part Number Frequency Recommended (MHz) Circuit Constant Oscillation Voltage Range MIN. (V) 4.0 MAX. (V) 5.5 On-chip capacitor Remarks
C1 C2 (pF)Note (pF)Note Murata Mfg. Co., Ltd CSTLS4M00G56A-B0 CSTCR4M00G55A-R0 CSTLS4M19G56A-B0 CSTCR4M19G55A-R0 CSTLS5M00G53A-B0 CSTCR5M00G53A-R0 CSTLS8M00G53A-B0 CSTCC8M00G53A-R0 CSTLS8M38G53A-B0 CSTCC8M38G53A-R0 4.0 4.0 4.194 4.194 5.0 5.0 8.0 8.0 8.388 8.388 47 39 47 39 15 15 15 15 15 15 47 39 47 39 15 15 15 15 15 15
Note Indicates the capacitance of the on-chip capacitor. 4.19 MHz oscillation mode (OSCM = 80H)
Manufacturer Part Number Frequency Recommended (MHz) Circuit Constant Oscillation Voltage Range MIN. (V) 4.0 MAX. (V) 5.5 On-chip capacitor Remarks
C1 C2 (pF)Note (pF)Note Murata Mfg. Co., Ltd CSTLS4M00G53A-B0 CSTCR4M00G53A-R0 CSTLS4M19G53A-B0 CSTCR4M19G53A-R0 4.0 4.0 4.194 4.194 15 15 15 15 15 15 15 15
Note Indicates the capacitance of the on-chip capacitor.
34
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
DC Characteristics (TA = -40 to +85C, VDD = 4.0 to 5.5 V)
Parameter Output current, high Symbol IOH1 Conditions P00 to P07, P40 to P44, P50 to P54, P60, P81 to P87, P90 to P97 P00 to P07, P40 to P44, P50 to P54, P60, P81 to P87, P90 to P97 Per pin Total Per pin Total 0.7VDD 0.7VDD 0.8VDD 0 0 0 IOH = -1 mA VDD - 1.0 MIN. TYP. MAX. -5 -10 10 20 VDD VDD VDD 0.3VDD 0.3VDD 0.2VDD VDD Unit mA mA mA mA V V V V V V V
Output current, low
IOL1
Input voltage, high
VIH1 VIH2 VIH3
P10 to P14, P51, P54, P60, P61, P81 to P87, P90 to P97 P00 to P07, P40 to P44, P50, P52, P53 RESET P10 to P14, P51, P54, P60, P61, P81 to P87, P90 to P97 P00 to P07, P40 to P44, P50, P52, P53 RESET P00 to P07, P40 to P44, P50 to P54, P60, P81 to P87, P90 to P97 P20 to P27, P30 to P37
Input voltage, low
VIL1 VIL2 VIL3
Output voltage, high
VOH1
VOH2
IOH = -27 mA (TA = 85C) IOH = -30 mA (TA = 25C) IOH = -40 mA (TA = -40C)
VDD - 0.5 VDD - 0.5 VDD - 0.5 VDD - 0.5
VDD - 0.07 VDD - 0.07 VDD - 0.07
V V V V
VOH3 Output voltage, low VOL1
P61 P00 to P07, P40 to P44, P50 to P54, P60, P81 to P87, P90 to P97 P20 to P27, P30 to P37
IOH = -20 mA IOL = 1.6 mA
0.4
V
VOL2
IOL = 27 mA (TA = 85C) IOL = 30 mA (TA = 25C) IOL = 40 mA (TA = -40C)
0.07 0.07 0.07
0.5 0.5 0.5 0.5 3
V V V V
VOL3 Input leakage current, high ILIH1
P61 P00 to P07, P10 to P14, P40 to P44, P50 to P54, P60, P61, P81 to P87, P90 to P97 P00 to P07, P10 to P14, P40 to P44, P50 to P54, P60, P61, P81 to P87, P90 to P97 VOUT = VDD
IOL = 20 mA VIN = VDD
A
Input leakage current, low
ILIL1
VIN = 0 V
-3
A
Output leakage current, high Output leakage current, low Software pull-up resistor
ILOH
3 -3
A A
k
ILOL
VOUT = 0 V
R
VIN = 0 V, P00 to P07
10
30
100
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14577EJ1V0DS
35
PD780851(A), 780852(A)
DC Characteristics (TA = -40 to +85C, VDD = 4.0 to 5.5 V)
Parameter Power supply currentNote 1 Symbol IDD1 Conditions 8.38 MHz oscillation operating mode 4.19 MHz oscillation operating mode IDD2 8.38 MHz oscillation HALT mode 4.19 MHz oscillation HALT mode IDD3 STOP mode
Note 2 Note 2
MIN.
TYP. 7 3.5 0.8 0.5 1.0
MAX. 21 10.5 1.6 1.0 30
Unit mA mA mA mA
Note 2, 3
Note 3
A
Notes 1. Refers to the current flowing to the CPU, peripheral functions (internal circuits), oscillator, and VDD pin. The current flowing to the series resistor string of an A/D converter, on-chip pull-up resistors, LCD division resistor, sound generator (SGO/P61), and meter controller/driver (SM11/P20 to SM14/P23, SM21/P24 to SM24/P27, SM31/P30 to SM34/P33, SM41/P34 to SM44/P37) is not included. 2. High-speed mode operation (when the processor clock control register (PCC) is set to 00H) 3. Operation when the oscillator mode register (OSCM) is set to 80H Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. LCD Controller/Driver Characteristics (TA = -40 to +85C, VDD = 4.0 to 5.5 V) 1/3 bias mode
Parameter LCD drive voltage LCD output voltage deviationNote (Common) LCD output voltage deviationNote (Segment) LCD division resistance current ILCD 3.0 V VLCD < VDD 50 260 VODS IO = 1 A Symbol VLCD VODC IO = 5 A 3.0 V VLCD VDD VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 0 0.2 V Conditions MIN. 3.0 0 TYP. MAX. VDD 0.2 Unit V V
A
Note The voltage deviation is the difference between the output voltage and the ideal value of segment and common outputs (VLCDn: n = 0, 1, 2). Since pins to which a reference voltage (VLCD1 and VLCD2) is applied do not exist in the PD780851(A),780852(A), the difference between the segment/common output voltage generated by the internal division resistance and the ideal reference potential (VDD to 1/3VDD) is regarded as the voltage deviation.
36
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 4.0 to 5.5 V)
Parameter Cycle time (MIN. instruction execution time) TI00 to TI02 input high-/low-level width TIO2, TIO3 input frequency TIO2, TIO3 input high-/low-level width Interrupt request input high-/low-level width RESET low-level width Symbol TCY Conditions Operating with main system clock MIN. 0.238 TYP. MAX. 8 Unit
s
tTIH2, tTIL2
At capture trigger TI00/P40 to TI02/P42
3/fSAMNote
s
fTI5
TIO2/P43, TIO3/P44
0
4
MHz
tTIH5, tTIL5
TIO2/P43, TIO3/P44
100
ns
tINTH, tINTL
INTP0 to INTP2
1
s s
tRSL
10
Note Selection of fSAM = fX/8, fX/16, fX/32, fX/64 is possible with bits 0 and 1 (PRM00, PRM01) of the prescaler mode register (PRM0).
TCY vs. VDD (main system clock operation)
10.0 fX = 4.00 MHz, PCC = 04H 5.0
Cycle time TCY [s]
Guaranteed operation range 1.0
0.5
fX = 8.38 MHz, PCC = 00H
0.1
0
1.0
2.0
3.0
4.0
5.0 5.5
6.0
Supply voltage VDD [V]
Data Sheet U14577EJ1V0DS
37
PD780851(A), 780852(A)
(2) Serial interface (TA = -40 to +85C, VDD = 4.0 to 5.5 V) (a) UART mode (Dedicated baud rate generator output)
Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 130.9 Unit kbps
(b) 3-wire serial I/O mode (SIO3)
Parameter SCK3 cycle time SCK3 high-/low-level width Symbol tKCY1 tKH1, tKL1 Internal clock selected External clock selected SI3 setup time (to SCK3) SI3 hold time (from SCK3) Delay time from SCK3 to SO3 output tSIK1 tKSI1 tKSO1 C = 100 pF
Note
Conditions
MIN. 800 tKCY1/2 - 50 400 100 400
TYP.
MAX.
Unit ns ns ns ns ns
300
ns
Note C is the load capacitance of the SCK3 and SO3 output lines. (c) 3-wire serial I/O mode (SIO2)
Parameter SCK2 cycle time SCK2 high-/low-level width Symbol tKCY2 tKH2, tKL2 Internal clock selected External clock selected SI2 setup time (to SCK2) SI2 hold time (from SCK2) Delay time from SCK2 to SO2 output tSIK2 tKSI2 tKSO2 C = 100 pF
Note
Conditions
MIN. 800 tKCY1/2 - 50 400 100 400
TYP.
MAX.
Unit ns ns ns ns ns
300
ns
Note C is the load capacitance of the SCK2 and SO2 output lines. AC Timing Test Points (excluding X1 input)
0.8VDD Test points 0.2VDD
0.8VDD 0.2VDD
Clock Timing
1/fX tXL tXH VDD 0.5 V
X1 input
0.4 V
38
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
TI Timing
tTIL2 tTIH2
TI00 to TI02
1/fTI5 tTIL5 tTIH5
TIO2, TIO3
Serial Transfer Timing 3-wire serial I/O mode
tKCY1, 2 tKL1, 2 tKH1, 2
SCK
tSIK1, 2
tKSI1, 2
SI
Input data
tKSO1, 2
SO
Output data
Data Sheet U14577EJ1V0DS
39
PD780851(A), 780852(A)
Sound Generator Characteristics (TA = -40 to +85C, VDD = 4.0 to 5.5 V)
Parameter Sound generator input frequency SGO output rise time SGO output fall time Symbol fSG1 tr tf C = 100 pF C = 100 pF
Note
Conditions
MIN.
TYP.
MAX. 4.19
Unit MHz ns ns
80 80
200 200
Note
Note C is the load capacitance of the SGO output line. Sound Generator Output Timing
tr tf 0.9VDD SGO 0.1VDD
Meter Controller/Driver Characteristics (TA = -40 to +85C, VDD = 4.0 to 5.5 V)
Parameter Meter controller input frequency PWM output rise time PWM output fall time Symmetry performance
Note 3
Symbol fMCNote 1 tr tf HSPmn C = 100 pF C = 100 pF
Note 2
Conditions
MIN.
TYP.
MAX. 4.19
Unit MHz ns ns mV
80 80
200 200 50
Note 2
IOH = -30 mA HSPmn = I VOH (SMmn) max - VOH (SMmn) min I
LSPmn
IOL = 30 mA LSPmn = I VOL (SMmn) max - VOL (SMmn) min I
50
mV
Notes 1. Source clock of the free-running counter. 2. C is the load capacitance of the PWM output line. 3. Indicates the dispersion of 16 PWM output voltages. Remark m = 1 to 4, n = 1 to 4
Meter Controller/Driver Output Timing
tr tf 0.9VDD SMmn 0.1VDD
Remark
m = 1 to 4, n = 1 to 4
40
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
A/D Converter Characteristics (TA = -40 to +85C, AVREF = VDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall error
Note
Symbol
Conditions
MIN.
TYP.
MAX. 8 0.6
Unit bit %FSR
Conversion time Analog input voltage Reference voltage Resistance between AVREF and AVSS
tCONV VIAN AVREF IADD A/D converter operating (ADCS1 = 1) A/D converter not operating (ADCS1 = 0)
14.0 AVSS 4.0 1.0 1.0 AVREF + 0.3 VDD 2.0 10
s
V V mA
A
Note Excludes quantization error (1/2 LSB). This value is indicated as a ratio to the full-scale value. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention supply voltage Data retention power supply current Release signal set time Oscillation stabilization wait time Symbol VDDDR IDDDR tSREL tWAIT Release by RESET Release by interrupt request
12 14 17
Conditions
MIN. 2.0
TYP.
MAX. 5.5
Unit V
VDDDR = 2.0 V 0
0.1
10
A s
2 /fX Note
17
s s
Note Selection of 2 /fX and 2 /fX to 2 /fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Data Retention Timing (STOP mode release by RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operating mode
VDD VDDDR
tSREL
STOP instruction execution
RESET tWAIT
Data Sheet U14577EJ1V0DS
41
PD780851(A), 780852(A)
Data Retention Timing (Standby release signal: STOP mode release by interrupt request signal)
HALT mode STOP mode Data retention mode Operating mode
VDD VDDDR
STOP instruction execution
tSREL
Standby release signal (interrupt request)
tWAIT
Interrupt Request Input Timing
tINTL tINTH
INTP0 to INTP2
RESET Input Timing
tRSL
RESET
42
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
11. PACKAGE DRAWING
80-PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end S C D R Q
80 1
21 20
F J G P H I
M
K S N S L M
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.200.20 14.000.20 14.000.20 17.200.20 0.825 0.825 0.320.06 0.13 0.65 (T.P.) 1.600.20 0.800.20 0.17 +0.03 -0.07 0.10 1.400.10 0.1250.075 3 +7 -3 1.70 MAX. P80GC-65-8BT-1
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
Data Sheet U14577EJ1V0DS
43
PD780851(A), 780852(A)
12. RECOMMENDED SOLDERING CONDITIONS
The PD780851(A), 780852(A) should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 12-1. Surface Mounting Type Soldering Conditions xxx-8BT: 80-pin plastic QFP (14 x 14) PD780851GC(A)-xxx xxx xxx-8BT: 80-pin plastic QFP (14 x 14) PD780852GC(A)-xxx xxx
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-00-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less Soldering bath temperature: 260C or less, Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature)
VPS
VP15-00-2
Wave soldering
WS60-00-1
Partial heating
Pin temperature: 300C or less, Time: 3 seconds max. (per pin row)
-
Caution Do not use different soldering methods together (except for partial heating).
44
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD780851(A) and 780852(A). Also refer to (6) Cautions on Using Development Tools. (1) Software Package
SP78K0 Software Package common to 78K/0 Series
(2) Language Processing Software
RA78K0 CC78K0 DF780852 CC78K0-L Assembler package common to 78K/0 Series C compiler package common to 78K/0 Series Device file for PD780852 Subseries C compiler library source file common to 78K/0 Series
(3) Flash Memory Writing Tools
Flashpro III (Part No. FL-PR3, PG-FP3) Dedicated flash programmer for microcomputers incorporating flash memory
(4) Debugging Tools
IE-78K0-NS(-A) IE-70000-MC-PS-B IE-78K0-NS-PA IE-780852-NS-EM4, IE-78K0-NS-P04 IE-70000-98-IF-C Interface adapter necessary when using PC-9800 series PC (except notebook type) as host machine (C bus supported) PC card and interface cable necessary when using notebook PC as host machine (PCMCIA socket supported) Interface adapter necessary when using IBM PC/ATTM compatible as host machine (ISA bus supported) Adapter necessary when using personal computer incorporating PCI bus as host machine Emulation probe for 80-pin plastic QFP (GC-8BT type) System simulator common to 78K/0 Series Integrated debugger for IE-78K0-NS Device file for PD780852 Subseries In-circuit emulator common to 78K/0 Series Power supply unit for IE-78K0-NS Performance board to enhance/expand functions of IE-78K0-NS Probe board and I/O board used to emulate PD780852 Subseries products
IE-70000-CD-IF-A
IE-70000-PC-IF-C
IE-70000-PCI-IF-A NP-80GC-TQ SM78K0 ID78K0-NS DF780852
Data Sheet U14577EJ1V0DS
45
PD780851(A), 780852(A)
(5) Real-time OS
RX78K0 MX78K0 Real-time OS for 78K/0 Series OS for 78K/0 Series
(6) Cautions on Using Development Tools * The ID78K0-NS and SM78K0 are used in combination with the DF780852. * The CC78K0 and RX78K0 are used in combination with the RA78K0 and DF780852. * The FL-PR3 and NP-80GC-TQ are products made by Naitou Densei Machidaseisakusho Co., Ltd. (TEL +8145-475-4191). * For third party development tools, see the Single-Chip Microcontroller Development Tool Selection Guide (U11069E). * The host machine and OS suitable for each software are as follows:
Host Machine [OS] Software RA78K0 CC78K0 ID78K0-NS SM78K0 RX78K0 MX78K0 PC PC-9800 series [Japanese WindowsTM] IBM PC/AT and compatibles [Japanese/English Windows] Note
Note
EWS HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, SolarisTM] - -

Note
Note
Note DOS-based software
46
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. * Documents Related to Devices
Document Name Document No. U14581E This document U14576E U12326E
PD780852 Subseries User's Manual PD780851(A), 780852(A) Data Sheet PD78F0852 Data Sheet
78K/0 Series User's Manual Instructions
* Documents Related to Development Tools (User's Manuals)
Document Name RA78K0 Assembler Package Operation Language Structured Assembly Language CC78K0 C Compiler Operation Language PG-FP3 Flash Memory Programmer IE-78K0-NS In-Circuit Emulator IE-78K0-NS-A In-Circuit Emulator IE-780852-NS-EM4, IE-78K0-NS-P04 SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later Windows Based SM78K Series System Simulator Ver. 2.10 or Later Operation External Part User Open Interface Specifications Operation Operation Document No. U11802E U11801E U11789E
U11517E U11518E U13502E U13731E U14889E To be prepared U14611E U15006E
ID78K0-NS Integrated Debugger Ver. 2.00 or Later Windows Based ID78K0-NS, ID78K0S-NS Integrated Debugger Ver. 2.20 or Later Windows Based ID78K0 Integrated Debugger Windows Based
U14379E U14910E
Guide Reference
U11649E U11539E
Data Sheet U14577EJ1V0DS
47
PD780851(A), 780852(A)
* Documents Related to Embedded Software (User's Manuals)
Document Name 78K/0 Series Real-Time OS Fundamental Installation 78K/0 Series OS MX78K0 Fundamental Document No. U11537E U11536E U12257E
* Other Related Documents
Document Name SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769E C10535E C11531E C10983E C11892E
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
48
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
[MEMO]
Data Sheet U14577EJ1V0DS
49
PD780851(A), 780852(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
FIP and IEBus are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS and Solaris are trademarks of Sun Microsystems, Inc.
50
Data Sheet U14577EJ1V0DS
PD780851(A), 780852(A)
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
J01.2
Data Sheet U14577EJ1V0DS
51
PD780851(A), 780852(A)
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is current as of October, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
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