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19-3151; Rev 1; 7/04
14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC
General Description
The MAX1338 14-bit, analog-to-digital converter (ADC) offers four simultaneously sampled, fully differential input channels, with independent track-and-hold (T/H) circuitry for each channel. The input channels are individually software programmable for input ranges of 10V, 5V, 2.5V, and 1.25V. The input channels feature fault tolerance to 17V. The internal T/H circuits have a 16ns aperture delay and 100ps aperture-delay matching. A 14-bit parallel bus provides the conversion result with a maximum per-channel output rate of 150ksps (600ksps for all four channels). The MAX1338 has an on-board oscillator and 2.5V internal reference. An external clock and/or reference can also be used. The MAX1338 operates from a +5V supply for analog inputs and digital core. The device operates from a +2.7V to +5.25V supply for the digital I/O lines. The MAX1338 features two power-saving modes: standby mode and shutdown mode. Standby mode allows rapid wake-up and reduces quiescent current to 4mA (typ), and shutdown mode reduces sleep current to less than 10A (typ). The MAX1338 is available in an 8mm x 8mm x 0.8mm, 56-pin, thin QFN package. The device operates over the extended -40C to +85C temperature range. 150ksps Sample Rate per Channel All Four Input Channels Simultaneously Sampled 16ns Aperture Delay 100ps Aperture-Delay Matching Channel-Independent Software-Selectable Input Range: 10V, 5V, 2.5V, 1.25V 17V Fault-Tolerant Inputs Dynamic Performance at 10kHz Input SNR: 77dB SINAD: 76dB SFDR: 98dBc THD: -83dBc DC Performance INL: 2 LSB DNL: 1 LSB Offset Error: 4 LSB Gain Error: 0.1% FSR 14-Bit Parallel Interface Internal Clock and Reference Voltage +5V Analog and Digital Supplies +2.7V to +5.25V Digital I/O Supply 56-Pin Thin QFN Package (8mm x 8mm x 0.8mm)
Features
MAX1338
Applications
Multiple-Channel Data Recorders Vibration Analysis Motor Control: 3-Phase Voltage, Current, and Power Measurement Optical Communication Equipment
Ordering Information
PART MAX1338ETN TEMP RANGE -40C to +85C PIN-PACKAGE 56 Thin QFN-EP*
*EP = Exposed pad.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
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14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V DVDD to DGND.........................................................-0.3V to +6V DRVDD to DRGND ....................................................-0.3V to +6V AVDD to DVDD .......................................................-0.3V to +0.3V DGND to DRGND ..................................................-0.3V to +0.3V AGND to DGND.....................................................-0.3V to +0.3V AGND to DRGND ..................................................-0.3V to +0.3V AIN0+, AIN0-, AIN1+, AIN1-, AIN2+, AIN2-, AIN3+, AIN3- to AGND .....................................................-17V to +17V D0-D13 to DRGND................................-0.3V to (DRVDD + 0.3V) REFADC, REFP1, REFP2, REFN1, REFN2, COM1, COM2 to AGND....................................................-0.3V to (AVDD + 0.3V) INTCLK/EXTCLK to AGND.......................-0.3V to (AVDD + 0.3V) CS, RD, WR, CONVST, to DRGND........-0.3V to (DRVDD + 0.3V) SHDN, STANDBY, CLK, EOC, EOLC to DRGND ................................-0.3V to (DRVDD + 0.3V) Maximum Current into Any Pin .........................................50mA Continuous Power Dissipation (TA = +70C) 56-Pin Thin QFN (derate 31.3mW /C above +70C)....2500mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Lead Temperature (soldering, 10s) .................................+300C Junction to Ambient Thermal Resistance JA ..................32C/W Junction to Case Thermal Resistance JC .........................2C/W
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = 10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0F and 0.1F from COM1 to AGND, 0.1F from REFP1 to AGND, 0.1F from REFN1 to AGND, 1.0F from REFP1 to REFN1. Typical values are at TA = +25C. TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset-Error Temperature Coefficient Offset-Error Matching Gain Error Channel Gain-Error Matching Gain-Error Temperature Coefficient Sampling Rate Per Channel Signal-to-Noise Ratio Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Isolation ANALOG INPUTS (AIN_) Range set bits = (0,0) Input Differential Voltage Range Range set bits = (0,1) Range set bits = (1,0) Range set bits = (1,1) -10 -5 -2.5 -1.25 +10 +5 +2.5 +1.25 V SNR SINAD THD SFDR Offset nulled (Notes 1, 2) Offset nulled Offset nulled N INL DNL (Note 1) No missing codes (Note 1) (Note 1) 14 1 0.25 4 5 10 0.1 20 10 0.35 3 1 16 Bits LSB LSB LSB ppm/C LSB %FSR LSB ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC PERFORMANCE (at fIN = 10kHz, AIN = -0.2dBFS) Simultaneous on all channels (Note 1) (Note 1) (Note 1) Range 0 (Note 1) (Note 1) 85 80 75 74 77 76 -83 -80 150 ksps dB dB dBc dBc dB
2
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14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = 10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0F and 0.1F from COM1 to AGND, 0.1F from REFP1 to AGND, 0.1F from REFN1 to AGND, 1.0F from REFP1 to REFN1. Typical values are at TA = +25C. TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS Range set bits = (0,0) Input Common-Mode Range Range set bits = (0,1) Range set bits = (1,0) Range set bits = (1,1) Input Resistance Input Capacitance Small-Signal Bandwidth Full-Power Bandwidth INTERNAL REFERENCE (REFADC) Output Voltage Differential Reference Voltage Output-Voltage Temperature Coefficient Load Regulation EXTERNAL REFERENCE REFADC Voltage Input Range REFADC Input Current REFADC Input Resistance REFADC Input Capacitance TRACK/HOLD (T/H) Aperture Delay Aperture-Delay Matching Aperture Jitter tAJ (Note 1) 0.7 x AVDD 0.3 x AVDD 0.7 x DRVDD 0.3 x DRVDD 50 CIN 15 CLOCK-SELECT INPUT (INTCLK/EXTCLK) Input-Voltage High Input-Voltage Low VIH VIL V V tAD (Note 1) 16 100 50 ns ps psRMS RREF (Note 3) 2.0 -250 5 15 2.5 3.0 +250 V A k pF REFP- REFN 2.475 2.5 2.5 50 5 2.525 V V ppm/C V/mA SSBW FPBW (Note 1) (Note 1) All settings MIN -5 -2.5 -1.25 -0.625 6.25 15 1 75 TYP MAX +5 +2.5 +1.25 +0.625 k pF MHz kHz V UNITS
MAX1338
DIGITAL INTERFACE AND CONTROL INPUTS (CS, RD, WR, CONVST, SHDN, CLK, STANDBY) Input-Voltage High Input-Voltage Low Input Hysteresis Input Capacitance VIH VIL V V mV pF
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14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = 10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0F and 0.1F from COM1 to AGND, 0.1F from REFP1 to AGND, 0.1F from REFN1 to AGND, 1.0F from REFP1 to REFN1. Typical values are at TA = +25C. TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER Input Current SYMBOL IIN CONDITIONS VIN = 0 or DRVDD DRVDD - 0.6 0.4 DRVDD 0.6 0.4 1 RD = 1 or CS = 1 VIH VIL 50 CIN IIN VIN = 0 or DRVDD DRVDD 0.6 0.4 1 15 AVDD DVDD DRVDD AIDD SHDN = 1 STANDBY = 1, SHDN = 0 Digital Supply Current DIDD SHDN = 1 STANDBY = 1, SHDN = 0 Digital Driver Supply Current Analog Power-Supply Rejection DRIDD SHDN = 1 STANDBY = 1, SHDN = 0 4.75V to 5.25V (Note 1) 4.75 4.75 2.70 41 Analog Supply Current 0.005 4.2 0.001 0.001 0 0 75 5 5 5.25 5.25 5.25 60 0.1 5 3 0.05 0.05 3 0.05 0.05 dB mA mA mA 15 1 0.7 x DRVDD 0.3 x DRVDD 15 MIN TYP MAX 1 UNITS A
DIGITAL INTERFACE AND CONTROL OUTPUTS (EOC, EOLC) Output-Voltage High Output-Voltage Low PARALLEL DIGITAL I/O (D0-D7) Output-Voltage High Output-Voltage Low Leakage Current Tristate Output Capacitance Input-Voltage High Input-Voltage Low Input Hysteresis Input Capacitance Input Current VOH VOL Sourcing 0.8mA Sinking 1.6mA V V A pF V V mV pF A VOH VOL Sourcing 0.8mA Sinking 1.6mA V V
PARALLEL DIGITAL OUTPUTS (D8-D13) Output-Voltage High Output-Voltage Low Leakage Current Tristate Output Capacitance POWER SUPPLIES Analog Supply Voltage Digital Supply Voltage Parallel Digital I/O Supply Voltage V V V VOH VOL Sourcing 0.8mA Sinking 1.6mA V V A pF
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14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = 10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0F and 0.1F from COM1 to AGND, 0.1F from REFP1 to AGND, 0.1F from REFN1 to AGND, 1.0F from REFP1 to REFN1. Typical values are at TA = +25C. TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL Internal clock Time to First Conversion Result tEOC1 External clock Internal clock Time to Subsequent Conversions tNEXT External clock Internal clock External clock 0.2 0.1 30 30 30 30 0 0 0 0 Figure 1 Figure 1 5 20 20 20 Internal clock EOC Pulse-Width Low Wake-Up Time From Standby Wake-Up Time From Shutdown All bypass capacitors discharged tEOC External clock 180 200 1 7 5 30 30 CONDITIONS MIN 2.9 TYP 3.2 16 600 3 MAX 3.5 UNITS s CLK Cycles ns CLK Cycles s ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK Cycle s ns
MAX1338
TIMING CHARACTERISTICS (Figures 4, 5, and 6)
CONVST Pulse-Width Low CS Pulse Width RD Pulse-Width Low RD Pulse-Width High WR Pulse-Width Low CS to WR Setup Time WR to CS Hold Time CS to RD Setup Time RD to CS Hold Time Data Access Time (RD Low to Valid Data) Bus Relinquish Time (RD High to D_ High-Z) CLK Rise to End-of-Conversion (EOC) Rise/Fall Delay CLK Rise to End-of-LastConversion (EOLC) Fall Delay CONVST Rise to EOLC Fall Delay
tCONVST tCS tRDL tRDH tWRL tCTW tWTC tCTR tRTC tACC tREQ tEOCD tEOLCD tCVEOLCD
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14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = 10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0F and 0.1F from COM1 to AGND, 0.1F from REFP1 to AGND, 0.1F from REFN1 to AGND, 1.0F from REFP1 to REFN1. Typical values are at TA = +25C. TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER EOC Fall to RD Fall Setup Time EOLC Fall to RD Fall Setup Time Input Data Setup Time Input Data Hold Time External CLK Period External CLK High Period External CLK Low Period External Clock Frequency Internal Clock Frequency CONVST High to CLK Edge Quiet Time SYMBOL tEOCRD tEOLCRD tDTW tWTD tCLK tCLKH tCLKL fCLK fINT tCNTC tQUIET Logic sensitive to rising edges Logic sensitive to rising edges (Note 4) CONDITIONS MIN 0 0 10 10 166 60 60 1 5.0 30 600 5.25 6 5.5 200 TYP MAX UNITS ns ns ns ns ns ns ns MHz MHz ns ns
Note 1: Note 2: Note 3: Note 4:
See definition for this parameter in the Definitions section. Differential reference voltage (REFP-REFN) error nulled. This is the load the MAX1338 presents to an external reference at REFADC. Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CONVST to the falling edge of EOLC to a maximum of 0.25ms.
1.6mA
TO OUTPUT PIN 50pF
1.6V
0.8mA
Figure 1. Load Circuit for Data Access Time and BusRelinquish Time
6
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14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
Typical Operating Characteristics
(AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = 10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0F and 0.1F from COM1 to AGND, 0.1F from REFP1 to AGND, 0.1F from REFN1 to AGND, 1.0F from REFP1 to REFN1.)
INTEGRAL NONLINEARITY vs. OUTPUT CODE
MAX1338 toc01
DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE
MAX1338 toc02
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1338 toc03
0.8 0.6 0.4
0.6 0.4 0.2 DNL (LSB) 0 -0.2 -0.4 -0.6 -8192
0 -1 OFFSET ERROR (LSB) CHANNEL 0 -2 -3 -4 -5 -6 CHANNEL 2 CHANNEL 1 CHANNEL 3
INL (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -8192 -4096 0 4096 8192
-4096
0
4096
8192
4.75
4.85
4.95
5.05
5.15
5.25
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
AVDD (V)
OFFSET ERROR vs. TEMPERATURE
MAX1338 toc04
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1338 toc05
GAIN ERROR vs. TEMPERATURE
MAX1338 toc06
15 10 5 0 -5 -10 -15 -40 -15 10 35 60
-0.13 -0.14 -0.15 GAIN ERROR (%FS) CH1 CH2 CH3
0.15 0.10 GAIN ERROR (%FS) 0.05 0 -0.05 -0.10
OFFSET (LSB)
-0.16 -0.17 -0.18 -0.19 -0.20 -0.21 4.75
CH0 REFERENCE ERROR NULLED
-0.15 4.85 4.95 5.05 5.15 5.25 -40 -15 10 35 60 85 SUPPLY VOLTAGE (V) TEMPERATURE (C)
85
TEMPERATURE (C)
OUTPUT HISTOGRAM (DC INPUT)
MAX1338 toc07
ANALOG INPUT BANDWIDTH
0 -0.1 ATTENUATION (dB) -0.2 -0.3 -0.4 -0.5 -0.6
MAX1338 toc08
6000 OFFSET NORMALIZED 5000 4000 COUNTS 3000 2000 1000 97.25 0 -2 -1 0 1 2 DIGITAL OUTPUT CODE 61 1802.75 1646.25 4584.25
0.1
-0.7 -0.8 0 50 100 fIN (kHz) 150 200
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14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = 10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0F and 0.1F from COM1 to AGND, 0.1F from REFP1 to AGND, 0.1F from REFN1 to AGND, 1.0F from REFP1 to REFN1.)
FFT AT fSAMPLE = 150ksps, fIN = 10kHz
MAX1338 toc10
SIGNAL-TO-NOISE RATIO vs. CLOCK FREQUENCY
MAX1338 toc11
SIGNAL-TO-NOISE PLUS DISTORTION vs. CLOCK FREQUENCY
79 78 77 SNR (dB) 76 75 74 73 72 71 70
MAX1338 toc12
0
80 79 78 77
80
-25 AMPLITUDE (dB)
-50
SNR (dB)
76 75 74 73
-75
-100
72 71
-125 0 15 30 45 60 75 FREQUENCY (kHz)
70 1 2 3 4 5 6 7 8 9 10 fCLK (MHz)
1
2
3
4
5
6
7
8
9
10
fCLK (MHz)
TOTAL HARMONIC DISTORTION vs. CLOCK FREQUENCY
MAX1338 toc13
SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK FREQUENCY
MAX1338 toc14
SIGNAL-TO-NOISE RATIO vs. REFERENCE VOLTAGE
79 78 77 SNR (dB) 76 75 74 73 72 71
MAX1338 toc15
-90 -92 -94 -96
110 105 100 SFDR (dB) 95 90 85 80
80
THD (dB)
-98 -100 -102 -104 -106 -108 -110 1 2 3 4 5 6 7 8 9 10 fCLK (MHz)
70 1 2 3 4 5 6 7 8 9 10 2.0 2.2 2.4 2.6 2.8 3.0 fCLK (MHz) VREFADC (V)
SIGNAL-TO-NOISE PLUS DISTORTION vs. REFERENCE VOLTAGE
MAX1338 toc16
TOTAL HARMONIC DISTORTION vs. REFERENCE VOLTAGE
MAX1338 toc17
SPURIOUS-FREE DYNAMIC RANGE vs. REFERENCE VOLTAGE
MAX1338 toc18
80 79 78 77 SINAD (dB)
-85 -87 -89 -91
110 105 100 SFDR (dB) 95 90 85 80
75 74 73 72 71 70 2.0 2.2 2.4 2.6 2.8 3.0 VREFADC (V)
THD (dB)
76
-93 -95 -97 -99 -101 -103 -105 2.0 2.2 2.4 2.6 2.8 3.0 VREFADC (V)
2.0
2.2
2.4
2.6
2.8
3.0
VREFADC (V)
8
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14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = 10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0F and 0.1F from COM1 to AGND, 0.1F from REFP1 to AGND, 0.1F from REFN1 to AGND, 1.0F from REFP1 to REFN1.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1338 toc19
SUPPLY CURRENT vs. TEMPERATURE
MAX1338 toc20
DRIVER SUPPLY CURRENT vs. SUPPLY VOLTAGE
3.5 3.0
MAX1338 toc21
44.0 EXCLUDES DRIVER CURRENT 43.8 43.6 A|DD + D|DD (mA)
46 EXCLUDES DRIVER CURRENT 45 A|DD + D|DD (mA) 44
4.0
43.2 43.0 42.8 42.6 42.4 4.75 4.85 4.95 5.05 5.15 5.25 AVDD (V)
DR|DD (mA)
43.4
2.5 2.0 1.5 1.0
43 42 41 40 -40 -15 10 35 60 85 TEMPERATURE (C)
0.5 0 2.75 3.25 3.75 4.25 4.75 5.25 DRVDD (V)
DRIVER SUPPLY CURRENT vs. TEMPERATURE
MAX1338 toc22
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
2.4986 2.4985 2.4984 VREFADC (V) 2.4983 2.4982 2.4981 2.4980 2.4979 2.4978
MAX1338 toc23
0.98 DRVDD = 3V 0.97 0.96 DR|DD (mA) 0.95 0.94 0.93 0.92 0.91 0.90 -40 -15 10 35 60
2.4987
85
4.75
4.85
4.95
5.05
5.15
5.25
TEMPERATURE (C)
AVDD (V)
REFERENCE VOLTAGE vs. TEMPERATURE
MAX1338 toc24
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
SHDN = AVDD 65 60 A|DD (A) 55 50 45 40
MAX1338 toc25
2.504 2.502 2.500 VREFADC (V) 2.498 2.496 2.494 2.492 2.490 -40 -15 10 35 60
70
85
4.75
4.85
4.95
5.05
5.15
5.25
TEMPERATURE (C)
AVDD (V)
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14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = 10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0F and 0.1F from COM1 to AGND, 0.1F from REFP1 to AGND, 0.1F from REFN1 to AGND, 1.0F from REFP1 to REFN1.)
SHUTDOWN CURRENT vs. TEMPERATURE
MAX1338 toc26
STANDBY CURRENT vs. SUPPLY VOLTAGE
STANDBY = AVDD 4.25 4.20 A|DD (mA) 4.15 4.10 4.05 4.00
MAX1338 toc27
70 SHDN = AVDD 65 60 A|DD (A) 55 50 45 40 -40 -15 10 35 60
4.30
85
4.75
4.85
4.95
5.05
5.15
5.25
TEMPERATURE (C)
AVDD (V)
STANDBY CURRENT vs. TEMPERATURE
MAX1338 toc28
CONVERSION TIME vs. SUPPLY VOLTAGE
INTERNAL CLOCK 5.6 CONVERSION TIME (s)
MAX1338 toc29
4.30 STANDBY = AVDD 4.25 4.20 A|DD (mA) 4.15 4.10 4.05 4.00 -40 -15 10 35 60
5.8
5.4
5.2
5.0
4.8 85 4.75 4.85 4.95 5.05 5.15 5.25 TEMPERATURE (C) AVDD (V)
CONVERSION TIME vs. TEMPERATURE
INTERNAL CLOCK 5.6 CONVERSION TIME (s)
MAX1338 toc30
ANALOG INPUT CURRENT vs. ANALOG INPUT VOLTAGE
3 INPUT CURRENT (mA) 2 1 0 -1 -2 -3
MAX1338 toc31
5.8
4
5.4
5.2
5.0
4.8 -40 -15 10 35 60 85 TEMPERATURE (C)
-4 -17.0 -8.5 0 INPUT VOLTAGE (V) 8.5 17.0
10
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14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC
Pin Description
PIN 1, 7, 9, 17, 19 2 3 4 5 6, 8, 14, 16, 18, 20, 28 10 11 12 13 15 NAME FUNCTION Analog Power Input. AVDD is the power input for the analog section of the converter. Connect a +4.75V to +5.25V power supply to AVDD. Bypass each AVDD to AGND with a 0.1F capacitor very close to the device. Bypass AVDD to AGND with a bulk capacitor of at least 4.7F where power enters the board. Connect all AVDD pins to the same potential. Channel 0 Differential Analog Input Channel 0 Differential Analog Input Channel 1 Differential Analog Input Channel 1 Differential Analog Input Analog Ground. AGND is the power return for AVDD. Connect all AGNDs to the same potential. Channel 2 Differential Analog Input Channel 2 Differential Analog Input Channel 3 Differential Analog Input Channel 3 Differential Analog Input Clock-Select Input. Force INTCLK/EXTCLK high for internal clock mode. Force INTCLK/EXTCLK low for external clock mode. ADC Reference Bypass or Input. REFADC is the bypass point for an internally generated reference voltage. Bypass REFADC with a 1.0nF capacitor to AGND. REFADC can be driven externally by a precision external voltage reference. See the Reference section and the Typical Operating Circuit. Positive Differential Reference Bypass Point 1. Connect REFP1 to REFP2. Positive Differential Reference Bypass Point 2. Connect REFP2 to REFP1. Bypass REFP2 with a 0.1F capacitor to AGND. Also bypass REFP2 to REFN2 with a 0.1F capacitor. Common-Mode Voltage Bypass Point 1. Connect COM1 to COM2. Common-Mode Voltage Bypass Point 2. Connect COM2 to COM1. Connect a 1.0F capacitor from COM2 to AGND. Negative Differential Reference Bypass Point 1. Connect REFN1 to REFN2. Negative Differential Reference Bypass Point 2. Connect REFN2 to REFN1. Bypass REFN2 with a 0.1F capacitor to AGND. Also bypass REFN2 to REFP2 with a 0.1F capacitor. Data Input/Output Bit 0 (LSB) Data Input/Output Bit 1 Data Input/Output Bit 2 Data Input/Output Bit 3 Data Input/Output Bit 4 Data Input/Output Bit 5 Data Input/Output Bit 6 Data Input/Output Bit 7 Data Output Bit 8 Data Output Bit 9 Data Output Bit 10 Data Output Bit 11
MAX1338
AVDD
AIN0+ AIN0AIN1+ AIN1AGND AIN2+ AIN2AIN3+ AIN3INTCLK/ EXTCLK REFADC REFP1 REFP2 COM1 COM2 REFN1 REFN2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
21 22 23 24 25 26 27 29 30 31 32 33 34 35 36 37 38 39 40
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11
14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
Pin Description (continued)
PIN 41 42 43 44 45 46 47 48 49 50 NAME D12 D13 DRVDD DRGND EOC EOLC RD WR CS CONVST Data Output Bit 12 Data Output Bit 13 (MSB) Digital I/O Power-Supply Input. DRVDD is the power input for the digital I/O buffers and drivers. Connect a +2.7V to +5.25V power supply to DRVDD. Bypass DRVDD to DRGND with a 0.1F capacitor very close to the device. Driver Ground. DRGND is the power-supply return for DRVDD. End-of-Conversion Output. EOC goes low to indicate the end of a conversion. EOC returns high after one clock period. End-of-Last-Conversion Output. EOLC goes low to indicate the end of the last conversion. EOLC returns high when CONVST goes low for the next conversion sequence. Read Input. Forcing RD low initiates a read command of the parallel data bus, D0-D13. D0-D13 are high impedance while either RD or CS is high. Write Input. Forcing WR low initiates a write command for configuring the device through D0-D7. Chip-Select Input. Forcing CS low activates the digital interface. D0-D13 are high impedance while either CS or RD is high. Convert Start Input. CONVST initiates the conversion process. The analog inputs are sampled on the rising edge of CONVST. External-Clock Input. CLK accepts a 1MHz to 6MHz external clock signal. For externally clocked conversions, apply the clock signal to CLK and force INTCLK/EXTCLK low. For internally clocked conversions, connect CLK to DGND and force INTCLK/EXTCLK high. Standby-Control Input. Forcing STANDBY high partially powers down the device but leaves all the reference-related circuitry alive. Use STANDBY instead of SHDN when quick wake-up is required. Shutdown-Control Input. Force SHDN high to place the device into full shutdown. When in full shutdown, all circuitry within the device is powered down and all reference capacitors are allowed to discharge. Allow 1ms for wake-up from full shutdown before starting a conversion. Digital Power-Supply Input. DVDD is the power input for the digital circuitry. Connect a +4.75V to +5.25V power supply to DVDD. Bypass DVDD to DGND with a 0.1F capacitor very close to the device. Digital Ground. Power return for DVDD. Exposed Pad. Connect to AGND. FUNCTION
51
CLK
52
STANDBY
53
SHDN
54 55, 56 --
DVDD DGND EP
Detailed Description
The MAX1338 simultaneously samples four differential analog inputs with internal T/H circuits, and sequentially converts them to a digital code with a 14-bit ADC. Output data is provided by a 14-bit parallel interface. At power-up, all channels default to a 10V input range. Program different input ranges (10V, 5V, 2.5V, or 1.25V) using the configuration register. Different input ranges between 12V and 1.0V are realized using an
external reference. All channels offer input protection to 17V, independent of the selected input range. The internal clock operates the ADC at 5MHz, or uses an external conversion clock from 1MHz to 6MHz. EOC goes low when the result of each conversion is available, and EOLC goes low when the last conversion result is available. Standby and shutdown modes, selectable through logic-control inputs, save power between conversions. Figure 2 shows a block diagram of the MAX1338.
12
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14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
DVDD AVDD AIN0+ AIN0S/H DRVDD
MAX1338
D13
4x1 MUX
AIN3+ AIN3S/H
14-BIT ADC
4 x 14 SRAM
OUTPUT DRIVERS
D8 D7
D0 REFP2 REFP1 COM2 COM1 CONFIGURATION REGISTER INTERFACE AND CONTROL WR CS REFN2 REFN1 RD CONVST SHDN 5k REFADC 2.500V INTCLK/EXTCLK AGND CLK STANDBY EOC EOLC
DRGND DGND
Figure 2. Functional Diagram
Power-Supply Inputs
Three separate power supplies power the MAX1338. A +5V analog supply, AVDD, powers the analog input and converter sections. A +5V digital supply, DVDD, powers the internal logic circuitry, and a +2.7V to +5V digital supply (DRVDD), powers the parallel I/O and the control I/O (see the Typical Operating Circuit). Bypass the power supplies as indicated in the Layout, Grounding, and Bypassing section. Power-supply sequencing is not required for the MAX1338.
parallel I/O. See the Configuration Register section for programming details. Input Protection Protection at the analog inputs provides 17V fault immunity for the MAX1338. This protection circuit limits the current at the analog inputs to less than 2mA. Input fault protection is active in standby, in shutdown, during normal operation, and over all input ranges. Track and Hold (T/H) To preserve relative phase information between input channels, each input channel has a dedicated T/H amplifier. The rising edge of CONVST represents the sampling instant for all channels. All samples are taken within an aperture delay (tAD) of 16ns. The aperture delay of all channels is matched to within 100ps.
Analog Inputs
Software-Selectable Input Range The MAX1338 provides four independent, softwareselectable, analog input voltage ranges for each channel. The selectable input ranges are VREF x 4 (the power-up default condition), VREF x 2, VREF, and V REF x 0.5. Using the 2.5V internal reference, the selectable input ranges are 10V (power-up default), 5V, 2.5V, and 1.25V. Program the analog input ranges with the configuration register through the
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13
14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
Figure 3 shows the equivalent analog input T/H circuit for one analog input. As conversion begins, the T/H circuits hold the analog signals. After the 12th clock cycle (or 2.4s in internal clock mode) into the conversion process, the last analog input sample begins shifting through the converter, and the T/H circuits begin to track the analog inputs again in preparation for the next CONVST rising edge. Due to the resistive load presented by the analog inputs, any significant analog input source resistance, RSOURCE, increases gain error. Limit R SOURCE to a maximum of 20 to limit the effect to less than 0.1%. Drive the input with a wideband buffer (>1MHz) that can drive the ADC's input impedance. Selecting an Input Buffer Most applications require an input buffer to achieve 14bit accuracy. Although slew rate and bandwidth are important, the most critical specification is output impedance. Use a low-noise, low-distortion amplifier with low output impedance, for best gain-accuracy performance. Input Bandwidth The input-tracking circuitry has a 1MHz small-signal bandwidth. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
R1 || R2 = 6.25k
MAX1338
R1 AIN_ R2 CHOLD
1.9V
Figure 3. Simplified Typical Input Circuit
CONVST
CONFIGURATION REGISTER ACTIVATES
RD tCS CS
Data Throughput
The data throughput (fTH) of the MAX1338 is a function of the clock speed (fCLK). The MAX1338 operates from a 5MHz internal clock or an external clock between 1MHz and 6MHz. For fastest throughput, read the conversion result during conversion (Figure 5), and calculate data throughput using: fTH = 1 t QUIET + 26 fCLK
WR
tCTW
tWRL
tWTC
tDTW D0-D7 DATA IN tWTD
Figure 4. Write Timing
where tQUIET is the period of bus inactivity before the rising edge of CONVST.
Clock Modes
The MAX1338 provides an internal clock of 5MHz. Alternatively, use an external clock of 1MHz to 6MHz.
Internal Clock Internal clock mode frees the microprocessor from the burden of running the ADC conversion clock. For internal-clock operation, connect INTCLK/EXTCLK to AVDD and CLK to DRGND. Note that INTCLK/EXTCLK is referenced to the analog power supply, AVDD. Total conversion time for all four channels using the internal clock is 6s (typ).
14
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14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC
External Clock For external clock operation, force INTCLK/EXTCLK low and connect an external clock source to CLK. Use an external clock frequency from 1MHz to 6MHz with a duty cycle between 40% and 60%. Choose a minimum clock frequency of 1MHz to prevent linearity errors caused by excessive droop in the T/H circuits.
MAX1338
Table 1. Configuration Register
I/O LINE D0 D1 D2 D3 D4 D5 D6 D7 REGISTER NAME CH0R0 CH0R1 CH1R0 CH1R1 CH2R0 CH2R1 CH3R0 CH3R1 FUNCTION Channel 0 input range setting bit 0 Channel 0 input range setting bit 1 Channel 1 input range setting bit 0 Channel 1 input range setting bit 1 Channel 2 input range setting bit 0 Channel 2 input range setting bit 1 Channel 3 input range setting bit 0 Channel 3 input range setting bit 1
Applications Sections
Power-On Reset
At power-up, all channels default to a 10V input range. After applying power, allow a 1ms wake-up time to elapse and perform one dummy conversion before initiating first conversion.
Power Saving
Full Shutdown During shutdown, the analog and digital circuits in the MAX1338 power down and the device draws less than 0.06mA from AVDD, and less than 10A from DVDD. Select shutdown mode using the SHDN input. Force SHDN high to enter shutdown mode. When coming out of shutdown, allow the 1ms wake-up and then perform one dummy conversion before making the first conversion. Standby Standby is similar to shutdown but the reference circuits remain powered up, allowing faster wake-up. Enter standby by forcing STANDBY high. After coming out of standby, perform a dummy conversion before making the first conversion.
Table 2. Input-Range Register Settings
REGISTER SETTING CH_R0 0 0 1 1 CH_R1 0 1 0 1 -10V to +10V -5V to +5V -2.5V to +2.5V -1.25V to +1.25V SELECTED INPUT RANGE ALLOWABLE COMMON-MODE RANGE 5V 2.5V 1.25V 0.625V
Configuration Register
The MAX1338 uses an 8-bit configuration word to set the input range for each channel. Table 1 and Table 2 describe the configuration word and the input-range settings. Write to the configuration register by forcing CS and WR low, loading bits D0-D7 onto the parallel bus, and then forcing WR high. The configuration bits are latched on the rising edge of WR (Figure 4). It is possible to write to the configuration register at any point during the conversion sequence. However, it will not be active until the next convert-start signal. At power-up, the configuration register contains all zeros, making all channels default to the maximum input range, -10V to +10V. Shutdown and standby do not change the configuration register, but the configuration register can be programmed while the MAX1338 is in shutdown or standby modes.
Digital Interface
The digital interface consists of two sections: a control I/O section and a parallel I/O section. The control I/O section includes the following control signals: chip select (CS), read (RD), write (WR), end of conversion (EOC), end of last conversion (EOLC), convert start (CONVST), power-down (SHDN), standby (STANDBY), and external-clock input (CLK). The bidirectional parallel I/O section sets the 8-bit input range configuration register using D0-D7 (see the Configuration Register section) and outputs the 14-bit conversion result using D0-D13. The I/O operations are controlled by the control I/O signals RD, WR, and CS. All parallel I/O bits are high impedance when either RD = 1 or CS = 1. Figures 4, 5, and 6 and the Timing Characteristics section detail the operation of the digital interface.
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15
14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
SAMPLE
tCONVST CONVST
CLK tEOC1 EOC
17
18 tNEXT
19
20
21
22
23
24
25
26
27
29
tEOC EOLC tQUIET RD tACC D0-D13 CH0 tREQ CH1 CH2 CH3 tRDL
Figure 5. Reading During a Conversion--Internal or External Clock
Starting a Conversion
Internal Clock For internal clock operation, force INTCLK/EXTCLK high. To start a conversion using internal clock mode, pull CONVST low for at least tCONVST. The T/H acquires the signal while CONVST is low. An EOC signal pulses low when the first result becomes available, and for each subsequent result until the end of the conversion cycle. The EOLC signal goes low when the last conversion result becomes available (Figure 6). External Clock For external clock operation, force INTCLK/EXTCLK low. To start a conversion using external clock mode, pull CONVST low for at least tCONVST. The T/H circuits track the input signal while CONVST is low. Conversion begins on the rising edge of CONVST. Apply an external clock to CLK. To avoid T/H droop degrading the sampled analog input signals, the first CLK pulse must occur within 10s after the rising edge of CONVST and have a minimum 1MHz clock frequency. The first conversion result is available for read on the rising edge of the 17th clock cycle, and subsequent conversions on every 3rd clock cycle thereafter, as indicated by EOC and EOLC.
Reading a Conversion Result
Reading During a Conversion Figure 5 shows the interface signals to initiate a read operation during a conversion cycle. CS can be held low permanently, low during the RD cycles, or it can be the same as RD. After initiating a conversion by bringing CONVST high, wait for EOC to go low (about 3.4s in internal clock mode) or 17 clock cycles (external clock mode) before reading the first conversion result. Read the conversion result by bringing RD low, which latches the data to the parallel digital output bus. Bring RD high to release the digital bus. Wait for the next falling edge of EOC (about 600ns in internal clock mode or three clock cycles in external clock mode) before reading the next result. When the last result is available, EOLC goes low, along with EOC. Wait three clock cycles, tQUIET, before starting the next conversion cycle. Reading After a Conversion Figure 6 shows the interface signals for a read operation after a conversion using an external clock. At the falling of EOLC, on the 26th clock pulse after the initiation of a conversion, driving CS and RD low places the first conversion result onto the parallel I/O bus. Read the conversion result on the rising edge of RD. Successive low pulses of RD place the successive conversion results
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14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
SAMPLE
tCONVST CONVST
tCNTC 1 CLK tCLK EOC ONLY LAST PULSE SHOWN tEOC 2 26
tCLKH 27 28 29 tCLKL 30 31
EOLC
tRTC CS
tCTR RD tEOCRD tEOLCRD
tRDL
tRDH
tQUIET
D0-D13 CH0 tACC CH1 CH2 tREQ CH3
Figure 6. Reading After a Conversion--External Clock
onto the bus. After reading all four channels, bring CS high to release the parallel I/O. After waiting tQUIET, pulse CONVST low to initiate the next conversion.
Table 3. Reference Bypass Capacitors
LOCATION REFADC bypass capacitor to AGND REFP1 bypass capacitor to AGND REFN1 bypass capacitor to AGND REFP1 to REFN1 capacitor COM1 bypass capacitor to AGND BYPASS CAPACITORS 1nF 0.1F 0.1F 1.0F 1.0F || 0.1F
Reference
Bypass the reference inputs as indicated in Table 3. Internal Reference The internal reference supports all input ranges for the MAX1338. External Reference Implement external-reference operation by overdriving the internal reference voltage. Override the internal reference voltage by connecting a 2.0V to 3.0V external reference at REF. The REF input impedance is typically 5k. For more information about using an external reference, see the Transfer Functions section.
Transfer Functions
Digital Correction Factory trim procedures digitally shift the transfer function to reduce bipolar zero-code offset to less than 4 LSBs (typ). Depending on initial conditions, the transfer function is shifted up or down, as required. The maximum shift that any transfer function experiences is 64 codes, which can have a small effect at the extremes of the transfer function, as shown in Figure 7.
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17
14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
0x1FFF 8 x VREFADC 0x1FFF 0x1FFE 0x1FFD 0x1FFC
INITIAL TRANSFER FUNCTION OUTPUT CODE ADJUSTED TRANSFER FUNCTION 0x0000 MAXIMUM 64 CODES
TWO'S COMPLEMENT BINARY OUTPUT CODE
0x0001 0x0000 0x3FFF
0x2000 -8192 0 INPUT VOLTAGE (LSBs) +8191
0x2003 0x2002 0x2001 0x2000 -8192 -8190 -1 0 +1
1 LSB =
8 x VREF 214
+8189 +8191
INPUT VOLTAGE (VAIN_+ - VAIN_- IN LSBs)
Figure 7. Example of Digitally Adjusted Transfer Function-- Shifted Down to Minimize Zero-Code Offset
Figure 8. 10V Transfer Function
Input Range Settings Table 4 shows the two's complement output for a selection of inputs. The full-scale input range (FSR) depends on the selected range, and the voltage at REF, as shown in Table 5. Also shown in Table 5 are the allowable common-mode ranges for the differential inputs. Calculate the LSB size using: 1 LSB = A x VREFADC 214
Applications Information
Layout, Grounding, and Bypassing
For best performance, the board layout must follow some simple guidelines. Separate the control I/O and parallel I/O signals from the analog signals, and run the clock signals separate from everything. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Run the parallel I/O signals together as a bundle. The MAX1338 has an exposed underside pad for a low-inductance ground connection and low thermal resistance. Connect the exposed pad to the circuit board ground plane. Figure 12 shows the recommended system ground connections. Establish an analog ground point at AGND and a digital ground point at DGND. Connect all analog grounds to the analog ground point. Connect all digital grounds to the digital ground point. For lowest noise operation, make the power-supply ground returns as low impedance and as short as possible. Connect the analog ground point to the digital ground point at one location. High-frequency noise in the power supplies degrades the ADC's performance. Bypass AVDD to AGND with a parallel combination of 0.1F and 2.2F capacitors, bypass DVDD to DGND with a parallel combination of 0.1F and 2.2F capacitors, and bypass DRVDD to DRGND with a parallel combination of 0.1F and 2.2F capacitors. If the supply is very noisy use a ferrite bead as a lowpass filter, as shown in Figure 12.
where A = gain multiplier for the selected input range, from Table 6. Determine the input voltage as a function of VREF, and the output code using: VAIN _ + - VAIN _ - = VREFADC x A x CODE 214
where A = gain multiplier for the selected input range, from Table 6. Figures 8, 9, 10, and 11 show the transfer functions for the four selectable input ranges.
18
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14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
Table 4. Code Table with VREF = 2.500V
INPUT VOLTAGE (V) 10V INPUT RANGE SELECTED 9.9988 9.9976 0.0012 0 -0.0012 -9.9988 -10.0000 5V INPUT RANGE SELECTED 4.9994 4.9988 0.0006 0 -0.0006 -4.9994 -5.0000 2.5V INPUT RANGE SELECTED 2.4998 2.4997 0.0002 0 -0.0002 -2.4998 -2.5000 1.25V INPUT RANGE SELECTED 1.2499 1.2498 0.0001 0 -0.0001 -1.2499 -1.2500 DECIMAL EQUIVALENT OUTPUT (CODE10) 8191 8190 1 0 -1 -8191 -8192 TWO'S COMPLEMENT BINARY OUTPUT CODE 01 1111 1111 1111 0x1FFF 01 1111 1111 1110 0x1FFE 00 0000 0000 0001 0x0001 00 0000 0000 0000 0x0000 11 1111 1111 1111 0x3FFF 10 0000 0000 0001 0x2001 10 0000 0000 0000 0x2000
Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. For these devices, this straight line is a line drawn between the endpoints of the transfer function, once offset and gain errors have been nulled.
Table 5. Input Ranges
SELECTED INPUT RANGE (V) VREFADC (V) 2.0 10 2.5 3.0 2.0 5 2.5 3.0 2.0 2.5 2.5 3.0 2.0 1.25 2.5 3.0 FULL-SCALE INPUT RANGE (V) 8 10 12 4 5 6 2 2.5 3 1 1.25 1.5 ALLOWABLE COMMON-MODE RANGE (V) 5 5 5 2.5 2.5 2.5 1.25 1.25 1.25 0.625 0.625 0.625
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. For these devices, the DNL of each digital output code is measured and the worst-case value is reported in the Electrical Characteristics table. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function.
Offset Error
Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point. Typically, the point at which the offset error is specified is at or near the zero scale of the transfer function or at or near the midscale of the transfer function. For the MAX1338, the ideal zero-scale digital output transition from 0x3FFF to 0x0000 occurs with an analog input voltage of zero. Offset error is the amount of analog input-voltage deviation between the measured input voltage and the calculated input voltage at the zeroscale transition.
Table 6. LSB Size with VREF = 2.500V
SELECTED INPUT RANGE (V) 10 5 2.5 1.25 GAIN MULTIPLIER (A) 8 4 2 1 LSB SIZE (mV) 1.2207 0.6104 0.1526 0.0736
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19
14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
4 x VREFADC 2 x VREFADC 0x1FFF 0x1FFE 0x1FFD 0x1FFC 0x1FFF 0x1FFE 0x1FFD 0x1FFC
TWO'S COMPLEMENT BINARY OUTPUT CODE
0x0001 0x0000 0x3FFF
TWO'S COMPLEMENT BINARY OUTPUT CODE
4 x VREF 214
0x0001 0x0000 0x3FFF
0x2003 0x2002 0x2001 0x2000 -8192 -8190 -1 0 +1
1 LSB =
0x2003 0x2002 0x2001 0x2000 -8192 -8190 -1 0 +1
1 LSB =
2 x VREF 214
+8189 +8191
+8189 +8191
INPUT VOLTAGE (VAIN_+ - VAIN_- IN LSBs)
INPUT VOLTAGE (VAIN_+ - VAIN_- IN LSBs)
Figure 9. 5V Transfer Function
Figure 10. 2.5V Transfer Function
VREFADC
TWO'S COMPLEMENT BINARY OUTPUT CODE
0x1FFF 0x1FFE 0x1FFD 0x1FFC
ANALOG POWER SUPPLY +5V FERRITE BEAD AGND +5V
DIGITAL POWER SUPPLIES +3V GND
0x0001 0x0000 0x3FFF
0x2003 0x2002 0x2001 0x2000 -8192 -8190 -1 0 +1
1 LSB =
VREF 2
14
AVDD
AGND DVDD
DGND DRVDD
DRGND
+5V
GND DIGITAL CIRCUITS
+8189 +8191
MAX1338
INPUT VOLTAGE (VAIN_+ - VAIN_- IN LSBs)
Figure 11. 1.25V Transfer Function
Figure 12. Power-Supply Grounding and Bypassing
Gain Error
Gain error indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. For the MAX1338, the gain error is the difference between the measured positive full-scale and negative full-scale transition points minus the difference between the ideal positive full-scale and negative fullscale bipolar transition points.
20
Signal-to-Noise Ratio (SNR)
SNR is a measure of the converter's noise characteristics. For a waveform perfectly reconstructed from digital samples, SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC's resolution (N bits):
______________________________________________________________________________________
14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC
SNR = (6.02 x N + 1.76)dB where N = 14 bits. In reality, there are other noise sources such as thermal noise, reference noise, and clock jitter. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. SFDR is specified in decibels relative to the carrier (dBc).
MAX1338
Aperture Delay
Aperture delay (tAD) is the time delay from the sampling clock edge to the instant when an actual sample is taken.
Signal-to-Noise Plus Distortion (SINAD)
SINAD indicates the converter's noise and distortion performance. SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset.
SIGNALRMS SINAD(dB) = 20 x log (NOISE + DISTORTION)RMS
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in aperture delay.
Channel-to-Channel Isolation
Channel-to-channel isolation indicates how well each analog input is isolated from the others. The channel-tochannel isolation for the MAX1338 is measured by applying a DC -0.5dBFS sine wave to the ON channel while a high frequency 10kHz -0.5dBFS sine wave is applied to all OFF channels. An FFT is taken for the ON channel. From the FFT data, channel-to-channel crosstalk is expressed in dB as the power ratio of the DC signal applied to the ON channel and the high-frequency crosstalk signal from the OFF channels.
Effective Number of Bits (ENOB)
ENOB specifies the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB for a fullscale sinusoidal input waveform is computed from:
Power-Supply Rejection (PSRR)
PSRR is defined as the shift in gain error when the analog power supply is changed from 4.75V to 5.25V.
ENOB =
SINAD - 1.76 6.02
Small-Signal Bandwidth
A -20dBFS sine wave is applied to the MAX1338 input. The frequency is increased until the amplitude of the digitized conversion result decreases 3dB.
Total Harmonic Distortion (THD)
THD is a dynamic indication of how much harmonic distortion the converter adds to the signal. THD is the ratio of the RMS sum of the first five harmonics of the fundamental signal to the fundamental itself. This is expressed as:
2 2 2 2 2 V2 + V3 + V4 + V5 + V6 THD = 20 x log V1
Full-Power Bandwidth
A -0.5dBFS sine wave is applied to the MAX1338 input. The frequency is increased until the amplitude of the digitized conversion result decreases 3dB.
where V1 is the fundamental amplitude and V2-V6 are the amplitudes of the 2nd- through 6th-order harmonics.
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21
14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
Typical Operating Circuit
15 +5V
INTCLK/EXTCLK
DVDD
54
+5V 0.1F
1 0.1F 0.1F 9 0.1F 17 0.1F 19 0.1F 0.001F 0.1F 23 21 22 7
AVDD AVDD AVDD AVDD
MAX1338
DGND SHDN CLK CONVST CS
55, 56 53 51 50 49 48 47 46 45 52
GND
AVDD REFADC REFP1 REFP2
WR RD EOLC EOC STANDBY
CONTROL I/O
1.0F 27 0.1F 1.0F 24 25 0.1F GND 6, 8, 14, 16, 18, 20, 28 AGND 2 AIN0+ 3 4 5 ANALOG INPUTS 10 11 12 13 AIN0AIN1+ AIN1AIN2+ AIN2AIN3+ AIN3COM1 COM2 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 42 41 40 39 38 37 36 35 34 33 32 31 30 29 DIGITAL I/O PARALLEL I/O DIGITAL OUTPUT REFN2 DRVDD 43 0.1F DRGND 44 GND +3V TO +5V
26 REFN1
22
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14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC
Pin Configuration
STANDBY CONVST
MAX1338
Chip Information
TRANSISTOR COUNT: 27,000 PROCESS: BiCMOS EXPOSED PAD: Connect to AGND
TOP VIEW
DGND DGND SHDN DVDD
DRGND
EOLC
CLK
WR
49
48
47
RD
46
45
EOC
44
56
55
54
53
52
51
50
43
DRVDD
CS
AVDD AIN0+ AIN0AIN1+ AIN1AGND AVDD AGND AVDD AIN2+ AIN2AIN3+ AIN3AGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
42 41 40 39 38 37 36
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MAX1338
35 34 33 32 31 30 29
REFN1
REFN2
REFP1
INTCLK/EXTCLK
AGND
AGND
AGND
THIN QFN
______________________________________________________________________________________
REFADC
REFP2
COM1
COM2
AGND
AVDD
AVDD
23
14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
56L THIN QFN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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