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128K x 32 SRAM Module
PUMA 2/67/77S4000/A-020/025/35
11403 West Bernado Court, Suite 100, San Diego, CA 92127. Tel No: (001) 858 674 2233, Fax No: (001) 858 674 2230
Issue 4.3 : December 1999
Description
Features 4 Megabit SRAM module. Fast Access Times of 20/25/35 ns. Output Configurable as 32 / 16 / 8 bit wide. Upgradeable footprint. Operating Power 3740 / 2310 / 1595 mW (Max). Low Power Standby (L version) 220 mW (Max). 3.0V Battery Back-up Capability. TTL Compatible Inputs and Outputs. May be screened in accordance with MIL-STD-883. PUMA 2 - 66 pin ceramic PGA. PUMA 67 - 68 pin ceramic JLCC. PUMA 77 - 68 pin ceramic Gullwing.
Available in PGA (PUMA 2), JLCC (PUMA 67) and * Gullwing (PUMA 77) footprints. The PUMA **S4000 * is a 4 Mbit SRAM module, user configurable as * 128K x 32, 256K x 16 or 512K x 8. The device is * available with fast access times of 20, 25 and 30ns. * A low power standby and Data Retention mode is available. The device may be screened in * accordance with MIL-STD-883C. * * * * *
Block Diagram PUMA 2S4000, 67S4000A and 77S4000A
A0~A16 OE WE4 WE3 WE2 WE1 128Kx8 SRAM CS1 CS2 CS3 CS4 D0~7 D8~15 D16~23 D24~31 128Kx8 SRAM 128Kx8 SRAM 128Kx8 SRAM
Block Diagram PUMA 67S4000 and 77S4000
A0-A16 OE WE 128Kx8 SRAM CS1 CS2 CS3 CS4 D0-7 D8-15 D16-23 D24-31 128Kx8 SRAM 128Kx8 SRAM 128Kx8 SRAM
Pin Functions A0~A16 CS1~4 OE GND Address Input Chip Select Output Enable Ground D0~D31 WE1~4 Vcc Data Inputs/Outputs Write Enables Power (+5V)
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PUMA 2/67/77S4000/A - 020/025/35
Issue 4.3 : December 1999
DC OPERATING CONDITIONS Absolute Maximum Ratings (1) Voltage on any pin relative to GND(2) Power Dissipation Storage Temperature VT PT TSTG -0.5V to +7.0 4 -65 to +150 V W C
Notes (1) Stresses above those listed may cause permanent damage. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (2) Pulse width: -3.0V for less than 10ns.
Recommended Operating Conditions
min
Supply Voltage Input High Voltage Input Low Voltage Operating Temperature VCC VIH VIL TA TAI TAM 4.5 2.2 -0.5 0 -40 -55
typ
5.0 -
max
5.5 6.0 0.8 70 85 125 V V V C C (Suffix I) C (Suffix M, MB)
DC Electrical Characteristics (VCC=5V10%,TA=-55C to +125C)
Parameter
Input Leakage Current Output Leakage Current Operating Supply Current 32 bit 16 bit 8 bit Standby Supply Current Output Voltage Low Output Voltage High (TTL) -L Version
Symbol Test Condition
ILI1 ILO ICC32 ICC16 ICC8 ISB1 ISB2 VOL VOH VIN=0V to VCC CS =VIH or OE=VIH, VI/O=0V to VCC WE=VIL Min cycle,duty=100%,II/O=0mA,CS=VIL As above Min cycle,duty=100%,II/O=0mA,CS=VIL CS VIH VCC = 5.5V
(1) (1) (1)
min
-8 -8 2.4
typ
-
max Unit
8 8 A A
680 mA 420 mA 290 mA 160 mA 40 0.4 mA V V
CS VIH, VIL VIN VIH, f = 0 Hz IOL = 8.0mA IOH = -4.0mA
Notes: (1) CS and WE above are accessed through CS1~4 and WE1~4 respectively. These inputs must be operated simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode.
Capacitance (VCC=5V10%,TA=25C) Note: (1) On the standard module, WE = 30 pF max.
Parameter
Input Capacitance Address, OE WE1~4(1), CS1~4 I/O Capacitance D0~D31
Symbol
CIN1 CIN2 CI/O
Test Condition
VIN =0V VIN =0V VI/O=0V
typ
-
max Unit
30 16 30 pF pF pF (8 bit mode)
These parameters are calculated, not measured.
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PUMA 2/67/77S4000/A - 020/025/35
Issue 4.3 : December 1999
Operating Modes The table below shows the logic inputs required to control the operating modes of each of the SRAMs on the modules.
Mode
Not Selected Output Disable Read Write 1 = VIH, 0 = VIL, X = Don't Care
CS
1 0 0 0
OE
X 1 0 X
WE
X 1 1 0
VCC Current
ISB1,ISB2 ICC ICC ICC
I/O Pin
High Z High Z DOUT DIN
Reference Cycle
Power Down Read Cycle Write Cycle
Note: CS above is accessed through CS1~4 (and WE by WE1~4 on the PUMA 2S4000, 67S4000A, 77S4000A). For correct operation, CS1~ 4 (and WE1~4) must operate simultaneously for 32 bit operation, in pairs for 16 bit operation, or singly for 8 bit operation.
AC Test Conditions *Input pulse levels: 0.0V to 3.0V *Input rise and fall times: 3 ns *Input and Output timing reference levels: 1.5V *Vcc=5V10% *PUMA module is tested in 32 bit mode.
Output Load
I/O Pin 166 1.76V 30pF
Low Vcc Data Retention Characteristics - L Version Only (TA=-55C to +125oC)
Parameter
VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Operation Recovery Time
Symbol Test Condition
VDR ICCDR tCDR tR
CS1~4 VCC-0.2V VCC = 3.0V, CS1~4 VCC-0.2V, VIN VCC-0.2V or 0.2V See Retention Waveform See Retention Waveform
min
2 -
typ
-
max
20 -
Unit
V mA ns ns
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PUMA 2/67/77S4000/A - 020/025/35
Issue 4.3 : December 1999
AC OPERATING CONDITIONS Read Cycle
Parameter
Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Hold from Address Change Chip Selection to Output in Low Z Output Enable to Output in Low Z
Symbol
tRC tAA tACS tOE tOH tCLZ tOLZ
(3) (3)
min
20 5 6 0 0 0
020 max
20 20 9 9 9
min
25 5 5 0 -
025 max
25 25 8 15 15
min
35 5 5 0 -
35 max Units
35 35 12 15 15 ns ns ns ns ns ns ns ns ns
Chip Deselection to Output in High Z tCHZ Output Disable to Output in High Z tOHZ
Write Cycle
020 Parameter
Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Output Active from End of Write Data Hold from Write Time Write to Output High Z
025 max
15 -
35 max
10
Symbol
tWC tCW tAW tAS tWP tWR tDW tOW tDH tWHZ
min
20 15 15 0 15 0 0 15 2* 5
min
25 16 16 0 15 5 10 3 2* 0
min
35 20 20 0 20 5 15 3 2* 0
max
10
Unit
ns ns ns ns ns ns ns ns ns ns
* Note : Only applies to PUMA 67S4000/A otherwise tDH (min) = 0
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PUMA 2/67/77S4000/A - 020/025/35
Issue 4.3 : December 1999
Read Cycle Timing Waveform (1,2)
t
A0~A16
RC
t AA
OE
t OE t OLZ
CS1~4
t OH
t CLZ t ACS t CHZ(3) t OHZ(3) High-Z
D0~31
Data Valid
Notes: (1) During the Read Cycle, WE is high for the modules. (2) Address valid prior to or coincident with CS transition Low. (3) tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
t WC
A0~A16
OE
t AS(3) t AW t CW(4)
(6)
tWR
(2)
CS1~4
t WP(1)
WE1~4
t OHZ(3,9)
D0~31out
High-Z t DW High-Z
t OW t DH
D0~31in
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PUMA 2/67/77S4000/A - 020/025/35
Issue 4.3 : December 1999
Write Cycle No.2 Timing Waveform (5)
t WC
A0~A16
tCW
CS1~4
(6)
(4)
t AW t WP(1)
WE1~4
t WR(2)
t AS(3) t WHZ(3,9) t OW High-Z t DW
t OH
(8) (7)
D0~31out
tDH
D0~31in
High-Z
Low VCC Data Retention Timing Waveform
DATA RETENTION MODE
4.5V 4.5V
Vcc
t CDR
2.2V
tR
2.2V
V DR
CS1~4 > Vcc-0.2V
0V
CS1~4
AC Characteristics Notes
(1) A write occurs during the overlap (tWP) of a low CS and a low WE. (2) tWR is measured from the earlier of CS or WE going high to the end of write cycle. (3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied. (4) If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain in a high impedance state. (5) OE is continuously low. (OE=VIL) (6) DOUT is in the same phase as written data of this write cycle. (7) DOUT is the read data of next address. (8) If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied. (9) tWHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. These parameters are sampled and not 100% tested. WE above refers to WE1~4 on the PUMA 2S4000, 67S4000A AND 77S4000A.
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PUMA 2/67/77S4000/A - 020/025/35
Issue 4.3 : December 1999
Package Details PUMA 67S4000
1.35 (0.053) 0.94 (0.037) 25.40 (1.000) sq. 24.89 (0.980) sq. 24.99 (0.984) sq. 24.49 (0.964) sq.
0.10 (0.004) 5.13 (0.202) max R=0.76 (0.030) typ.
1.27 (0.050) typ. 20.07 (0.790) sq. 20.57 (0.810) sq. 24.13 (0.950) sq. 23.11 (0.910) sq. 21.37 (0.840) 21.08 (0.830)
0.43 (0.017) typ.
0.64 (0.025) min
PUMA 77S4000
25.15 (0.990) sq. 24.67 (0.970) sq. 22.61 (0.890) sq. 22.10 (0.870) sq. 0.76 (0.030) 1.78 (0.070)
1.27 (0.050)
PUMA 2S4000
27.69 (1.090) square 27.08 (1.066) square 4.83 (0.190) 4.32 (0.170) 2.54 (0.010)
0.43 (0.017)
5.44 (0.214) max 0.10 (0.004)
15.24 (0.60) typ
24.13 (0.950) sq. 23.62 (0.930) sq.
20.57 (0.810) sq. 20.10 (0.790) sq.
3.81 (0.150) ref 0.53 (0.021) 0.38 (0.015)
1.27 (0.050)
2.54 (0.010)
LEAD FINISH IS 300 INCH MINIMUM SOLDER OVER 50 TO 350 INCH NICKEL
1.27 (0.050) 1.66 (0.026) 1.52 (0.060) 1.02 (0.040)
10.67 (0.420) 10.16 (0.400)
6.86 (0.270) max
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PUMA 2/67/77S4000/A - 020/025/35
Issue 4.3 : December 1999
Pin Definitions PUMA 67S4000 / PUMA 77S4000
GND WE1 A6 CS3 CS4 A10 Vcc NC
PUMA 67S4000A / PUMA 77S4000A
GND WE1 A6 CS3 CS4 A10 NC A1 Vcc
A1
A0
A2
A3
A4
A5
A7
A8
A0
A2
A3
A4
A5
A7
A8
A9
9 D0 D1 D2 D3 D4 D5 D6 D7 GND D8 D9 D10 D11 D12 D13 D14 D15 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 D16 D17 D18 D19 D20 D21 D22 D23 GND D24 D25 D26 D27 D28 D29 D30 D31 D0 D1 D2 D3 D4 D5 D6 D7 GND D8 D9 D10 D11 D12 D13 D14 D15 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 D16 D17 D18 D19 D20 D21 D22 D23 GND D24 D25 D26 D27 D28 D29 D30 D31
PUMA 67S4000
VIEW FROM ABOVE
PUMA 67S4000A
VIEW FROM ABOVE
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A11 A12 A13 A14 A15 A16 Vcc CS1 OE NC NC CS2 NC NC NC GND NC
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A11 A12 A13 A14 A15 A16 Vcc CS1 WE2 WE3 WE4 OE CS2 NC NC GND NC
PUMA 2S4000
1 D8
2
12 WE2 13 CS2 14 GND 15 D11 16 A10 17 A11 18 A12 19 VCC 20 CS1 21 NC 22 D3
23 D15 24 D14 25 D13 26 D12 27 OE 28 NC 29 WE1 30 D7 31 D6 32 D5 33 D4
34 D24 35 D25 36 D26 37 A6
45 VCC 46 CS4 47 WE4 48 D27 49 A3 50 A4 51 A5 52 WE3 53 CS3 54 GND 55 D19
56 D31 57 D30 58 D29 59 D28 60 A0 61 A1 62 A2 63 D23 64 D22 65 D21
66
D9 3 D10 4 A13 5 A14 6 A15 7 A16 8 NC 9 D0 10 D1 11 D2
VIEW FROM ABOVE
38 A7 39 NC 40 A8 41 A9 42 D16 43 D17 44 D18
D20
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A9
PUMA 2/67/77S4000/A - 020/025/35
Issue 4.3 : December 1999
SCREENING Military Screening Procedure MultiChip Screening Flow for high reliability product is in accordance with Mil-883 method 5004 .
MB MULTICHIP MODULE SCREENING FLOW
SCREEN
Visual and Mechanical
Internal visual Temperature cycle Constant acceleration 2010 Condition B or manufacturers equivalent 1010 Condition C (10 Cycles,-65oC to +150oC) 2001 Condition B (Y1 & Y2) (10,000g) 100% 100% 100%
TEST METHOD
LEVEL
Burn-In
Pre-Burn-in electrical Burn-in Per applicable device specifications at TA=+25oC TA=+125oC,160hrs minimum. Per applicable Device Specification a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes Calculated at post-burn-in at TA=+25oC 1014 Condition A Condition C Per applicable Device Specification 2009 Per vendor or customer specification 100% 100% Sample 100% 100% 100% 100% 100% 100% 100% 10% 100% 100%
Final Electrical Tests
Static (DC) Functional Switching (AC)
Percent Defective allowable (PDA) Hermeticity
Fine Gross
Quality Conformance External Visual
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PUMA 2/67/77S4000/A - 020/025/35
Issue 4.3 : December 1999
Ordering Information
PUMA 2S4000ALMB-020
Speed 020 025 35 = 20 ns = 25 ns = 35 ns = = = = Commercial Temperature Industrial Temperature Military Temperature May be processed in accordance with MIL-STD-883
Temp. range/screening Blank I M MB
Power Consumption
Blank = Standard Power L = Low Power Blank = Single WE (PUMA 67 / 77 only) WE1~4 (PUMA 2 only) A = WE1~4 (PUMA 67 / 77 only) 4000 = 128Kx 32, user confiurable as 256K x 16 and 512K x 8 S = SRAM MEMORY = JEDEC 66 Pin Ceramic PGA package = JEDEC 68 J-Leaded Ceramic Surface Mount package = JEDEC 68 Leaded Gull Wing Ceramic Surface Mount package
WE Option
Organisation Technology Package
PUMA 2 PUMA 67
PUMA 77
Note : Although this data is believed to be accurate, the information contained herein is not intended to, and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed at any time without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director.
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