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2Mx16x4 Banks Synchronous DRAM
FEATURES
Single 3.3V power supply Fully Synchronous to positive Clock Edge Clock Frequency = 100, 83MHz SDRAM CAS Latency = 3 (100MHz), 2 (83MHz) Burst Operation Sequential or Interleave Burst length = programmable 1,2,4,8 or full page Burst Read and Write Multiple Burst Read and Single Write
WED416S8030A
DESCRIPTION
The WED416S8030A is 134,217,728 bits of synchronous high data rate DRAM organized as 4 x 2,097,152 words x 16 bits. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Available in a 54 pin TSOP type II package the WED416S8030A is tested over the industrial temp range (-40C to +85C) providing a solution for rugged main memory applications.
DATA Mask Control per byte Auto Refresh (CBR) and Self Refresh 4096 refresh cycles across 64ms Automatic and Controlled Precharge Commands Suspend Mode and Power Down Mode Industrial Temperature Range
FIG. 1
PIN CONFIGURATION
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CE BA0 BA1 A10/AP A0 A1 A2 A3 VDD
PIN DESCRIPTION
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC/RFU UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
A0-11 CE WE CLK CKE DQ0-15 RAS CAS VDD VDDQ VSS VSSQ NC Address Inputs Chip Select Write Enable Clock Input Clock Enable Data Input/Output Row Address Strobe Column Address Strobe Power (3.3V) Data Output Power Ground Data Output Ground No Connection BA0, BA1 Bank Select Addresses
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
TERMINAL CONNECTIONS
(TOP VEIW)
L(U)DQM Data Input/Output Mask
May 2001 Rev. 1 ECO #14194
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INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol CLK CKE CE RAS, CAS WE BA0,BA1 A0-11, A10/AP Type Input Input Input Input Input Signal Pulse Level Pulse Pulse Level Polarity Function
WED416S8030A
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Active High Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. Active Low Active Low CE disable or enable device operation by masking or enabling all inputs except CLK, CKE and DQM. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-11 defines the row address (RA0-11) when sampled at the rising clock edge.
Input
Level
During a Read or Write command cycle, A0-8 defines the column address (CA0-8) when sampled at the rising clock edge. In addition to the row address, A10/AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged . If A10/AP is low, autoprecharge is disabled. During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the state of BA0, BA1. If A10/AP is low, then BA0, BA1 is used to define which bank to precharge.
DQ0-15 L(U)DQM
Input/Output Input
Level Pulse
Data Input/Output are multiplexed on the same pins
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled Mask high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an Active High output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the Write operation if DQM is high. Power and ground for the input buffers and the core logic. Isolated power and ground for the output buffers to improve noise immunity.
VDD, Vss
Supply
VDDQ, VSSQ Supply
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current Symbol VDD VIN VOUT TOPR TSTG PD IOS Min -1.0 -1.0 -1.0 -40 -55 Max +4.6 +4.6 +4.6 +85 +125 1.0 50 Units V V V C C W mA Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Voltage Output Leakage Voltage
WED416S8030A
RECOMMENDED DC OPERATING CONDITIONS (VOLTAGE REFERENCED TO: VSS = 0V, TA = -40C TO +85C)
Symbol Min VDD VIH VIL VOH VOL IIL IOL 3.0 2.0 -0.3 2.4 -5 -5 Typ 3.3 Max 3.6 0.8 0.4 5 5 Unit V V V V (IOH = -2mA) V (IOL = 2mA) A A Notes
3.0 VDD +0.3
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = 25C, f = 1MHZ, VDD = 3.3V TO 3.6V)
Parameter Input Capacitance (A0-11, BA0-1) Input Capacitance (CLK, CKE, RAS, CAS, WE, CE, L(U)DQM ) Input/Output Capacitance (DQ0-15) Symbol CI1 CI2 COUT Max 4 4 5 Unit pF pF pF
OPERATING CURRENT CHARACTERISTICS (VCC = 3.3V, TA = -40C TO +85C)
Parameter Operating Current (One Bank Active) Operating Current (Burst Mode) Precharge Standby Current in Power Down Mode Symbol ICC1 ICC4 ICC2P ICC2PS ICC1N Precharge Standby Current in Non-Power Down Mode ICC1NS ICC3P ICC3PS ICC2N Active Standby Current in Non-Power Down Mode ICC2NS Refresh Current Self Refresh Current NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms. ICC5 ICC6 CKE Conditions Burst Length = 1, tRC CKE CKE, CLK
tRC(min)
-10 140 200 2 2 50 35 12 12 30 20 210 3
-12 125 165 2 2 50 35 12 12 30 20 210 3
Units Notes mA mA mA mA mA mA mA mA mA mA mA mA 2 1 1
Page Burst, 2 banks active, tCCD = 2 clocks
VIL(max), tCC = 15ns VIL(max), tCC = , Inputs Stable
CKE = VIH, tCC = 15ns Input Change every 30ns CKE VIH(min), tCC = No Input Change CKE CKE
Active Standby Current in Power Down Mode
VIL(max), tCC = 15ns VIL(max), tCC = , No Input Change tRC(min) CKE 0.2V
tCC =
VIH(min),
CKE = VIH, tCC = 15ns Input Change every 30ns tRC
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AC CHARACTERISTICS
OPERATING AC PARAMETERS (VCC = 3.3V, TA = -40C TO +85C)
Parameter Clock Cycle Time Clock to Valid Output Delay Output Data Hold Time Clock High Pulse Width Clock Low Pulse Width Input Setup Time Input Hold Time Clock to Output in Low-Z Clock to Output in High-Z Row Active to Row Active Delay RAS to CAS Delay Row Precharge Time Row Active Time Row Cycle Time - Operation Row Cycle Time - Auto Refresh Last Data In to New Column Address Delay Last Data In to Row Precharge Last Data In to Burst Stop Column Address to Column Address Delay Number of Valid Output Data CAS latency = 3 CAS latency = 2 CAS latency = 3 CAS latency = 2 tSAC tOH tCH tCL tSS tSH tSLZ tSHZ tRRD tRCD tRP tRAS tRC tRFC tCDL tRDL tBDL tCCD 20 24 24 50 80 80 1 1 1 1 2 1 100,000 3 3.5 3.5 2.5 1 1 7 Symbol Min tCC 10 13 -10 Max 1000 1000 7
WED416S8030A
-12 Min 12 15 3 4.0 4.0 3 1 1 8 24 26 26 60 90 90 1 1 1 1 2 1 100,000 Max 1000 1000 8
Unit
Notes
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK CLK CLK CLK ea
1 1,2 2 3 3 3 3 2 4 4 4 4 4 4, 8 5 5 5 6 7
NOTES: 1. Parameters depend on programmed CAS latency. 2. If clock rising is longer than 1ns, (trise/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If tr & tf are longer than 1ns, [(trise + tfall)/2-1]ns should be added to the parameter. 4. The minimum number of clock cycles required is determined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address change 7. In case of row precharge interrupt, auto precharge and read burst stop. 8. A new command may be given tRFC after self refresh exit.
REFRESH CYCLE PARAMETERS
-10 Parameter Refresh Period Self Refresh Exit Time Symbol tREF tSREX Min tRFC Max 64 Min tRFC -12 Max 64 Units ms ns Notes 1,2 3
NOTES: 1. 4096 cycles. 2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device. 3. The self refresh is exited by restarting the external clock and then asserting CKE high. This must be followed by NOPs for minimum time of tRFC before the SDRAM reaches idle state to begin normal operation.
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Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) CAS Latency 3 3 2 2 tRC 80ns 8 7 6 6 tRAS 50ns 5 5 4 4 tRP 24ns 3 2 2 2 tRRD 20ns 2 2 2 2 tRCD 24ns 3 2 2 2
WED416S8030A
CLOCK FREQUENCY AND LATENCY PARAMETERS - 100MHZ (UNITS = NUMBER OF CLOCKS)
tCCD 10ns 1 1 1 1 tCDL 10ns 1 1 1 1 tRDL 10ns 1 1 1 1
CLOCK FREQUENCY AND LATENCY PARAMETER - 83MHZ (UNITS = NUMBER OF CLOCKS)
Frequency 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) CAS Latency 3 3 2 tRC 90ns 8 7 6 tRAS 60ns 5 5 4 tRP 26ns 3 2 2 tRRD 24ns 2 2 2 tRCD 26ns 3 2 2 tCCD 12ns 1 1 1 tCDL 12ns 1 1 1 tRDL 12ns 1 1 1
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COMMAND TRUTH TABLE
CKE Command Register Refresh Precharge Bank Activate Write Read Burst Stop No Operation Device Select Clock Suspend/Standby Mode Data Write/Output Enable Mask/Output Disable Power Down Mode Entry Exit Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Mode Register Set Auto(CBR) Refresh Entry Self Refresh Single Bank All Banks Previous Current Cycle Cycle H H H H H H H H H L H X X H L X X X X X X X X X L H CE L L L L L L L L H X X H RAS L L L L H H H H X X X X CAS L L H H L L H H X X X X WE L H L H L H L H X X X X DQM X X X X X X X X X X L H X
WED416S8030A
BA
A10/Ap
A11, A9-0
Notes
OP CODE X BA X BA BA BA X X X X X X X L H L H L H X X X X X X X X X 2 2 2 2 2 3 Column Address Column Address X X X X X X 4 5 5 6 6 2
Row Address
(X = Don't Care, H = Logic High, L = Logic Low) NOTES: 1. All of the SDRAM operations are defined by states of CE, WE, RAS, CAS, and DQM at the positive rising edge of the clock. 2. Bank Select (BA), if BA0, BA1 = 0, 0 then bank A is selected, if BA0, BA1 = 1, 0 then bank B, if BA0, BA1 = 0, 1 then bank C, if BA0, BA1 = 1, 1 then bank D is selected, respectively. 3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency. 4. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibted (zero clock latency). 6. All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not perform any Refresh operations, therefore the device cannot remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
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CLOCK ENABLE (CKE0) TRUTH TABLE
CKE Current State Previous Current H L L Self Refresh L L L L H Power Down L L H H H H H H All Banks Idle H H H H H L H Any State other than listed above H L L X H H H H H L X H H X H H H H H L L L L H X H L H L Command CE X H L L L L X X H L L H L L L L H L L L L X X X X X RAS X X H H H L X X X X H X H L L L X H L L L X X X X X CAS X X H H L X X X X X L X X H L L X X H L L X X X X X WE X X H L X X X X X X L X X X H L X X X H L X X X X X X X X X X X OPCode X X X X X X X OPCode X BA X X X X X X X X X X X A0-11 X X X X X X X X X X
WED416S8030A
Action INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down Mode exit, all banks idle ILLEGAL Maintain Power Down Mode Refer to the Idle State section of the Current State Truth Table CBR Refresh Mode Register Set Refer to the Idle State section of the Current State Truth Table Entry Self Refresh Mode Register Set Power Down Refer to the Operations in the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend
Notes 1 2 2 2 2 2 1 2 2
3
4 3 4 4
5
NOTES: 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCKS) must be satisfied before any command other than Exit is issued. 3. The address inputs (A11-A0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state. Must be a legal command as defined in the Current State Truth Table.
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CURRENT STATE TRUTH TABLE
Current State Command CE L L L L Idle L L L L H L L L L Row Active L L L L H L L L L Read L L L L H L L L L Write L L L L H L L L Read with Auto Precharge L L L L L H RAS L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X CAS L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X WE L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X X X B A B A B A X X X X X B A B A B A X X X OPCode X X Row Address Column Column X X X
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WED416S8030A
BA X X B A B A B A X X X
A11, A10/AP-A0 OP Code X X Row Address Column Column X X X OPCode X X Row Address Column Column X X X OPCode X X Row Address Column Column X X X OPCode X X Row Address Column Column X X X
Description Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect
Action Set the Mode Register Start Auto orSelf Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst
Notes 2 2,3
4 4
5
X X B A B A B A X X X X X B A B A B A X X X
6 4 7,8 7,8
4 8,9 8,9
4 8,9 8,9
4 4
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CURRENT STATE TRUTH TABLE (CONT.)
Current State CE L L L Write with Auto Precharge L L L L L H L L L L Precharging L L L L H L L L L Row Activating L L L L H L L L L Write Recovering L L L L H L L L Write Recovering with Auto Precharge L L L L L H RAS L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X CAS L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X Command WE L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X BA A11, A10/AP-A0 OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X Description Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect
WED416S8030A
Action
Notes
ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Row active after tRCD No Operation; Row active after tRCD No Operation; Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation; Row active after tDPL No Operation; Row active after tDPL No Operation; Row active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Precharge after tDPL No Operation; Precharge after tDPL No Operation; Precharge after tDPL 4 4 4,9 4,9 4 4 9 9 4 4,10 4 4 4 4 4 4 4
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CURRENT STATE TRUTH TABLE (CONT.)
Current State Command CE L L L L Refreshing L L L L H L L L Mode Register Accessing L L L L L H RAS L L L L H H H H X L L L L H H H H X CAS L L H H L L H H X L L H H L L H H X WE L H L H L H L H X L H L H L H L H X X X B A B A B A X X X X X B A B A B A X X X OPCode X X Row Address Column Column X X X BA A11, A10/AP-A0 OPCode X X Row Address Column Column X X X Description Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect
WED416S8030A
Action ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after tRC No Operation; Idle after tRC No Operation; Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles No Operation; Idle after two clock cycles
Notes
NOTES: 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to. 2. Both Banks must be idle otherwise it is an illegal action. 3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered. 4.The Current State refers only to one of the banks, if BA0, BA1 selects this bank then the action is illegal. If BA0, BA1 selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered, otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
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MODE REGISTER DEFINITION
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
WED416S8030A
BURST DEFINITION
Mode Register (Mx) Reserved* WB Op Mode CAS Latency BT Burst Length
*Should program M11, M10 = "0, 0" to ensure compatibility with future devices.
Burst Length M2 M1 M0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 M3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page M3 = 1 1 2 4 8 Reserved Reserved Reserved Reserved
M3 0 1
Burst Type Sequential Interleaved
Burst Starting Column Order of Accesses Within a Burst Type = Sequential Type = Interleaved Length Address A0 2 0 0-1 0-1 1 1-0 1-0 A1 A0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Cn, Cn + 1, Cn + 2 Full n = A0-A8 Cn + 3, Cn + 4... Not Supported Page (location 0-y) ...Cn - 1, (y) Cn...
M6 M5 M4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
M8 0 -
M7 0 -
M6-M0 Defined -
Operating Mode Standard Operation All other states reserved
M9 0 1
Write Burst Mode Programmed Burst Length Single Location Access
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WED416S8030A
FIG. 2 SINGLE BIT READ-WRITE CYCLE (SAME PAGE) @ CAS LATENCY=3, BURST LENGTH=1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
tCC
CKE
tCH
tCL
HIGH
tRAS
CE
tRCD
tRCD
tSS
tSH
tRP
tSS
RAS
tSH
tSS
CAS
tSH
tCCD
tSS
ADDR Ra
tSH
Ca
tSS
Cb
tSH
Cc Rb
Note 2
Note 2, 3
Note 2, 3
Note 2, 3 Note 4
Note 2
BA
BS
BS
BS
BS
BS
BS
A10/AP
Ra
Note 3
Note 3
Note 3
Note 4
Rb
tRAC tSAC
DQ Qa
tSS
Db
tSH
Qc
tSLZ
WE
tOH
tSS
tSH
tSS
DQM
tSH
Row Active
Read
Write
Read Precharge
Row Active
DON'T CARE
NOTES: BA0 BA1 Active & Read/Write 1. All input except CKE & 0 0 Bank A DQM can be don't care 0 1 Bank B when CE is high at the 1 0 Bank C CLK high going edge. 1 1 Bank D 2. Bank active & read/write are controlled by BA0~BA1. 4. A10/AP and BA0~BA1 control bank precharge when precharge command is asserted. A10/AP BA0 BA1 Precharge 0 0 0 Bank A 0 0 1 Bank B 0 1 0 Bank C 0 1 1 Bank D 1 x x All Banks
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command. A10/AP BA0 BA1 00 01 0 10 11 00 01 1 10 11 Operation Distribute auto precharge, leave bank A active at end of burst. Disable auto precharge, leave bank B active at end of burst. Disable auto precharge, leave bank C active at end of burst. Disable auto precharge, leave bank D active at end of burst. Enable auto precharge, precharge bank A at end of burst. Enable auto precharge, precharge bank B at end of burst. Enable auto precharge, precharge bank C at end of burst. Enable auto precharge, precharge bank D at end of burst.
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FIG. 3 POWER UP SEQUENCE
WED416S8030A
0 CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
High level is necessary
CE
tRP
RAS
tRFC
tRFC
CAS
ADDR
Key
RAa
BA
A10/AP
RAa
DQ
HIGH-Z
WE
DQM
High level is necessary
Precharge (All Banks)
Auto Refresh
Auto Refresh
Mode Register Set Row Active (A-Bank)
DON'T CARE
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WED416S8030A
FIG. 4 READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
tRC
CE
Note 1
tRCD
RAS
Note 2
CAS
ADDR
Ra
Ca0
Rb
Cb0
BA
A10/AP
Ra
Rb
Note 3
tRAC
tSAC
Qa0
tOH
Qa1 Qa2
tSHZ
Qa3
Note 4
tRDL
Db0 Db1 Db2 Db3
CL = 2 DQ CL = 3
Note 3
tRAC
tSAC
Qa0
tOH
Qa1 Qa2
tSHZ
Qa3
Note 4
tRDL
Db0 Db1 Db2 Db3
WE
DQM
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Row Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. Minimum row cycle times are required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock. 3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC. 4. Output will be Hi-Z after the end of burst (1, 2, 4, 8 & full page bit burst).
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WED416S8030A
FIG. 5 PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
HIGH
CE
tRCD
RAS
Note 2
CAS
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA
A10/AP
Ra
tRDL
CL = 2 DQ CL = 3 Qa0 Qa1 Qb0 Qb1 Dc0 Qa0 Qa1 Qb0 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1
tCDL
Dc1 Dd0 Dd1
WE
Note 1
Note 3
DQM
Row Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. To write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row prechage cycle will be masked internally.
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WED416S8030A
FIG. 6 PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
Note 1
HIGH
CE
RAS
Note 2
CAS
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
CAe
BA
A10/AP
RAa
RBb
CL = 2 DQ
CL = 3
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2 QBb3
QAc0
QAc1
QBd0
QBd1 QAe0
QAe1
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2
QBb3
QAc0
QAc1
QBd0 QBd1
QAe0
QAe1
WE
DQM
Row Active (A-Bank)
Row Active (B-Bank) Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. CE can be don't cared when RAS, CAS, and WE are high at the clock high going edge. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
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White Electronic Designs
WED416S8030A
FIG. 7 PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CE
RAS
Note 2
CAS
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
BA
A10/AP
RAa
RBb
tCDL
DQ DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0
tRDL
DBd1
WE
Note 1
DQM
Row Active (A-Bank)
Row Active (B-Bank) Write (A-Bank)
Write (B-Bank)
Write (A-Bank)
Write (B-Bank)
Precharge (Both Banks)
DON'T CARE
NOTES: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
17
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White Electronic Designs
WED416S8030A
FIG. 8 READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CE
RAS
CAS
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
BA
A10/AP
RAa
RBb
RAc
tCDL
CL = 2 DQ CL = 3 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3
Note 1
QAc0
QAc1
QAc2
QAc0
QAc1
WE
DQM
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank) Row Active (B-Bank)
Write (B-Bank) Row Active (A-Bank)
Read (A-Bank)
DON'T CARE
NOTES: 1. tCDL should be met to complete write.
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WED416S8030A
FIG. 9 READ & WRITE CYCLE WITH AUTO PRECHARGE @ BURST LENGTH=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
HIGH
CE
RAS
CAS
ADDR
Ra
Rb
Ca
Cb
BA
A10/AP
Ra
Rb
CL = 2 DQ CL = 3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
WE
DQM
Row Active (A-Bank)
Read with Auto Precharge (A-Bank) Row Active (B-Bank)
Auto Precharge Start Point (A-Bank)
Write with Auto Precharge (B-Bank)
Auto Precharge Start Point (B-Bank)
DON'T CARE
NOTES: 1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length=1 & 2 and BRSW mode)
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WED416S8030A
FIG. 10 CLOCK SUSPENSION & DQM OPERATION CYCLE @ CAS LATENCY=2, BURST LENGTH=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
CE
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
BA
A10/AP
Ra
tSHZ
DQ Qa0 Qa1 Qa2 Qa3 Qb1
tSHZ
Qb1 Dc0 Dc2
WE
Note 1
DQM
Row Active
Read
Clock Suspension
Read
Read DQM Write
Write DQM Clock Suspension
Write DQM
DON'T CARE
NOTES: 1. DQM is needed to prevent bus contention.
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WED416S8030A
FIG. 11 READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @ BURST LENGTH=FULL PAGE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CE
RAS
CAS
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa
Note 2
1
1
CL = 2 DQ
QAa0
QAa1
QAa2
QAa3
QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
2
2
CL = 3
QAa0
QAa1
QAa2
QAa3
QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
WE
DQM
Row Active (A-Bank)
Read (A-Bank)
Burst Stop
Read (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated in above timing diagram. See the label 1, 2. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer to the timing diagram of "Full page write burst stop cycle." 3. Burst stop is valid at every burst length.
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White Electronic Designs
WED416S8030A
FIG. 12 WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP CYCLE @ BURST LENGTH=FULL PAGE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CE
RAS
CAS
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa
tBDL
DQ DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4
tRDL
Note 2
DAb5
WE
DQM
Row Active (A-Bank)
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. Data-in at the cycle of interrupted by precharge cannnot be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length.
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WED416S8030A
FIG. 13 BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
Note 1
CKE
HIGH
CE
RAS
Note 2
CAS
ADDR
RAa
CAa
RBb
CAb
RAc
CBc
CAd
BA
A10/AP
RAa
RBb
RAc
CL = 2
DQ CL = 3
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
WE
DQM
Row Active (A-Bank)
Row Active (B-Bank) Write (A-Bank) Read with Auto Precharge (A-Bank)
Row Active (A-Bank) Write with Auto Precharge (B-Bank)
Read (A-Bank)
Precharge (Both Banks)
DON'T CARE
NOTES: 1. BRSW mode is enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge.
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WED416S8030A
FIG. 14 ACTIVE/PRECHARGE POWER DOWN MODE @ CAS LATENCY=2, BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
tSS
CKE
Note 1 Note 3
Note 2
tSS
tSS
CE
RAS
CAS
ADDR
Ra
Ca
BA
A10/AP
Ra
tSHZ
DQ Qa0 Qa1 Qa2
WE
DQM
Precharge Power-Down Entry
Row Active Precharge Active Power-Down Power-Down Exit Entry
Read Active Power-Down Exit
Precharge
DON'T CARE
NOTES: 1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + tss prior to Row active command. 3. Can not violate minimum refresh specification (64ms).
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FIG. 15 SELF REFRESH ENTRY & EXIT CYCLE
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14
WED416S8030A
15
16
17
18
19
tSS
CKE
Note 1
Note 2 Note 3 Note 4
tRFC min
Note 6
CE
Note 5
RAS
Note 7
CAS
ADDR
BA
A10/AP
DQ
HI-Z
HI-Z
WE
DQM
Self Refresh Entry
Self Refresh Exit
Auto Refresh
DON'T CARE
NOTES: TO ENTER SELF REFRESH MODE 1. CE, RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low." Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CE starts from high. 6. Minimum tRFC is required after CKE going high to complete self refresh exit. 7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
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FIG. 16 MODE REGISTER SET CYCLE
WED416S8030A
FIG. 17 AUTO REFRESH CYCLE
0 CLOCK
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
9
10
CKE
HIGH
HIGH
CE
Note 2
tRFC
RAS
Note 1
CAS
Note 3
ADDR
Key
Ra
DQ
HI-Z
HI-Z
WE
DQM
MRS
New Command
Auto Refresh
New Command
DON'T CARE
NOTES: Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE 1. CE, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table.
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PACKAGE DIMENSION: 54 PIN TSOP II
22.35 (0.880) 22.10 (0.870) Note 1
WED416S8030A
VIEW A
1.20 (0.047) MAX
10.29 (0.405) 10.03 (0.395) Note 2
11.96 (0.471) 11.56 (0.455)
0.15 (0.006) 0.05 (0.002)
0.61 (0.024) 0.41 (0.016)
0.80 (0.0315) TYP
NOTES: 1. Dimension does not include 0.006 inch Flash each side. 2. Dimension does not include 0.010 inch Flash each side.
0.51 (0.020) 0.25 (0.010)
SEE VIEW A 0-8
0.203 (0.008) 0.125 (0.005)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
Part Number WED416S8030A10SI WED416S8030A12SI Organization 2Mx16bitsx4banks 2Mx16bitsx4banks Operating Frequency 100MHz 83MHz Package 54 TSOP II 54 TSOP II
NOTE: This product does not include the prefix "WED" for part marking due to package size constraints.
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