 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU TARGET DATASHEET MARCH 2003 DESCRIPTION The 78P2352 is TDK's second generation LIU for 155 Mbit/s SDH/SONET (OC-3, STS-3, or STM-1) and 140Mbit/s PDH (E4) applications. The device is a dual channel, single chip solution that includes an integrated CDR in the transmit path for flexible NRZ to CMI conversion. The device can interface to 75 coaxial cable using CMI coding or directly to a fiber optics module using NRZ coding. The 78P2352 is compliant with all respective ANSI, ITU-T, and Telcordia standards for jitter tolerance, generation, and transfer. APPLICATIONS * * * * Central Office Interconnects DSLAMs Add Drop Multiplexers (ADMs) PDH/SDH test equipment FEATURES * * * * * * * * * * * * BLOCK DIAGRAM EACH CHANNEL: Tx TXxCKP/N CMIxP/N SIxCKP/N PIxCK PIx[3:0]D PTOxCK SOxCKP/N SOxDP/N POx[3:0]D POxCK CMI-LCV Detect EACH CHANNEL: Rx CMI Decoder Rx CDR Lock Detect Adaptive Eq. G.775 LOS Detect RXxP/N FIFO CMI Encoder ECLxP/N G.703 compliant line interface for 139.264 Mbps or 155.52 Mbps CMI-coded coax transmission. LVPECL compatible line interface for 155.52 Mbps NRZ-coded fiber applications. Integrated adaptive CMI equalizer and CDR in receive path. Serial, LVPECL-compatible system interface with integrated CDR in transmit path for NRZ to CMI conversion. 4-bit parallel CMOS system interface with master/slave Tx clock modes. Configurable via HW control pins or 4-wire P interface Operates from a single reference clock input. Compliant with ANSI T1.105.03-1994; ITU-T G.751, G.813, G.823, G.825, G.958; and Telcordia GR-253-CORE for jitter performance. Provides Loss of Lock (LOL), CMI Line Code Violation (LCV), and G.775 compliant Loss of Signal (LOS) detection. Receiver Monitor Mode Operates from a single 3.3V supply 128-pin TQFP (JEDEC LQFP) package Lock Detect SIxDP/N Tx CDR 1 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit TABLE OF CONTENTS FUNCTIONAL DESCRIPTION MODE SELECTION REFERENCE CLOCK RECEIVER OPERATION Receiver Monitor Mode Loss of Signal / Loss of Lock TRANSMITTER OPERATION Serial Modes Parallel Modes Transmit Driver Clock Synthesizer POWER-DOWN FUNCTION LOOPBACK MODES POWER-ON RESET SERIAL CONTROL INTERFACE PROGRAMMABLE INTERRUPTS 2 4 4 4 4 4 4 5 5 6 6 6 6 7 7 7 7 REGISTER DESCRIPTION REGISTER ADDRESSING REGISTER TABLE LEGEND GLOBAL REGISTERS ADDRESS 0-0: MASTER CONTROL REGISTER ADDRESS 0-1: INTERRUPT CONTROL REGISTER PORT-SPECIFIC REGISTERS ADDRESS N-0: MODE CONTROL REGISTER ADDRESS N-1: SIGNAL CONTROL REGISTER ADDRESS N-2: ADVANCED CONTROL REGISTER 1 ADDRESS N-3: ADVANCED CONTROL REGISTER 2 ADDRESS N-4: MODE CONTROL REGISTER 2 ADDRESS N-5: STATUS MONITOR REGISTER 8 8 8 9 9 9 10 11 11 12 12 12 13 13 PIN DESCRIPTION LEGEND TRANSMITTER PINS RECEIVER PINS REFERENCE AND STATUS PINS CONTROL PINS SERIAL-PORT PINS POWER AND GROUND PINS 14 14 14 15 15 16 17 17 2 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit TABLE OF CONTENTS (continued) ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS DC CHARACTERISTICS ANALOG PINS CHARACTERISTICS DIGITAL I/O CHARACTERISTICS Pins of type CI, CIU, CID Pins of type CIS Pins of type CO and COZ Pins of type PO SERIAL-PORT TIMING CHARACTERISTICS TRANSMITTER TIMING CHARACTERISTICS TIMING DIAGRAM: Transmitter Waveforms REFERENCE CLOCK CHARACTERISTICS RECEIVER TIMING CHARACTERISTICS TIMING DIAGRAM: Receive Waveforms TRANSMITTER SPECIFICATIONS FOR CMI INTERFACE TRANSMITTER OUTPUT JITTER RECEIVER (Transformer-coupled) RECEIVER SPECIFICATIONS FOR CMI INTERFACE RECEIVER JITTER TOLERANCE RECEIVER JITTER TRANSFER FUNCTION CMI Mode Loss of Signal Condition 18 18 18 18 19 19 19 19 19 19 20 21 21 22 22 22 23 28 29 29 30 32 33 APPLICATION INFORMATION EXTERNAL COMPONENTS TRANSFORMER SPECIFICATIONS RECOMMENDED LVPECL TERMINATIONS 34 34 34 34 MECHANICAL SPECIFICATIONS PACKAGE INFORMATION Revision History 35 36 37 3 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit FUNCTIONAL DESCRIPTION The 78P2352 contains all the necessary transmit and receive circuitry for connection between 139.264Mbit/s and 155.52Mbit/s signals and the digital universe. The chip is controllable through pins or serial port register settings. In hardware mode (pin control) the SPSL pin must be low. In software mode (SPSL pin high), control pins are disabled and the 78P2352 must be configured via the 4-wire serial port. MODE SELECTION The SDO_E4 pin or E4 register bit determines which rate the device operates in according to the table below. This control combined with CKSL also selects the global reference frequency. Rate E4 STM-1, STS-3, OC-3 SDO_E4 pin High Low E4 bit 1 0 RECEIVER OPERATION The receiver accepts serial data, at 155.52Mbit/s or 139.264Mbit/s from the RXxP/N inputs. In CMI mode, the CMI-coded inputs come from a coaxial cable that is transformer-coupled to the chip. In ECL (NRZ) mode, the input pins receive NRZ LVPECL level signals from an O/E converter. The CMI signal first enters an AGC, which has a selectable gain range setting. When Receiver Monitor Mode is enabled, the AGC can compensate for a monitor signal with 16 to 20 dB of flat loss. The signal then enters a high performance adaptive equalizer designed to overcome inter-symbol interference caused by long cable. The variable gain differential amplifier automatically controls the gain to maintain a constant voltage level output regardless of the input voltage level. In ECL (NRZ) mode, the input signals bypass the adaptive equalizer. The outputs of the data comparators are connected to the clock recovery circuits. The clock recovery system employs a digital PLL, which uses a reference frequency derived from the clock applied to the CKREFP/N pins. After the clock and data have been recovered, the data is converted to binary by the CMI to binary decoder. The CMI Line Code Violation (LCV) detector will flag code errors while the decoder continues to function normally. The three conditions that will flag a LCV are: * `0' has a falling transition mid-bit instead of a rising transition * A high `1' is recovered when it should have been a low `1' * A low `1' is recovered when it should have been a high `1' In serial mode, the clock and data are transmitted through the LVPECL drivers. In parallel mode, the data is converted into four bit parallel segments before being transmitted through the CMOS drivers. Receiver Monitor Mode The SCK_MON pin or MONx register bit puts the receiver in monitor mode and adds 20dB of flat gain to the receive signal before equalization. The SCK_MON pin controls the monitor mode for both channels simultaneously. Individual monitor mode selection can be done using the MONx register bit. Note that Receiver Monitor Mode is available in CMI mode only. Loss of Signal / Loss of Lock The 78P2352 includes standards compliant Loss of Signal (LOS) and Loss of Lock (LOL) indicators for the receive signals. During LOS conditions, the receive data outputs are squelched while the receive clock outputs a line rate clock generated from the reference clock input. The LOS indicator is intended for electrical CMI interfaces only. 4 The SEN_CMI pin or CMI register bit selects one of two media for reception and transmission: coaxial cable in CMI mode or optical fiber in ECL (NRZ) mode. Independent operation is available with register controls (CMI bit). Media (coding) 75 ohm Coax (CMI) Fiber (NRZ) SEN_CMI pin High Low CMI bit 1 0 The SDI_PAR pin or PAR register bit selects the interface to the framer to be four bit parallel or serial. For each interface there are different clocking schemes for the transmitter. These modes and their controls are described in the TRANSMITTER OPERATION section. REFERENCE CLOCK The 78P2352 requires a reference clock supplied to the CKREFP/N pins. For reference frequencies of 77.76MHz or lower, the device accepts a single ended CMOS input at CKREFP. For reference frequencies of 139.264/155.52MHz, the device accepts a differential clock input at CKREFP/N. The frequency of this reference input is selected by the rate selection and the CKSL control pin or register bit. CKSL pin Low Float High CKSL[1:0] bits 00 10 11 Reference Frequency SDO_E4 low SDO_E4 high 19.44MHz 77.76MHz 155.52MHz E4 bit = 0 19.44MHz 77.76MHz 155.52MHz 17.408MHz N/A 139.264MHz E4 bit = 1 17.408MHz N/A 139.264MHz 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit TRANSMITTER OPERATION The transmitter section generates an analog signal for transmission through either a transformer onto the coaxial cable or directly to a fiber optics module. The 78P2352 provides a flexible system interface for compatibility with most off-the-shelf framers and custom ASICs. The device supports a 4-bit parallel interface in either slave or master clocking modes and a number of serial NRZ modes. Serial Modes In Figure 1, serial NRZ data is input to the 78P2352 on the SIDxP/N pins at LVPECL levels. The data is latched in on the rising edge of SICKxP/N. A clock decoupling FIFO is provided to decouple the on chip and off chip clocks. The SICKxP/N clock provided by the framer/mapper IC should be source synchronous with the internal reference transmit clock if the FIFO is to be used. Since both clocks go through different delay paths, it is inevitable that the phase relationship between the two clocks can vary in a bounded manner due to the fact that the absolute delays in the two paths can vary over time. The FIFO is designed to allow long-term clock phase drift not exceeding +/- 25.6ns to be handled without transmit error. If the clock wander exceeds the specified limits, the FIFO will over or under flow, and the FERRx register signal will be asserted. The FIFO is then automatically re-centered. This signal can be used to trigger an interrupt. This interrupt event is cleared when an FRSTx pulse is applied, and the FIFO is re-centered. If no serial transmit clock is available, as in Figure 2, the 78P2352 will recover a clock from the serial NRZ data input and pass the data through the FIFO. In this mode, the NRZ data should be source synchronous with the reference clock applied at CKREFP/N. Each transmitter also includes a Loss of Lock indicator (TXLOL) which can be used to trigger and interrupt. Note that the FIFO is automatically re-centered when the TXLOL register bit transitions from high to low. Figure 3 represents the condition where no serial transmit clock is available and the data is not source synchronous to the reference clock input. In this mode, the 78P2352 will recover a clock from the serial plesiochronous data and bypass the FIFO. Each of the described transmit serial modes can be configured in HW mode and SW mode as shown in the table below: Serial Mode Synchronous clock + data (CDR bypass) Synchronous data Plesiochronous data (FIFO bypass) HW Control Pins SW Control Bits SDI_PAR Low CKMODE Low PAR 0 SMOD[1:0] 00 Low Floating 0 10 Low High 0 01 Reference Clock CKREFP/N NRZ SIxDP/N CMI CMIxP/N 140 / 155 MHz XFMR Coax Framer/ Mapper SIxCKP/N NRZ 140 / 155 MHz SOxCKP/N SOxDP/N TDK 78P2352 RXxP/N CMI XFMR Coax Figure 1: Synchronous; clock and data available (Tx CDR bypassed, FIFO enabled) Reference Clock CKREFP/N NRZ SIxDP/N CMIxP/N CMI XFMR Coax Framer/ Mapper NRZ 140 / 155 MHz SOxCKP/N SOxDP/N TDK 78P2352 RXxP/N CMI XFMR Coax Figure 2: Synchronous; data only (Tx CDR enabled, FIFO enabled) Reference Clock Reference Clock CKREFP/N NRZ SIxDP/N CMIxP/N CMI XFMR Coax Framer/ Mapper NRZ 140 / 155 MHz SOxCKP/N SOxDP/N TDK 78P2352 RXxP/N CMI XFMR Coax Figure 3: Plesiochronous; data only (Tx CDR enabled, FIFO bypassed) 5 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit Parallel Modes In parallel modes, 4-bit CMOS data segments are input to the chip with a 38.88MHz clock. These inputs are passed to the 4x8 decoupling FIFO and then to a serializer for transmission. For maximum compatibility, the 78P2352 can operate in both slave and master clock modes as shown in Figures 4, 5 respectively.. Parallel Mode Slave HW Control Pins SDI_PAR High CKMODE Low/Float SW Control Bits PAR 1 PMODE 0 Transmit Driver When the CMI pin is high, the chip is in CMI mode and a 75 coaxial cable is used as the transmission medium. In this mode, the CMIxP/N pins connect the chip to the coaxial cable through a transformer and termination resistors. In CMI mode, the transmitter shapes the transmit pulses to meet the appropriate template. Advanced peaking and amplitude controls are also available in both HW and SW modes to accommodate for less than ideal board conditions When the CMI pin is low, the chip is in ECL (NRZ) mode. The output data signal from the ECLxP/N pins have LVPECL levels and interface directly to a fiber module. The CMI driver, encoder and decoder are disabled in ECL (NRZ) mode. A 2x line rate clock is also available at the TXCKxP/N pins for downstream synchronization or interfacing to equipment lacking integrated clock recovery. Master High High 1 1 Reference Clock CKREFP/N 4-bit CMOS TTL PIx[3:0]D PIxCK CMIxP/N CMI XFMR Coax Framer/ Mapper 34/39 MHz 4-bit CMOS TTL 34/39 MHz POx[3:0]D POxCK TDK 78P2352 RXxP/N CMI XFMR Coax Clock Synthesizer The transmitter clock synthesizer is a low-jitter PLL that generates a 311.04MHz (278.528MHz) clock for the CMI encoder. A synthesized line rate reference clock is also used in both the receive and transmit sides. POWER-DOWN FUNCTION Figure 4: Slave Parallel Mode Reference Clock CKREFP/N 4-bit CMOS TTL PIx[3:0]D PTOxCK CMIxP/N CMI XFMR Coax Framer/ Mapper 34/39 MHz 4-bit CMOS TTL 34/39 MHz POx[3:0]D POxCK TDK 78P2352 RXxP/N CMI XFMR Coax Power-down control is provided to allow the 78P2352 to be shut off. Transmit and receive power-down can be set independently through SW control. Global power-down is achieved by powering down the transmit and receive sections in both channels. Note the serial interface and Configuration Registers are not affected by powerdown. In HW mode, both transmitters can be powered down using the TXPD control pin. Figure 5: Master Parallel Mode 6 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit LOOPBACK MODES In SW mode, LLBKx and RLBKx bits are provided to activate the local and remote loopback modes respectively. In HW mode, the LPBKx pins can be used to activate local and remote loopback modes as shown below. LPBK pin Low Float Loopback Mode Normal operation Remote (digital) Loopback: Recovered receive clock and data looped back to transmitter Local (analog) Loopback: Transmit clock and data looped back to receiver Lock Detect SIxDP/N SIxCKP/N PIxCK PIx[3:0]D PTOxCK SOxCKP/N SOxDP/N POx[3:0]D POxCK CMI-LCV Detect EACH CHANNEL: Rx CMI Decoder Rx CDR Lock Detect Adaptive Eq. G.775 LOS Detect RXxP/N Tx CDR FIFO CMI Encoder EACH CHANNEL: Tx TXxCKP/N CMIxP/N ECLxP/N SERIAL CONTROL INTERFACE The serial port controlled register allows a generic controller to interface with the 78P2352. It is used for mode settings, diagnostics and test, retrieval of status and performance information, and for on-chip trimming. The SPSL pin must be high in order to use the serial port. The serial interface consists of four pins: Serial Port Enable (SEN_CMI), Serial Clock (SCK_MON), Serial Data In (SDI_PAR), and Serial Data Out (SDO_E4). The SEN_CMI pin initiates the read and write operations. It can also be used to select a particular device allowing SCK_MON, SDI_PAR and SDO_E4 to be bussed together. SCK_MON is the clock input that times the data on SDI_PAR and SDO_E4. Data on SDI_PAR is latched in on the rising-edge of SCK_MON, and data on SDO_E4 is clocked out using the falling edge of SCK_MON. SDI_PAR is used to insert mode, address, and register data into the chip. Address and Data information are input least significant bit (LSB) first. The mode and address bit assignment and register table are shown in the following section. SDO_E4 is a tristate capable output. It is used to output register data during a read operation. SDO_E4 output is normally high impedance, and is enabled only during the duration when register data is being clocked out. Read data is clocked out least significant bit (LSB) first. If SDI_PAR coming out of the micro-controller chip is also tristate capable, SDI_PAR and SDO_E4 can be connected together to simplify connections. The maximum clock frequency for register access is 20MHz. PROGRAMMABLE INTERRUPTS In addition to the receiver LOS and LOL status pins, the 78P2352 provides a programmable interrupt for each transmitter and receiver. In HW control mode, the default functions of each interrupt is as follows: * * INTTXx = Transmit Loss of Lock (TXLOL) or FIFO error (FERR) INTRXx = (CMIERR) CMI Line Code Violation High Figure 6: Local (Analog) Loopback Lock Detect SIxDP/N SIxCKP/N PIxCK PIx[3:0]D PTOxCK SOxCKP/N SOxDP/N POx[3:0]D POxCK CMI-LCV Detect EACH CHANNEL: Rx CMI Decoder Rx CDR Lock Detect Adaptive Eq. G.775 LOS Detect RXxP/N Tx CDR FIFO CMI Encoder EACH CHANNEL: Tx TXxCKP/N CMIxP/N ECLxP/N Figure 7: Remote (Digital) Loopback POWER-ON RESET Power-On Reset (POR) function is provided on chip. Upon initial power-up, a reset pulse is internally generated. This resets all registers to their default values as well as all state machines within the transceiver to known initial values. The reset signal is also brought out to the POR pin. The POR pin is a special function pin that allows for the following: * * * Override the internal POR signal by driving in an external POR signal; Use the POR signal to drive other IC's poweron reset; Add external capacitor to slow down the release of power-on reset (approximately 8s per nF added). The internal resistance of the POR pin is approximately 5k. 7 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit REGISTER DESCRIPTION REGISTER ADDRESSING Address Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Sub-Address PA[0] SA[2] SA[1] SA[0] Bit 1 Bit 0 Read/ Write R/W* Port Address Assignment PA[3] PA[2] PA[1] REGISTER TABLE a) PA[3:0] = 0 : Global Registers Sub Addr 0 1 2 Reg. Name MSCR (R/W) INTC (R/W) -Description Master Control Interrupt Control Reserved Bit 7 E4 <0> INPOL <0> -Bit 6 ---Bit 5 PAR <0> MCERR <1> -Bit 4 CKSL[1] b) PA[3:0] = 1, 2 : Port-Specific Registers Sub Addr 0 1 2 3 4 5 6-7 Reg. Name MDCR (R/W) SGCR (R/W) ACR1 (R/W) ACR2 (R/W) MCR2 (R/W) STAT (R/C) -Description Mode Control Signal Control Advanced Control 1 Advanced Control 2 Mode Control 2 Status Monitor Reserved Bit 7 PDTX <0> ---CMI <1> --Bit 6 PDRX <0> ------Bit 5 PMODE SMOD[1] SMOD[0] 8 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit REGISTER DESCRIPTION (CONTINUED) LEGEND TYPE R/O R/C DESCRIPTION Read only Read and Clear TYPE R/W DESCRIPTION Read or Write GLOBAL REGISTERS ADDRESS 0-0: MASTER CONTROL REGISTER BIT NAME TYPE DFLT VALUE DESCRIPTION Line Rate Selection: Selects the line rate of all channels as well as the input clock frequency at the CKREFP/N pins. 0: OC-3, STS-3, STM-1 (155.52MHz) 1: E4 (139.264MHz) Unused Serial/Parallel Selection: Selects the interface to the framer. 0: Serial 1: Parallel Reference Clock Frequency Selection: Selects the reference clock frequency input at CKREFP/N pins. Secondary values correspond to E4 frequencies. Default values depend on the pin selection upon reset. 11: 155.52MHz / 139.264MHz 10: 77.76MHz / NA 00: 19.44MHz / 17.408MHz Unused Register Soft-Reset: When this bit is set, all registers are reset to their default values. This register bit is self-clearing. 7 E4 R/W 0 6 5 -PAR R/W R/W 0 0 4:3 CKSL [1:0] R/W X 2:1 0 -SRST R/W R/W 0 0 9 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit REGISTER DESCRIPTION (CONTINUED) ADDRESS 0-1: INTERRUPT CONTROL REGISTER This register selects the events that would cause the interrupt pins to be activated. User may set as many bits as required. BIT NAME TYPE DFLT VALUE 0 0 DESCRIPTION Interrupt Pin Polarity Selection: 7 6 INPOL -R/W R/W 0 : Interrupt output is active-low 1 : Interrupt output is active-high Reserved Receive CMI Code Error Mask (active low): Gates the respective RXCER register bit to the INTRXx interrupt pin. 0: Mask 1: Pass 4 MRLOS R/W 0 Receive Loss of Signal Error Mask (active low): Gates the respective RXLOS register bit to the INTRXx interrupt pin. 0: Mask 1: Pass Receive Loss of Lock Error Mask (active low): Gates the respective RXLOL register bit to the INTRXx interrupt pin. 0: Mask 1: Pass Unused TXLOL Error Mask (active low): Gates the TXLOL register bit to the INTTXx interrupt pin. 0: Mask 1: Pass FIERR Error Mask (active low): Gates the respective FIERR register bit to the INTTXx interrupt pin. 0: Mask 1: Pass 5 MCERR R/W 1 3 MRLOL R/W 0 2 -- R/W 0 1 MTLOL R/W 1 0 MFERR R/W 1 10 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit REGISTER DESCRIPTION (CONTINUED) PORT-SPECIFIC REGISTERS For PA[3:0] = 1-2 = N only. Accessing a register with port address greater than 2 constitutes an invalid command, and the read/write operation will be ignored. ADDRESS N-0: MODE CONTROL REGISTER BIT 7 NAME PDTX TYPE R/W DFLT VALUE 0 DESCRIPTION Transmitter Power-Down: 0 : Normal Operation 1 : Power-Down Receiver Power-Down: (Setting PDTX and PDRX for both channels will power down the reference clock generator) 0 : Normal Operation 1 : Power-Down Parallel Mode Interface Selection: When PAR=1 (Master Control Regsiter: bit 5), PMODE selects the source of the transmit parallel input clock, either taken from the framer externally or generated internally. 0: Parallel clock is taken as an input to the transmitter 1: Parallel clock is given as an output from the transmitter Serial Mode Interface Selection: When PAR=0 (Master Control Regsiter: bit 5), SMOD[1:0] configures the transmitter's system interface. SMOD[1] SMOD[0] 0 0 Synchronous clock and data are passed through a FIFO. The CDR is bypassed. 1 0 Synchronous data is passed through the CDR and then through the FIFO. 0 1 Plesiochronous data is passed through the CDR to recover a clock, but the FIFO is bypassed because the data is not synchronous with the reference clock. 1 1 Loop Timing Mode Enable: The recovered receive clock is used as the reference for the transmit section. The transmit data is passed through the CDR, but the FIFO is bypassed. Receive Monitor Mode Enable: 0: Normal Operation 1: Adds 20dB of flat gain to the receive signal before equalization NOTE: Monitor mode is only available in CMI mode. Reserved Reserved 6 PDRX R/W 0 5 PMODE R/W X 4 SMOD[1] R/W X 3 SMOD[0] R/W X 2 1 0 MON --- R/W R/W R/W 0 0 1 11 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit REGISTER DESCRIPTION (CONTINUED) ADDRESS N-1: SIGNAL CONTROL REGISTER BIT 7:5 4 NAME -RLBK TYPE R/W R/W DFLT VALUE 0 0 DESCRIPTION Reserved Loopback Selection: RLBK LLBK 0 0 Normal operation 1 0 Remote Loopback Enable: Recovered receive data and clock are looped back to the transmitter for retransmission. Valid for both parallel and serial modes. 0 1 Local Loopback Enable: The serial transmit data is looped back and used as the input to the receiver. Receive Clock Inversion Select: This bit will invert the receive output clock. 0: Normal 1: Invert Transmit Clock Inversion Select: This bit will invert the transmit input system clock. 0: Normal 1: Invert FIFO Reset: 0: Normal operation 1: Reset FIFO pointers to default locations. 3 LLBK R/W 0 2 RCLKP R/W 0 1 TCLKP R/W 0 0 FRST R/W 0 ADDRESS N-2: ADVANCED CONTROL REGISTER 1 BIT 7:2 1 0 NAME -TPK DU TYPE R/W R/W R/W DFLT VALUE 0 0 0 DESCRIPTION Reserved Transmit Driver Peaking Enable: TBD Transmit Driver Reverse Peaking Enable: TBD ADDRESS N-3: ADVANCED CONTROL REGISTER 2 BIT 7:3 2:1 0 NAME ---BST[1:0] ---TYPE R/W R/W R/W DFLT VALUE 10101 00 0 DESCRIPTION Reserved Transmit Driver Amplitude Boost: TBD Reserved 12 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit REGISTER DESCRIPTION (CONTINUED) ADDRESS N-4: MODE CONTROL REGISTER 2 BIT 7 6:0 NAME CMI -TYPE R/W R/W DFLT VALUE 1 0 DESCRIPTION Line Interface Mode Selection: 0: Optical (LVPECL) 1: Coaxial cable (CMI encoded) Reserved ADDRESS N-5: STATUS MONITOR REGISTER BIT 7 6 5 NAME --CMIERR TYPE R/C R/C R/C DFLT VALUE X X X DESCRIPTION Unused Reserved Receive CMI Coding Error Indication: This bit is set when the recovered receive CMI data is incorrectly coded. 0: Normal operation 1: CMI code error detected Loss of Signal Indication: 0: Normal operation 1: Loss of signal condition detected NOTE: RXLOS is intended for CMI mode only. Receive Loss of Lock Indication: 0: Normal operation 1: Recovered receive clock frequency differs from the reference by more than +/- 1000ppm. Unused Transmit Loss of Lock Indication: 0: Normal operation 1: Transmit CDR unlocked Transmit FIFO Error Indication: This bit is set whenever the internal FERR signal is asserted, indicating that the FIFO is operating at its depth limit. It is reset to 0 when the FRST pin is asserted. 0: Normal operation 1: Transmit FIFO phase error 4 RXLOS R/C X 3 2 1 RXLOL -TXLOL R/C R/C R/C X X X 0 FERR R/C X 13 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit PIN DESCRIPTION LEGEND TYPE A CIT CI CIU CID CIS DESCRIPTION Analog Pin (Tie unused pins to ground) 3-State CMOS Digital Input CMOS Digital Input (Tie unused pins to ground) CMOS Digital Input w/ Pull-up CMOS Digital Input w/ Pull-down CMOS Schmitt Trigger Input (Tie unused pins to ground) TYPE PO CO COZ PI S G DESCRIPTION LVPECL-Compatible Differential Output (Tie unused pins to supply) CMOS Digital Output (Leave unused pins floating) CMOS Tristate Digital Output (Leave unused pins floating) LVPECL-Compatible Differential Input (Tie unused pins to ground) Supply Ground TRANSMITTER PINS NAME PIx0D PIx1D PIx2D PIx3D PIxCK PIN 31, 66 32, 65 33, 64 34, 63 30, 67 TYPE DESCRIPTION Transmit Data Parallel Input: CI The four bit CMOS parallel inputs are latched in on the rising edge of the transmit parallel input clock. MSB of the data is transmitted first. Transmit Parallel Clock Input: CI A 38.88MHz CMOS clock input that should be source synchronous with the reference clock supplied at the CKREFP/N pins. Transmit Parallel Clock Output: A 38.88MHz CMOS clock output that is intended to latch in synchronous parallel data. Transmit Serial Data Input: This differential input is clocked in on the rising edge of the transmit serial input clock. If source synchronous with the reference clock, this data can be input to a FIFO, otherwise the clock and data can be transmitted directly. A CDR can be multiplexed in to the transmit path if no serial clock is available. Transmit Serial Clock Input: A 155.52MHz synchronous differential input clock used to clock in the serial data Transmit Serial CMI Data Output: A CMI encoded data signal conforming to the relevant pulse templates Transmit Serial Clock Output: A 2x line rate LVPECL clock output used to clock out the transmit data Transmit Serial LVPECL Data Output: Transmit NRZ data PTOxCK 35, 62 CO SIxDP SIxDN 10, 87 11, 86 PI SIxCKP SIxCKN CMIxP CMIxN TXxCKP TXxCKN ECLxP ECLxN 7, 90 8, 89 121, 104 122, 103 124, 101 125, 100 127, 98 128, 97 PI A PO PO 14 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit PIN DESCRIPTION (CONTINUED) RECEIVER PINS NAME POx0D POx1D POx2D POx3D POxCK SOxDP SOxDN SOxCKP SOxCKN RXxP RXxN PIN 46, 51 45, 52 42, 55 41, 56 38, 59 28, 69 29, 68 25, 72 26, 71 118, 107 119, 106 TYPE DESCRIPTION Receive Data Parallel Output: The four bit CMOS parallel outputs are clocked out on the falling edge of the receive parallel output clock. The MSB of the output is received first. Receive Parallel Clock Output: A 38.88MHz CMOS clock output generated by dividing down the recovered receive clock. The output is multiplexed in from the divided down reference clock whenever LOSx is high. Receive Serial Data Output: Recovered receive serial data Receive Serial Clock Output: Recovered receive serial clock Receive Serial CMI or LVPECL Input: The input signal is either transformer coupled for CMI data or at LVPECL levels for NRZ data CO CO PO PO A/ PI REFERENCE AND STATUS PINS NAME PIN TYPE DESCRIPTION Reference Clock Input: A differential 139.264MHz, 155.52MHz differential clock input at CKREFP/N or a single-ended 17.408MHz, 19.44MHz, 77.78MHz CMOS clock input at CKREFP (tie CKREFN to ground when unused). All reference clocks are +/- 20ppm. Loss of Signal: Standards compliant loss of signal indicator. To be used for electrical CMI interfaces only. Loss of Lock: This condition is met when the recovered clock frequency differs from the reference clock frequency by more than +/- 1000ppm. Transmitter Fault Interrupt Flag (active low): When a transmitter error event occurs (as defined in the Interrupt Control Register Description), the INTTXx pin will change state to indicate an interrupt. The interrupt is cleared by a read to the STAT Register or issue of a FRSTx FIFO reset pulse if the FIERRx signal caused the interrupt. The default interrupt condition is a loss of lock in the transmitter CDR. Receiver Fault Interrupt Flag (active low): When a receiver error event occurs (as defined in the Interrupt Control Register Description), the INTRXx pin will change state to indicate an interrupt. The interrupt is cleared by a read to the STAT Register. The default interrupt condition is a CMI line code violation. Power-On Reset (active low): See Power-On Reset description on use of this pin. 15 CKREFP CKREFN 111 110 PI LOS1 LOS2 LOL1 LOL2 80 19 79 20 CO CO INTTX! INTTX@ 88 9 CO INTRX! INTRX@ 70 27 CO POR 83 A 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit PIN DESCRIPTION (CONTINUED) CONTROL PINS NAME PIN TYPE DESCRIPTION FIFO Phase-Initialization Control: Should normally be floating. When asserted, the transmit FIFO pointers are reset to the respective "centered" states. Also resets the FIERR interrupt bit. De-assertion edge of FRSTx will resume FIFO operation. * * * * LPBKx 17, 18 CIT * * Low: Channel 1 FRST assertion Float: Normal High: Channel 2 FRST assertion Low: Normal operation Float: Remote Loopback Enable: Recovered receive data and clock are looped back to the transmitter for retransmission. High: Local Loopback Enable: The serial transmit data is looped back and used as the input to the receiver. FRST 78 CIT Loopback Selection: Clock Mode Selection: Selects the method of inputting transmit data into the chip. In PARALLEL mode (SDI_PAR high): * CKMODE 15 CIT Low/Float: Parallel transmit clock is input to the 78P2352 * High: Parallel transmit clock is output from the 78P2352 In SERIAL mode (SDI_PAR low): * * * 1 2 14 77 CIT CIT CID CID Low: Reference clock is synchronous to transmit clock and data. Data is passed through a FIFO Float: Reference clock is synchronous to transmit data. Clock is recovered with a CDR and data is passed through a FIFO High: Reference clock is plesiochronous to transmit data. Clock is recovered with a CDR and the FIFO is bypassed TXOUT1 TXOUT0 TXPD SPSL CMI Driver Peaking Control: Functionality TBD. Should be floating for normal operation CMI Driver Amplitude Control: Functionality TBD. Should be tied low for normal operation Transmitter Power Down: When high, powers down the transmitter on both channels. Serial Port Selection: When high, chip is controlled through the serial port. Reference Clock Frequency Selection: Selects the reference frequency that is supplied at the CKREFP/N pins. Its level is read in only at power-up or on the rising edge of a reset signal at the POR pin. * * * Low: 19.44MHz or 17.408MHz Float: 77.76MHz High: 155.52MHz or 139.264MHz CKSL 81 CIT 16 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit PIN DESCRIPTION (CONTINUED) SERIAL-PORT PINS NAME PIN TYPE DESCRIPTION [SPSL=1] Serial-Port Enable: High during read and write operations. Low disables the serial port. While SEN is low, SDO remains in high impedance state, and SDI and SCK activities are ignored. [SPSL=0] Medium Select: Low: ECL (NRZ) mode Float: CMI mode (input/output polarity inverted) High: CMI mode (normal input/output) [SPSL=1] Serial Clock: Controls the timing of SDI and SDO. [SPSL=0] Receive Monitor Mode Enable: When high, adds 20dB of flat gain to the incoming signal before equalization. NOTE: Channel specific monitor modes can only be enabled through the serial port. Rx Monitor Mode is only available in CMI mode [SPSL=1] Serial Data Input: Inputs mode and address information. Also inputs register data during a Write operation. Both address and data are input least significant bit first. [SPSL=0] Data Width Select: Selects 4 bit parallel (input high) or serial mode (input low) [SPSL=1] Serial Data Output: Outputs register information during a Read operation. Data is output least significant bit first [SPSL=0] Rate Select: Selects E4 operation (input high) or STM1/STS3 operation (input low) SEN_CMI 95 CI SCK_MON 96 CIS SDI_PAR 94 CI SDO_E4 93 COZ/ CI POWER AND GROUND PINS It is recommended that all supply pins be connected to a single power supply plane and all ground pins be connected to a single ground plane. NAME VCC VDD PIN 5, 12, 21, 74, 85, 92, 99, 105, 109, 116, 120, 126 23, 37, 40, 44, 48, 49, 53, 57, 60 6, 13, 16, 22, 73, 82, 84, 91, 102, 108, 112, 113, 114, 115, 117, 123 24, 36, 39, 43, 47, 50, 54, 58, 61 TYPE S DESCRIPTION Power Supply S G CMOS Driver Supply Ground GND VSS G CMOS Driver Ground 17 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Operation beyond these limits may permanently damage the device. PARAMETER Supply Voltage (Vdd) Storage Temperature Junction Temperature Theta-JA (JA ) - Still Air Pin Voltage (CMIxP,CMIxN) Pin Voltage (all other pins) Pin Current RATING -0.5 to 4.0 VDC -65 to 150 C -40 to 125 C 50 C/W Vdd + 1.5 VDC -0.3 to (Vdd+0.6) VDC 100 mA RECOMMENDED OPERATING CONDITIONS Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges. PARAMETER DC Voltage Supply (Vdd) Ambient Operating Temperature RATING 3.15 to 3.45 VDC -40 to 85C DC CHARACTERISTICS: PARAMETER Supply Current (including transmitter current through transformer) SYMBOL CONDITIONS VP = 3.3V STM-1 mode CMI mode Max. cable length VP=3.3V STM-1 mode NRZ (optical) mode VP = 3.3V Transmitter disabled STM-1 mode CMI mode Max. cable length VP = 3.3V STM-1 mode CMI mode Max. cable length MIN NOM TBD MAX UNIT mA Idd Supply Current Idde TBD mA Supply Current Iddr TBD mA Supply Current per Port (including transmitter current through transformer) Iddx TBD mA 18 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS (continued) ANALOG PINS CHARACTERISTICS: The following table is provided for informative purpose only. Not tested in production. PARAMETER RXxP and RXxN Common-Mode Bias Voltage RXxP and RXxN Differential Input Impedance Analog Input/Output Capacitance DIGITAL I/O CHARACTERISTICS: Pins of type CI, CIU, CID: PARAMETER Input Voltage Low Input Voltage High Input Current Pull-up Resistance Pull-down Resistance Input Capacitance Pins of type CIS: PARAMETER Low-to-High Threshold High-to-Low Threshold Input Current Input Capacitance Pins of type CO and COZ: PARAMETER Output Voltage Low Output Voltage High Output Transition Time Tri-state Output Leakage Current Pins of type PO: PARAMETER Output Voltage Low Output Voltage High Rise Time Fall Time SYMBOL Vol Voh Tr Tf 19 CONDITIONS Vdd referenced Vdd referenced MIN NOM -1.4 -0.9 1 1 MAX UNIT V V ns ns SYMBOL Vol Voh Tt Iz CONDITIONS Iol = 8mA Ioh = -8mA CL = 20pF Type COZ only 0 2.4 4 MIN NOM MAX 0.4 UNIT V V ns A SYMBOL Vt+ VtIil, Iih Cin CONDITIONS MIN NOM 1.5 0.9 0 8 MAX UNIT V V A pF SYMBOL Vil Vih Iil, Iih Rpu Rpd Cin Type CIU only Type CID only 2.0 0 70 58 8 CONDITIONS MIN NOM MAX 0.8 UNIT V V A k k pF SYMBOL Vblin Rilin Cin CONDITIONS Ground Reference MIN NOM 2.1 10 8 MAX UNIT V k pF 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS (continued) SERIAL-PORT TIMING CHARACTERISTICS: PARAMETER SDI to SCK setup time SDI to SCK hold time SCK to SDO propagation delay SYMBOL tsu th tprop CONDITION MIN 2 2 3 TYP MAX UNIT ns ns ns CS tsu th SCK tsu th SDI X 1 SA0 SA1 SA2 PA0 PA1 PA2 PA3 tprop X or Z SDO Z D0 D1 D2 D3 D4 D5 D6 D7 Z Figure 8: Read Operation CS tsu th SCK tsu th SDI X 0 SA0 SA1 SA2 PA0 PA1 PA2 PA3 D0 D1 D2 D3 D4 D5 D6 D7 X SDO Z Figure 9: Write Operation 20 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS (continued) TRANSMITTER TIMING CHARACTERISTICS: PARAMETER Clock Duty Cycle Transition Time Setup Time Hold Time Setup Time Hold Time SYMBOL TTCF/TTC TTCT TPS TPH TSS TSH 10%-90% Parallel mode Parallel mode Serial mode Serial mode 4 4 1 1 CONDITIONS MIN NOM 50 1 MAX UNIT % ns ns ns ns ns TIMING DIAGRAM: Transmitter Waveforms TSS SIDxP/N TPS PIxXD TSH TPH 21 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS (continued) REFERENCE CLOCK CHARACTERISTICS: PARAMETER CKREF Duty Cycle CKREF Frequency Stability SYMBOL --w.r.t. line-rate frequency CONDITIONS MIN 40 -20 NOM MAX 60 +20 UNIT % ppm RECEIVER TIMING CHARACTERISTICS: PARAMETER Transition Time Receive Clock Duty Cycle Clock to Q Clock to Q SYMBOL TRCT TRCF/TRC RSCQ RPCQ Serial mode Parallel mode CONDITIONS MIN NOM 1 50 0.6 0.6 MAX UNIT ns % ns ns TIMING DIAGRAM: Receive Waveforms RSCQ RPCQ Data Clock 22 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS (continued) TRANSMITTER SPECIFICATIONS FOR CMI INTERFACE Bit Rate: 139.264Mbit/s 15ppm or 155.52Mbits/s 20ppm Code: coded mark inversion (CMI) Relevant Specification: ITU-T G.703 With the coaxial output port driving a 75 load, the output pulses conform to the templates in Figures 10, 11, 12, and 13. These specifications are tested during production test. PARAMETER Peak-to-peak Output Voltage Rise/ Fall Time Transition Timing Tolerance CONDITION Template, steady state 10-90% Negative Transitions Positive Transitions at Interval Boundaries Positive Transitions at midinterval -0.1 -0.5 -0.35 MIN 0.9 NOM MAX 1.1 2 0.1 0.5 0.35 UNIT V ns ns ns ns The following specifications are not tested during production test. They are included for information only. Note that the return loss depends on the board layout and the particular transformer used. PARAMETER Return Loss CONDITION 7MHz to 240MHz MIN 15 NOM MAX UNIT dB 23 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS (continued) V 0.60 0.55 0.50 0.45 0.40 1ns 0.1ns 0.1ns 0.35ns T = 7.18ns (Note 1) (Note 1) Nominal Pulse 1.795 ns 1ns 0.1ns 0.35ns 0.1ns 1.795 ns 1ns 0.05 -0.05 Nominal Zero Level (Note 2) -0.40 -0.45 -0.50 -0.55 -0.60 1ns 1.795 ns 1ns 1.795 ns 1ns (Note 1) (Note 1) Note 1 - The maximum "steady state" amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 - For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 F, to the input of the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any such adjustment should be the same for both masks and should not exceed 0.05V. This may be checked by removing the input signal again and verifying that the trace lies with 0.05V of the nominal zero level of the masks. Note 3 - Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask, it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 - For the purpose of these masks, the rise time and decay time should be measured between -0.4V and 0.4V, and should not exceed 2ns. Figure 10 - Mask of a Pulse corresponding to a binary Zero in E4 mode 24 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS (continued) V 0.60 0.55 0.50 0.45 0.40 1ns 0.1ns 0.1ns T = 7.18ns (Note 1) (Note 1) 1ns 0.5ns 0.5ns Nominal Pulse 0.05 -0.05 Nominal Zero Level (Note 2) 3.59ns 1.35ns 1.35ns 3.59ns -0.40 -0.45 -0.50 -0.55 -0.60 1ns 1.795 ns 1ns 1.795 ns (Note 1) Note 1 - The maximum "steady state" amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 - For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 F, to the input of the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any such adjustment should be the same for both masks and should not exceed 0.05V. This may be checked by removing the input signal again and verifying that the trace lies with 0.05V of the nominal zero level of the masks. Note 3 - Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask, it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 - For the purpose of these masks, the rise time and decay time should be measured between -0.4V and 0.4V, and should not exceed 2ns. Note 5 -The inverse pulse will have the same characteristics, noting that the timing tolerance at the level of the negative and positive transitions are 0.1ns and 0.5ns respectively. Figure 11 - Mask of a Pulse corresponding to a binary One in E4 mode. 25 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS (continued) V 0.60 0.55 0.50 0.45 0.40 1ns 0.1ns 0.1ns 0.35ns T = 6.43ns (Note 1) (Note 1) Nominal Pulse 1.608ns 1ns 0.1ns 0.35ns 0.1ns 1.608ns 1ns 0.05 -0.05 Nominal Zero Level (Note 2) -0.40 -0.45 -0.50 -0.55 -0.60 1ns 1.608ns 1ns 1.608ns 1ns (Note 1) (Note 1) Note 1 - The maximum "steady state" amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 - For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 F, to the input of the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any such adjustment should be the same for both masks and should not exceed 0.05V. This may be checked by removing the input signal again and verifying that the trace lies with 0.05V of the nominal zero level of the masks. Note 3 - Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask, it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 - For the purpose of these masks, the rise time and decay time should be measured between -0.4V and 0.4V, and should not exceed 2ns. Figure 12 - Mask of a Pulse corresponding to a binary Zero in STS-3/STM-1 mode. 26 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS (continued) V 0.60 0.55 0.50 0.45 0.40 1ns 0.1ns 0.1ns 6.43ns (Note 1) (Note 1) 1ns 0.5ns 0.5ns Nominal Pulse 0.05 -0.05 Nominal Zero Level (Note 2) 3.215ns 1.2ns 1.2ns 3.215ns -0.40 -0.45 -0.50 -0.55 -0.60 1ns 1.608ns 1ns 1.608ns (Note 1) Note 1 - The maximum "steady state" amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 - For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 F, to the input of the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any such adjustment should be the same for both masks and should not exceed 0.05V. This may be checked by removing the input signal again and verifying that the trace lies with 0.05V of the nominal zero level of the masks. Note 3 - Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask, it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 - For the purpose of these masks, the rise time and decay time should be measured between -0.4V and 0.4V, and should not exceed 2ns. Note 5 -The inverse pulse will have the same characteristics, noting that the timing tolerance at the level of the negative and positive transitions are 0.1ns and 0.5ns respectively. Figure 13 - Mask of a Pulse corresponding to a binary One in STS-3/STM-1 mode 27 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS (continued) TRANSMITTER OUTPUT JITTER The transmit jitter specification ensures compliance with ITU-T G.813, G.823, G.825 and G.958; ANSI T1.1021993 and T1.105.03-1994; and GR-253-CORE for all supported rates. Transmit output jitter is not tested during production test. Jitter Detector Transmitter Output 20dB/decade Measured Jitter Amplitude f1 f2 PARAMETER CONDITION CMI Mode; 200 Hz to 3.5 MHz, measured with respect to CKREF for 60s NRZ (optical) Mode; 12 kHz to 1.3 MHz, measured with respect to CKREF MIN NOM MAX 0.075 UNIT UIpp Transmitter Output Jitter 0.01 UIrms 28 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS (continued) RECEIVER (Transformer-coupled) PARAMETER Peak Differential Input Amplitude, RXxP and RXxN Peak Differential Input Amplitude, RXxP and RXxN Flat-loss Tolerance CONDITION CMI mode; MON=0 CMI mode; MON=1 CMI mode; MON=0 All valid cable lengths. STM-1 mode; CMI mode with maximum cable a) Normal receive mode b) Remote loopback mode MIN TYP 500 50 2 MAX UNIT mVpk mVpk dB Receive Clock Jitter 0.1 0.07 UIpp UIpp RECEIVER SPECIFICATIONS FOR CMI INTERFACE The input signal is assumed compliant with ITU-T G.703 and can be attenuated by the dispersive loss of a cable. The minimum cable loss is 0dB and the maximum is -12dB at 70MHz. The "Worst Case" line corresponds to the ITU-T G.703 recommendation. The "Typical" line corresponds to a typical installation referred to in ANSI T1.102-1993. The receiver is tested using the cable model. It is a lumped element approximation of the "Worst Case" line. 30 25 Attenuation (dB) 20 15 10 5 0 1.00E+05 1.00E+06 1.00E+07 Frequency (Hz) Worst Case Typical 1.00E+08 1.00E+09 Figure 14: Typical and worst-case Cable attenuation 29 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS (continued) RECEIVER JITTER TOLERANCE The 78P2352 is compliant with all relevant jitter tolerance specifications shown in Figures 15, 16. STS-3/OC-3 jitter tolerance specifications are in ANSI T1.105.03-1994 and Telcordia GR-253-CORE. STM-1 (optical) jitter tolerance specifications are in ITU-T G.813, G.825, and G.958. STM-1e (electrical) jitter tolerance specifications are in ITU-T G.825. E4 specifications are found in ITU-T G.823. Receive jitter tolerance is not tested during production test. 100 Electrical (CMI) Interfaces G.825 - STM-1e Tolerance (for 2048 kbps networks) G.825 - STM-1e Tolerance (for 1544 kbps networks) G.823 - E4 Tolerance 10 Jitter Tolerance ( UIpp ) 1 0.1 0.01 1.E+00 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz Jitter Frequency Figure 15: Jitter Tolerance - electrical (CMI) interfaces PARAMETER E4 Jitter Tolerance CONDITION 200Hz to 500Hz 10kHz to 3.5MHz 10Hz to 19.3Hz 68.7Hz to 6.5kHz 65kHz to 1.3MHz MIN 1.5 0.075 38.9 1.5 0.15 NOM MAX UNIT UIpp STM-1e Jitter Tolerance 30 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS (continued) 100 Optical (NRZ) Interfaces G.813, G.958, T1.105.03, GR-253 STM-1 / STS-3 / OC-3 Tolerance G.825 - STM-1 Tolerance 10 Jitter Tolerance ( UIpp ) 1 0.1 0.01 1.E+00 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz Jitter Frequency Figure 16: Jitter Tolerance - optical (NRZ) interfaces PARAMETER OC-3/STS-3/STM-1 (optical) Jitter Tolerance CONDITION 10Hz to 19.3Hz 68.7Hz to 6.5kHz 65kHz to 1.3MHz MIN 38.9 1.5 0.15 NOM MAX UNIT UIpp 31 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS (continued) RECEIVER JITTER TRANSFER FUNCTION The receiver clock recovery loop filter characteristics such that the receiver has the following transfer function. The corner frequency of the PLL is approximately 120 kHz. Receiver jitter transfer function is not tested during production test. 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 Figure 17: Jitter Transfer PARAMETER Receiver Jitter transfer function Jitter transfer function roll-off CONDITION below 120 kHz MIN NOM MAX 0.1 UNIT dB dB per decade 20 32 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS (continued) CMI Mode Loss of Signal Condition Nominal value Maximum cable loss P 3 dB "Transition condition" must be detected Tolerance range "No transition condition" or "transition condition" may be detected Q Level below Nominal "No transition condition" must be detected T151 7 7 20 -9 5/d 0 1 NOTES 1 2 The signal level P is (maximum cable loss +3) dB below nominal. The signal level Q is greater than the maximum expected cross-talk level. 33 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit ELECTRICAL SPECIFICATIONS (continued) APPLICATION INFORMATION EXTERNAL COMPONENTS: COMPONENT Receiver Termination Resistor Transmitter Termination Resistor PIN(S) RXxP RXxN CMIxP CMIxN VALUE 75 75 UNITS TOLERANCE 1% 1% TRANSFORMER SPECIFICATIONS: COMPONENT Turns Ratio for the Receiver Turns Ratio for the Transmitter (center-tapped) Suggested Manufacturer: Pulse, MiniCircuits VALUE UNITS 1:1 1:1 TOLERANCE RECOMMENDED LVPECL TERMINATIONS: = 50 O/E converter or OC3 Framer 200 200 = 50 100 RXxP/N or SIxDP/N Figure 18: Differential LVPECL Inputs = 50 100 E/O Converter ECLxP/N 200 200 = 50 Figure 19: Differential LVPECL Outputs 34 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit MECHANICAL SPECIFICATIONS (0.622) 15.8 (0.637) 16.2 (0.622) 15.8 (0.637) 16.2 (0.543) 13.8 (0.559) 14.2 (0.002) 0.5 (0.006) .15 (0.015) .40 Typ. (0.024) .06 Typ. (0.005) .13 (0.009) .23 (0.062) 1.60 Max. 128-pin TQFP (JEDEC LQFP) 35 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit PACKAGE INFORMATION (Top View) ECL1N ECL1P VCC TX1CKN TX1CKP GND CMI1N CMI1P VCC RX1N RX1P GND VCC GND GND GND GND CKREFP CKREFN VCC GND RX2P RX2N VCC CMI2P CMI2N GND TX2CKP TX2CKN VCC ECL2P ECL2N TXOUT1 TXOUT0 N/C N/C VCC GND SI1CKP SI1CKN INTTX@ SI1DP SI1DN VCC GND TXPD CKMODE GND LPBK1 LPBK2 LOS2 LOL2 VCC GND VDD VSS SO1CKP SO1CKN INTRX@ SO1DP SO1DN PI1CK PI10D PI11D 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 78P2352-IGT 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Target Datasheet: This Target Datasheet is proprietary to TDK Semiconductor Corporation (TSC) and sets forth design goals for the described product. The data sheet is subject to change. TSC assumes no obligation regarding future manufacture, unless agreed to in writing. If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. TDK Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780 TEL (714) 508-8800, FAX (714) 508-8877, http://www.tdksemiconductor.com PI12D PI13D PTO1CK VSS VDD PO1CK VSS VDD PO13D PO12D VSS VDD PO11D PO10D VSS VDD VDD VSS PO20D PO21D VDD VSS PO22D PO23D VDD VSS PO2CK VDD VSS PTO2CK PI23D PI22D 62 63 64 SEN_MON SCK_CMI SDI_PAR SDO_E4 VCC GND SI2CKP SI2CKN INTTX! SI2DP SI2DN VCC GND POR GND CKSL LOS1 LOL1 FRST SPSL N/C N/C VCC GND SO2CKP SO2CKN INTRX! SO2DP SO2DN PI2CK PI20D PI21D (c) 2003 TDK Semiconductor Corporation 03/25/03 - rev 1.3 36 78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit Revison History February 13, 2003: Initial customer release March 25, 2003: Modified pinout (pins 73-76) ; Added conditions for LCV ; Added thermal data ; Updated Jitter Specs v1-2 v1-3 37 |
Price & Availability of 78P2352
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |