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| HY531000A 1Mx1, Fast Page mode DESCRIPTION This family is a 1M bit dynamic RAM organized 1,048,576 x 1-bit configuration with Fast Page mode CMOS DRAMs. Fast Page mode offers high speed of random access memory within the same row. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(60, 70 or 80ns) and power consumption (Normal or Low power). Hyundai's advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and high reliability. FEATURES Y Fast Page Mode operation Y Read-modify-write Capability Y TTL compatible inputs and outputs Y /CAS-before-/RAS, /RAS-only, Hidden and Self refresh capability Y Max. Active power dissipation Speed 60 70 80 Y Refresh cycle Part number HY531000A Refresh 512 Normal 8ms L-part 64ms Power 467mW 412mW 357mW Y JEDEC standard pinout Y 20/26-pin SOJ (300mil) Y Single power supply of 5V 10% Y Early Write or output enable controlled write Y Fast access time and cycle time Speed 60 70 80 tRAC 60ns 70ns 80ns tCAC 15ns 20ns 20ns tPC 40ns 40ns 45ns ORDERING INFORMATION Part Name HY531000AJ HY531000ALJ *L : Low power Refresh 512 512 Power Package 20/26Pin SOJ L-part 20/26Pin SOJ This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of circuits described. No patent licences are implied Hyundai Semiconductor Rev.10 / Jan.98 1 HY531000A FUNCTIONAL BLOCK DIAGRAM D Q Data Input Buffer Data Output Buffer OE WE CAS CAS Clock Generator A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Address Buffer Cloumn Predecoder (10) 10 Column Decoder Refresh Controller Sense Amp I/O Gate Refresh Counter (9) Row Decoder 9 Memory Array 1,048,576 x 1 Row Predecoder (10) RAS RAS Clock Generator Substrate Bias Generator VCC VSS 1Mx1,FP DRAM Rev.10 / Jan.98 2 HY531000A PIN CONFIGURATION (Marking Side) D WE RAS NC NC 1 2 3 4 5 26 25 24 23 22 VSS D CAS NC A9 A0 A1 A2 A3 Vcc 9 10 11 12 13 18 17 16 15 14 A8 A7 A6 A5 A4 20/26 Pin Plastic SOJ (300mil) PIN DESCRIPTION Pin Name /RAS /CAS /WE /OE A0~A9 D Q Vcc Vss Parameter Row Address Strobe Column Address Strobe Write Enable Output Enable Address Input Data Input Data Output Power (5V) Ground 1Mx1,FP DRAM Rev.10 / Jan.98 3 HY531000A ABSOLUTE MAXIMUM RATINGS Symbol TA TSTG VIN, VOUT VCC IOS PD TSOLDER Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VCC relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature Y Time Rating 0 to 70 -55 to 150 -1.0 to 7.0 -1.0 to 7.0 50 0.9 260 Y 10 Unit C C V V mA W C Y sec Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability RECOMMENDED DC OPERATING CONDITIONS (TA = 0C to 70C ) Symbol VCC VIH VIL Parameter Power Supply Voltage Input High Voltage Input Low Voltage Min 4.5 2.4 -1.0 Typ 5.0 Max 5.5 VCC+1.0 0.8 UNIT V V V Note : All voltages are referenced to VSS. DC OPERATING CHARACTERISTICS Symbol ILI ILO Parameter Input Leakage Current (Any input) Output Leakage Current (Any input) Output Low Voltage Output High Voltage Test condition VSS VIN VCC All other pins not under test = VSS VSS VOUT VCC /RAS & /CAS at VIH IOL = 4.2mA IOH = -5.0mA Min -10 -10 2.4 Max 10 10 0.4 Unit A A V V VOL VOH 1Mx1,FP DRAM Rev.10 / Jan.98 4 HY531000A DC CHARACTERISTICS (TA = 0C to 70C , VCC = 5V 10%, VSS = 0V, unless otherwise noted.) Symbol ICC1 Parameter Operating Current Test condition /RAS, /CAS Cycling tRC = tRC(min) /RAS, /CAS VIH(min) Other inputs VSS 60 70 80 60 70 80 Speed 60 70 80 Max. 85 75 65 2 Unit mA ICC2 TTL Standby Current mA ICC3 /RAS-only Refresh Current /RAS Cycling,/CAS = VIH tRC = tRC(min) 85 75 65 70 55 45 1 200 85 75 65 300 mA ICC4 Fast Page mode Current /CAS Cycling, /RAS = VIL tPC = tPC(min) /RAS = /CAS VCC - 0.2V /RAS & /CAS = 0.2V tRC = tRC(min.) tRC=125s /CAS = CBR cycling or 0.2V /OE & /WE = VCC - 0.2V Address = Vcc-0.2V or 0.2V D = Vcc-0.2, 0.2V or Open Q = open mA mA A mA ICC5 CMOS Standby Current /CAS-before-/RAS Refresh Current Battery Back-up Current (L-part) L-part 60 70 80 tRAS 300ns tRAS 1us ICC6 ICC7 A 400 Note 1. ICC1, ICC3, ICC4, ICC6 and Icc7 depend on output loading and cycle rates. 2. Specified values are obtained with output unloaded. 3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4, address can be changed maximum once while /CAS=VIH within one cycle time tPC. 4. Only tRAS(max) = 1s is applied to refresh of battery backup but tRAS(max) = 10s is to applied to normal functional operation. 5. Icc5(max.), Icc7 are applied to L-part only. 1Mx1,FP DRAM Rev.10 / Jan.98 5 HY531000A AC CHARACTERISTICS (TA = 0 C to 70 C, VCC = 5V 10% , VSS = 0V, unless otherwise noted.) 60ns Symbol tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tCLZ tOFF tT tRP tRAS tRASP tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL Parameter Min Random read or write cycle time Read-modify-write cycle time Fast Page mode cycle time Fast Page mode read-modify-write cycle time Access time from /RAS Access time from /CAS Access time from column address Access time from /CAS precharge /CAS to output low impedance Output Buffer Turn-off Dealy Time Transition time(rise and fall) /RAS precharge time /RAS pulse width /RAS pulse width(Fast Page Mode) /RAS hold time /CAS hold time /CAS pulse width /RAS to /CAS delay time /RAS to column address delay time /CAS to /RAS precharge time /CAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address hold time from /CAS Column address to /RAS lead time Read command set-up time Read command hold time referenced to /CAS Read command hold time referenced to /RAS Write command hold time Write command hold time from /RAS Write command pulse width Write command to /RAS lead time 110 130 40 60 0 0 3 40 60 60 15 60 15 20 15 5 10 0 10 0 15 45 25 0 0 0 15 45 10 15 Max 60 15 30 35 20 50 10K 100K 10K 45 30 Min 130 155 40 65 0 0 3 50 70 70 20 70 15 20 15 5 10 0 10 0 15 50 30 0 0 0 15 50 15 20 Max 70 20 35 35 20 50 10K 100K 10K 50 35 Min 150 175 45 70 0 0 3 60 80 80 20 80 20 20 15 5 10 0 10 0 15 55 35 0 0 0 15 55 15 20 Max 80 20 40 40 20 50 10K 100K 10K 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 6 13 9 10 15 17 4,9,10 4,9 4,10 4, 4 4 3 70ns 80ns Unit Note 1Mx1,FP DRAM Rev.10 / Jan.98 6 HY531000A AC CHARACTERISTICS Continued 60ns Symbol tCWL tDS tDH tREF Refresh period(L-part) tWCS tCWD tRWD tAWD tCSR tCHR tRPC tCPT tCPWD tRHCP Write command set-up time /CAS to /WE delay time /RAS to /WE delay time Column address to /WE delay time /CAS set-up time(CBR cycle) /CAS hold time(CBR cycle) /RAS to /CAS precharge time /CAS precharge time(CBR counter test) /WE delay time from /CAS precharge /RAS hold time from /CAS precharge 64 0 15 60 30 5 15 0 40 30 30 64 0 20 70 35 5 15 0 40 35 35 64 0 20 80 40 5 15 0 40 40 35 ms ns ns ns ns ns ns ns ns ns ns 8 Parameter Min Write command to /CAS lead time Data-in set-up time Data-in hold time Refresh period(512 cycles) 15 0 15 8 Max Min 20 0 15 8 Max Min 20 0 15 8 Max ns ns ns ms 7 7 11 11 8 8 8 8 70ns 80ns Unit Note 1Mx1,FP DRAM Rev.10 / Jan.98 7 HY531000A NOTE 1. An initial pause of 200s is required after power-up followed by 8 /RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CBR refresh cycles instead of 8 /RAS-only refresh cycles are required. 2. AC measurements assume tT=5ns 3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min.) and VIL(max.). 4. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 2TTL loads and 100pF. 5. tOFF(max.) defines the time at which the output achieves in early write cycles and to /WE leading edge in ReadModify-Write cycles. 6. Either tRCH or tRRH must be satisfied for a read cycle. 7. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in read-modify-write cycles. 8. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. If tRWD tRWD(min.), tCWD tCWD(min.), tAWD tAWD(min), and tCPWD tCPWD(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 9. Operation within the tRCD(max.) limit insures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC. 10.Operation within the tRAD(max.) limit insures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA. 11.tREF(max.)=64ms is applied to L-parts only.(HY531000ALS and HY531000ALJ) CAPACITANCE (TA = 25C, VCC = 5V 10%, VSS = 0V and f=1MHz, unless otherwise noted.) Symbol CIN1 CIN2 COUT Parameter Input Capacitance (A0~A9) Input Capacitance (/RAS, /CAS, /WE) Data Output Capacitance (Q) Typ. Max 5 7 7 Unit pF pF pF 1Mx1,FP DRAM Rev.10 / Jan.98 8 |
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