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K7A163630B K7A161830B
www..com 512Kx36 & 1Mx18 Synchronous SRAM
18Mb B-die Sync. SRAM Specification
100TQFP with Pb & Pb-Free
(RoHS compliant)
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* Samsung Electronics reserves the right to change products or specification without notice.
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July 2005 Rev 1.0
K7A163630B K7A161830B
Document Title
www..com 512Kx36 & 1Mx18 Synchronous SRAM
512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No. 0.0 0.1 0.2 History 1. Initial draft 1. Update the DC current spec(ICC, ISB) 1. Change the ISB,ISB1,ISB2 - ISB ; from 120mA to 170mA - ISB1 ; from 80mA to 150mA - ISB2 ; from 80mA to 130mA 1. Remove the 1.8V Vdd Voltage level 1. Remove the -14 speed bin 1. Finalize the datasheet Draft Date Mar. 22. 2004 May. 21, 2004 Sep. 21. 2004 Remark Advance Preliminary Preliminary
0.3 0.4 1.0
Oct. 18, 2004 Jan. 04, 2005 July 18, 2005
Preliminary Preliminary Final
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July 2005 Rev 1.0
K7A163630B K7A161830B
www..com 512Kx36 & 1Mx18 Synchronous SRAM
18Mb SB/SPB Synchronous SRAM Ordering Information
Org. Part Number Mode VDD Speed SB ; Access Time(ns) SPB ; Cycle Time(MHz) 7.5ns 250/167MHz 200MHz 7.5ns 250/167MHz 200MHz P : Lead free 100TQFP I ; Industrial Temp.Range PKG Temp
K7B161835B-Q(P)C(I)75 1Mx18 K7A161830B-Q(P)C(I)25/16 K7A161831B-Q(P)C(I)20 K7B163635B-Q(P)C(I)75 512Kx36 K7A163630B-Q(P)C(I)25/16 K7A163631B-Q(P)C(I)20
SB SPB(2E1D) SPB(2E2D) SB SPB(2E1D) SPB(2E2D)
3.3/2.5 3.3/2.5 3.3/2.5 3.3/2.5 3.3/2.5 3.3/2.5
C ; Commercial Q : 100TQFP Temp.Range
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July 2005 Rev 1.0
K7A163630B K7A161830B
www..com 512Kx36 & 1Mx18 Synchronous SRAM
512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
* Synchronous Operation. * 2 Stage Pipelined operation with 4 Burst. * On-Chip Address Counter. * Self-Timed Write Cycle. * On-Chip Address and Control Registers. * VDD= 2.5 or 3.3V +/- 5% Power Supply. * 5V Tolerant Inputs Except I/O Pins. * Byte Writable Function. * Global Write Enable Controls a full bus-width write. * Power Down State via ZZ Signal. * LBO Pin allows a choice of either a interleaved burst or a linear burst. * Three Chip Enables for simple depth expansion with No Data Contention only for TQFP ; 2cycle Enable, 1cycle Disable. * Asynchronous Output Enable Control. * ADSP, ADSC, ADV Burst Control Pins. * TTL-Level Three-State Output. * 100-TQFP-1420A (Lead and Lead free package) * Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7A163630B and K7A161830B are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 512K(1M) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor (ADSP) or address status cache controller (ADSC) inputs. Subsequent burst addresses are generated internally in the systems burst sequence and are controlled by the burst address advance(ADV) input. LBO pin is DC operated and determines burst sequence (linear or interleaved). ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The K7A163630B and K7A161830B are fabricated using SAMSUNGs high performance CMOS technology and is available in a 100pin TQFP. Multiple power and ground pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE -25 4.0 2.6 2.6 -16 6.0 3.5 3.5 Unit ns ns ns
LOGIC BLOCK DIAGRAM
CLK LBO CONTROL REGISTER ADV ADSC BURST CONTROL LOGIC BURST ADDRESS COUNTER A0~A1 A0~A18 or A0~A19 ADDRESS REGISTER A2~A18 or A2~A19 A0~A1 512Kx36, 1Mx18 MEMORY ARRAY
ADSP
CS1 CS2 CS2 GW BW WEx (x=a,b,c,d or a,b) OE ZZ
DATA-IN REGISTER CONTROL REGISTER
CONTROL LOGIC
OUTPUT REGISTER BUFFER
DQa0 ~ DQd7 or DQa0 ~ DQb7 DQPa,DQPb DQPa ~ DQPd
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July 2005 Rev 1.0
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PIN CONFIGURATION(TOP VIEW)
www..com 512Kx36 & 1Mx18 Synchronous SRAM
ADSC
ADSP
WEd
WEb
WEa
WEc
ADV 83
CLK
CS1
CS2
CS2
VDD
GW
VSS
BW
OE
A6
A7
A8 82
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
100
81
A9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
VSS
VDD
A5
A4
A3
A2
A1
A0
A18
A17
A10
A12
A13
A14
A15
LBO
PIN NAME
SYMBOL A0 - A18 PIN NAME Address Inputs TQFP PIN NO. SYMBOL VDD VSS N.C. DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~Pd or N.C VDDQ VSSQ PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs TQFP PIN NO. 15,41,65,91 17,40,67,90 14,16,38,39,66 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 32,33,34,35,36,37,42 43,44,45,46,47,48,49 50,81,82,99,100 ADV Burst Address Advance 83 Address Status Processor 84 ADSP ADSC Address Status Controller 85 CLK Clock 89 CS1 Chip Select 98 CS2 Chip Select 97 CS2 Chip Select 92 WEx(x=a,b,c,d) Byte Write Inputs 93,94,95,96 OE Output Enable 86 GW Global Write Enable 88 BW Byte Write Enable 87 ZZ Power Down Input 64 LBO Burst Mode Control 31
Output Power Supply (3.3V or 2.5V) Output Ground
A16
A11
50
NC/DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 N.C. VDD N.C. VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 NC/DQPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
K7A163630B(512Kx36)
DQPb/NC DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS N.C. VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa/NC
4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76
Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
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July 2005 Rev 1.0
K7A163630B K7A161830B
PIN CONFIGURATION(TOP VIEW)
www..com 512Kx36 & 1Mx18 Synchronous SRAM
ADSC
ADSP
WEb
WEa
A6
ADV 83
N.C.
N.C.
CLK
CS1
CS2
CS2
VDD
GW
VSS
BW
OE
A7
A8 82
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
100
81
A9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
VDD
A5
A4
A3
A2
A1
A0
A19
A18
A12
A13
A14
A15
A16
N.C.
LBO
N.C.
VSS
PIN NAME
SYMBOL A0 - A19 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37,42 43,44,45,46,47,48,49 50 80,81,82,99,100 83 84 85 89 98 97 92 93,94 86 88 87 64 31 SYMBOL VDD VSS N.C. PIN NAME Power Supply(+3.3V) Ground No Connect TQFP PIN NO. 15,41,65,91 17,40,67,90 1,2,3,6,7,14,16,25,28,29 30,38,39,51,52,53,56,57 66,75,78,79,95,96 58,59,62,63,68,69,72,73 8,9,12,13,18,19,22,23 74,24 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76
ADV ADSP ADSC CLK CS1 CS2 CS2 WEx(x=a,b) OE GW BW ZZ LBO
Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control
DQa0 ~ a7 DQb0 ~ b7 DQPa, Pb VDDQ VSSQ
Data Inputs/Outputs
Output Power Supply (3.3V or 2.5V) Output Ground
Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
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A17
A11
50
N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. DQb0 DQb1 VSSQ VDDQ DQb2 DQb3 N.C. VDD N.C. VSS DQb4 DQb5 VDDQ VSSQ DQb6 DQb7 DQPb N.C. VSSQ VDDQ N.C. N.C. N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
K7A161830B(1Mx18)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A10 N.C. N.C. VDDQ VSSQ N.C. DQPa DQa7 DQa6 VSSQ VDDQ DQa5 DQa4 VSS N.C. VDD ZZ DQa3 DQa2 VDDQ VSSQ DQa1 DQa0 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C.
July 2005 Rev 1.0
K7A163630B K7A161830B
FUNCTION DESCRIPTION
www..com 512Kx36 & 1Mx18 Synchronous SRAM
The K7A163630B and K7A161830B are synchronous SRAM designed to support the burst address accessing sequence of the Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins. The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV. When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally. Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read operation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are carried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to control signals by disabling CS1. All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx when GW is high. Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that samples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initiated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows; ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC. WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high). Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is selected.
BURST SEQUENCE TABLE
LBO PIN HIGH First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 0 1 1 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3 A0 0 1 0 1
(Interleaved Burst)
Case 4 A1 1 1 0 0 A0 1 0 1 0
(Linear Burst)
Fourth Address
BQ TABLE
LBO PIN LOW First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 1 1 0 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3 A0 0 1 0 1 A1 1 0 0 1
Case 4 A0 1 0 1 0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
ASYNCHRONOUS TRUTH TABLE
Operation Sleep Mode Read Write Deselected ZZ H L L L L OE X L H X X I/O STATUS High-Z DQ High-Z Din, High-Z High-Z
Notes 1. X means "Dont Care". 2. ZZ pin is pulled down internally 3. For write cycles that following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Sleep Mode means power down state of which stand-by current does not depend on cycle time. 5. Deselected means power down state of which stand-by current depends on cycle time.
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July 2005 Rev 1.0
K7A163630B K7A161830B
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1 H L L L L L L L X H X H X H X H CS2 X L X L X H H H X X X X X X X X CS2 X X H X H L L L X X X X X X X X ADSP ADSC X L L X X L H H H X H X H X H X L X X L L X L L H H H H H H H H ADV X X X X X X X X L L L L H H H H WRITE X X X X X X L H H H L L H H L L
www..com 512Kx36 & 1Mx18 Synchronous SRAM
CLK
ADDRESS ACCESSED N/A N/A N/A N/A N/A External Address External Address External Address Next Address Next Address Next Address Next Address Current Address Current Address Current Address Current Address
OPERATION Not Selected Not Selected Not Selected Not Selected Not Selected Begin Burst Read Cycle Begin Burst Write Cycle Begin Burst Read Cycle Continue Burst Read Cycle Continue Burst Read Cycle Continue Burst Write Cycle Continue Burst Write Cycle Suspend Burst Read Cycle Suspend Burst Read Cycle Suspend Burst Write Cycle Suspend Burst Write Cycle
Notes : 1. X means "Dont Care".
2. The rising edge of clock is symbolized by .
3. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE(x36)
GW H H H H H H L BW H L L L L L X WEa X H L H H L X WEb X H H L H L X WEc X H H H L L X WEd X H H H L L X OPERATION READ READ WRITE BYTE a WRITE BYTE b WRITE BYTE c and d WRITE ALL BYTEs WRITE ALL BYTEs
Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
WRITE TRUTH TABLE(x18)
GW H H H H H L BW H L L L L X WEa X H L H L X WEb X H H L L X OPERATION READ READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ALL BYTEs
Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
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July 2005 Rev 1.0
K7A163630B K7A161830B
ABSOLUTE MAXIMUM RATINGS*
PARAMETER Voltage on VDD Supply Relative to VSS Voltage on VDDQ Supply Relative to VSS Voltage on Input Pin Relative to VSS Voltage on I/O Pin Relative to VSS Power Dissipation Storage Temperature Operating Temperature Storage Temperature Range Under Bias
www..com 512Kx36 & 1Mx18 Synchronous SRAM
SYMBOL VDD VDDQ VIN VIO PD TSTG Commercial Industrial TOPR TOPR TBIAS
RATING -0.3 to 4.6 VDD -0.3 to VDD+0.3 -0.3 to VDDQ+0.3 1.6 -65 to 150 0 to 70 -40 to 85 -10 to 85
UNIT V V V V W C C C C
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS (0C TA 70C)
PARAMETER SYMBOL VDD1 Supply Voltage VDDQ1 VDD2 VDDQ2 Ground VSS MIN 2.375 2.375 3.135 3.135 0 Typ. 2.5 2.5 3.3 3.3 0 MAX 2.625 2.625 3.465 3.465 0 UNIT V V V V V
Notes: 1. The above parameters are also guaranteed at industrial temperature range. 2. It should be VDDQ VDD.
CAPACITANCE*(TA=25C, f=1MHz)
PARAMETER Input Capacitance Output Capacitance
*Note : Sampled not 100% tested.
SYMBOL CIN COUT
TEST CONDITION VIN=0V VOUT=0V
MIN -
MAX 5 6
UNIT pF pF
VIH
VSS
VSS-1.0V 20% tCYC(MIN)
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July 2005 Rev 1.0
K7A163630B K7A161830B
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Current(except ZZ) Output Leakage Current Operating Current SYMBOL IIL IOL ICC
www..com 512Kx36 & 1Mx18 Synchronous SRAM
TEST CONDITIONS VDD = Max ; VIN=VSS to VDD Output Disabled, VOUT=VSS to VDDQ Device Selected, IOUT=0mA, ZZVIL , Cycle Time tCYC Min Device deselected, IOUT=0mA, -25 -16 -25 -16
MIN -2 -2 2.4 2.0 -0.3* 2.0 -0.3* 1.7
MAX +2 +2 360 300 170 170 150 130 0.4 0.4 0.8 VDD+0.3** 0.7 VDD+0.3**
UNIT A A mA
NOTES
1,2
ISB Standby Current
ZZVIL, f=Max, All Inputs0.2V or VDD-0.2V
mA
ISB1 ISB2
Device deselected, IOUT=0mA, ZZ0.2V, f = 0, All Inputs=fixed (VDD-0.2V or 0.2V) Device deselected, IOUT=0mA, ZZVDD-0.2V, f=Max, All InputsVIL or VIH IOL=8.0mA IOH=-4.0mA IOL=1.0mA IOH=-1.0mA
mA mA V V V V V V V V 3 3
Output Low Voltage(3.3V I/O) Output High Voltage(3.3V I/O) Output Low Voltage(2.5V I/O) Output High Voltage(2.5V I/O) Input Low Voltage(3.3V I/O) nput High Voltage(3.3V I/O) Input Low Voltage(2.5V I/O) Input High Voltage(2.5V I/O)
VOL VOH VOL VOH VIL VIH VIL VIH
Notes : 1. The above parameters are also guaranteed at industrial temperature range. 2. Reference AC Operating Conditions and Characteristics for input and timing. 3. Data states are all zero. 4. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V.
TEST CONDITIONS
PARAMETER Input Pulse Level(for 3.3V I/O) Input Pulse Level(for 2.5V I/O) Input Rise and Fall Time(Measured at 20% to 80% for 3.3/2.5V I/O) Input and Output Timing Reference Levels for 3.3V I/O Input and Output Timing Reference Levels for 2.5V I/O Output Load
* The above parameters are also guaranteed at industrial temperature range.
VALUE 0 to 3.0V 0 to 2.5V 1.0V/ns 1.5V VDDQ/2 See Fig. 1
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July 2005 Rev 1.0
K7A163630B K7A161830B
Output Load(A)
www..com 512Kx36 & 1Mx18 Synchronous SRAM
Dout Zo=50
RL=50 VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O
Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) +3.3V for 3.3V I/O /+2.5V for 2.5V I/O Dout 319 / 1667 5pF*
353 / 1538
* Including Scope and Jig Capacitance Fig. 1
AC TIING CHARACTERISTICS
Parameter Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width Clock Low Pulse Width Address Setup to Clock High Address Status Setup to Clock High Data Setup to Clock High Write Setup to Clock High (GW, BW, WEX) Address Advance Setup to Clock High Chip Select Setup to Clock High Address Hold from Clock High Address Status Hold from Clock High Data Hold from Clock High Write Hold from Clock High (GW, BW, WEX) Address Advance Hold from Clock High Chip Select Hold from Clock High ZZ High to Power Down ZZ Low to Power Up Symbol tCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tCH tCL tAS tSS tDS tWS tADVS tCSS tAH tSH tDH tWH tADVH tCSH tPDS tPUS -25 MIN 4.0 0 1.5 0 1.5 1.7 1.7 1.2 1.2 1.2 1.2 1.2 1.2 0.3 0.3 0.3 0.3 0.3 0.3 2 2 MAX 2.6 2.6 2.6 2.6 Min 6.0 0 1.5 0 1.5 2.1 2.1 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 2 2 -16 Max 3.5 3.5 3.0 3.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cycle cycle
Notes : 1. The above parameters are also guaranteed at industrial temperature range. 2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
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July 2005 Rev 1.0
TIMING WAVEFORM OF READ CYCLE
tCH tCL
K7A163630B K7A161830B
CLOCK
tSS tSH tCYC
ADSP
tSS tSH
ADSC
tAS tAH A1 tWS - 12 July 2005 Rev 1.0 tWH A2
BURST CONTINUED WITH NEW BASE ADDRESS
ADDRESS
A3
www..com 512Kx36 & 1Mx18 Synchronous SRAM
WRITE
tCSS tCSH
CS
tADVS tADVH
ADV
(ADV INSERTS WAIT STATE)
OE
tOE tLZOE tHZOE Q1-1 tCD tOH Q2-1 Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 tHZC Q3-4
Data Out
NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
Dont Care Undefined
TIMING WAVEFORM OF WRTE CYCLE
tCH tCL
K7A163630B K7A161830B
CLOCK
tSS tSH tCYC
ADSP
tSS tSH
ADSC
tAS tAH A1 A2
(ADSC EXTENDED BURST)
ADDRESS
A3 tWS tWH
www..com 512Kx36 & 1Mx18 Synchronous SRAM
WRITE
tCSS tCSH
- 13 July 2005 Rev 1.0
CS
(ADV SUSPENDS BURST)
tADVS
tADVH
ADV
OE
tDS tDH D3-2 D3-3 D3-4
Data In
tHZOE
D1-1
D2-1
D2-2
D2-2
D2-3
D2-4
D3-1
Data Out
Q0-3
Q0-4
Dont Care Undefined
K7A163630B K7A161830B
TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED , ADSC=HIGH)
tCH tCL
CLOCK
tSS tSH tCYC
ADSP
tAS tAH A2 A3 tWH
ADDRESS
A1
tWS
WRITE
www..com 512Kx36 & 1Mx18 Synchronous SRAM
- 14 July 2005 Rev 1.0
CS
tADVS tADVH
ADV
OE
tDS tDH D2-1 tHZC tCD tLZC Q1-1 tHZOE tLZOE tOH Q3-1 Q3-2 Q3-3 Q3-4
Data In
Data Out
Dont Care Undefined
K7A163630B K7A161830B
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED , ADSP=HIGH)
tCH tCL
CLOCK
tSS tSH tCYC
ADSC
tWS tWH A8 A9
ADDRESS
A1
A2
A3
A4
A5 tWS
A6 tWH
A7
WRITE
tCSS - 15 July 2005 Rev 1.0 tCSH
www..com 512Kx36 & 1Mx18 Synchronous SRAM
CS
ADV
OE
tOE tLZOE tHZOE Q1-1 Q2-1 Q3-1 Q4-1 tDS tDH D6-1 D7-1 tLZOE Q8-1 tOH Q9-1
Data Out
Data In
D5-1
Dont Care Undefined
TIMING WAVEFORM OF POWER DOWN CYCLE
tCH tCL
K7A163630B K7A161830B
CLOCK
tSS tSH tCYC
ADSP
ADSC
tAS tAH A1 A2 tWS tWH
ADDRESS
WRITE
www..com 512Kx36 & 1Mx18 Synchronous SRAM
- 16 July 2005 Rev 1.0 tCSS tCSH
CS
ADV
OE
tOE tLZOE
Data In
tHZC tHZOE
D2-1
D2-2
Data Out
Q1-1 tPDS tPUS
ZZ Recovery Cycle Normal Operation Mode
ZZ
ZZ Setup Cycle Sleep State
Dont Care Undefined
K7A163630B K7A161830B
APPLICATION INFORMATION
DEPTH EXPANSION
www..com 512Kx36 & 1Mx18 Synchronous SRAM
The Samsung 512Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic. Data Address I/O[0:71] A[0:19] A[19] A[0:18] A[19] A[0:18] Address Data CS2 CS2 512Kx36 SPB SRAM (Bank 0) CLK ADSC WEx OE CS1 ADSP ADV ADSP 512Kx36 SPB SRAM (Bank 1)
CLK
Address Data CS2 CS2 CLK
Microprocessor
Address CLK Cache Controller
ADSC WEx OE CS1 ADV
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS tSH
ADSP
tAS tAH A2 tWS tWH A1
ADDRESS [0:n] WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
tADVS tADVH
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
ADV
OE
tOE
Data Out (Bank 0) Data Out (Bank 1)
tLZOE Q1-1 Q1-2 Q1-3
tHZC Q1-4 tCD tLZC Q2-1 Q2-2 Q2-3 Q2-4
Undefined
*Notes : n = 14 32K depth , 16 128K depth , 18 512K depth ,
15 64K depth 17 256K depth 19 1M depth
Dont Care
- 17 -
July 2005 Rev 1.0
K7A163630B K7A161830B
APPLICATION INFORMATION
DEPTH EXPANSION
www..com 512Kx36 & 1Mx18 Synchronous SRAM
The Samsung 1Mx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 1M depth to 2M depth without extra logic.
Data Address
I/O[0:71] A[0:20] A[20] A[0:19] Address Data CS2 CS2 A[20] A[0:19] Address Data CS2 CS2 1Mx18 SPB SRAM (Bank 0) CLK ADSC WEx OE CS1 ADSP ADV ADSP 1Mx18 SPB SRAM (Bank 1)
CLK
Microprocessor
Address CLK Cache Controller
CLK ADSC WEx OE CS1 ADV
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH)
Clock tSS ADSP tAS ADDRESS [0:n] WRITE tCSS CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2 tCSH tSH
tAH A2
A1 tWS tWH
An+1 tADVS ADV tADVH
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
OE tOE Data Out (Bank 0) Data Out (Bank 1) tLZOE Q1-1 Q1-2 Q1-3
tHZC
Q1-4 tCD tLZC Q2-1 Q2-2 Undefined Q2-3 Q2-4
*Notes : n = 14 16 18 20
32K depth , 128K depth , 512K depth , 2M depth
15 64K depth 17 256K depth 19 1M depth
Dont Care
- 18 -
July 2005 Rev 1.0
K7A163630B K7A161830B
PACKAGE DIMENSIONS
100-TQFP-1420A (Lead and Lead free package)
22.00 0.30 20.00 0.20
www..com 512Kx36 & 1Mx18 Synchronous SRAM
Units ; millimeters/Inches
0~8
0.10 0.127 + 0.05 -
16.00 0.30 14.00 0.20 0.10 MAX
(0.83) 0.50 0.10 #1 0.65 0.30 0.10 0.10 MAX (0.58)
1.40 0.10 1.60 MAX 0.50 0.10 0.05 MIN
- 19 -
July 2005 Rev 1.0

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