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20MHz ~ 170MHz FSPLL
General Description
The AL2007LA is a Phase-Locked Loop (PLL) frequency synthesizer constructed in CMOS on single monolithic structure. The PLL macrofunctions provide frequency multiplication capabilities. The output clock frequency Fout is related to the reference input clock frequency Fin by the following equation: S Fout = ( m*Fin ) / ( p* 2 ) Where, Fout is the output clock frequency. Fin is the reference input clock frequency. m,p and s are the values for programmable dividers. AL2007LA consists of a phase/Frequency Detector(PFD), a Charge Pump an External Loop Filter, a Voltage Controlled Oscillator(VCO), a 6bit Pre-divider, an 8bit Main divider and 2bit Post Scaler as shown in Figure1.
AL2007LA
Dec 1998 Version1.0
Features
* 0.35um CMOS device technology
* 3.3 Volt Single power supply
* Output frequency range: 20~ 170 MHz
* Jitter 150ps
* Duty ratio 40% to 60% at 170MHz
* Frequency changed by programmable divider
* Power down mode
IMPORTANT NOTICE - Please contact SEC application engineer to confirm the proper selection of M,P,S value.
FUNCTIONAL BLOCK DIAGRAM
Fin
Pre Divider P
PFD
Charge Pump
Loop Filter (External)
VCO
Fout Post Scaler S
Main Divider M
Figure 1. Phase Lockd Loop Block Diagram
SAMSUNG ELECTRONICS Co. LTD
20MHZ~170MHZ FSPLL
CORE PIN DESCRIPTION
NAME VDD VSS VDDA VSSA VBB FIN FILTER I/O TYPE DP DG AP AG AB/DB DI AO I/O PAD vddd vssd vdda vssa vbba picc_bb poar50_bb PIN DESCRIPTION Digital power supply Digital ground Analog power supply Analog ground Analog/Digital sub bias Power PLL clock input . Pump out is connected to Filter . A capacitor is connected between the pin and analog ground 20MHz~170MHz clock output FSPLL clock power down. -PWRDN is High, PLL do not operating under this condition. -If isn't used this pin, tied to VSS. The values for 6bit programmable pre-divider. The values for 8bit programmable main divider. The values for 2bit programmable post scaler.
AL2007LA
I/O TYPE ABBR.
*AI : Analog Input *DI : Digital Input *AO : Analog Output *DO : Analog Output *AP *AG *AB *DP *DG *DB : Analog Power : Analog Ground : Analog Sub Bias : Digital Power : Digital Ground : Digital Sub Vias
FOUT PWRDN
DO DI
pot12_bb picc_bb
*BD : Bidirectional Port
P[5:0] M[7:0] S[1:0]
DI DI DI
picc_bb picc_bb picc_bb
CORE CONFIGURATION
FIN PWRDN M[7:0] M[0] M[1] M[2] M[3] M[4] M[5] M[6] M[7] P[0] P[1] P[2] P[3] P[4] P[5] S[0] S[1] FOUT
FILTER
AL2007LA
P[5:0]
S[1:0]
SEC ASIC
1
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ANALOG
20MHZ~170MHZ FSPLL
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Symbol VDD VDDA Voltage on Any Digital Pin Storage Temperature Vin Tstg Vss-0.3 to Vdd+0.3 -45to 125 V C Value -0.3 to 3.8 Unit V
AL2007LA
Applicable pin VDD,VDDA,VSS,VSSA P[5:0],M[7:0],S[1:0] PWRDN -
NOTES 1. ABSOLUTE M AXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIM UM RATING conditions for extended periods may a ffect reliability. Each condition value is applied with the other values kept within the following operating c onditions and function operation under any of these conditions is not implied. 2. All volta ges are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5K resistor (Human body model)
Recommended Operating Conditions
Characteristics Supply Voltage Differential Oscillator Frequency External Loop Filter Capacitance Operating Temperature Symbol VDD - VDDA Fosc LF Topr 0 Min -0.1 10 820 70 Typ 0 Max +0.1 40 Unit V Mhz pF C
NOTES 1. It is strongly recommended that all the supply pins (VDDA, VDD) be powered from the same source to avoid power latch-up.
SEC ASIC
2
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ANALOG
20MHZ~170MHZ FSPLL
AL2007LA
DC ELECTRICAL CHARACTERISTICS
Characteristics Operating Voltage Digital Input Voltage High Digital Input Voltage Low Dynamic Current (CORE Level without I/O Cell) Power Down Current Symbol VDD/VDDA Vih Vil Idd Ipd Min 3.15 2.0 0.8 3.5 120 Typ 3.3 Max 3.45 Unit V V V mA uA
AC ELECTRICAL CHARACTERISTICS
Characteristics Input Frequency Output Clock Frequency Input Clock Duty Cycle Output Clock Duty Cycle Input Glitch Pulse Width Locking Time Cycle to Cycle Jitter Symbol FIN FOUT TID TOD TIGP TLT TJCC -150 Min 2 20 40 40 1 150 +150 Typ 14.318 Max 40 170 60 60 Unit MHz Mhz % % ns us ps
SEC ASIC
3
/11
ANALOG
20MHZ~170MHZ FSPLL
Functional Description
A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference or input signal in frequency as well as in phase. In this application, it includes the following basic blocks. . The voltage-controlled oscillator to generate the output frequency . The divider P devides the reference frequency by p . The divider M devides the VCO output frequency by m . The divider S divides the VCO output frequency by s . The phase frequency detector detects the phase difference between the reference frequency and the output frequency (after division) and controls the charge pump voltage. . The loop filter removes high frequency components in charge pump voltage and does smooth and clean control of VCO The m, p, s values can be programmed by 16bit digital data from the external can be locked in the desired frequency. Fout = m * Fin / p*s If Fin = 14.318MHz, and m=M+8 , p=P+2, s=2^S Digital data format: Main Divider M7,M6,M5,M4,M3,M2,M1,M0 Pre Divider P5,P4,P3,P2,P1,P0
AL2007LA
source. So the PLL
Post Scaler S0,S1
NOTES . S[1] - S[0] : Output Frequency Scaler . M[7] - M[0] : VCO Frequency Divider . P[5] - P[0] : Reference Frequency Input Divider
OUTPUT FREQUENCY EQUATION & TABLE (M+8) FOUT = Frequency Equation : S (P+2) x 2
Table 1. Example of Divider Ratio
M7 0 M6 1 M5 0 M4 1 M3 0 M2 1 M1 0 M0 1 M 85 m (M+8) 93 P6 0 P5 1 P4 0
x FIN
P3 1
P2 0
P1 1
P0 0
P
p (P+2)
S1 0
S0 0
2S
42
44
1
IMPORTANT NOTICE - Please contact SEC application engineer to confirm the proper selection of M,P,S value.
SEC ASIC
4
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ANALOG
20MHZ~170MHZ FSPLL
CORE EVALUATION GUIDE
AL2007LA
For the embedded PLL, we must consider the test circuits for the embedded PLL core inmultiple applications. Hence the following requirements should be satisfied. - The FILTER and FOUT pins must be bypassed for external test. - For PLL test (Below 2 examples), it is needed to control the dividers - M[7:0],P[5:0] and S[1:0] -that generate multiple clocks. Example #1. Registers can be used for easy control of divider values. Example #2. N sample bits of 16-bit divider pins can be bypassed for test using MUX.
3.3V Power
Digital
3.3V Analog Power
GND
External Clock Source FIN
GND
VDD VSS
VDDA VSSA VBBA
FOUT PWRDN M[7:0]
AL2007LA
FILTER
#1.16bit Register Block
P[5:0]
820pF S[1:0] VSSA
Select Pin
NOTES
Test Pins of N Sample bits
#2 M U X
: 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 103 CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED
Internal Divider Signal Line
SEC ASIC
5
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ANALOG
20MHZ~170MHZ FSPLL
CORE LAYOUT GUIDE
AL2007LA
- The digital power(VDD,VSS) and the analog power(VDA,VSSA) must be dedicated to PLL only and seperated. If the dedicated VDD and VSS is not allowed that of the least power consuming block is shared with the PLL. - The PIA pad is used as a FILTER pad that contains only ESD production diodes without any resistors and buffers. - The FOUT and FILTER pins must be placed far from the internal signals in order to avoid overlapping signal lines. - The blocks having a large digital switching current must be located away from the PLL core. - The PLL core must be shielded by guardring. - For the FOUT pad, you can use a custom drive buffer or POT12 buffer considering the drive current.
WITHOUT XTAL-DRIVER USERS GUIDE
- There are two crystal driver cell (XTAL-OSC and PSOSCM2) options for the AL2007LA PLL core. 1. If the crystal component not used , an external clock source is applied to the FIN *Please contact an SEC application engineer when using a crystal. 2. If the crystal component not used , an external clock I/O Buffer offered from Samsung's STD90 library is recommanded for use - When implementing an embedded PLL block, the following pins must be bypassed externally for testing the PLL locking function: * Without Xtal-driver : FIN,FILTER,FOUT,VDDA,VSSA,VDD and VSS.
Figure2. The example of PLL block without crystal component (Normal Case)
FILTER FOUT
VDDA VSSA FIN VDD VSS VBBA
Used PICC_BB PAD
Divider P
PFD &CP
LF
VCO
Scaler S
PWRDN
Divider M
P[5:0] M[7:0] S[1:0]
Glue Logic
MUX
* Divider Bus
* Optional Test Pins
SEC ASIC
6
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ANALOG
20MHZ~170MHZ FSPLL
AL2007LA
PACKAGE CONFIGURATION
2bit Post Scaler Dummy Test Block Control pins
L L H L H L H
3.3V Digital PAD Power C
3.3V I/O Power C
H
36
35
34
33
32
31
30
29
28
27
26
25
8bit Main Divider
L L L L L L L L L L L L H H H H H H H H H H H H
37 M0 38 M1 39 M2 40
V D D D
V D D D
V S S D
V S S D
S 0
S 1
T S E L 0
T S E L 1
V D D O
V S S O
N C
N C NC
24
FOUT 23 NC
22 21
M3
AL2007LA
C
10uF 103
NC
41 M4 42 M5 43 M6 44
VBBA 20 VBBA 19 PWRDN 18 FILTER NC
17 16
H L
820pF
M7
45 P0 46 P1 47 P2 48 P3
External Clock Source
FIN 15 VDDA 14 V S S A
11
6bit Pre Divider Input
P 4
1
P 5
2
N C
3
N C
4
N C
5
N C
6
N C
7
N C
8
N C
9
N C
10
V VDDA S S A
12
C
13
3.3V Analog Power
H L
H L
NOTES * TSEL0,TSEL1 pins are internal dummy block test pins. * NC is Noconnection pin
SEC ASIC
7
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ANALOG
20MHZ~170MHZ FSPLL
AL2007LA
PACKAGE PIN DESCRIPTION
NAME VDDD VSSD PWRDN
PIN NO 35,36 33,34 18
I/O TYPE DP DG DI
PIN DESCRIPTION Digital power supply Digital ground FSPLL clock power down -PWRDN is High, PLL do not operating under this condition. - If isn't used this pin, tied to VSS. Pre-Divider Input(LSB) Analog power supply Analog ground Analog / Digtal Sub Bias Power Crystal input or external FREF input 20MHZ~170MHz clock output Pump out is connected to the FILTER. A 820pF Capcitor is connected between the pin and analog pin FOUT divide control pins. -End users used not this pins, tied to VDD or VSS FOUT divide control pins. -End users used not this pins, tied to VDD or VSS Post scaler input 8bit main divider input I/O PAD Power I/O PAD Ground
P[0]~P[5] VDDA VSSA VBBA FIN FOUT FILTER
1,2,45~48 13,14 11,12 19,20 15 22 17
DI AP AG AB/DB AI DO AO
TSEL0 TSEL1
30 29
DI DI
S[0]~S[1] M[0]~M[7] VDDO VSSO
31,32 37~44 28 27
DI DI PP PG
NOTES 1. I/O TYPE PP and PG denote PAD powe r and PAD ground respectively.
SEC ASIC
8
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ANALOG
20MHZ~170MHZ FSPLL
PLL Components
Figure1 is block diagram of the components of a PLL: phase frequency detector, chrge pump, voltage controlled oscillator, and loop filter. In SEC technology, the loop filter is implemented as external components close to chip. Phase detector : The phase dectector monitors the phase dfference between the Fref and Fvco,and generates a control signal when it detects difference between the two.
AL2007LA
If the Fref frequency is higher than the Fvco frequency, its falling edge occures before(lead) the falling edge of the Fvco output. When this occures the phase detector signals the VCO to increase the frequency of the on-chip clock. If the falling edge of the Fref occures after(lag) the falling edge of the Fvco output, the detector signals the VCO to decrease on-chip clock frequency. Figure7 illustrates the lead and lag conditions. If the frequencies of the Fref and Fvco are the same, the detect or does not generate a control signal, so the frequencies remain the same.
Fref Fvco UP
DOWN
Figure3. Lead and Lag Clocking Relationships
Charge Pump : The charge pump converts the phase detector control signal to a charge in voltage across the external filter that drives the VCO. As the vcoltage Controlled Oscillator decreases, or increases, If the voltage remains constant, the frequency of the oscillator remains constant. Loop Filter : The control signal that the phase detector generates for the charge pump may generate large excursions(ripples) each time the VCO output is compared to the system clock. To avoid overloading the VCO, a low pass filter samples and filters the high-frequency components out of the control signal. the filter is typically a single-pole RC filter consisting of a resistor and capacitor. Voltage Controlled Oscillator(VCO) : The output voltage from the loop filter drives the VCO, causing its oscillation frequency to increas or decrease as a function of variations in voltage. When the VCO output matches the system clock in frequency and phase, the pahse detector stops sending a control signal to the charge pump, which in turn stabilizes the input voltage to the loop filter. The VCO frequency then remains constant, and the PLL remains locked onto the system clock
SEC ASIC
9
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ANALOG
20MHZ~170MHZ FSPLL
Frequency Synthesis
AL2007LA
Frequency synthesis uses the system clock as a base frequency to generate higher/lower frequency clocks for internal logic. For high speed applications in high-end designs, transmission line effects cause problems because of parastics and impedance mismatch among various on-board components. These problems can be eliminated by moving the high frequency to the chip level. On-chip clocks that are faster than the external system clock can be synthesized by inserting a divider in the feedback path. The divider is placed after voltage controlled oscillator, as illustrated in Figure1. The signal is running at M times the system clock frequency, so the PLL matches the divider signal output to the system clock. This configuation reduces the problem of interfacing to the system clock on the board, and it reduces the noise generated by the system clock oscillator and driver for all the components in the system
Design Considerations
The following design consideratios apply: * Phase tolerance and jitter are independent of the PLL frequency. * Jitter is affected by the noise frequency in the power(VDD/VSS,VDDA/VSSA) . It increases when the noise level increases. * A CMOS-level input reference clock is recommend for signal compatibility with the PLL circuit. Other levels such as TTL may degrade the tolerances. * The use of two, or more PLLs requires special design considerations. Please consult your application engineer for more information. * The following apply to the noise level, which can be minimized by using good analog power and ground isolation techniques in the system: - Use wide PCB traces for POWER(VDD/VSS, VDDA/VSSA) connections to the PLL core. Seperate the traces from the chip's VDD/VSS,VDDA/VSSA supplies. - Use proper VDD/VSS,VDDA/VSSA de-coupling. - Use good power and ground sources on the board. - Use Power VBB for minimize substrate noise * The PLL core should be placed as close as possible to the dedicated loop filter and analog Power and ground pins. * It is inadvisable to locate noise-generating signals, such as data buses and high-current outputs, near the PLL I/O cells. * Other related I/O signals should be placed near the PLL I/O but do not have any predefined placement restriction
SEC ASIC
10 /11
ANALOG
20MHZ~170MHZ FSPLL
PLL Specification
We appreciate your interest in our products. If you have further questions, please specify in the attached form. Thank you very much. Parameter Supply Voltage Output frequency range Input frequency range Cycle to Cycle Jitter Lock up time Dynamic current Stand by current Output clock duty ratio Long term jitter Output slew rate Min Typ Max Unit
AL2007LA
Remarks
- Do you need XTAL driver buffer in PLL Core? If you need it, what's the crystal frequency range? If not, What's the input frequency range? Do you need the lock detector? Do you need the I/O cell of SEC? Do you need the external pin for PLL test? What's the main frequency & frequency range? How many FSPLLs do you use in your system? What's output loading? Could you external/internal pin configurations as required?
Specially requested function list :
SEC ASIC
11 /11
ANALOG

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