View AN1126_808170.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
AN1126 APPLICATION NOTE CURRENT SHARING OF THE L4973 IN A MULTIPHASE APPLICATION
by Domenico Arrigo & Giuseppe Gattavari
INTRODUCTION The L4973 family is a 3.5A monolithic step-down dc-dc converter, available in POWERDIP18( 12+3+3) and SO20L (12+4+4) plastic packages. The operating input supply voltage range is from 8V to 55V, and the output ranges from 3.3V (L4973D3.3) and 5.1V(L4973D5.1) to 40V. Other regulated outputs below 3.3V are also possible (See Application Note AN938). Using two L4973D is possible to deliver up to 7A with a good sharing between the two sections or a redundant 3.5A. The two devices work at a switching frequency of 200kHz. At Vcc = 24V, Vo = 5.1V at 7A the efficiency is 87%. At 3.5A output, the efficiency is 90%. Electrical Specifications
Input Voltage range Output Voltage Output Voltage Ripple Output Current range Max Output Ripple current Min Iomax Current limit Switching frequency 8V-30V 5.1V 3% (Line, Load and Temperature) 47mV (0.92%/Vo) 0 to 7A 15% 8A 200kHz
Current Sharing Operating Principle The current sharing configuration, shown in fig. 1, is based upon two L497x devices U1 and U2. Any device in the L497x family can be used for this purpose. The U1 regulator acts as a master which regulates the output voltage. The second section U2 works as a current follower. Its task is to deliver an output current equal to the Figure 1. Current Sharing Operating Principle
FB Vcc OUT
L
I-
U1 L497x
COMP
Rs
Cint Vcc GND
Rint Vout
+
OP-AMP
FB L Vcc COMP I+ Cout
U2 L497x
GND
OUT
Rs
May 1999
1/16
AN1126 APPLICATION NOTE
current delivered from the first section. An op-amp compares the voltage drop through Rs which is proportional to the current delivered from the U2 section with the voltage drop across Rs proportional to the current delivered from the U1 section. The Cin and Rin components introduce a pole and a zero in the current loop which allows integration of the error signal. The current loop regulates I+ equal to I- . As a result the output current delivered to the load is Iout = 2I- = 2I+ for every load condition. Current Sharing Accuracy The accuracy of the current sharing between the two sections depends on the op-amp offset voltage, Voff, and the value of Rs and its accuracy . The offset voltage introduce an error in the sensing voltage , Vs=Rs Iout/2 . The relative percentage current error due to the offset is given by : e%= ( I/I) 100 = (Voffset 100) / (Rs Iout) This error is minimum at maximum load. The larger the value of Rs, the smaller the error. Rs must be chosen as a compromise between error minimization and system efficiency. For example with Iout = 7A choosing Rs = 25m ,considering a maximum offset voltage of 3mV (LM358A), the maximum relative percentage error is 1.7% (120mA @ Iout = 7A). The total error is given by the sum of this error plus the error due to the sensing resistor ( which corresponds to its accuracy of 1% ). So the maximum error is 2.7% (190mA @Iout = 7A) Layout Hints The PCB layout requires some care. The power paths of the two sections must be as short and symmetrical as possible. The current sensing wires must be parallel and short to avoid induced noises. The sensing resistor must be non inductive. The ground pins of the two devices must be at the same voltage and connected to the output ground point. Figure 2. Layout hints.
FB Vcc
L OUT
I-
U1 L497x
COMP Vcc GND
Rs
to the current FB
Vout
Cout
GND GND Vcc L
to the current FB
GND I+
COMP
U2 L497x
OUT
Rs
Syncronization or Multiphase In a current sharing application the two sections can be synchronized. This permits a reduction of noise induced from one section to another. In this case a single RC network can be used for both the oscillators and the two SYNC pins are connected. In many application, instead of synchronizing the two oscillator, it is useful to introduce a delay between the two PWM signals in order to achieve a multiphase application. The phase shift between the two PWM signals can be easily achieved by two methods :
2/16
AN1126 APPLICATION NOTE
Case 1) Programmable Phase Delay. Fig. 3 shows how to program a phase delay with a monostable multivibrator whose on time is equal to the desired phase delay. Case 2) Fixed Phase Delay. Figure 3 shows a method of setting a delay time for the 2nd PWM section to be slightly larger than the ON-time of the 1st PWM section. Figure 3. Case 1) Programmable Phase Delay.
PWM OUTPUTS
Vcc R1 OSC Vcc
U1 L4973D3.3
OSC
U2 L4973D3.3
U1
C2
GND
SYNC
Vref=5.1
SYNC
GND
0
1B Vcc CLR
M74HC123
GND 1A
U2
_ 1Q
0 t
Figure 4. Case 2) Programmable Phase Delay.
PWM OUTPUTS
Vcc
U1 L4973D3.3
Vref=5.1
OUT1
L Rs
R1 OSC C2
U1
Vcc
Vout
0
18V
SYNC Vcc
*
Cout
L OUT2 Rs
U2
U2
OSC
L4973D3.3
0 t
* necessary if Vcc>18V
3/16
AN1126 APPLICATION NOTE
Multiphase Benefits The main benefits are : Minimization of the RMS current through the input capacitor therefore increasing of the efficiency and reducing of the capacitor cost and size. Minimization of ripple current through the output capacitor and ground path. Fast load transient response. Improved reliability /MTBF. RMS current through the input capacitor are equivalent in Case 1) and Case 2). Even though the circuitry of Case 2) is simplifier than Case 1), Case 1) provides the opportunity to optimize this ripple current. Minimization of the RMS Current Through the Input Capacitor. In Case 1) , Figure 3 shows the RMS current through the input capacitor, referred to the output current (Iout), for various phase delays, , of the two PWM sections. This assumes a duty cycle of 0.5 and a ripple current through the coil of 0.1 Iout. For equal to a half period (180 degrees of phase delay) the RMS current is approximately zero. If the two PWM signals are synchronized the RMS value is Irms = Iout/2. For example if Vout = 5V and Iout = 7A the Output Power is 35W. If the Input capacitor has an ESR of 100mOhm the phase delay allows a savings of 1.23W which corresponds to the 3.5% of the power delivered to the load. Figure 5. RMS current through the input capacitor for a different phase delay, , with a duty cycle of 0.5.
[A] =120 Iout/2 =180 =90
0
- Iout/2 =40 0 =0
time
Assuming the same duty cycle for the two sections, the RMS Current through the input filter for different duty cycle, considering a phase delay of the second PWM signal equal to the Ton of the first section ( Case 2) ), is given approximately (the output current ripple can be negleted for this calculation) by the following formula:
IRMS() =
-
2
Iout 2 2
(Iout )2
2
if 0.5 Multiphase (1) if > 0.5
Iout - (iout ) 2 (3 -1) 2
2
where = duty cycle
4/16
AN1126 APPLICATION NOTE
Iout is the total output current equal to the sum of the individual output currents delivered from the two sections. Figure 6. Input current of the two sections for different duty cycle.
1 PWM1 PWM2 PWM1 PWM2
1
1 PWM1 PWM2
0 0 t
0 0
0 t 0 t
<0.5
=0.5
>0.5
If the PWM signals are synchronized without any delay, the RMS current through the input filter as a function of duty cycle is :
(Iout )2 - (Iout ) Irmssync () = 2
synchronized (2)
Figure 7. RMS current through the input capacitor with synchronization and with multiphase.
[ A ] Iout
3Iout/4 Irms ( ) Irmssync ( ) Iout/2 Irms Iout/4 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Irmssync
Figure 7 shows Equations (1) and (2) versus the duty cycle. The maximum RMS current with synchronized PWMs is 1/2 of the total output current and it is obtained for = 0.5. In contrast, considering the multiphase PWM, the RMS value is 0 with = 0.5 and the max value of the RMS value is 1/4 of the total output current. So the maximum RMS current with multiphased PWMs is a half of that syncronized PWMs. For every duty cycle condition the RMS current with multiphase application is lower than the case with synchronized PWMs and it is quite regular for different duty cycles. It allows to optimize the input capacitor for the real working condition. In the synchronized case the input capacitor has to be dimensioned for the worst case of = 0.5 that can be far from the real working conditions.
5/16
AN1126 APPLICATION NOTE
If Psync is the wasted power on the input capacitor with synchronized PWMs, given by : Psync = ESR Irmssync2 and Pmulti is the wasted power with multiphased PWMs, given by : Pmulti = ESR Irms2 the power saved using the multiphase instead of the synchronized method for various duty cycle is : Psaved () = ESR (Irmssync2 () - Irms2 ()) ESR 2 2 Iout Psaved () = ESR Iout 2 (1 - ) 2 if 0.5 if > 0.5
For example considering an input capacitor ESR of 0.1 Ohm and an output current of 7A the power saved using the multiphase instead of the synchronized method for different duty cycle is shown in fig.8. Figure 8. Power saved using the multiphase instead of the synchronized method for various duty cycle.
[W] 2 1.5 Psaved () Psync () Pmulti () 1 Psync Psaved 0.5 Pmulti 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Figure 9. Power saved vs. Vout
[W]
2
Vin=12V
1.5
[W]
2
Vin=12V
1.5
ESR=60m Iout=10A
Iout=7A
ESR=100m
Psaved
1
Psaved
1
Iout=7A
0.5
ESR=75m Iout=5A
0.5
ESR=50m
0
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
0
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
Vout [ V ]
Vout [ V ]
6/16
AN1126 APPLICATION NOTE
Figure 10. Power saved vs. Iout.
2
Psaved [W]
1.5 Psave( Iout , 5.1 , 12 , 0.05 ) Psave( Iout , 5.1 , 12 , 0.085 ) Psave( Iout , 5.1 , 12 , 0.1 ) 0.5
Vcc=12V Vo=5.1V fsw=200kHz ESR=100m
85m
1
50m
0
0
1
2
3
4
5 Iout
6
7
8
9
10
[A]
The gained power as a percentage of the output power using the multiphase PWMs instead of synchronized PWMs is : P%() =
Psaved ()
Po
100
P%() =
ESR Iout 100 2 Vcc
So the percentage gained power, P%, for a fixed Iout, Vcc and ESR does not change with the output voltage. For example if the input capacitor has an ESR of 100mOhm for a 12V/3.3V or 12V/5V power conversion, with Iout = 7A, there is in both cases a P% gain of 3% . Table1 shows in details the major tips for different output voltages. Table 1. Vcc = 12V , Iout = 7A, ESR=100m.
Vo (V) 3.3 5.1 6 Irmssync (A) 3.13 3.46 3.5 Irmsmulti (A) 1.74 1.25 0 Irms (A) 1.39 2.21 3.5 Psync (W) 0.98 1.2 1.23 Pmulti (W) 0.3 0.16 0 Psaved (W) 0.68 1.04 1.23 P% Gained 3% 3% 3%
The gained power P% versus duty cycle is shown in figure 10.
7/16
AN1126 APPLICATION NOTE
Figure 11. P% vs. duty cycle. The gained power P% as a function of input voltage, output voltage, output current and input capacitor ESR is shown in figure 12. Figure 12 shows the measured efficiency with the L4973D board , with Vin = 12V, Vout = 5.1V, fsw = 200kHz, using a input capacitor 470F/50V ROE with an ESR = 85m. Using the multiphase application with a phase delay, , equal to half period, case1) , there is a gained efficiency of 2% compared to the synchronous application. So it is possible to maintain high efficiency values using low cost and size capacitor.
6 5 P%() 4 3 2 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Figure 12. P%
P%=(Psaved/Po) * 100
6
P%=(Psaved/Po) * 100
10
ESR=60m
5
Vcc=8V
Vcc=12V
Vcc=12V
8
P%
4
ESR=100m
6
3
Vcc=24V
2 1 0 0 2 4 6 8 10 12 Iout [ A ] 14 16 18 20
P%
4 2
75m 50m
0
2
4
6
8
10
12
14
16
18
20
Iout [ A ]
Figure 13. Efficiency vs. Output Current. VO IO = 100 [%] VIN IIN 95
Cin = 470F/50V ROE EKE ESR = 85mOhm Multiphase =180
Conclusions To sum up in application in which the duty cycle is between 0.2 and 0.8 there is a big advantage using the multiphase PWMs, in terms of dissipated power on the input capacitor compared with the added circuitry to achieve it. The more the output current is the more this advantage increases. Applications with = 0.5, using a half period of multiphase phase delay, gives the best benefit because the RMS current through the input capacitor is approximately zero.
90
synchronous
85
Vcc = 12V Vo = 5.1V fsw = 200kHz
80
0
1
2
3
4 5 Io [A]
6
7
8
Minimization of the Ripple Current Through the Output Capacitor. Figure 13 shows the current ripple through the output filter for different phase delay, , of the two PWMs considering a duty cycle of 0.5.
8/16
AN1126 APPLICATION NOTE
For equal to half period (180 degrees of phase delay) the ripple current is approximately zero. This allows to chose low cost output filtering capacitor. Or, with the same ESR, to reduce drastically the output voltage ripple. The phase shift between the two PWM signals can be easily achieved in two way. If the duty cycle is far from 0.5, the ripple current through the output capacitor is higher in Case 2 than in Case 1 in which the delay time can be programmed. Figure 14. Ripple current through the output capacitor for different phase delay, .
+/2
=90
=0 =180
=40
0
=120 -/2
=240
0
t
Current Sharing Evaluation Board for L4973D Figure 15. Current sharing schematic diagram.
J2
INH1 FB Vcc (8V to 30V) Vcc 22k R1 OSC C1 C7 680uF 35V 220nF C2 1.2nF INH BOOT C6 220nF L1 43uH (77120) N=34 Iout=7A
25m
R6
11 8,9
13
10
U1 L4973D
2,3 OUT
D1 STPS COMP 640CB
1 19 20
SS
12 4,..,7 18 14,..,17
GND
R3 C8 C12 220nF
SYNC V5.1 C5 C10 1uF 15nF
C4 22nF
C9 R2 10K 220pF R4
220uF
1/2 LM358 SO8 7
R7*
C14 4 8
Cin=10nF 6 5
R11
+
Rin=10K
R5
Vcc
Z1* 220nF
C13
100nF
10K
SYNC FB OSC Vcc INH2
BOOT
C18
25m
L2 43uH (77120) N=34 R9
1 8,9
20
13
10
U2 L4973D
2,3 OUT
D2 STPS 640CB
J3
C3 680uF 35V C17 220nF
INH
4,..,7 11 18 19 14,..,17
SS
12
C21 C23 220nF C19 220pF 220uF
V5.1 C20 1uF
GND COMP C16 4.7nF C15 R8 15nF 10K
* Z1 and R1 are necessary only if Vcc>25V
9/16
AN1126 APPLICATION NOTE
Electrical Specifications and Performance:
Input Voltage range Output Voltage Output Voltage Ripple Output Current range Max Output Ripple current Min Iomax Current limit Switching frequency Efficiency 8V-30V 5.1V 3% (Line, Load and Temperature) 47mV (0.92%/Vo) 0 to 7A 15% 8A 200kHz 87% @ 7A Vin = 24V
Figure 16. Board efficiency vs. output current. [%] 95 Vcc=8V 90 85 80 75 Vo=5.1V 70
10V 12V 15V 20V 24V
Table 2. Output voltage selection
L4973D3.3 Vo (V) 3.3 5.1 R3 (K) 0 2.7 L4973D5.1 5.1 0 4.7 R4 (K) 4.7 4.7
fsw=200kHz
Main Components Description. It follows a description of the chosen output and input capacitor and of the inductor for each of the two sections. 2 3 4 Io [A] 5 6 7 8
0
1
Input Capacitors The input capacitors have to be able to support the maximum input operating voltage of the device and the maximum RMS input current. At full load, Io = 7A and duty cycle of 50% the RMS current flowing through the input capacitors is maximum and is given by Io/2 . So the RMS current to be sustained is 3.5A. The two selected capacitor, FA 680F/50V Panasonic, are able to support this current. Inductor Selection The minimum duty cycle is: Dmin = (Vo + Vf )/(Vin max + Vf )= 0.184 where Vf is the freewheeling diode forward voltage. The inductor ripple current is fixed at 15% of Iomax and it is 0.525A. The inductor needed for each of the two sections is: L= (Vo + Vf) (1 - Dmin) = 43H Io fsw
The L Io2 is 0.533 and the size core chose is 77120 (125) Magnetics KoolM material. In order to compensate a 40% reduction of inductance at full load due to the DC current level, it is necessary to wire 34 turns, which correspond to 84H of inductance at light load.
10/16
AN1126 APPLICATION NOTE
With this choice the core losses are approximately 280mW. The temperature increasing of the core is 12C approximately. Output Capacitor The selection of Cout is driven by the output ripple voltage required, 1% of Vo. This is defined by the ESR of the output capacitance and by the maximum ripple current (0.525A). The maximum ESR is: ESR = Vo/Io = 0.051/0.525 = 97m The selected capacitance is 220F/35V FA Panasonic with ESR = 90mW and the ripple voltage is 0.92% of Vo (47mV). Bill of Material
C1, C3 C2 C4 C16 C13 C5,C15 C6,C7,C12,C17,C18,C23 C8,C21 C10,C20 C11,C22 C14 C9,C19 U1,U2 R1 R2 R3,R10 R4,R12 R6,R9 R7 R11,R5,R8 D1 D2 U3 Z1 L1,L2 680F / 35V FA PANASONIC 16x15 Irms=1690mA 1.2nF/35V SMD 1206 22nF SMD 1206 4.7nF SMD 1206 100nF/35V SMD 1206 15nF/35V SMD 1206 220nF/50V SMD 10% Kemet 1206 X7R 220F/35V FA PANASONIC 8x15 1F/10V electrolitic (not SMD) not used 10nF/35V SMD 1206 220pF SMD 1206 L4973D3.3 22k SMD 1% 1206, 0.25W 9.1k SMD 1% 1206, 0.25W 2.7k SMD 1% 1206, 0.25W 4.7k SMD 1% 1206, 0.25W 0.025 Ohm 1W 1% DALE WSL-2512 0 SMD 1206 10K SMD 1% 1206, 0.25W STPS640CB (DPAK) STPS640CB (DPAK) LM358 SO8 ST Diodo Zener 25V SOT23 43H KoolMu Magnetics core 77120 34 Turns d(mm)=0.91 AWG19
Stability Analysis of the Current Loop. In the current sharing configuration the U1 regulator acts as a master in order to regulate the output voltage. The second section U2 works as current follower. Its task is to deliver an output current equal to the current delivered from the first section. For the analysis of the stability, see Fig. 21, the current loop of the U2 section can be considered as a separated loop from the voltage loop of the U1 section, considering that the current loop is quite faster than the voltage one.
11/16
AN1126 APPLICATION NOTE
For the stability of the voltage loop see the AN938. The open loop transfer functions is composed of the following blocks : - Error amplifier and compensation block : A(s) = Avo (1 + s Rc Cc) s2 Ro Co Rc Cc + s (Ro Cc + Ro Co + Rc Cc) + 1
in which Ro = 1.2M and Co = 220pF are internal capacitance and resistance of the Error Amplifier while Rc and Cc are the compensation values. Figure 17. Error Amplifier Compensation Circuit Figure 18. Output filter
L I+ Vout
Cc gm Ro Rc Co
Rs Cout RL
D99IN1022
ESR
- Output LC filter: Gfil(s) =
1 RL + Rs
s Cout (RL + ESR) + 1 (ESR + RL) L Cout Rs (RL + ESR) + L + RL ESR Cout s2 Cout +s +1 RL + Rs RL + Rs
Rs is the sensing resistor, RL is the load resistance. PWM gain: Gpwm = Vcc Vct = where Vct is the peak to peak saw tooth oscillator. Figure 19. Current feedback.
Cint IVout FB
Vcc 6 6 Vcc - 1
6 7 + 5
Rint R
Rs Cout
LM358
I+
Rs Cout
12/16
AN1126 APPLICATION NOTE
The LM358 configured as an integrator introduces a gain given by Rs , a pole in Gint(s) and a zero in Z(s) : Vfb= ( Rs / s Cint Rint )[ (I+) (1 + s Cint Rint) - (I-) ] Assuming : 1 Gint(s) = Rs s Rint Cint and : H(s) = (1 + s Rint Cint) the current control loop block diagram can be considered as shown in Figure 20. Figure 20. Block diagram of the current loop
G(s) ( Compensated E/A, PWMGain, Output Filter ) IGint(s) Current integrator Vfb
A(s) Compensated E/A
PWM Gain
Gfilt(s) Output Filter
I+
Current Feedback H(s)
The complete block diagram of the current sharing loop is shown is figure 21. Figure 21. Complete block diagram of the current sharing loop
U1 section (Voltage Loop )
U2 section ( Current Loop )
Vref
V
G(s) ( Compensated E/A, PWMGain, Output Filter )
Vout 1/Rload
Iout
I-
I Gint(s)
I+
-
G(s) ( Compensated E/A, PWMGain, Output Filter )
I+
Vfb Av
H(s)
The open loop function of the current loop is given by : F(s) := GpwmZint(s) Gfil(s) A(s) In figures 22 and 23 are shown the open loop Gain and Phase Bode plot . The capacitor C5 does not influence the system stability but is useful only to reduce the noise. The cut off frequency and a phase margin are: Fc = 8KHz; Angle = 40
13/16
AN1126 APPLICATION NOTE
Figure 22. Gain Bode open loop plot.
|F| [ dB ]
120 100 80 60 40 20 0 -20 1 10 100 3 1 10 4 1 10 5 1 10
f [ Hz ]
Figure 23. Phase Bode open loop plot.
F []
0 -20 -40 -60 -80 -100 -120 -140 -160 -180 1 10 100 3 1 10 4 1 10 5 1 10
f [ Hz ]
Figure 24. Load transient response. Load Transient Response Figure 24 shows the load transient behavior of the schematic circuit of Figure 15. In Figure 24 are shown the current deliveder from the two sections, the load current and the drop voltage on the output . After 20s the total current delivered from the two section is equal to the current required from the load. So the response time of the application is 20s approximately for a load transient from 1A to 6A.
TEST CONDITIONS (fig 24): Vin = 5V, Vout = 3.3V, Load transient form 1A to 6A, dIout/dt = 20A/s.
14/16
AN1126 APPLICATION NOTE
Figure 25. PCB Layout top view: Silk, component side and bottom layer (1:1.25 scale).
15/16
AN1126 APPLICATION NOTE
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
16/16

▲Up To Search▲

Price & Availability of AN1126

	To Download AN1126 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .