View PLL2013X_637562.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

20MHz ~ 170MHz FSPLL
General Description
The PLL2013X is a Phase-Locked Loop (PLL) frequency synthesizer constructed in CMOS on single monolithic structure. The PLL macro-functions provide frequency multiplication capabilities. The output clock frequency Fout is related to the input clock frequency Fin(XTALIN) by the following equation: s Fout=(m*Fin)/(p*2 ) Where, Fout is the output clock frequency. Fin is the input clock frequency. m,p and s are the values for programmable dividers. PLL2013X consists of a phase/Frequency Detector(PFD), a Charge Pump an External Loop Filter, a Voltage Controlled Oscillator(VCO), a 6bit Pre-divider, an 8bit Main divider and 2bit Post Scaler as shown inFigure1.
PLL2013X
Features
* * * * * * 0.25mm CMOS device technology 2.5 Volt single power supply Output frequency range: 20 ~ 170 MHz Jitter 150ps at 170MHz Duty ratio 45% to 55%(All tuned range) Frequency changed by programmable divider * Provision for 14.318Mhz crystal oscillator buffer - OPTION * Power down mode
IMPORTANT NOTICE - Please contact SEC application engineer to confirm the proper selection of M,P,S value.
FUNCTIONAL BLOCK DIAGRAM
FIN
Pre Divider P
PFD
Charge Pump
VCO
Post Scaler S
FOUT
Loop Filter
Main Divider M
Figure 1. Phase Locked Loop Block Diagram
NOTE
* Xtal oscillator is OPTIONAL block. If customer concerns about this bloc k - xtal buffer or lock detector, re fer to next chapter.
Ver 2.3 ( DEC. 1999 ) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The contents of the datasheet is subject to change without any notice.
SAMSUNG ELECTRONICS Co. LTD
20MHZ~170MHZ FSPLL
CORE PIN DESCRIPTION
NAME
VDD25A2 VSS25A2 VDD25A1 VSS25A1 VBBA FIN FILTER
PLL2013X
I/O TYPE
DP DG AP AG AB/DB DI AO
I/O PAD
vdd2t_abb vss2t_abb vdd2t_abb vss2t_abb vbb_abb picc_abb poar50_abb
PIN DESCRIPTION
Digital power supply Digital ground Analog power supply Analog ground Analog / Digital sub bias Reference Frequency Input . Pump out is connected to Filter . A capacitor is connected between the pin and analog ground 20MHz~170MHz clock output FSPLL clock power down. -When PWRDN is High, PLL do not operate. -If Customer don't use this pin, Apply to VSS. The values for 6bit programmable pre-divider. The values for 8bit programmable main divider. The values for 2bit programmable post scaler.
I/O TYPE ABBR.
* * * * * * * * * * AI : Analog Input DI : Digital Input AO : Analog Output DO : Analog Output AP AG AB DP DG DB : : : : : : Analog Power Analog Ground Analog Sub Bias Digital Power Digital Ground Digital Sub Vias
FOUT PWRDN
DO DI
pot8_abb picc_abb
* BD : Bidirectional Port
P[5:0] M[7:0] S[1:0]
DI DI DI
picc_abb picc_abb picc_abb
NOTE
- SEC recommends customers to use power cell type - vdd2t_abb, vss2t_abb. When using the recommended power cells, customers must use slot cells for separating digital and analog power. - Please contact SEC when customers can not use the recommended power cells or customer is to arrange this I/O cells in product..
CORE CONFIGURATION
FIN PWRDN M[7:0]
M[0] M[1] M[2] M[3] M[4] M[5] M[6] M[7]
FOUT
PLL2013X
P[5:0]
P[0] P[1] P[2] P[3] P[4] P[5] S[0] S[1]
FILTER
S[1:0]
SEC ASIC
2 / 14
ANALOG
20MHZ~170MHZ FSPLL
PLL2013X
Recommended Operating Conditions
Characteristics
Supply Voltage Differential Oscillator Frequency External Loop Filter Capacitance Operating Temperature
NOTES 1. It is strongly recommended that all the supply pins (VDD25A1, VDD25A2) be powered to the same supply voltage to avoid powe r latch-up.
Symbol
VDD25A2-VDD25A1 Fosc LF Topr
Min
-0.1
Typ
14.318 820
Max
+0.1
Unit
V MHz pF
0
70
C
DC ELECTRICAL CHARACTERISTICS
Characteristics
Operating Voltage Digital Input Voltage High Digital Input Voltage Low Dynamic Current Power Down Current
Symbol
VDD25A2/VDD25A1 V IH VIL Idd Ipd
Min
2.375 1.9
Typ
2.5
Max
2.625
Unit
V V
0.5 3 10
V mA uA
AC ELECTRICAL CHARACTERISTICS
Characteristics
Crystal frequency Input Frequency Output Clock Frequency Input Clock Duty Cycle Output Clock Duty Cycle (at 170MHz) Input Glitch Pulse Width Locking Time Jitter,Cycle to Cycle
Symbol
F XTAL FIN FOUT TID TOD TIGP TLT TJCC
Min
Typ
14.318
Max
Unit
MHz
3 20 40 45 1
40 170 60 55
MHz MHz % % ns
150 -150 +150
us ps
NOTES 1. It is strongly recommended that input signal is not generated glitch, but if c onsumer cannot help generating glitch, Consume r must carefully conside rate the specification.
SEC ASIC
3 / 14
ANALOG
20MHZ~170MHZ FSPLL
Functional Description
A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference or input signal in frequency as well as in phase. In this application, it includes the following basic blocks. . The voltage-controlled oscillator to generate the output frequency . The divider P devides the input frequency by p . The divider M devides the VCO output frequency by m . The divider S divides the VCO output frequency by s . The phase frequency detector detects the phase difference between the reference frequency and the output frequency (after division) and controls the charge pump voltage. . The loop filter removes high frequency components in charge pump voltage and does smooth and clean control of VCO
PLL2013X
The m, p, s values can be programmed by 16bit digital data from the external source. So the PLL can be locked in the desired frequency. Fout = m * Fin / p*s Fin = 14.318MHz, m=M+8 , p=P+2, s=2^S Digital data format:
Main Divider
M7,M6,M5,M4,M3,M2,M1,M0
Pre Divider
P5,P4,P3,P2,P1,P0
Post Scaler
S1,S0
NOTES . S[1] - S[0] : Output Frequency Scaler . M[7] - M[0] : VCO Frequency Divider . P[5] - P[0] : Reference Frequency Input Divider
OUTPUT FREQUENCY EQUATION & TABLE Frequency Equation:
Table 1. Example of Divider Ratio
FOUT =
(M+8) s (P+2) x 2
x FIN
M7 M6 M5 M4 M3 M2 M1 M0 M
m P5 P4 (M+8)
P3 P2
P1 P0
P
p S1 S0 2 (P+2)
S
0
1
0
1
0
1
0
1
85
93
1
0
1
0
1
0
42
44
0
0
1
IMPORTANT NOTICE - Please contact SEC application engineer to confirm the proper selection of M,P,S value.
SEC ASIC
4 / 14
ANALOG
20MHZ~170MHZ FSPLL
PLL2013X
CORE EVALUATION GUIDE
For the embedded PLL, we must consider the test circuits for the embedded PLL core in multiple applications. Hence the following requirements should be satisfied. - The FILTER and FOUT pins must be bypassed for external test. - For PLL test (Below 2 examples), it is needed to control the dividers - M[7:0],P[5:0] and S[1:0] -that generate multiple clocks. #1. Registers can be used for easy control of divider values. #2. N sample bits of 16-bit divider pins can be bypassed for test using MUX.
2.5V Digital Power 2.5V Analog Power
GND GND
VDD25A2 VSS25A2
VDD25A1VSS25A1 VBBA
FIN
FOUT
PWRDN M[7:0] #1. 16bit Resistor Block P[5:0] FILTER
PLL2013X
S[1:0]
820pF
VSS25A1 Select Pin
Test Pins of N Sample bits #2. MUX NOTES : 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 104 CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED
Internal Divider Signal Line
SEC ASIC
5 / 14
ANALOG
20MHZ~170MHZ FSPLL
CORE LAYOUT GUIDE
PLL2013X
* The digital power(VDD25A2,VSS25A2) and the analog power(VDD25A1,VSS25A1) must be dedicated to PLL only and seperated. If the dedicated VDD25A2 and VSS25A2 is not allowed that of the least power consuming block is shared with the PLL. * The poar50_abb pad is used as a FILTER pad that contains only ESD production diodes with 50Ohm resistors. * The FOUT and FILTER pins must be placed far from the internal signals in order to avoid overlapping signal lines. * The blocks having a large digital switching current must be located away from the PLL core. * For the FOUT pad, you can use a custom drive buffer or pot8_abb buffer considering the drive current.
OPTIONAL BLOCK USERS GUIDE
-- There are crystal driver cell options for the PLL2013X core. 1. If the crystal component not used , an external clock source is applied to the FIN - If the crystal component not used , an external clock I/O Buffer offered from Samsung's STD110 library is recommanded for use - When implementing an embedded PLL block, the following pins must be bypassed externally for testing the PLL locking function: * Without Xtal-driver : FIN,FILTER,FOUT,VDD25A1,VSS25A1,VDD25A2 and VSS25A2,VBBA. 2. If the crystal componet and the Lock detector used, please contact an SEC application engineer - When implementing an embedded PLL block, the following pins must be bypassed externally for testing the PLL locking function: * With Xtal-driver : XTALIN,XTALOUT,LDOUT,FILTER,FOUT,VDD25A1,VSS25A1,VDD25A2 and VSS25A2,VBBA
Figure2. The example of PLL block without crystal component and Lock Detector
FILTER FOUT
VDD25A1
VSS25A1
FIN
Pre Divide P
PFD
Charge Pump
VCO
Post Scaler S
Loop Filter Used picc_abb P A D Main Divider M
PWRDN P[5:0] M[7:0] S[1:0]
VDD25A2
VSS25A2
Glue Logic
VBBA
MUX
*Divider Bus
* Optional Test Pins
SEC ASIC
6 / 14
ANALOG
20MHZ~170MHZ FSPLL
PLL2013X
Figure3. The example of PLL block with dedicated XTAL-OSC and Lock Detector
FILTER LDOUT FOUT
VDD25A1
VSS25A1
LD
XTALIN
XTAL OSC
Pre Divide P PFD Charge Pump VCO Post Scaler S
XTAOUT
Loop Filter PWRDN P[5:0] Main Divider M M[7:0] S[1:0]
VDD25A2
VSS25A2
Glue Logic
VBBA
MUX
*Divider Bus
* Optional Test Pins
XTAL Buffer Cell
E YN PADA
PADB PO PI
Figure4.
Xtal buffer cell Symbol
* A XTAL Buffer cell for PLL is supported MDL110 databook of SEC * The XTAL must be located between PADA and PADB. Enable pin(E) must be HIGH in normal operation. * PI pin must be connected to VDD25A2 and the PO pin floated.
SEC ASIC
7 / 14
ANALOG
20MHZ~170MHZ FSPLL
PLL2013X
Lock Detector
Internal UP Signal
LOCK STATE
LS
LDOUT
Detector
LO
Internal DOWN Signal
Figure5.
Lock Detector Block
The built-in Lock Detector circuit will only work, When it is used in conjunction with PFD block output up/down signal. (Figure5). We represent the output of lock detector in the timing diagram. (Figure6) - Unlock State : LOW - Lock State : HIGH
UP/DOWN LO
LDOUT Unlock Lock
Figure6.
Lock Detector Timing Diagram
SEC ASIC
8 / 14
ANALOG
20MHZ~170MHZ FSPLL
PLL2013X
PACKAGE CONFIGURATION
P4 P5 TST1 TST2 TST3 NC NC NC NC LDOUT VSSA VSSA VDDA VDDA XTALIN XTALOUT FILTER PWRDN VBB VBB NC NC FOUT NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
P3 P2 P1 P0 M7 M6 M5 M4 M3 M2 M1 M0 VDDD VDDD VSSD VSSD S0 S1 TST5 TST4 VDDO VSSO NC NC
PLL2013X
10uF 0.1uF
NOTES * NC is No connection pin
SEC ASIC
9 / 14
ANALOG
20MHZ~170MHZ FSPLL
PLL2013X
PACKAGE PIN DESCRIPTION
NAME
VDDD VSSD VBB PWRDN
PIN NO
35,36 33,34 19,20 18
I/O TYPE
DP DG AB/DB DI
PIN DESCRIPTION
Digital power supply Digital ground Analog / Digital Sub Bias FSPLL clock power down -PWRDN is High, PLL do not operating under this condition. - If isn't used this pin, tied to VSSD. Pre-Divider Input Analog power supply Analog ground Xtal external input, Load Cap : 25pF If Customer don't use the Xtal, use this pin to Input Port. Xtal external output, Load Cap. : 25pF If Customer don't use the Xtal, Float this pin. 20MHZ~170MHz clock output Lock detector output Pump out is connected to the FILTER. A 820pF Capacitor is connected between the filter pin and analog ground pin. Post scaler input 8bit main divider input Test Pin, Apply to Analog vdda. Test Pin, Apply to Ground I/O PAD Power I/O PAD Ground
P[0]~P[5] VDDA VSSA XTALIN
45~48,1,2 13,14 11,12 15
DI AP AG AI
XTALOUT FOUT LDOUT FILTER S[0]~S[1] M[0]~M[7] TST1, TST3 TST2,TST4,TST5 VDDO VSSO
16 23 10 17 32,31 37~44 3,5 4,29,30 28 27
AO DO DO AO DI DI DI DI PP PG
NOTES 1. I/O TYPE PP and PG denote PAD powe r and PAD ground respectively. 2. XTALIN, XTALOUT ,LDOUT is test pin for PLL in SEC
SEC ASIC
10 / 14
ANALOG
20MHZ~170MHZ FSPLL
PLL Components
Figure1 is block diagram of the components of a PLL: phase frequency detector, chrge pump, voltage controlled oscillator, and loop filter. In SEC technology, the loop filter is implemented as external components close to chip. Phase detector : The phase dectector monitors the phase dfference between the Fref and
PLL2013X
Fvco,and generates a control signal when it detects difference between the two. If the Fref frequency is higher than the Fvco frequency, its falling edge occures before(lead) the falling edge of the Fvco output. When this occures the phase detector signals the VCO to increase the frequency of the on-chip clock. If the falling edge of the Fref occures after(lag) the falling edge of the Fvco output, the detector signals the VCO to decrease on-chip clock frequency. Figure4 illustrates the lead and lag conditions. If the frequencies of the Fref and Fvco are the same, the detect or does not generate a control signal, so the frequencies remain the same.
Fref Clk Fvco Clk UP
DOWN
Figure4. Lead and Lag Clocking Relationships
Charge Pump : The charge pump converts the phase detector control signal to a charge in voltage across the external filter that drives the VCO. As the vcoltage Controlled Oscillator decreases, or increases, If the voltage remains constant, the frequency of the oscillator remains constant. Loop Filter : The control signal that the phase detector generates for the charge pump may generate large excursions(ripples) each time the VCO output is compared to the system clock. To avoid overloading the VCO, a low pass filter samples and filters the high-frequency components out of the control signal. the filter is typically a single-pole RC filter consisting of a resistor and capacitor. Voltage Controlled Oscillator(VCO) : The output voltage from the loop filter drives the VCO, causing its oscillation frequency to increas or decrease as a function of variations in voltage. When the VCO output matches the system clock in frequency and phase, the pahse detector stops sending a control signal to the charge pump, which in turn stabilizes the input voltage to the loop filter. The VCO frequency then remains constant, and the PLL remains locked onto the system clock
SEC ASIC
11 / 14
ANALOG
20MHZ~170MHZ FSPLL
Frequency Synthesis
PLL2013X
Frequency synthesis uses the system clock as a base frequency to generate higher/lower frequency clocks for internal logic. For high speed applications in high-end designs, transmission line effects cause problems because of parastics and impedance mismatch among various on-board components. These problems can be eliminated by moving the high frequency to the chip level. On-chip clocks that are faster than the external system clock can be synthesized by inserting a divider in the feedback path. The divider is placed after voltage controlled oscillator, as illustrated in Figure1. The signal is running at M times the system clock frequency, so the PLL matches the divider signal output to the system clock. This configuation reduces the problem of interfacing to the system clock on the board, and it reduces the noise generated by the system clock oscillator and driver for all the components in the system
Design Considerations
The following design consideratios apply:. * Jitter is affected by the power noise, substrate noise...etc. It increases when the noise level increases. * A CMOS-level input reference clock is recommend for signal compatibility with the PLL circuit. Other levels such as TTL may degrade the tolerances. * The use of two, or more PLLs requires special design considerations. Please consult your application engineer for more information. * The following apply to the noise level, which can be minimized by using good analog power and ground isolation techniques in the system: - Use wide PCB traces for POWER(VDD25A2/VSS25A2, VDD25A1/VSS25A1) connections to the PLL core. Seperate the traces from the chip's VDD25A2/VSS25A2,VDD25A1/VSS25A1 supplies. - Use proper VDD25A2/VSS25A2,VDD25A1/VSS25A1 de-coupling. - Use good power and ground sources on the board. - Use Power VBBA for minimize substrate noise * The PLL core should be placed as close as possible to the dedicated loop filter and analog Power and ground pins. * It is inadvisable to locate noise-generating signals, such as data buses and high-current outputs, near the PLL I/O cells. * Other related I/O signals should be placed near the PLL I/O but do not have any pre-defined placement restriction
SEC ASIC
12 / 14
ANALOG
20MHZ~170MHZ FSPLL
Phantom Cell Information
- Pins of the core can be assigned externally(Package pins) or internally(internal ports) depending on design methods. The term "external" implies that the pins should be assigned externally like power pins. The term "internal/external" implies that these pins are user dependant
VSS25A2:G VDD25A2: P VBB A:G VSS25A2:G
PLL2013X
VDD25A2: P
VBB A:G
M [0] M [1] M [2] S[1] M [3] M [4] M [5] M [6] M [7] FOUT S[0]
FIN
P[5] P[4] P[3] P[2] P[1] P[0]
PLL2013X
PWRDN
VDD25A1: P
VSS25A1:G
VBB A:G
FILTER
VBB A:G
VSS25A1:G
VDD25A1: P
Figure. Phantom cell feature (Chip size : 631.46*422.16 um )
2
Pin Name
VDD25A2 VSS25A2 VDD25A1 VSS25A1 VBBA FIN
Pin Usage
External External External External External External
Pin Layout Guide
Pin Name
Pin Usage
Pin Layout Guide
-. Neighboring circuitry pads -. Ground Shielding -. The external loop filter pin is placed between the analog power to avoid stray coupling outside the chip and magnetic coupling via bond wires -. Closely placed Loop Filter components
-. Dedicated power/ground pins -. Power cuts are required to provide on-chip isolation => between dedicated PLL power/ground and all other power/ground -. Us e good power and ground source on board
FILTER
External
PWRDN M[7]~M[0]
Interanl/External Internal/External Internal/External Internal/External
-. Neighboring circuitry pads -. Us e proper low jitter refernce clock
P[5]~P[0] S[1]~S[0]
FOUT
External
-. Neighboring circuitry pads -. Internal routing path should not be long, This will minimize loading effect. -. Fout signals should not be crossed by any signals and should not run next to digital signals. This will minimize capacitive coupling between the two signals.
Table. Pin Layout Guide
SEC ASIC
13 / 14
ANALOG
20MHZ~170MHZ FSPLL
PLL Specification
We appreciate your interest in our products. If you have further questions, please specify in the attached form. Thank you very much.
PLL2013X
Parameter
Supply Voltage Output frequency range Input frequency range Cycle to Cycle Jitter Lock up time Dynamic current Stand by current Output clock duty ratio Long term jitter Output slew rate
Min
Typ
Max
Unit
Remarks
* Do you need XTAL driver buffer in PLL Core? If you need it, what's the crystal frequency range? If not, What's the input frequency range? * * * * * * * Do you need the lock detector? Do you need the I/O cell of SEC? Do you need the external pin for PLL test? What's the main frequency & frequency range? How many FSPLLs do you use in your system? What's output loading? Could you external/internal pin configurations as required?
Specially requested function list :
SEC ASIC
14 / 14
ANALOG
20MHZ~170MHZ FSPLL
PLL2013X
Version
Ver 1.0
Date
98.12.1 Original version published
Modified Items
Comments
Ver 1.1
99.5.10
1. Change power name - VDDA -> VDD25A1 VSSA ae VSS25A1 VDDD ae VDD25A2 VSSD ae VSS25A2 VBB ae VBBA
Ver 2.0 Ver 2.1 Ver 2.2 Ver 2.3
99.12.10 1. Font check 00.3.29 00.07.13 1. Phantom Inform / Layout Guide A 1. Pre-Divider Divisor ratio guide 2. Power Down1/2A current AcAA page 2> Aui.
01.02.23 1. Power cell Guide A.
SEC ASIC
ANALOG

▲Up To Search▲

Price & Availability of PLL2013X

	To Download PLL2013X Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .