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19-3706; Rev 0; 5/05
Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL
General Description
The MAX7030 crystal-based, fractional-N transceiver is designed to transmit and receive ASK/OOK data at factory-preset carrier frequencies of 315MHz, 345MHz, or 433.92MHz with data rates up to 33kbps (Manchester encoded) or 66kbps (NRZ encoded). This device generates a typical output power of +10dBm into a 50 load, and exhibits typical sensitivity of -114dBm. The MAX7030 features separate transmit and receive pins (PAOUT and LNAIN) and provides an internal RF switch that can be used to connect the transmit and receive pins to a common antenna. The MAX7030 transmit frequency is generated by a 16bit, fractional-N, phase-locked loop (PLL), while the receiver's local oscillator (LO) is generated by an integer-N PLL. This hybrid architecture eliminates the need for separate transmit and receive crystal reference oscillators because the fractional-N PLL is preset to be 10.7MHz above the receive LO. Retaining the fixed-N PLL for the receiver avoids the higher current-drain requirements of a fractional-N PLL and keeps the receiver current drain as low as possible. All frequencygeneration components are integrated on-chip, and only a crystal, a 10.7MHz IF filter, and a few discrete components are required to implement a complete antenna/digital data solution. The MAX7030 is available in a small, 5mm x 5mm, 32pin thin QFN package, and is specified to operate over the automotive -40C to +125C temperature range.
Consult factory for availability.
Features
+2.1V to +3.6V or +4.5V to +5.5V Single-Supply Operation Single-Crystal Transceiver Factory-Preset Frequency (No Serial Interface Required) ASK/OOK Modulation +10dBm Output Power into 50 Load Integrated TX/RX Switch Integrated Transmit and Receive PLL, VCO, and Loop Filter > 45dB Image Rejection Typical RF Sensitivity*: -114dBm Selectable IF Bandwidth with External Filter < 12.5mA Transmit-Mode Current < 6.7mA Receive-Mode Current < 800nA Shutdown Current Fast-On Startup Feature, <250s Small, 32-Pin, Thin QFN Package
*0.2% BER, 4kbps Manchester-encoded data, 280kHz IF BW
MAX7030
Ordering Information
PART TEMP RANGE PIN-PACKAGE PKG CODE T3255-3
Applications
2-Way Remote Keyless Entry Security Systems Home Automation Remote Controls Remote Sensing Smoke Alarms Garage Door Openers Local Telemetry Systems
MAX7030_ATJ -40C to +125C 32 Thin QFN-EP**
**EP = Exposed paddle. Note: The MAX7030 is available with factory-preset operating frequencies. See the Product Selector Guide for complete part numbers.
Product Selector Guide
PART MAX7030LATJ MAX7030MATJ MAX7030HATJ CARRIER FREQUENCY (MHz) 315 345 433.92
Pin Configuration, Typical Application Circuit, and Functional Diagram appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030
ABSOLUTE MAXIMUM RATINGS
HVIN to GND..........................................................-0.3V to +6.0V PAVDD, AVDD, DVDD to GND ................................-0.3V to +4.0V ENABLE, T/R, DATA, AGC0, AGC1, AGC2 to GND .......................................-0.3V to (HVIN + 0.3V) All Other Pins to GND ...............................-0.3V to (_VDD + 0.3V) Continuous Power Dissipation (TA = +70C) 32-Pin Thin QFN (derate 21.3mW/C above +70C).............................................................1702mW Operating Temperature Range .........................-40C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, 50 system impedance, AVDD = DVDD = HVIN = PAVDD = +2.1V to +3.6V, fRF = 315MHz, 345MHz, or 433.92MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at AVDD = DVDD = HVIN = PAVDD = +2.7V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Supply Voltage (3V Mode) Supply Voltage (5V Mode) SYMBOL VDD HVIN CONDITIONS HVIN, PAVDD, AVDD, and DVDD connected to power supply PAVDD, AVDD, and DVDD unconnected from HVIN, but connected together Transmit mode, PA off, VDATA at 0% duty cycle (Note 2) Transmit mode, VDATA at 50% duty cycle (Notes 3, 4) Transmit mode, VDATA at 100% duty cycle (Note 2) fRF = 315MHz fRF = 434MHz fRF = 315MHz fRF = 434MHz fRF = 315MHz fRF = 434MHz Receiver 315MHz Supply Current IDD Receiver 434MHz TA < +85C, typ at +25C (Note 4) Deep-sleep (3V mode) Deep-sleep (5V mode) Receiver 315MHz Receiver 434MHz TA < +125C, typ at +125C (Note 2) Deep-sleep (3V mode) Deep-sleep (5V mode) Voltage Regulator DIGITAL I/O Input-High Threshold Input-Low Threshold VIH VIL (Note 2) (Note 2) 0.9 x HVIN 0.1 x HVIN V V VREG HVIN = 5V, ILOAD = 15mA MIN 2.1 4.5 TYP 2.7 5.0 3.5 4.3 7.6 8.4 11.6 12.4 6.1 6.4 0.8 2.4 6.4 6.7 8.0 14.9 3.0 MAX 3.6 5.5 5.4 6.7 12.3 13.6 19.1 20.4 7.9 8.3 8.8 A 10.9 8.2 8.4 34.2 A 39.3 V mA mA UNITS V V
2
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Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL
DC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, 50 system impedance, AVDD = DVDD = HVIN = PAVDD = +2.1V to +3.6V, fRF = 315MHz, 345MHz, or 433.92MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at AVDD = DVDD = HVIN = PAVDD = +2.7V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Pulldown Sink Current Output-Low Voltage Output-High Voltage VOL VOH SYMBOL ISINK = 500A ISOURCE = 500A CONDITIONS AGC0-2, ENABLE, T/R, DATA (HVIN = 5.5V) MIN TYP 20 0.15 HVIN - 0.26 MAX UNITS A V V
MAX7030
AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, 50 system impedance, PAVDD = AVDD = DVDD = HVIN = +2.1V to +3.6V, fRF = 315MHz, 345MHz, or 433.92MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at PAVDD = AVDD = DVDD = HVIN = +2.7V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER GENERAL CHARACTERISTICS Frequency Range Maximum Input Level Transmit Efficiency 100% Duty Cycle Transmit Efficiency 50% Duty Cycle PRFIN fRF = 315MHz (Note 6) fRF = 434MHz (Note 6) fRF = 315MHz (Note 6) fRF = 434MHz (Note 6) ENABLE or T/R transition low to high, transmitter frequency settled to within 50kHz of the desired carrier ENABLE or T/R transition low to high, transmitter frequency settled to within 5kHz of the desired carrier ENABLE transition low to high, or T/R transition high to low, receiver startup time (Note 5) RECEIVER Sensitivity Image Rejection POWER AMPLIFIER TA = +25C (Note 4) TA = +125C, PAVDD = AVDD = DVDD = HVIN = +2.1V (Note 2) TA = -40C, PAVDD = AVDD = DVDD = HVIN = +3.6V (Note 4) With output-matching network 4.6 3.9 10.0 6.7 13.1 82 -40 -50 15.8 dB dBc dBc 15.5 dBm 0.2% BER, 4kbps Manchester data rate, 280kHz IF BW, average RF power 315MHz 434MHz -114 dBm -113 46 dB 315/345/ 433.92 0 32 30 24 22 200 MHz dBm % % SYMBOL CONDITIONS MIN TYP MAX UNITS
Power-On Time
tON
350
s
250
Output Power
POUT
Modulation Depth Maximum Carrier Harmonics Reference Spur
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3
Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, 50 system impedance, PAVDD = AVDD = DVDD = HVIN = +2.1V to +3.6V, fRF = 315MHz, 345MHz, or 433.92MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at PAVDD = AVDD = DVDD = HVIN = +2.7V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER PHASE-LOCKED LOOP Transmit VCO Gain Transmit PLL Phase Noise Receive VCO Gain Receive PLL Phase Noise Loop Bandwidth Reference Frequency Input Level LOW-NOISE AMPLIFIER/MIXER (Note 8) LNA Input Impedance ZINLNA Normalized to 50 High-gain state Voltage-Conversion Gain Low-gain state Input-Referred, 3rd-Order Intercept Point Mixer-Output Impedance LO Signal Feedthrough to Antenna RSSI Input Impedance Operating Frequency 3dB Bandwidth Gain ANALOG BASEBAND Maximum Data-Filter Bandwidth Maximum Data-Slicer Bandwidth Maximum Peak-Detector Bandwidth Maximum Data Rate Manchester coded Nonreturn to zero (NRZ) 50 100 50 33 66 kHz kHz kHz kbps fIF 330 10.7 10 15 MHz MHz mV/dB IIP3 High-gain state Low-gain state fRF = 315MHz fRF = 434MHz fRF = 315MHz fRF = 434MHz fRF = 315MHz fRF = 434MHz 1 - j4.7 1- j3.3 50 45 13 9 -42 -6 330 -100 dBm dBm dB 10kHz offset, 500kHz loop BW 1MHz offset, 500kHz loop BW Transmit PLL Receive PLL SYMBOL KVCO 10kHz offset, 200kHz loop BW 1MHz offset, 200kHz loop BW CONDITIONS MIN TYP 340 -68 -98 340 -80 -90 200 500 0.5 MAX UNITS MHz/V dBc/Hz MHz/V dBc/Hz kHz VP-P
4
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Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, 50 system impedance, PAVDD = AVDD = DVDD = HVIN = +2.1V to +3.6V, fRF = 315MHz, 345MHz, or 433.92MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at PAVDD = AVDD = DVDD = HVIN = +2.7V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER CRYSTAL OSCILLATOR Crystal Frequency Maximum Crystal Inductance Frequency Pulling by VDD Crystal Load Capacitance (Note 7) fXTAL (fRF -10.7) / 24 50 2 4.5 MHz mH ppm/V pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX7030
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8:
Supply current, output power, and efficiency are greatly dependent on board layout and PAOUT match. 100% tested at TA = +125C. Guaranteed by design and characterization overtemperature. 50% duty cycle at 10kHz ASK data (Manchester coded). Guaranteed by design and characterization. Not production tested. Time for final signal detection; does not include baseband filter settling. Efficiency = POUT / (VDD x IDD). Dependent on PC board trace capacitance. Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 12nH inductive degeneration from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from the LNA source to ground. The equivalent input circuit is 50 in series with ~2.2pF. The voltage conversion is measured with the LNA input-matching inductor, the degeneration inductor, and the LNA/mixer tank in place, and does not include the IF filter insertion loss.
Typical Operating Characteristics
(Typical Operating Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25C, unless otherwise noted.)
RECEIVER
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX7030 toc01
SUPPLY CURRENT vs. RF FREQUENCY
MAX7030 toc02
DEEP-SLEEP CURRENT vs. TEMPERATURE
16 DEEP-SLEEP CURRENT (A) 14 12 10 8 6 4 2 0 VCC = +3.6V VCC = +3.0V VCC = +2.1V
MAX7030 toc03
7.0 6.8 SUPPLY CURRENT (mA) 6.6 6.4 6.2 6.0 -40C 5.8 5.6 2.1 2.4 2.7 3.0 3.3 +25C +85C +125C
6.8 6.7 SUPPLY CURRENT (mA) 6.6 6.5 +85C 6.4 6.3 6.2 6.1 6.0 -40C +25C +125C
18
3.6
300
325
350
375
400
425
450
-40
-15
-10
35
60
85
110
SUPPLY VOLTAGE (V)
RF FREQUENCY (MHz)
TEMPERATURE (C)
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5
Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030
Typical Operating Characteristics (continued)
(Typical Operating Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25C, unless otherwise noted.)
RECEIVER
BIT-ERROR RATE vs. AVERAGE INPUT POWER
MAX7030 toc04
SENSITIVITY vs. TEMPERATURE
MAX7030 toc05
RSSI vs. RF INPUT POWER
1.6 1.4 1.2 RSSI (V) 1.0 0.8 0.6 AGC SWITCH POINT LOW-GAIN MODE AGC HYSTERESIS: 3dB HIGH-GAIN MODE
MAX7030 toc06
100
-102 -105 SENSITIVITY (dBm) -108 -111 -114 fRF = 315MHz -117 fRF = 434MHz
1.8
BIT-ERROR RATE (%)
10 fRF = 434MHz 1 0.2% BER 0.1 fRF = 315MHz 0.01 -121 -119 -117 -115 -113 -111 AVERAGE INPUT POWER (dBm)
0.4 0.2
-120 -40 -15 10 35 60 85 110 TEMPERATURE (C)
0 -130 -110 -90 -70 -50 -30 -10 10 RF INPUT POWER (dBm)
RSSI AND DELTA vs. IF INPUT POWER
2.1 1.8 1.5 RSSI (V) 1.2 0.9 0.6 0.3 0 -90 -70 -50 -30 -10 10 IF INPUT POWER (dBm) DELTA RSSI
MAX7030 toc07
SYSTEM GAIN vs. IF FREQUENCY
MAX7030 toc08
IMAGE REJECTION vs. TEMPERATURE
fRF = 433MHz IMAGE REJECTION (dB)
MAX7030 toc09 MAX7030 toc12
3.5 2.5 1.5 0.5 -0.5 -1.5 -2.5 -3.5 DELTA (%) SYSTEM GAIN (dBm)
50 40 30 20 10 0 -10 -20 0 5 10 15 20 25 LOWER SIDEBAND 48dB IMAGE REJECTION FROM RFIN TO MIXOUT fRF = 434MHz UPPER SIDEBAND
48
46
fRF = 315MHz
44
42 30 -40 -15 10 35 60 85 110 IF FREQUENCY (MHz) TEMPERATURE (C)
NORMALIZED IF GAIN vs. IF FREQUENCY
MAX7030 toc10
S11 vs. RF FREQUENCY
MAX7030 toc11
S11 SMITH PLOT OF RFIN
0
0
NORMALIZED IF GAIN (dB)
-4
-6 S11 (dB) 433MHz -12 433.92MHz
-8
-12 -18
-16
400MHz
500MHz
-20 1 10 IF FREQUENCY (MHz) 100
-24 200 250 300 350 400 450 500 RF FREQUENCY (MHz)
6
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Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL
Typical Operating Characteristics (continued)
(Typical Operating Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25C, unless otherwise noted.)
MAX7030
RECEIVER
INPUT IMPEDANCE vs. INDUCTIVE DEGENERATION
90 fRF = 315MHz 80 REAL IMPEDANCE () 70 60 50 40 30 20 1 10 INDUCTIVE DEGENERATION (nH) 100 REAL IMPEDANCE IMAGINARY IMPEDANCE -230 IMAGINARY IMPEDANCE () REAL IMPEDANCE () -240 -250 -260 -270 -280 -290
MAX7030 toc13
INPUT IMPEDANCE vs. INDUCTIVE DEGENERATION
-220 90 80 70 60 50 40 30 20 1 10 INDUCTIVE DEGENERATION (nH) 100 REAL IMPEDANCE IMAGINARY IMPEDANCE
MAX7030 toc14
fRF = 434MHz
-150 -160 -170 -180 -190 -200 -210 -220 IMAGINARY IMPEDANCE ()
PHASE NOISE vs. OFFSET FREQUENCY
MAX7030 toc15
PHASE NOISE vs. OFFSET FREQUENCY
fRF = 433MHz
MAX7030 toc16
-50 -60 PHASE NOISE (dBc/Hz) -70 -80 -90 -100 -110 -120 100 1k 10k 100k
fRF = 315MHz
-50 -60 PHASE NOISE (dBc/Hz) -70 -80 -90 -100 -110 -120
1M
10M
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
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7
Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030
Typical Operating Characteristics (continued)
(Typical Operating Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25C, unless otherwise noted.)
TRANSMITTER
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX7030 toc17
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX7030 toc18
SUPPLY CURRENT vs. SUPPLY VOLTAGE
fRF = 434MHz PA ON WITHOUT ENVELOPE SHAPING TA = +85C 13 TA = +125C TA = -40C TA = +25C 11
MAX7030 toc19
16
fRF = 315MHz PA ON WITHOUT ENVELOPE SHAPING TA = +85C
6.0 5.5 SUPPLY CURRENT (mA) 5.0
fRF = 315MHz PA OFF
17
SUPPLY CURRENT (mA)
TA = +125C 4.5 4.0 3.5 3.0 2.5 TA = +25C TA = -40C TA = +85C
12
TA = +125C TA = -40C
10
TA = +25C
8 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
2.0 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
14
15
9 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX7030 toc20
SUPPLY CURRENT vs. OUTPUT POWER
MAX7030 toc21
SUPPLY CURRENT vs. OUTPUT POWER
13 SUPPLY CURRENT (mA) 12 11 10 9 8 7 6 5 50% DUTY CYCLE PA ON fRF = 434MHz PA ON ENVELOPE SHAPING ENABLED
MAX7030 toc22
6.0 5.5 SUPPLY CURRENT (mA) 5.0 4.5 4.0 3.5 3.0 2.1
fRF = 434MHz PA OFF TA = +125C TA = +85C
12 11 SUPPLY CURRENT (mA) 10 9
fRF = 315MHz PA ON ENVELOPE SHAPING ENABLED
14
PA ON 8 7 6
TA = +25C TA = -40C
5 4 3.3 3.6 -14 -10 -6 -2
50% DUTY CYCLE
2.4
2.7
3.0
2
6
10
-14
-10
-6
-2
2
6
10
SUPPLY VOLTAGE (V)
AVERAGE OUTPUT POWER (dBm)
AVERAGE OUTPUT POWER (dBm)
SUPPLY CURRENT AND OUTPUT POWER vs. EXTERNAL RESISTOR
18 16 SUPPLY CURRENT (mA) 14 12 10 8 6 4 2 0.1 fRF = 315MHz PA ON 1 10 100 1k 10k CURRENT POWER
MAX7030 toc23-1
SUPPLY CURRENT AND OUTPUT POWER vs. EXTERNAL RESISTOR
16 12 SUPPLY CURRENT (mA) OUTPUT POWER (dBm) 8 4 0 -4 -8 -12 -16 18 16 14 12 10 8 6 4 2 0.1 fRF = 433MHz PA ON 1 10 100 1k 10k CURRENT POWER
MAX7030 toc23-2
16 12 OUTPUT POWER (dBm) 8 4 0 -4 -8 -12 -16
EXTERNAL RESISTOR ()
EXTERNAL RESISTOR ()
8
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Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL
Typical Operating Characteristics (continued)
(Typical Operating Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25C, unless otherwise noted.)
MAX7030
TRANSMITTER
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX7030 24-1
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX7030 24-2
OUTPUT POWER vs. SUPPLY VOLTAGE
fRF = 434MHz PA ON ENVELOPE SHAPING DISABLED TA = -40C TA = +25C
MAX7030 25-1
14
12 OUTPUT POWER (dBm)
fRF = 315MHz PA ON ENVELOPE SHAPING DISABLED TA = -40C TA = +25C
14
12 OUTPUT POWER (dBm)
10
TA = +25C 10
OUTPUT POWER (dBm)
fRF = 315MHz PA ON ENVELOPE SHAPING ENABLED TA = -40C
14
12
10
8 TA = +85C
TA = +125C
8 TA = +125C 6 TA = +85C
8 TA = +125C 6 TA = +85C
6
4 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
4 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
4 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
OUTPUT POWER vs. SUPPLY VOLTAGE
fRF = 434MHz PA ON ENVELOPE SHAPING ENABLED TA = -40C TA = +25C 10
MAX7030 25-2
EFFICIENCY vs. SUPPLY VOLTAGE
MAX7030 toc26
EFFICIENCY vs. SUPPLY VOLTAGE
fRF = 434MHz PA ON
MAX7030 toc27
14
40
fRF = 315MHz PA ON
40
TA = -40C
TA = -40C
OUTPUT POWER (dBm)
12 EFFICIENCY (%)
35
TA = +25C EFFICIENCY (%) TA = +85C
35 TA = +25C 30 TA = +85C
30
8
TA = +125C TA = +85C
25
TA = +125C
25 TA = +125C 20
6 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
20 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
2.1
2.4
2.7
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
EFFICIENCY vs. SUPPLY VOLTAGE
MAX7030 toc28
EFFICIENCY vs. SUPPLY VOLTAGE
MAX7030 toc29
PHASE NOISE vs. OFFSET FREQUENCY
-50 -60 PHASE NOISE (dBc/Hz) -70 -80 -90 -100 -110 -120 -130 -140 3.6 100 1k 10k 100k 1M 10M fRF = 315MHz
MAX7030 toc30
30
fRF = 315MHz 50% DUTY CYCLE TA = -40C TA = +25C
30
fRF = 434MHz 50% DUTY CYCLE
-40
TA = -40C
25 EFFICIENCY (%)
EFFICIENCY (%)
25
TA = +25C
20 TA = +85C TA = +125C 15
20 TA = +85C TA = +125C
10 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
15 2.1 2.4 2.7 3.0 3.3 SUPPLY VOLTAGE (V)
OFFSET FREQUENCY (Hz)
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9
Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030
Typical Operating Characteristics (continued)
(Typical Operating Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25C, unless otherwise noted.)
TRANSMITTER
PHASE NOISE vs. OFFSET FREQUENCY
REFERENCE SPUR MAGNITUDE (dBc) -50 -60 PHASE NOISE (dBc/Hz) -70 -80 -90 -100 -110 -120 -130 -140 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (Hz) -70 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) fRF = 434MHz
MAX7030 toc31
REFERENCE SPUR MAGNITUDE vs. SUPPLY VOLTAGE
MAX7030 toc32
-40
-40 -45 -50 315MHz -55 -60 -65
434MHz
FREQUENCY STABILITY vs. SUPPLY VOLTAGE
8 FREQUENCY STABILITY (ppm) 6 4 2 0 -2 -4 -6 -8 -10 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) fRF = 315MHz fRF = 434MHz
MAX7030 toc33
10
10
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Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL
Pin Description
PIN 1 NAME PAVDD FUNCTION Power-Amplifier Supply Voltage. Bypass to GND with 0.01F and 220pF capacitors placed as close to the pin as possible. Envelope-Shaping Output. ROUT controls the power-amplifier envelope's rise and fall times. Connect ROUT to the PA pullup inductor or optional power-adjust resistor. Bypass the inductor to GND as close to the inductor as possible with 680pF and 220pF capacitors, as shown in the Typical Application Circuit. Transmit/Receive Switch Throw. Drive T/R high to short TX/RX1 to TX/RX2. Drive T/R low to disconnect TX/RX1 from TX/RX2. Functionally identical to TX/RX2. Transmit/Receive Switch Pole. Typically connected to ground. See the Typical Application Circuit. Power-Amplifier Output. Requires a pullup inductor to the supply voltage (or ROUT if envelope shaping is desired), which can be part of the output-matching network to an antenna. Analog Power-Supply Voltage. AVDD is connected to an on-chip +3.0V regulator in 5V operation. Bypass AVDD to GND with a 0.1F and 220pF capacitor placed as close to the pin as possible. Low-Noise Amplifier Input. Must be AC-coupled. Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set the LNA input impedance. Low-Noise Amplifier Output. Must be connected to AVDD through a parallel LC tank filter. AC-couple to MIXIN+. Noninverting Mixer Input. Must be AC-coupled to the LNA output. Inverting Mixer Input. Bypass to AVDD with a capacitor as close to the LNA LC tank filter as possible. 330 Mixer Output. Connect to the input of the 10.7MHz filter. Inverting 330 IF Limiter-Amplifier Input. Bypass to GND with a capacitor. Noninverting 330 IF Limiter-Amplifier Input. Connect to the output of the 10.7MHz IF filter. Minimum-Level Peak Detector for Demodulator Output Maximum-Level Peak Detector for Demodulator Output Inverting Data Slicer Input Noninverting Data Slicer Input Noninverting Op-Amp Input for the Sallen-Key Data Filter Data-Filter Feedback Node. Input for the feedback capacitor of the Sallen-Key data filter. No Connection. Do not connect to this pin. Transmit/Receive. Drive high to put the device in transmit mode. Drive low or leave unconnected to put the device in receive mode. It is internally pulled down. Enable. Drive high for normal operation. Drive low or leave unconnected to put the device into shutdown mode. Receiver Data Output/Transmitter Data Input Digital Power-Supply Voltage. Bypass to GND with a 0.01F and 220pF capacitor placed as close to the pin as possible. High-Voltage Supply Input. For 3V operation, connect HVIN to AVDD, DVDD, and PAVDD. For 5V operation, connect only HVIN to 5V. Bypass HVIN to GND with a 0.01F and 220pF capacitor placed as close to the pin as possible.
MAX7030
2
ROUT
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21, 25 22 23 24 26
TX/RX1 TX/RX2 PAOUT AVDD LNAIN LNASRC LNAOUT MIXIN+ MIXINMIXOUT IFINIFIN+ PDMIN PDMAX DSDS+ OP+ DF N.C. T/R ENABLE DATA DVDD
27
HVIN
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11
Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030
Pin Description (continued)
PIN 28 29 30 31 32 EP NAME AGC2 AGC1 AGC0 XTAL1 XTAL2 GND FUNCTION AGC Enable/Dwell Time Control 2 (MSB). See Table 1. Bypass to GND with a 10pF capacitor. AGC Enable/Dwell Time Control 1. See Table 1. Bypass to GND with a 10pF capacitor. AGC Enable/Dwell Time Control 0 (LSB). See Table 1. Bypass to GND with a 10pF capacitor. Crystal Input 1. Bypass to GND if XTAL2 is driven by an AC-coupled external reference. Crystal Input 2. XTAL2 can be driven from an external AC-coupled reference. Exposed Paddle. Solder evenly to the board's ground plane for proper operation.
Detailed Description
The MAX7030 315MHz, 345MHz, and 433.92MHz CMOS transceiver and a few external components provide a complete transmit and receive chain from the antenna to the digital data interface. This device is designed for transmitting and receiving ASK data. All transmit frequencies are generated by a fractional-Nbased synthesizer, allowing for very fine frequency steps in increments of fXTAL / 4096. The receive LO is generated by a traditional integer-N-based synthesizer. Depending on component selection, data rates as high as 33kbps (Manchester encoded) or 66kbps (NRZ encoded) can be achieved.
The LC tank filter connected to LNAOUT consists of L5 and C9 (see the Typical Application Circuit). Select L5 and C9 to resonate at the desired RF input frequency. The resonant frequency is given by: f= 1 2 L TOTAL x C TOTAL
Receiver
Low-Noise Amplifier (LNA) The LNA is a cascode amplifier with off-chip inductive degeneration that achieves approximately 30dB of voltage gain that is dependent on both the antenna-matching network at the LNA input and the LC tank network between the LNA output and the mixer inputs. The off-chip inductive degeneration is achieved by connecting an inductor from LNASRC to AGND. This inductor sets the real part of the input impedance at LNAIN, allowing for a more flexible match for low-input impedances such as a PC board trace antenna. A nominal value for this inductor with a 50 input impedance is 12nH at 315MHz and 10nH at 434MHz, but the inductance is affected by PC board trace length. LNASRC can be shorted to ground to increase sensitivity by approximately 1dB, but the input match must then be reoptimized.
where LTOTAL = L5 + LPARASITICS and CTOTAL = C9 + CPARASITICS. LPARASITICS and CPARASITICS include inductance and capacitance of the PC board traces, package pins, mixer-input impedance, LNA-output impedance, etc. These parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank filter center frequency. Lab experimentation should be done to optimize the center frequency of the tank. The total parasitic capacitance is generally between 5pF and 7pF. Automatic Gain Control (AGC) When the AGC is enabled, it monitors the RSSI output. When the RSSI output reaches 1.28V, which corresponds to an RF input level of approximately -55dBm, the AGC switches on the LNA gain-reduction attenuator. The attenuator reduces the LNA gain by 36dB, thereby reducing the RSSI output by about 540mV to 740mV. The LNA resumes high-gain mode when the RSSI output level drops back below 680mV (approximately -59dBm at the RF input) for a programmable interval called the AGC dwell time (see Table 1). The AGC has a hysteresis of approximately 4dB. With the AGC function, the RSSI dynamic range is increased, allowing the MAX7030 to reliably produce an ASK output for RF input levels up to 0dBm with a modulation depth of 18dB. AGC is not required and can be disabled (see Table 1).
12
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Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL
Table 1. AGC Dwell Time Settings for MAX7030
AGC2 0 0 0 0 1 1 1 1 AGC1 0 0 1 1 0 0 1 1 AGC0 0 1 0 1 0 1 0 1 K = 11 K = 13 K = 15 K = 17 K = 19 K = 21 K = 23 DESCRIPTION AGC disabled, high gain selected
For Manchester Code (50% duty cycle), set the dwell time to at least twice the bit period. For nonreturn-tozero (NRZ) data, set the dwell to greater than the period of the longest string of zeros or ones. For example, using Manchester Code at 315MHz (f XTAL = 12.679MHz) with a data rate of 2kbps (bit period = 250s), the dwell time needs to be greater than 500s: K 3.3 x log10 (500s x 12.679) 12.546 Choose the AGC pin settings for K to be the next oddinteger value higher than 12.546, which is 13. This says that AGC1 is set high and AGC0 and AGC2 are set low. Mixer A unique feature of the MAX7030 is the integrated image rejection of the mixer. This eliminates the need for a costly front-end SAW filter for many applications. The advantage of not using a SAW filter is increased sensitivity, simplified antenna matching, less board space, and lower cost. The mixer cell is a pair of double-balanced mixers that perform an IQ downconversion of the RF input to the 10.7MHz intermediate frequency (IF) with low-side injection (i.e., fLO = fRF - fIF). The image-rejection circuit then combines these signals to achieve a typical 46dB of image rejection over the full temperature range. Lowside injection is required as high-side injection is not possible due to the on-chip image rejection. The IF output is driven by a source follower, biased to create a driving impedance of 330 to interface with an off-chip 330 ceramic IF filter. The voltage-conversion gain driving a 330 load is approximately 20dB. Note that the MIXIN+ and MIXIN- inputs are functionally identical. Integer-N Phase-Locked Loop (PLL) The MAX7030 utilizes a fixed-integer-N PLL to generate the receive LO. All PLL components, including the loop filter, voltage-controlled oscillator, charge pump, asynchronous 24x divider, and phase-frequency detector are integrated internally. The loop bandwidth is approximately 500kHz. The relationship between RF, IF, and reference frequencies is given by: fREF = (fRF - fIF) / 24
MAX7030
AGC Dwell-Time Settings The AGC dwell timer holds the AGC in low-gain state for a set amount of time after the power level drops below the AGC switching threshold. After that set amount of time, if the power level is still below the AGC threshold, the LNA goes into high-gain state. This is important for ASK since the modulated data may have a high level above the threshold and low level below the threshold, which without the dwell timer would cause the AGC to switch on every bit. The MAX7030 uses the three AGC control pins (AGC0, AGC1, AGC2) to set seven user-controlled, dwell-timer settings. The AGC dwell time is dependent on the crystal frequency and the bit settings of the AGC control pins. To calculate the dwell time, use the following equation: Dwell Time = 2K fXTAL
where K is an odd integer in decimal from 11 to 23, determined by the control pin settings shown in Table 1. To calculate the value of K, use the following equation and use the next integer higher than the calculated result: K 3.3 x log10 (Dwell Time x fXTAL)
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13
Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL
Intermediate Frequency (IF) The IF section presents a differential 330 load to provide matching for the off-chip ceramic filter. The internal six AC-coupled limiting amplifiers produce an overall gain of approximately 65dB, with a bandpass filter type response centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately 10MHz. For ASK data, the RSSI circuit demodulates the IF to baseband by producing a DC output proportional to the log of the IF signal level with a slope of approximately 15mV/dB. Data Filter The data filter for the demodulated data is implemented as a 2nd-order, lowpass, Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. Set the corner frequency in kHz to approximately 3 times the fastest expected Manchester data rate in kbps from the transmitter (1.5 times the fastest expected NRZ data rate). Keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. The configuration shown in Figure 1 can create a Butterworth or Bessel response. The Butterworth filter offers a very-flat-amplitude response in the passband and a rolloff rate of 40dB/decade for the two-pole filter. The Bessel filter has a linear phase response, which works well for filtering digital data. To calculate the value of the capacitors, use the following equations, along with the coefficients in Table 2: b CF1 = a(100k)()(fc ) a CF2 = 4(100k)()(fc )
DS+
Data Slicer The data slicer takes the analog output of the data filter and converts it to a digital signal. This is achieved by using a comparator and comparing the analog input to a threshold voltage. The threshold voltage is set by the voltage on the DS- pin, which is connected to the negative input of the data slicer comparator. Numerous configurations can be used to generate the data-slicer threshold. For example, the circuit in Figure 2 shows a simple method using only one resistor and one capacitor. This configuration averages the analog output of the filter and sets the threshold to approximately 50% of that amplitude. With this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. The values of R and C affect how fast the threshold tracks the analog amplitude. Be sure to keep the corner frequency of the RC circuit much lower (about 10 times) than the lowest expected data rate. With this configuration, a long string of NRZ zeros or ones can cause the threshold to drift. This configuration works best if a coding scheme, such as Manchester coding, which has an equal number of zeros and ones, is used. Figure 3 shows a configuration that uses the positive and negative peak detectors to generate the threshold. This configuration sets the threshold to the midpoint between a high output and a low output of the data filter.
MAX7030
MAX7030
RSSI
100k
100k
OP+ CF2
DF CF1
where fC is the desired 3dB corner frequency. For example, choose a Butterworth filter response with a corner frequency of 5kHz:
Figure 1. Sallen-Key Lowpass Data Filter
CF1 =
1.000 450pF (1.414)(100k)(3.14)(5kHz) 1.414 CF2 = 225pF (4)(100k)(3.14)(5kHz)
Table 2. Coefficients to Calculate CF1 and CF2
FILTER TYPE Butterworth (Q = 0.707) Bessel (Q = 0.577) a 1.414 1.3617 b 1.000 0.618
Choosing standard capacitor values changes CF1 to 470pF and CF2 to 220pF. In the Typical Application Circuit, CF1 and CF2 are named C16 and C17, respectively.
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Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030
MAX7030
DATA SLICER
DATA SLICER PEAK DET PEAK DET
MAX7030
DATA
DSR C
DS+
DATA
PDMAX R C
PDMIN R C
Figure 2. Generating Data-Slicer Threshold Using a Lowpass Filter
Peak Detectors The maximum peak detector (PDMAX) and minimum peak detector (PDMIN), with resistors and capacitors shown in Figure 3, create DC output voltages equal to the high- and low-peak values of the filtered demodulated signal. The resistors provide a path for the capacitors to discharge, allowing the peak detectors to dynamically follow peak changes of the data filter output voltages. The maximum and minimum peak detectors can be used together to form a data slicer threshold voltage at a value midway between the maximum and minimum voltage levels of the data stream (see the Data Slicer section and Figure 3). Set the RC time constant of the peak detector combining network to at least 5 times the data period. If there is an event that causes a significant change in the magnitude of the baseband signal, such as an AGC gain-switch or a power-up transient, the peak detectors may "catch" a false level. If a false peak is detected, the slicing level is incorrect. The MAX7030 peak detectors correct these problems by temporarily tracking the incoming baseband filter voltage when an AGC state switch occurs, or forcing the peak detectors to track the baseband filter output voltage until all internal circuits are stable following an enable pin low-to-high transition and also T/R pin high-to-low transition. The peak detectors exhibit a fast attack/slow decay response. This feature allows for an extremely fast startup or AGC recovery.
Figure 3. Generating Data-Slicer Threshold Using the Peak Detectors
trace and a 50 antenna. The output-matching network for a 50 antenna is shown in the Typical Application Circuit. The output-matching network suppresses the carrier harmonics and transforms the antenna impedance to an optimal impedance at PAOUT (pin 5). The optimal impedance at PAOUT is 250. When the output-matching network is properly tuned, the PA transmits power with a high overall efficiency of up to 32%. The efficiency of the PA itself is more than 46%. The output power is set by an external resistor at PAOUT, and is also dependent on the external antenna and antenna-matching network at the PA output. Envelope Shaping The MAX7030 features an internal envelope-shaping resistor, which connects between the open-drain output of the PA and the power supply (see the Typical Application Circuit). The envelope-shaping resistor slows the turn-on/turn-off of the PA in ASK mode, and results in a smaller spectral width of the modulated PA output signal. Fractional-N Phase-Locked Loop (PLL) The MAX7030 utilizes a fully integrated, fractional-N, PLL for its transmit frequency synthesizer. All PLL components, including the loop filter, are integrated internally. The loop bandwidth is approximately 200kHz.
Power-Supply Connections
The MAX7030 can be powered from a 2.1V to 3.6V supply or a 4.5V to 5.5V supply. If a 4.5V to 5.5V supply is used, then the on-chip linear regulator reduces the 5V supply to the 3V needed to operate the chip. To operate the MAX7030 from a 3V supply, connect PAVDD, AVDD, DVDD, and HVIN to the 3V supply. When using a 5V supply, connect the supply to HVIN only and
15
Transmitter
Power Amplifier (PA) The PA of the MAX7030 is a high-efficiency, opendrain, class-C amplifier. The PA with proper outputmatching network can drive a wide range of antenna impedances, which includes a small-loop PC board
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Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030
connect AVDD, PAVDD, and DVDD together. In both cases, bypass DVDD, HVIN, and PAVDD to GND with 0.01F and 220pF capacitors and bypass AVDD to GND with 0.1F and 220pF capacitors. Bypass T/R, ENABLE, DATA, and AGC0-2 with 10pF capacitors to GND. Place all bypass capacitors as close to the respective pins as possible. In actuality, the oscillator pulls every crystal. The crystal's natural frequency is really below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. This pulling is already accounted for in the specification of the load capacitance. Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given by: fP = Cm 1 1 - x 106 C 2 CASE + CLOAD CCASE + CSPEC
Transmit/Receive Antenna Switch
The MAX7030 features an internal SPST RF switch that, when combined with a few external components, allows the transmit and receive pins to share a common antenna (see the Typical Application Circuit). In receive mode, the switch is open and the power amplifier is shut down, presenting a high impedance to minimize the loading of the LNA. In transmit mode, the switch closes to complete a resonant tank circuit at the PA output and forms an RF short at the input to the LNA. In this mode, the external passive components couple the output of the PA to the antenna and protect the LNA input from strong transmitted signals. The switch state is controlled by the T/R pin (pin 22). Drive T/R high to put the device in transmit mode; drive T/R low to put the device in receive mode.
where: fp is the amount the crystal frequency is pulled in ppm. Cm is the motional capacitance of the crystal. CCASE is the case capacitance. CSPEC is the specified load capacitance. CLOAD is the actual load capacitance. When the crystal is loaded as specified, i.e., CLOAD = CSPEC, the frequency pulling equals zero.
Crystal Oscillator (XTAL)
The XTAL oscillator in the MAX7030 is designed to present a capacitance of approximately 3pF between the XTAL1 and XTAL2 pins. In most cases, this corresponds to a 4.5pF load capacitance applied to the external crystal when typical PC board parasitics are added. It is very important to use a crystal with a load capacitance that is equal to the capacitance of the MAX7030 crystal oscillator plus PC board parasitics. If a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing an error in the reference frequency. Crystals designed to operate with higher differential load capacitance always pull the reference frequency higher.
ENABLE
Pin Configuration
TOP VIEW
DATA N.C. OP+ DS+ DST/R DF
24
N.C. DVDD HVIN AGC2 AGC1 AGC0 XTAL1 XTAL2
23
22
21
20
19
18
17 16 15 14 13
PDMAX PDMIN IFIN+ IFINMIXOUT MIXINMIXIN+ LNAOUT
25 26 27 28 29 30 31 32 1
PAVDD
MAX7030
12 11 10 9
2
ROUT
3
TX/RX1
4
TX/RX2
5
PAOUT
6
AVDD
7
LNAIN
8
LNASRC
THIN QFN
16
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Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030
Table 3. Component Values for Typical Application Circuit
COMPONENT C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 L1 L2 L3 L4 L5 L6 R1 R2 R3 Y1 Y2 VALUE FOR 433.92MHz RF 220pF 680pF 6.8pF 6.8pF 10pF 220pF 0.1F 100pF 1.8pF 100pF 220pF 100pF 1500pF 0.047F 0.047F 470pF 220pF 220pF 0.01F 100pF 100pF 220pF 0.01F 0.01F 22nH 22nH 22nH 10nH 16nH 68nH 100k 100k 0 17.63416MHz 10.7MHz ceramic filter VALUE FOR 315MHz RF 220pF 680pF 12pF 10pF 22pF 220pF 0.1F 100pF 2.7pF 100pF 220pF 100pF 1500pF 0.047F 0.047F 470pF 220pF 220pF 0.01F 100pF 100pF 220pF 0.01F 0.01F 27nH 30nH 30nH 12nH 30nH 100nH 100k 100k 0 12.67917MHz 10.7MHz ceramic filter DESCRIPTION 10% 10% 5% 5% 5% 10% 10% 5% 0.1pF 5% 10% 5% 10% 10% 10% 10% 10% 10% 10% 5% 5% 10% 10% 10% Coilcraft 0603CS Coilcraft 0603CS Coilcraft 0603CS Coilcraft 0603CS Murata LQW18A Coilcraft 0603CS 5% 5% -- Crystal, 4.5pF load capacitance Murata SFECV10.7 series
Note: Component values vary depending on PC board layout.
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Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030
Typical Application Circuit
AGC0 AGC1 VDD Y1 3.0V C23 VDD C18 C21 VDD 1 C24 C22 2 R3* T/R 3 C2 C1 L1 4 5 L2 C4 C3 C5 C7 C8 L3 C6 L6 DS+ 7 8 L4 LNAOUT MIXOUT LNAIN LNASRC MIXINPDMIN PDMAX MIXIN+ 18 VDD 6 AVDD EXPOSED PADDLE OP+ 19 C17 C16 TX/RX1 TX/RX2 ROUT PAVDD 32 XTAL2 31 XTAL1 C20 30 AGC0 29 AGC1 28 AGC2 27 HVIN 26 DVDD 25 N.C. 24 C19 AGC2
DATA
DATA
ENABLE
23
ENABLE TRANSMIT/ RECEIVE
22
MAX7030
N.C.
21
PAOUT
DF
20
IFIN-
IFIN+
DS-
17
9
10 C10 C9 L5
11 C12 VDD
12
13 C13
14
15
16
R1 C15
IN C11 *OPTIONAL POWER-ADJUST RESISTOR
GND Y2
OUT C14
R2
Chip Information
PROCESS: CMOS
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Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030
Functional Diagram
LNAOUT MIXIN+ MIXIN9 10 11
MIXOUT 12
IFIN+ 14
IFIN13
0 LNAIN 7 LNA
IF LIMITING AMPS
LNASRC 8 90 I Q RX FREQUENCY DIVIDER XTAL1 31 CRYSTAL OSCILLATOR XTAL2 32 CHARGE PUMP 16 PDMAX TX VCO HVIN 27 3.0V REGULATOR LOOP FILTER MODULATOR RX DATA AVDD 6 EXPOSED PADDLE 17 DSPHASE DETECTOR TX FREQUENCY DIVIDER 15 PDMIN RSSI 100k RX VCO 100k 19 OP+ 20 DF
DATA FILTER
18 DS+
MAX7030
PA
DIGITAL LOGIC
30 AGC0 29 AGC1 28 AGC2 24 DATA
2 ROUT
1 PAVDD
5 PAOUT
3 TX/RX1
4 TX/RX2
22 T/R
26 DVDD
23 ENABLE
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19
Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX7030
D2 D D/2 MARKING k L E/2 E2/2 E (NE-1) X e
C L C L
b D2/2
0.10 M C A B
XXXXX
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
e/2
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3 PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
H
1
2
COMMON DIMENSIONS
PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
EXPOSED PAD VARIATIONS PKG. CODES T1655-1 T1655-2 T1655N-1 T2055-2 T2055-3 T2055-4 T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1 T4055-1
D2
MIN. NOM. MAX. MIN.
E2
NOM. MAX.
L
0.15
A A1 A3 b D E e k L
DOWN BONDS ALLOWED
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.50 BSC. 0.40 BSC. 0.65 BSC. 0.50 BSC. 0.25 - 0.25 - 0.25 0.35 0.45 - 0.25 - 0.25 0.20 REF. 0.20 REF. 0.20 REF.
3.00 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.20
3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30
3.20 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40
** ** ** ** ** ** 0.40 ** ** ** ** ** ** ** 0.40 ** ** ** ** ** **
NO YES NO NO YES NO YES NO NO YES YES NO NO YES YES NO NO YES NO NO YES
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 - 0.30 0.40 0.50 16 20 28 32 N 40 ND 4 5 7 8 10 4 5 7 8 10 NE WHHB WHHC WHHD-1 WHHD-2 ----JEDEC L1
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3, AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", 0.05.
3.30 3.40 3.20
** SEE COMMON DIMENSIONS TABLE
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
H
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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