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Programmable Synchronous DC/DC Hysteretic Controller with VRM 9.0 VID Range
POWER MANAGEMENT Description
The SC1155 is a synchronous-buck switch-mode controller designed for use in single ended power supply applications where efficiency is the primary concern. The controller is a hysteretic type, with a user selectable hysteresis. The SC1155 is ideal for implementing DC/DC converters needed to power advanced microprocessors such as Pentium(R) llI and Athlon(R), in both single and multiple processor configurations. Inhibit, under-voltage lockout and soft-start functions are included for controlled power-up. SC1155 features include an integrated 5 bit D/A converter, temperature compensated voltage reference, current limit comparator, over-current protection, and an adaptive deadtime circuit to prevent shoot-through of the power MOSFET during switching transitions. Power good signaling, logic compatible shutdown, and over-voltage protection are also provided. The integrated D/A converter provides programmability of output voltage from 1.1V to 1.85V in 25mV increments. The SC1155 high side driver can be configured as either a ground-referenced or as a floating bootstrap driver. The high and low side MOSFET drivers have a peak current rating of 2 amps.
SC1155
PRELIMINARY
Features
u u u u u u
Programmable hysteresis 5 bit DAC programmable output (1.1V-1.85V) On-chip power good and OVP functions Designed to meet latest Intel specifications Up to 95% efficiency +1% tolerance over temperature
Applications
u u u u u
Server Systems and Workstations Pentium(R) III Core Supplies AMD Athlon(R) Core Supplies Multiple Microprocessor Supplies Voltage Regulator Modules
Typical Application Circuit
U1
SC1155CSW
1 R1 2k R3 2.7k 2 3 R2 1k C2 0.01 R4 1k C3 0.01 R5 100 C4 0.01 R6 20k C6 0.1 4 5 6 7 C5 0.001 8 C7 0.1 C8 0.01 +5V 9 10 11 12 13 14 IOUT DROOP OCP VHYST VREFB VSENSE AGND SOFTST N/C LODRV LOHIB DRVGND LOWDR DRV PWRGD VID0 VID1 VID2 VID3 VID4 INHIBIT IOUTLO LOSENSE HISENSE BOOTLO HIGHDR BOOT VIN12V 28 27 26 25 24 23 22 21 20 19 18 17 16 +12V 15 Q2 R12 IRL2203S 3.9 C9 2.2uF GND R7 150 C21-C26 150uF/4V C27 0.1 R11 2.2 C13 0.33 Q1 IRL3103S C12 0.33 GND C16 0.1 L1 1uH Vin C17-C19 150uF/16V C20 0.1 R10 10k INHIB R9 10k +5V PWRGD
Vin +5 to +12V
R8 10k
L2 1.5uH Vout
Vout = 1.1 to 1.85V
C8 2.2uF
Revision 1, December 2000
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SC1155
POWER MANAGEMENT Absolute Maximum Ratings
Parameter VIN12V BOOT to D RVGND BOOT to BOOTLO D i gi tal Inputs AGND to D RVGND LOHIB to AGND LOSENSE to AGND IOTLO to AGND HISENSE to AGND VSENSE to AGND C onti nuous Power D i ssi pati on, TA = 25 0C C onti nuous Power D i ssi pati on, TC = 25 0C Operati ng Juncti on Temperature Range Lead Temperature (Solderi ng) 10 Sec. Storage Temperature PD PD TJ TL TSTG Sy mbol VINMAX Maximum 14 25 15 -0.3 to +7.3 +0.5 14 14 14 14 5 1.2 6.25 0 to +125 300 -65 to 150
PRELIMINARY
U nits V V V V V V V V V V W W C C C
Electrical Characteristics
Unless specified: 0 < TJ < 125C, VIN = 12V
Parameter Supply Voltage Range Supply C urrent (Qui escent)
Sy mbol VIN12V IINq
C onditions
Min 11.4
Ty p 12 15
Max 13
U nits V
INH = 5V, VID not 11111, Vi n above UVLO threshold duri ng start-up, fsw = 200 kHz, BOOTLO = 0V, C D H = C D L = 50pF INH = OV or VID = 11111 or Vi n below UVLO threshold duri ng start-up, BOOT = 13V, BOOTLO = OV INH = 5V, VID not 11111, VIN above UVLO threshold duri ng start-up, I fsw = 200kHz, BOOT = 13V, BOOTLO = 0V, C D H = 50pF
Hi gh Si de D ri ver Supply C urrent (Qui escent)
IBOOTq
10
A
5
mA
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SC1155
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: 0 < TJ < 125C, VIN = 12V
PRELIMINARY
Parameter Reference/Voltage Identification Reference Voltage Accuracy
Sy mbols
Conditions
Min
Ty p
Max
Units
VREF
11.4V < VIN12V< 12.6V, over full VID range (see Output Voltage Table)
-1
1
%
VIDO - VID4 High Threshold Voltage VIDO - VID4 Low Threshold Voltage Power Good Undervoltage Threshold Output Saturation Voltage Hy steresis Over Voltage Protection OVP Trip Point Hy steresis Soft Start Charge Current
(1)
VTH(H) VTH(L)
2.25 1
V V
VTH(PWRGD) VSAT VHYS(PWRGD) IO = 5mA
90 0.5 10
95
%VREF V mV
VOVP VHYS(OVP)
38
42 10
46
%VOUT mV
ICHG
VSS = 0.5V, resistance from VREFB pin to AGND = 20kW, VREFB = 1.3V Note: ICHG = (IVREFB / 5) V(S/S) = 1V
10.4
13
15.6
A
Discharge Current Inhibit Comparator Start Threshold VIN 12V UVLO Start Threshold Hy steresis Hy steretic Comparator Input Offset Voltage Input Bias Current Hy steresis Accuracy Hy steresis Setting
Idischg
1
mA
Vstart(NH)
1
2.0
2.4
V
VstartUVLO Vhsy UVLO
9.25 1.8
10.25 2
11.25 2.2
V V
VosHYSCMP IbiasHYSCMP
VDROOP pin grounded
5 1 7 60
mV uA mV mV
VHYS ACC VHYS SET
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SC1155
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter D roop C ompensation Ini ti al Accuracy Ov ercurrent Protection OC P Tri p Poi nt Input Bi as C urrent H igh-Side VD S Sensing Gai n Ini ti al Accuracy IOUT Source IOUT Si nk C urrent Output Voltage Swi ng VIOUT
AC C
PRELIMINARY
C onditions Min Ty p Max U nits
Sy mbols
VDROOP ACC VDROOP = 50 mV
5
mV
VOCP Ibi asOCP
0.09
0.1
0.11 100
V nA
2 VHISENSE = 12V, VIOUTLO = 11.9V VIOUT = 0.5V, VHISENSE = 12V, VIOUTLO = 11.5V VIOUT =0.05V, VHISENSE = 12V, VIOUTLO = 12V VHISENSE = 11V, RIOUT = 10K0hm VHISENSE = 4.5V, RIOUT = 10k0hm VHISENSE = 3V, RIOUT = 10k0hm 500 40 0 0 0 2.85 1.8 50 65 80 50 3.75 2.0 1.0 6
V/V mV A A V V V V V W
IsourceIOUT Isi nkIOUT VIOUT(11) VIOUT(4.5) VIOUT(3)
LOSENSE Hi gh Level Input Voltage LOSENSE Low Level Input Voltage Sample/Hold Resi stance B uffered R eference VREFB Load Regulati on D eadtime C ircuit LOHIB Hi gh Level Voltage LOHIB Low Level Input Voltage LOWD R Hi gh Level Input Voltage LOWD R Low Level Input Voltage D riv e R egulator D RV Voltage Load Regulati on Short C i rcui t C urrent
Vi hLOISENSE VHISENSE = 4.5V (Note 1) Vi lLOISENSE RS/H VHISENSE = 4.5V (Note 1) 3.0V VHISENSE 12.6V
VldregREFB 10A < IREFB < 500A
2
mV
Vi hLOHIB Vi lLOHIB Vi hLOWDR Vi lLOWDR (Note 1) (Note 1)
2 1.0 2 1.0
V V V V
VDRV
11.4 < VIN12V < 12.6V, IDRV = 50mA
7 100 100
9
V mV mA
VldregDRV 1mA < 1DRV < 50mA IshortDRV
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SC1155
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter H igh-Side Output D riv er Peak Output C urrent IsrcHIGHDR Isi nkHIGHDR duty cycle < 2%, tpw < 100us, TJ = 1250C VBOOT - VBOOTLO = 6.5V, VHIGHDR = 1.5V (src), or VHIGHDR = 5V (si nk) (Note 1) Output Resi stance RsrcHIGHDR Rsi nkHIGHDR Low-Side Output D riv er Peak Outout C urrent IsrcLOWDR Isi nkLOWDR duty cycle < 2%, tpw < 100us, TJ = 1250C VDRV - VBOOTLO = 6.5V, VLOWDR = 1.5V (src), or VLOWDR = 5V (si nk) (Note 1) TJ = 1250C VDRV = 6.5V, VLOWDR = 6V TJ = 1250C VDRV = 6.5V, VLOWDR = 0.5V 2 TJ = 1250C VBOOT - VBOOTLO = 6.5V, VHIGHDR = 6V TJ = 1250C VBOOT - VBOOTLO = 6.5V, VHIGHDR = 0.05V 45 W 2 A Sy mbol C onditions Min Ty p
PRELIMINARY
Max U nits
5
Output Resi stance
RsrcLOWDR Rsi nkLOWDR
45 W 5
H y steretic C omparators Propagati on D elay Ti me from VSENSE to HIGHD R or LOWD R (excludi ng deadti me) Output D riv ers HIGHD R ri se/fall ti me
(1)
tHCPROP
10mV overdri ve, 1.3V Vref 3.5V
150
250
ns
trHIGHDR trHIGHDR trLOWDR tfLOWDR
(1)
C I = 9nF, VBOOT = 6.5v, VBOOTLO = grounded, TJ =125 0C C I = 9nF, VDRV = 6.5v, TJ =125 0C
60
ns
LOWD R ri se/fallti me Ov ercurrent Protection C omparator Propagati on D elay Ti me D egli tch Ti me (Includes comparator propagati on delay ti me)
60
ns
tOVPROP tOVDGL 2
1
s
5
s
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SC1155
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter H igh-Side Vds Sensing (1) Response Ti me tVDSRESP VHISENSE = 12V, VIOUTLO pulsed from 12V to 11.9V, 100ns ri se and fall ti mes VHISENSE = 4.5V, VIOUTLO pulsed from 4.5V to 4.4V, 100ns ri se and fall ti mes VHISENSE = 3V, VIOUTLO pulsed from 3.0v to 2.9V, 100ns ri se and fall ti mes Short C i rcui t Protecti on Ri si ng Edge D elay Sample/Hold swi tch turnon/turn-off D elay Power Good C omparator Propagati on D elay Softstart(1) C omparator Propagati on D elay D eadtime(2) D ri ver Nonoverlap Ti me LOD R V(1) Propagati on D elay TLODRVDLY 400 NS tNUL C LOWDR = 9nF, 10% threshold on LOWD R 30 100 ns tSLST overdri ve = 10mV 560 900 ns tPWRGD 1 s tVDSRED tSWXDLY LOSENSE grounded 3V < VHISENSE < 11V VLOSENSE + VHISENSE 300 30 500 100 ns ns 2 s Sy mbols C onditions Min Ty p
PRELIMINARY
Max U nits
3
s
Note: (1) Guaranteed, but not tested. (2) Test circuit and timing diagram (3) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC1155
POWER MANAGEMENT Test Circuit PRELIMINARY
Timing Diagram
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SC1155
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
D ev ice
(1)
PRELIMINARY
Temp R ange (TJ) 0 to 125C
P ackag e SO-28
SC 1155C SW.TR
Note: (1) Only available in tape and reel packaging. A reel contains 1000 devices.
(28-Pin SOIC)
Pin Descriptions
Pin # 1 Pin N ame IOUT D ROOP OC P VHYST VREFB VSENSE AGND SOFTST NC LOD RV LOHIB D RVGND LOWD R Pin Function C urrent Out. The output voltage on thi s pi n i s proporti onal to the load current as measured across the hi gh si de MOSFET, and i s approxi mately equal to 2 x RD S(ON) x ILOAD. D roop Voltage. Thi s pi n i s used to set the amount of output voltage set-poi nt droop as a functi on of load current. The voltage i s set by a resi stor di vi der between IOUT and AGND . Over C urrent Protecti on. Thi s pi n i s used to set the tri p poi nt for over current protecti on by a resi stor di vi der between IOUT and AGND . Hysteresi s Set Pi n. Thi s pi n i s used to set the amount of hysteresi s requi red by a resi stor di vi der between VREFB and AGND . Buffered Reference Voltage (from VID ci rcui try). Output Voltage Sense. Small Si gnal Analog and D i gi tal Ground. Soft Start. C onnecti ng a capaci tor from thi s pi n to AGND sets the ti me delay. Not connected. Low D ri ve C ontrol. C onnecti ng thi s pi n to +5V enables normal operati on. When LOHIB i s grounded, thi s pi n can be used to control LOWD R. Low Si de Inhi bi t. Thi s pi n i s used to eli mi nate shoot-thru current. Power Ground. Insure output capaci tor ground i s connected to thi s pi n. Low Si de D ri ver Output. C onnect to gate of low si de MOSFET.
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2 3 4 5 6 7 8 9 10 11 12 13
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SC1155
POWER MANAGEMENT Pin Descriptions (Cont.)
Pin # 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin N ame D RV VIN12V BOOT HIGHD R BOOTLO HISENSE LOSENSE IOUTLO INHIBIT VID 4 VID 3 VID 2 VID 1 VID 0
(1) (1) (1) (1) (1)
PRELIMINARY
Pin Function
D ri ve Regulator for the MOSFET D ri vers. 12V Supply. connect to 12V power rai l. Bootstrap. Thi s pi n i s used to generate a floati ng dri ve for the hi gh si de FET dri ver. Hi gh Si de D ri ver Output. C onnect to gate of hi gh si de MOSFET. Bootstrap Low. In desktop appli cati ons, thi s pi n connect to D RVGND . Hi gh C urrent Sense. C onnected to the drai n of the hi gh si de FET,or the i nput si de of a current sense resi stor between the i nput and the hi gh si de FET. Low C urrent Sense. C onnected to the source of the hi gh si de FET, or the FET si de of a current sense resi stor between the i nput and the hi gh si de FET. Thi s i s the sampli ng capaci tors bottom leg. Voltage on thi s pi n i s voltage on the LOSENSE pi n when the hi gh si de FET i s on. Inhi bi t. If thi s pi n i s grounded, the MOSFET dri vers are di sabled. Usually connected to +5V through a pull-up resi stor. Programmi ng Input (MSB) Programmi ng Input Programmi ng Input Programmi ng Input Programmi ng Input (LSB) Power Good. Thi s open collector logi c output i s hi gh i f the output voltage i s wi thi n 5% of the set poi nt.
PWRGD (1)
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POWER MANAGEMENT Block Diagram
PWRGD
IOUT
HISENSE IOUTLO
LOSENSE
SOFTST
++ --
50uA G=2 ANALOG BIAS PREREG I(VREFB) / 5 FAULT
BANDGAP RISING EDGE DELAY
Vcc
VIN12V DRIVE REGULATOR DRV
R + -
Q
-
+
S
SHUTDOWN 1.15VREF 0.93VREF
HIGHDR LOWDR
FILTER
0.93VREF
BOOT
DEGLITCH
UVLO
+ + +
10
VID DAC
INH
DEGLITCH
HIGHDR
-
+
-
+
BOOTLO
10V +
FILTER
Vcc VREF
+
1.15VREF
FILTER
+ + -
LOWDR
VSENSE
DRVGND 2V
-
-
+
VREF
+
11111
DECODE
100mV
OCP
AGND
INHIBIT
VID0 VID2 VID4 VID1 VID3
DROOP VSENSE
VHYST VREFB
LOHIB
LODRV
PRELIMINARY
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SC1155
SC1155
POWER MANAGEMENT Output Voltage Table
0 = VSS; 1 = OPEN
PRELIMINARY
V ID 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
V ID 3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
V ID 2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
V ID 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
V ID O 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0
VD C (V ) Output Off 1.1 1.125 1.15 1.175 1.2 1.225 1.250 1.275 1.3 1.325 1.35 1.375 1.4 1.425 1.45 1.475 1.5 1.525 1.55 1.575 1.6 1.625 1.65 1.675 1.7 1.725 1.75 1.775 1.8 1.825 1.85
NOTE: (1) If the VID bits are set to 11111, then the high-side and the low-side driver outputs will be set low, and the controller will be set to a low-Iq state.
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SC1155
POWER MANAGEMENT Applications Information - Functional Description
Reference/Voltage Identification The reference/voltage identification (VID) section consists of a temperature compensated bandgap reference and a 5-bit voltage selection network. The 5 VID pins are TTL compatable inputs to the VID selection network. They are internally pulled up to +5V generated from the +12V supply by a resistor divider, and provide programmability of output voltage from 2.0V to 3.5V in 100mV increments and 1.3V to 2.05V in 50mV increments. Refer to the Output Voltage Table for the VID code settings. The output voltage of the VID network, VREF is within 1% of the nominal setting over the full input and output voltage range and junction temperature range. The output of the reference/VID network is indirectly brought out through a buffer to the REFB pin. The voltage on this pin will be within 3mV of VREF. It is not recommended to drive loads with REFB other than setting the hysteresis of the hysteretic comparator, because the current drawn from REFB sets the charging current for the soft start capacitor. Refer to the soft start section for additional information. Hysteretic Comparator The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is set by connecting the center point of a resistor divider from REFB to AGND to the HYST pin. The hysteresis of the comparator will be equal to twice the voltage difference between REFB and HYST, and has a maximum value of 60mV. The maximum propagation delay from the comparator inputs to the driver outputs is 250ns. Low Side Driver The low side driver is designed to drive a low RDS(ON) Nchannel MOSFET, and is rated for 2 amps source and sink. The bias for the low side driver is provided internally from VDRV. High Side Driver The high side driver is designed to drive a low RDS(ON) Nchannel MOSFET, and is rated for 2 amps source and sink. It can be configured either as a ground referenced driver or as a floating bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from the DRV regulator. The internal bootstrap
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PRELIMINARY
diode, connected between the DRV and BOOT pins, is a Schottky for improved drive efficiency. The maximum voltage that can be applied between the BOOT pin and ground is 25V. The driver can be referenced to ground by connecting BOOTLO to PGND, and connecting +12V to the BOOT pin. Deadtime Control Deadtime control prevents shoot-through current from flowing through the main power FETs during switching transitions by actively controlling the turn-on times of the FET drivers. The high side driver is not allowed to turn on until the gate drive voltage to the low-side FET is below 2 volts, and the low side driver is not allowed to turn on until the voltage at the junction of the 2 FETs (VPHASE) is below 2 volts. An internal low-pass filter with an 11MHz pole is located between the output of the low-side driver (DL) and the input of the deadtime circuit that controls the high-side driver, to filter out noise that could appear on DL when the high-side driver turns on. Current Sensing Current sensing is achieved by sampling and holding the voltage across the high side FET while it is turned on. The sampling network consists of an internal 50W switch and an external 0.1F hold capacitor. Internal logic controls the turn-on and turn-off of the sample/hold switch such that the switch does not turn on until VPHASE transitions high and turns off when the input to the high side driver goes low. Thus sampling will occur only when the high side FET is conducting current. The voltage at the IO pin equals 2 times the sensed voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can be placed in series with the high side FET and the voltage across the sense resistor can be sampled by the current sensing circuit. Droop Compensation The droop compensation network reduces the load transient overshoot/undershoot at VOUT, relative to VREF. VOUT is programmed to a voltage greater than VREF (equal to VREF x (1+R7/R8)) by an external resistor divider from VOUT to the VSENSE pin to reduce the undershoot on VOUT during a low to high load current transient. The overshoot during a high to low load current transient is reduced by subtracting the voltage that is on
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SC1155
POWER MANAGEMENT Applications Information - Functional Description (Cont.)
the DROOP pin from VREF. The voltage on the IO pin is divided down with an external resistor divider, and connected to the DROOP pin. Thus, under loaded conditions, VOUT is regulated to Vout = Vref (1+R7/R8) IOUT R2/(R1+R2). Inhibit The inhibit pin is a TTL compatible digital pin that is used to enable the controller. When INH is low, the output drivers are low, the soft start capacitor is discharged, the soft start current source is disabled, and the controller is in a low IQ state. When INH goes high, the short across the soft start capacitor is removed, the soft start current source is enabled, and normal converter operation begins. When the system logic supply is connected to INH, it controls power sequencing by locking out controller operation until the system logic supply exceeds the input threshold voltage of the INH circuit; thus the +12V supply and the system logic supply (either +5V or 3.3V) must be above UVLO thresholds before the controller is allowed to start up. VIN The VIN undervoltage lockout circuit disables the controller while the +12V supply is below the 10V start threshold during power-up. While the controller is disabled, the output drivers will be low, the soft start capacitor will be shorted and the soft start current is disabled and the controller will be in a low IQ state. When VIN exceeds the start threshold, the short across the soft start capacitor is removed, the soft start current source is enabled and normal converter operation begins. There is a 2V hysteresis in the undervoltage lockout circuit for noise immunity. Soft Start The soft start circuit controls the rate at which VOUT powers up. A capacitor is connected between SS and AGND and is charged by an internal current source. The value of the current source is proportional to the reference voltage so the charging rate of CSS is also proportional to the reference voltage. By making the charging current proportional to VREF, the power-up time for VOUT will be independent of VREF. Thus, CSS can remain the same
PRELIMINARY
value for all VID settings. The soft start charging current is determined by the following equation: ISS = IREFB/5. Where IREFB is the current flowing out of the REFB pin. It is recommended that no additional loads be connected to REFB, other than the resistor divider for setting the hysteresis voltage. Thus these resistor values will determine the soft start charging current. The maximum current that can be sourced by REFB is 500A. Power Good The power good circuit monitors for an undervoltage condition on VOUT. If VSENSE is 7% (nominal) below VREF, then the power good pin is pulled low. The PWRGD pin is an open drain output. Overvoltage Protection The overvoltage protection circuit monitors VOUT for an overvoltage condition. If VSENSE is 15% above VREF, than a fault latch is set and both output drivers are turned off. The latch will remain set until VIN goes below the undervoltage lockout value. A 1ms deglitch timer is included for noise immunity. Overcurrent Protection The overcurrent protection circuit monitors the current through the high side FET. The overcurrent threshold is adjustable with an external resistor divider between IO and AGND, with the divider voltage connected to the OCP pin. If the voltage on the OCP pin exceeds 100mV, then a fault latch is set and the output drivers are turned off. The latch will remain set until VIN goes below the undervoltage lockout value. A 1ms deglitch timer is included for noise immunity. The OCP circuit is also designed to protect the high side FET against a short-toground fault on the terminal common to both power FETs (VPHASE). Drive Regulator The drive regulator provides drive voltage to the low side driver, and to the high side driver when the high side driver is configured as a floating driver. The minimum drive voltage is 7V. The minimum short circuit current is 100mA.
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POWER MANAGEMENT Application Circuit
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PRELIMINARY
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SC1155
SC1155
POWER MANAGEMENT Typical Characteristics
5V Efficiency
95% 93% 91% 89% Effiency 87% 85% 83% 81% 79% 77% 75% 0 2 4 6 8 10 12 14 16 18 20 Current, A 1.85Vout 1.50Vout 1.10Vout SC1155 Effiency, 5Vin
PRELIMINARY PRELIMINARY
5V Regulation
3% 2% 1% 0% -1% -2% -3% 0 2 4
SC1155 Voltage Regulation, 5Vin
Regulation
1.85Vout 1.50Vout 1.10Vout
6
8
10
12
14
16
18
20
Current, A
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SC1155
POWER MANAGEMENT Typical Characteristics
12V Efficiency
SC1155 Effiency, 12Vin 95% 93% 91% 89% Effiency 87% 85% 83% 81% 79% 77% 75% 0 2 4 6 8 10 12 14 16 18 20 Current, A 1.85Vout 1.50Vout 1.10Vout
PRELIMINARY
12V Regulation
3% 2% 1% 0% -1% -2% -3% 0 2 4
SC1155 Voltage Regulation, 12Vin
Regulation
1.85Vout 1.50Vout 1.10Vout
6
8
10
12
14
16
18
20
Current, A
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SC1155
POWER MANAGEMENT Evaluation Board Artwork PRELIMINARY
Top Layer
Bottom Layer
Top View
Bottom View
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SC1155
POWER MANAGEMENT Materials List
Quantity 1 6 3 7 2 6 2 1 1 1 1 1 2 1 2 1 1 1 1 3 1 1 1 R eference C5 C 1-C 4, C 8, C 11 C 17 - C 19 C 6, C 7, C 9, C 12, C 16, C 20, C 27 C 13, C 14 C 21- C 26 C 10, C 15 D1 L1 L2 Q1 Q2 RA, RB R1 R2, R4 R3 R5 R6 R7 R8, R9, R10 R11 R12 U1 Part/D escription 0.001F 0.01F 150, 16V (TPS) 0.1F 0.33F 470F, 6.3V (TPS) 2.2F, 16v MBRD 1035 1H, D O5022P-102 1.5H, D 05022P152HC IRL3103NS, D 2PAK IRL2203NS, D 2PAK 0W 2K 1K 2.7K 100 20K 150 10K 2.2 3.9 SC 1155, S0-28 SEMTEC H MOT C oi lcraft C oi lcraft Int. Rect. Int. Rect. AVX Vendor
PRELIMINARY
N otes
Layout Guidelines
1. Locate R8 and C5 close to pins 6 and 7.
2. Locate C6 close to pins 5 and 7. 3. Components connected to IOUT, DROOP, OCP, VHYST, VREFB, VSENSE, and SOFTST should be referenced to AGND. 4. The bypass capacitors C10 and C15 should be placed close to the IC and referenced to DRVGND. 5. Locate bootstrap capacitor C13 close to the IC. 6. Place bypass capacitor C14 close to Drain of the top FET and Source of the bottom FET to be effective. 7. Route HISENSE and LOSENSE close to each other to minimize induced differential mode noise. 8. Bypass a high frequency disturbance with ceramic capacitor at the point where HISENSE is connected to Vin.
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SC1155
POWER MANAGEMENT Layout Guidelines (Cont.)
9. Input bulk capacitors should placed as close as possible to the power FETs because of the very high ripple current flow in this pass. 10. If Schottky diode used in parallel with a synchronous (bottom) FET, to achieve a greater efficiency at lower Vout settings, it needs to be placed next to the aforementioned FET in very close proximity. 11. Since the feedback path relies on the accurate sampling of the output ripple voltage, the best results can be achieved
PRELIMINARY
by connecting the AGND to the ground side of the bulk output capacitors. 12. DRVGND pin should be tight to the main ground plane utilizing very low impedance connection, e.g., multiple vias. 13. In order to prevent substrate glitching, a small (0.5A) Schottky diode should be placed in close proximity to the chip with the cathode connected to BOOTLO and anode connected to DRVGND.
Outline Drawing - SO-28
Contact Information
Semtech Corporation Power Management Products Division 652 Mitchell Rd., Newbury Park, CA 91320 Phone: (805)498-2111 FAX (805)498-3804
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