To Download AP105-69 Datasheet File

gaas ic linear p o wer amplifier AP105-69 2 alpha industr ies , inc. [781] 935-5150 f ax [617] 824-4579 email sales@alphaind.com www .alphaind.com specifications subject to change without notice. 3/98a i n p u t p o w e r ( d b m ) p o u t , p . a . e . v s . p i n o u t p u t p o w e r ( d b m ) p o w e r a d d e d e f f i c i e n c y ( % ) 2 5 2 0 1 5 1 0 3 0 5 0 4 0 3 0 2 0 1 0 0 6 0 - 6 - 4 - 2 0 2 4 5 0 6 8 i n p u t p o w e r ( d b m ) d i s t o r t i o n . v s . p i n i m 3 , i m 5 , i m 7 ( d b c ) - 6 - 4 - 2 0 2 4 6 8 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i m 7 i m 5 i m 3 i n p u t p o w e r ( d b m ) p o u t , g a i n v s . p i n 3 0 2 5 3 0 2 5 2 0 1 5 1 0 2 0 1 5 1 0 5 0 3 5 - 6 - 4 - 2 0 2 4 6 8 o u t p u t p o w e r ( d b m ) g a i n ( d b ) o u t p u t p o w e r ( d b m ) b i a s c u r r e n t v s . p o u t b i a s c u r r e n t ( m a ) 3 4 3 2 3 0 2 8 2 6 2 4 2 2 2 0 1 8 1 6 1 4 1 2 1 0 8 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 typical performance data (824C849 mhz) characteristic condition frequenc y min. t yp. max. unit v oltage 5 6 7.5 v im3@ rated p out p out = 31 dbm pep -24 dbc im5@ rated p out p out = 31 dbm pep -34 dbc im7@ rated p out p out = 31 dbm pep -38 dbc har monic p o w er 2f o -30 dbc 3f o -45 modulation channel spacing = 30 khz, 832 channels , pi/4 qpsk p adj 30 khz -28 dbc 60 khz -49 90 khz -60 input impedance 50 w operating characteristics at 25c
gaas ic linear p o wer amplifier AP105-69 alpha industr ies , inc. [781] 935-5150 f ax [617] 824-4579 email sales@alphaind.com www .alphaind.com 3 specifications subject to change without notice. 3/98a standby mode the po w er amplifier should be tur ned off whene v er possib le in order to reduce the o v er all po w er consumption. the ap105 can be tur ned off in se v er al w a ys . the simplest is to s witch the bias controller supply v oltage (pin 1) open. this , in eff ect, s witches the gate v oltages to v ss . the bias current of the p a in this condition will drop to less than 1 ma. by adding pmos s witches to the dr ain lines bias- off currents on the order of a f e w a can be achie v ed. power amplifier typical configuration pin out assignments + 4 . 8 r _ a n a l o g r _ a n a l o g 2 k 7 5 0 1 1 2 2 u 2 u 1 c 1 1 n f l 1 5 . 6 n h + 5 . 8 1 n c 3 3 3 p f c 2 3 3 p f c 4 r 2 1 8 k r f _ i n p u t v r e f v g s 2 v d s 1 v g s 1 r f i n v d d v s s i n r f o u t / v d s 2 r f o u t / v d s 2 r f o u t / v d s 2 g n d g n d g n d c a c b v s s o u t v g e n g n d g n d g n d g n d g n d a p 1 0 5 l 3 1 . 5 n c 1 2 1 0 0 p l 2 6 . 8 n c 1 1 5 . 6 p 3 3 p f c 9 1 n c 1 0 + 5 . 8 c 8 3 . 3 p 1 0 0 n c 5 1 0 0 n c 7 1 0 0 n c 6 - 4 v _ e x t r f _ o u t p u t output matching circuit the output match f or the ap105 is pro vided e xter nally in order to impro v e perf or mance , reduce cost, and add fle xibility . by making use of cer amic surf ace mount components with better qs than gaas matching elements , a lo w er loss matching netw or k can be made . this lo w er loss results in higher po w er and efficiency f or the amplifier . also , b y k eeping these elements e xter nal the gaas die siz e is reduced and the o v er all cost is less . this approach also per mits the fle xibility to tw eak the amplifier f or optim um perf or mance at diff erent po w ers , and/or frequencies . the board schematic demonstr ates one w a y to present the optim um load match while pro viding a path f or the dc bias . bias controller circuit an on-chip bias controller circuit eliminates the need to individually adjust the gate bias v oltages . this circuit uses +4.8 v and the negativ e v oltage from the dc con v er ter (-3.5 v to -4.5 v) to set the gate v oltages on each stage f or the proper bias current. pin 1 can be used to adjust the bias current betw een a linear and a satur ated mode of oper ation. by s witching resistors betw een this pin and +4.8 v , diff erent quiescent currents can be selected. a current of 100-200 ma f or good linear ity in the digital mode , and a lo w er current, less than 100 ma, f or better po w er consumption in the analog mode is optim um. 2 8 2 7 2 6 2 5 2 4 1 9 1 8 1 7 1 6 1 5 1 2 3 4 5 1 0 1 1 1 2 1 3 1 4 d c / d c c o n v e r t e r b i a s c o n t r o l pin 1: v ref sets the quiescent bias current. nominally +3.5 v f or a bias of 120-200 ma with best gain and linear ity . lo w er v oltages in the r ange of +1 to +3.5 v will set the amplifier f or less quiescent bias current. this is useful f or analog or satur ated oper ation where linear ity is not cr itical. a resistor
gaas ic linear p o wer amplifier AP105-69 4 alpha industr ies , inc. [781] 935-5150 f ax [617] 824-4579 email sales@alphaind.com www .alphaind.com specifications subject to change without notice. 3/98a divider netw or k can be used with the +4.8 v regulated supply to achie v e the nominal v oltage . the input impedance of this pin is 2 k w . a s witch can be used to change the resistance and toggle the amp betw een digital and analog mode . pin 2: v gs2 second stage gate v oltage tap . should be b ypassed with a 1nf capacitor . this v alue is not cr itical. pin 3: v ds1 first stage dr ain bias f eed. requires a matching inductor with good rf b ypassing and the +5.8 v nominal supply v oltage . pin 4: v gs1 first stage gate v oltage . requires rf b ypassing and an 18k resistor to proper ly bias the first stage . pin 5: rf in 50 w rf input. pin 6-14: gnd connect to g round. pin 15: v gen supply v oltage to dc/dc con v er ter . requires +4.8 v with a 100 nf b ypassing capacitor . pin 16: v ss out negativ e output v oltage from the dc/dc con v er ter . a 100 nf capacitor is required. this v oltage should be supplied to the bias controller netw or k at pin 27. exter nal circuitr y (lcd displa y , dr iv er amplifiers , etc.) can tap off the negativ e v oltage at this point. maxim um current 2 ma. pin 17: cb switched capacitor f or dc/dc con v er ter . 100 nf capacitor should be connected betw een pin 17 and pin 18 with minimal distance betw een the capacitor and the chip . pin 18: ca switch capacitor f or dc/dc con v er ter , shared with pin 17. pin 19-23: gnd connect to g round. pin 24-26: rf out/v ds2 rf output and bias f eed f or the second stage dr ain. output matching circuitr y is required to tr ansf or m the optim um load impedance to 50 w . the circuit m ust also pro vide a path f or the +5.8 v nominal dc bias and ha v e good rf b ypassing. pin 27: v ss in negativ e v oltage f or the bias controller circuit. the negativ e v oltage from the dc/dc con v er ter (pin 16) should be f ed to this pin. characteristics symbol v alue units dr ain v oltage v dd 10 v bias v oltage v ss -6 v ref erence v oltage v ref 6 v p o w er input p in 12 dbm oper ating t emper ature t opt -30 to 100 c stor age t emper ature t stg -35 to 120 c absolute maximum ratings t erminal symbol function 1 v ref ref erence v oltage 2 v gs2 gate v oltage 2 3 v ds1 supply v oltage 1 4 v gs1 gate v oltage 1 5 rf in rf input 6 gnd ground 7 gnd ground 8 gnd ground 9 gnd ground 10 gnd ground 11 gnd ground 12 gnd ground 13 gnd ground 14 v ngnd v oltage gener ator ground 15 v gen gener ator v oltage 16 v ss out bias v oltage out 17 cb gener ator flying cap 18 ca gener ator flying cap 19 gnd ground 20 gnd ground 21 gnd ground 22 gnd ground 23 gnd ground 24 rf out/v ds2 rf output/supply v oltage 2 25 rf out/v ds2 rf output/supply v oltage 2 26 rf out/v ds2 rf output/supply v oltage 2 27 v ss in negativ e bias v oltage input 28 v dd p ositiv e bias v oltage input pin configuration pin 28: v dd bias controller supply v oltage . the regulated 4.8 v supply m ust be connected to this pin. disconnecting this v oltage will tur n the p a bias off . a s witch at this pin can tur n the p a on or off while lea ving v gen connected and the negativ e supply unchanged.

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