overview the l64754 is a satellite receiver demodulator designed specifically to meet the needs of japanese satellite broadcast digital tv. providing maximum INTEGRAtion and flexibility for system designers at a minimum cost, the l64754 chip reduces the number of external components required to build a system. lsi logic fabricates the l64754 using its g12, 1.8 core/3.3 volt i/o, 0. i 8- micron, hcmos process technology. the l64754 demodulator interfaces with any tuner ic, which directly down- converts satellite signal from l-band to baseband, and includes an on-chip synthesizer controller. the l64754 generates control signals for a tuner ic synthesizer (using frequency information programmed into the l64754 configuration registers), and generates dual agc control voltages for the two-stage automatic gain control on a tuner ic chip. the l64754 satellite demodulator contains two main blocks: a bpsk/qpsk/8psk demodulator and a concatenated fec decoder. the b/q/8psk demodulator performs demodulation for any of the three modulation formats, a method of extracting a digital signal from a phase-modulated analog signal. the b/q/8psk module is designed specifically for a satellite broadcast digital tv receiver, and is compliant with the japanese isdb-s standard. the demodulator works as per the european digital video broadcast (dvb-s) standard and the technical specifications for dss systems. INTEGRA tm l64754 isdb-s dvb/dss satellite receiver INTEGRA? l64754 block diagram to tuner ic? agc control carrier loop control timimg loop control matched filter output control linear eq. dual adc interpolator /decimation filter external microcontroller data and address bus synthesizer control lowpass filter control microcontroller data and address bus microcontroller data and address bus b/q/8psk demodulator fec decoder pipeline channel output (mpeg-2) transport stream) n/t " to tuner ic to tuner ic channel imput from tuner ic i q clk (from l64754 onchip pll) out, interface reed solomon decoder block deinterleaver and frame data descrambler tmcc descrambler pragmatic tcm decoder tmcc control demi demq 1/t the communications company tm features ? on-chip dual differential 6-bit a/d converters variable data rate of 1 to 45 mbaud serial host interface compatible with the lsi logic serial control bus interface correction for quadrature phase, amplitude imbalance INTEGRAted pll for clock synthesis for use of fundamental mode crystal fast channel-switching mode anti-aliasing filters on-chip digital clock synchronization programmable matched filter synthesizer control-programmable counters power estimation for agc control-dual agc outputs to allow two-stage agc on-chip c/n, ber estimators bit-error monitoring for channel performance measurements for all possible isdb-s/dvb/dss rates on-chip block de-interleaver power-down and standby modes on-chip controller frees host processor
for more information please call: lsi logic corporation north american headquarters milpitas, ca tel: 866 574 5741 lsi logic europe ltd. european headquarters united kingdom tel: 44 1344 426544 fax: 44 1344 481039 lsi logic kk headquarters tokyo, japan tel: 81 3 5463 7165 fax 81 3 5463 7820 lsi: logic web site: www.lsilogic.com lsi logic logo design, the communications company and INTEGRA are either registered trade- marks or trademarks of lsi logic corporation. all other brand and product names may be trade- marks of their respective companies. lsi logic corporation reserves the right to make changes to any products and services herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase, lease, or use of a product or service from lsi logic con- vey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or of third parties. copyright ?2001 by lsi logic corporation. all rights reserved. order no. i20096 1201.1k.jg.ik - printed in usa the communications company tm INTEGRA ? l64754 isdb-s, dvb/dss satellite receiver the forward error correction (fec) decoder pipeline is a complete fec concatenated decoder utilizing a tcm inner code in isdb-s mode and viterbi inner code in dvb/dss mode with reed-solomon outer code. the fec decoding pipeline contains necessary synchronizations-de-interleaving and scrambling functions-for a complete decoding solution. isdb-s mode: b/q/8psk demodulation for 28.86 mbaud tmcc based synchronization frame synchronization with input frequency error of less than +/- 720khz for fast carrier acquisition programmable frame and super frame synchronization, enabling fast and reliable frame acquisition on-chip digital carrier synchronization featuring afc for coarse acquisition and frequency sweep for fine acquisition pragmatic tcm decoder module for rates 1/2, 2/3, 3/4, 5/6, and 7/8 (204/188), (64/48) reed-solomon decoder mask control option for choice of transmission layers (i.e., supports ? graceful degradation ? , under severe environmental conditions) on-chip transport stream divider allowing user selection of one-of-eight (or all) interleaved ts streams output pcr jitter less than ioons dvb/dss mode supports: dvb and dss system specifications synchronous parallel interface protocol for fec data output reference design board to accelerate development of set-top box solutions, the l64754 is available with a developer ? s kit that allows manufacturers to select the best option for their target market and application requirements. the kit provides the hard- ware and software components to shorten development cycles and to ensure fast time-to-market. the reference design board consists of a complete evaluation board with a pc interface and mpeg-2 transport output. software to enable system resting and code optimization is included, along with a manual that provides test and evaluation information and pc board layout. complete micro code for the l64754 ? s micro controller is included, with the option of customizing the micro code.
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