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ps3210b-1299 the data coding leader advanced hardware architectures tm advanced hardware architectures, inc. 2365 ne hopkins court pullman, wa 99163-5601 509.334.1000 fax: 509.334.9000 e-mail: sales@aha.com http://www.aha.com product specification AHA3210B 10 mbytes/sec dclz data compression coprocessor ic
advanced hardware architectures, inc. ps3210b-1299 i table of contents 1.0 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 port a and b port data bus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1.1 dual data bus mode: in-line application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1.2 single data bus mode: look-aside application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2.1.3 port a peripheral chip interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 data processing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2.1 compression mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2.2 compression flush mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.3 decompression mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2.4 decompression output disabled mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.5 pass through a to b mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.6 pass through b to a mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.0 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 dclz control: address 00 hex - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 dclz status: address 01 hex - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 comp ratio optimization: address 02 hex - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 dma configuration: address 03 hex - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 port a control 0: address 04 hex - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 port a control 1: address 05 hex - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7 port a status: address 06 hex - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.8 port a byte count: address 07,08,09 hex - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.9 port b control 0: address 0a hex - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.10 port b control 1: address 0b hex - read/write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11 port b status: address 0c hex - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 port b byte count: address 0d,0e,0f hex - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.13 port b byte comparator: address 10,11,12 hex - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.14 record length: address 13,14,15 hex - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15 record count: address 16,17,18 hex - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 interrupt status: address 19 hex - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.17 interrupt clear: address 19 hex - write only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.18 interrupt disable: address 1a hex - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.19 identification: address 1f hex - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.0 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 port a interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3 port b interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.0 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.0 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2.1 dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2.2 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2.3 pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.0 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
advanced hardware architectures, inc. ii ps3210b-1299 8.0 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.0 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1 available parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.0 aha related technical publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
advanced hardware architectures, inc. ps3210b-1299 iii figures figure 1: functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 2: dual data bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 3: single data bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 4: port a peripheral chip interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 5: compression mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 6: compression flush mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 7: decompression mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 8: decompression output disabled mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 9: pass through a to b mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 10: pass through b to a mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 11: pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 12: dynamic current - idd vs. compression ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 13: clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 14: reset timing - power up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 15: reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 16: processor read cycle - dsn, rwn controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 17: processor write cycle - dsn, rwn controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 18: processor read cycle - iordn controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 19: processor write cycle - iowrn controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 20: processor read cycle from port a peripheral - dsn, rwn controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 21: processor write cycle to port a peripheral - dsn, rwn controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 22: processor read cycle from port a peripheral - iordn controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 23: processor write cycle to port a peripheral - iowrn controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 24: dma slave transfer timing for data into port a,b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 25: dma slave transfer timing for data out of port a,b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 26: dma master transfer timing for data into port a,b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 27: dma master transfer timing for data out of port a,b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 28: AHA3210B package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
advanced hardware architectures, inc. iv ps3210b-1299 tables table 1: data bus modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 2: register address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3: dclz mode bit decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4: supported modes for dclz control register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5: data bus mode bit decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6: port a dma bus master/slave pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7: port b dma bus master/slave pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8: clock timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 9: reset timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10: processor read cycle timings - dsn, rwn controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 11: processor write cycle timings - dsn, rwn controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 12: processor read cycle timings - iordn controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 13: processor write cycle timings - iowrn controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 14: processor read cycle timings from port a peripheral - dsn, rwn controlled . . . . . . . . . . . . . . . . . . . 36 table 15: processor write cycle to port a peripheral timings - dsn, rwn controlled. . . . . . . . . . . . . . . . . . . . . . 37 table 16: processor read cycle from port a peripheral timings - iordn controlled . . . . . . . . . . . . . . . . . . . . . . . 38 table 17: processor write cycle to port a peripheral timings - iowrn controlled. . . . . . . . . . . . . . . . . . . . . . . . . 39 table 18: dma slave transfer timing for data into port a,b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 19: dma slave transfer timing for data out of port a,b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 20: dma master transfer timing for data into port a,b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 21: dma master transfer timing for data out of port a,b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
ps3210b-1299 page 1 of 45 advanced hardware architectures, inc. 1.0 introduction the AHA3210B is a single-chip cmos lossless compression and decompression integrated circuit under development implementing the industry standard data compression lempel ziv (dclz) adaptive compression algorithm. the device processes data in compression, decompression or pass-through modes. the AHA3210B is based on the earlier 10 mbytes/sec introduction, aha3210. it maintains the same pinout, performance, flexibility and i/o interface as aha3210. content addressable memory within the dclz engine eliminates external srams typically required for dictionary storage in a compression system. other supporting system features include two 24-bit counters, automatic multiple-record transfer, compression ratio optimization and dclz error detection logic. the dclz algorithm is approved by several standards organizations including qic, dat, ansi, iso and ecma. dclz has been accepted by hewlett-packard and other system companies worldwide as their standard of choice in their tape storage peripherals. the algorithm exhibits an average compression ratio of 2 to 1 over typical computer data. this specification contains a functional overview, operation modes, register descriptions, dc and ac electrical characteristics, ordering information and related technical publications. it is intended for hardware and software engineers designing a compression system using AHA3210B. aha designs and develops lossless compression, forward error correction and data storage formatter/controller ics. technical publications are available upon request from us or our sales representatives/agents worldwide. 1.1 features performance: ? 10 mbytes/sec data compression, decompression or pass-through rate with a 20 mhz clock ? 2 to 1 average compression ratio ? high compression of small records ? automatic multiple-record transfers without microprocessor intervention ? dynamic compression ratio monitoring ? error checking in decompression mode reportable via an interrupt flexibility: ? in-line and look-aside architectures supported ? polled or interrupt driven i/o ? two independent dma ports programmable for 8 or 16-bit transfers; master or slave mode system interface: ? single chip data compression solution ? no sram required ? programmable interrupts ? interfaces directly with ahas tape format controller, aha5140, and industry standard scsi controllers others: ? open standard dclz adaptive lossless compression algorithm ? standards include: qic dds/dat, ansi, iso and ecma ? low power stand-by operation ? eiaj-standard 100 pin plastic quad flat package ? software emulation of the algorithm available 1.2 applications ? dds-dat, qic, 8mm or dlt tape drives ? high performance laser printers 1.3 functional overview the AHA3210B data compression coprocessor ic is a high performance, single chip data compression solution, for use in tape drives, disk drives and embedded controller applications. the processor interface is used to transfer data to the registers inside the chip. the procmode strapping pin selects between a motorola and an intel style processor interface. the dclz engine implements the dclz lossless data compression algorithm. it contains a compressor, which inputs uncompressed data from the port a interface, compresses it, and sends the compressed codes to the port b interface. the dclz engine also contains a decompressor, which inputs compressed codes from the port b interface, decompresses it, and sends the uncompressed data to the port a interface. the record length register and record count register allow uncompressed data to be partitioned into fixed sized blocks, and then compressed and decompressed automatically.
page 2 of 45 ps3210b-1299 advanced hardware architectures, inc. figure 1: functional block diagram the pass through controller block allows data to be transferred between port a and port b without being compressed or decompressed. port a and port b are two independent dma interfaces. for compression and decompression operations, port a transfers uncompressed data and port b transfers compressed codes. each port has a byte counter, which counts the number of bytes that are transferred through the port. the configuration of the dma interface on each port is programmable. these functions include dma master or slave, eight or sixteen bit transfers, and control pin enabling and polarity. the port b byte count register has a port b byte comparator register, allowing the chip to interrupt after a programmed amount of data has been transferred on the port b data bus, db[15:0]. register accesses to a peripheral chip connected to port a are also supported. 2.0 modes of operation there are two classes of the modes of operation for this chip. the first class is determined by the port a and port b dma data bus configurations. port a and port b can be dual independent data buses, or port a and port b can be connected to create a single data bus. the second class is determined by the method data is processed through the chip in compression, decompression or pass through modes. 2.1 port a and b port data bus configuration port a and port b data bus configuration is controlled by the data bus mode[2:0] bits in the dma configuration register. these bits control the single and dual data bus modes, as well as port a and port b being the dma bus master or slave (see table 1). port a byte counter port b byte counter port a dma state machine port a fifo port b dma state machine port b fifo single data bus arbiter record count register record length register processor interface state machine pass through controller interrupt logic processor interface dclz engine port a interface port b interface acsn dreqa dacka aoe awe dapty[1:0] da[15:0] a[4:0] portacsn csn rwn/iowrn dsn/iordn procmode tristaten test restn clk dtackn/ready d[7:0] intn/int dreqb dackb boe bwe dbpty[1:0] db[15:0] (8 bytes) (8 bytes) AHA3210B compression chip
ps3210b-1299 page 3 of 45 advanced hardware architectures, inc. table 1: data bus modes 2.1.1 dual data bus mode: in-line application in dual data bus mode, port a and port b transfer data on unique, independent data buses. this is used for in-line applications, when data is transferred from the host interface, through the data compression coprocessor, and into the system buffer (see figure 2). in dual data bus mode, the data rate during compression is sustained at 10 mb/sec, except when the compression ratio is less than 1 (which occurs briefly when a compression dictionary is first being built, or when data is actually expanding). the data rate during decompression, pass through a to b, and pass through b to a modes is sustained at 10 mbytes/sec (see figure 3). 2.1.2 single data bus mode: look-aside application in single data bus mode, port a and port b transfer data on a common data bus. this connection is made external to the chip, on the pc board. this is used in a look aside application, when the data compression coprocessor transfers data into and out of the system buffer. figure 2: dual data bus mode figure 3: single data bus mode data bus mode[2] data bus mode[1] data bus mode[0] function 0 0 0 dual data bus: port b slave, port a slave 0 0 1 dual data bus: port b slave, port a master 0 1 0 dual data bus: port b master, port a slave 0 1 1 dual data bus: port b master, port a master 1 0 0 dual data bus: port b slave, port a slave with peripheral access 101reserved 1 1 0 dual data bus: port b master, port a slave with peripheral access 1 1 1 single data bus: port b master, port a master host interface bus interface processor interface system tape drive bus controller buffer interface port a interface single data bus arbiter dclz engine port b interface host interface bus interface processor interface system tape drive bus controller buffer interface port a interface single data bus arbiter dclz engine port b interface
page 4 of 45 ps3210b-1299 advanced hardware architectures, inc. 2.1.3 port a peripheral chip interface a peripheral chip can be connected to port a, and have its registers accessed through the processor interface of the data compression chip (see figure 4). this is used in in-line applications, for peripheral chips with a common dma and processor data bus (such as the ncr 53c90a/b and the ncr 53c94/5/6 scsi controllers). it is the firmware's responsibility to ensure accesses to the peripheral chip's registers do not occur while dma transfers are occurring on port a. this mode is only supported when port a is a dma slave, in dual data bus mode. 2.2 data processing modes the data processing modes are controlled by the dclz mode[2:0] bits in the dclz control register. 2.2.1 compression mode during compression mode, uncompressed data flows into port a. it is then compressed by the dclz engine. the resulting compressed data is then transferred out of port b (see figure 5). the uncompressed data is partitioned into fixed sized records. the size is stored in the record length register inside the chip. after a record has been compressed, an end of record codeword is inserted into the compressed data. the end of record codewords are then used during decompression, to control data flow. multiple records can be compressed without processor intervention. the record count register inside the chip stores the number of records to compress. a compression sequence has been completed after the last byte of the last record has been compressed and transferred out of port b. this event sets the port b end of transfer interrupt. compression ratio is defined as the number of uncompressed bytes divided by the number of compressed bytes. the port a byte counter counts the number of uncompressed bytes. the port b byte counter counts the number of compressed bytes. the compression ratio can also be automatically controlled, by programming the comp ratio optimization register. the following sequence is used to program the chip to compress multiple, fixed size records: - program record length register - program record count register - program interrupt disable register - enable port b end of transfer interrupt - program comp ratio optimization register - program dclz control register dclz mode[2:0] compression comp ratio opt enable 1 reset dict after eor 0 reset dict 0 pause after eor 0 pause 0 - the port b end of transfer interrupt signals compression completed figure 4: port a peripheral chip interface processor interface dclz engine port b cs/ dreq dack/ dbwr/ rd/ dbp[1:0] db[15:0] dreqb dackb boe bwe dbpty[1:0] db[15:0] interface acsn dreqa dacka aoe awe dapty[1:0] da[15:0] wr/ a[3:0] port a interface peripheral a[4:0] portacsn csn rwn/iowrn dsn/iordn procmode tristaten test resetn clk dtackn/ready d[7:0] intn/int chip AHA3210B compression chip
ps3210b-1299 page 5 of 45 advanced hardware architectures, inc. figure 5: compression mode 2.2.2 compression flush mode normal compression operations complete when the record length register and the record count register both decrement to zero. all data in the chip is then compressed, and transferred out of port b. there is no data in the chip, and the chip is said to be flushed (see figure 6). consider the scenario when a compression operation is required to complete prematurely (i.e., before the record length register and the record count register have both decremented to zero). in this scenario, port a dma is inactive, because there is no more uncompressed data to transfer into the chip. due to the dclz data compression algorithm, there may be partially compressed data in the dclz engine at this time. compression flush mode is used to complete the compression operation, transfer all compressed data out of port b, and get the chip into the flushed state. note that the compression flush operation inserts an end of record code word at the appropriate location, near the end of the compressed data stream. the chip should only be programmed into compression flush mode when the port a interface is empty (i.e., when the port interface byte count in the port a status register is zero) and the dclz engine contains data (i.e., when the dclz engine flushed bit in the dclz status register is zero) and the dclz engine is not already in the process of flushing (i.e., the dclz eor count bit in the dclz status register is zero). port a byte counter port b byte counter port a dma state machine port a fifo port b dma state machine port b fifo single data bus arbiter record count register record length register processor interface state machine pass through controller interrupt logic processor interface dclz engine port a interface port b interface acsn dreqa dacka aoe awe dapty[1:0] da[15:0] a[4:0] portacsn csn rwn/iowrn dsn/iordn procmode tristaten test restn clk dtackn/ready d[7:0] intn/int dreqb dackb boe bwe dbpty[1:0] db[15:0] (8 bytes) (8 bytes) AHA3210B compression chip
page 6 of 45 ps3210b-1299 advanced hardware architectures, inc. the following sequence is used to program the chip for compression flush mode for the scenario described above: - program dclz control register dclz mode[2:0] compression comp ratio opt enable 1 reset dict after eor 0 reset dict 0 pause after eor 0 pau s e 1 - wait until the paused bit in the dclz status register is set - program record count register to 000000 hex - program interrupt disable register - enable port b end of transfer interrupt - if the dclz engine flushed bit is zero and the dclz eor count bit is zero, then there is data in the dclz engine to transfer out via compression flush mode. begin - program dclz control register dclz mode[2:0] compression flush comp ratio opt enable 1 reset dict after eor 0 reset dict 0 pause after eor 0 pau s e 0 - the port b end of transfer interrupt signals compression completed end - if the dclz engine flushed bit is zero and the dclz eor count bit is one, then the dclz engine is already in the process of flushing. begin - program dclz control register dclz mode[2:0] compression comp ratio opt enable 1 reset dict after eor 0 reset dict 0 pause after eor 0 pause 0 - the port b end of transfer interrupt signals compression completed end - if the dclz engine flushed bit is one and the port b interface byte count is not zero, then there is data in the port b interface to transfer out. begin - program dclz control register dclz mode[2:0] compression comp ratio opt enable 1 reset dict after eor 0 reset dict 0 pause after eor 0 pause 0 - the port b end of transfer interrupt signals compression completed end - if the dclz engine flushed bit is one and the port b interface byte count is zero, then the dclz engine and the port b interface are already flushed. figure 6: compression flush mode port a byte counter port b byte counter port a dma state machine port a fifo port b dma state machine port b fifo single data bus arbiter record count register record length register processor interface state machine pass through controller interrupt logic processor interface dclz engine port a interface port b interface acsn dreqa dacka aoe awe dapty[1:0] da[15:0] a[4:0] portacsn csn rwn/iowrn dsn/iordn procmode tristaten test restn clk dtackn/ready d[7:0] intn/int dreqb dackb boe bwe dbpty[1:0] db[15:0] (8 bytes) (8 bytes) AHA3210B compression chip
ps3210b-1299 page 7 of 45 advanced hardware architectures, inc. 2.2.3 decompression mode during decompression mode, compressed data flows into port b. it is then uncompressed by the dclz engine. the resulting uncompressed data is then transferred out of port a. the compressed data is partitioned into records, with end of record codewords embedded in the compressed data. multiple records can be automatically decompressed, by programming the number of records into the record count register. a decompression sequence has been completed after the last byte of the last record has been uncompressed and then transferred out of port a. this event sets the port a end of transfer interrupt. the following sequence is used to program the chip to decompress multiple records: - program record count register - program interrupt disable register - enable port a end of transfer interrupt - program dclz control register dclz mode[2:0] decompression comp ratio opt enable 0 reset dict after eor 0 reset dict 0 pause after eor 0 pause 0 - the port a end of transfer interrupt signals decompression completed figure 7: decompression mode port a byte counter port b byte counter port a dma state machine port a fifo port b dma state machine port b fifo single data bus arbiter record count register record length register processor interface state machine pass through controller interrupt logic processor interface dclz engine port a interface port b interface acsn dreqa dacka aoe awe dapty[1:0] da[15:0] a[4:0] portacsn csn rwn/iowrn dsn/iordn procmode tristaten test restn clk dtackn/ready d[7:0] intn/int dreqb dackb boe bwe dbpty[1:0] db[15:0] (8 bytes) (8 bytes) AHA3210B compression chip
page 8 of 45 ps3210b-1299 advanced hardware architectures, inc. 2.2.4 decompression output disabled mode the dclz algorithm allows the compression dictionary to be shared between multiple records. to decompress records in the middle of a multiple record sequence, the preceding records must first be decompressed, in order to properly build the compression dictionary. decompression output disabled mode allows the preceding records to be decompressed, while discarding the unwanted uncompressed data. once this is completed, the chip can be programmed to decompression mode, to decompress and output the desired records. in decompression output disabled mode, the data is discarded between the port a interface and the port a pins. port a dma remains inactive. the port b byte counter, the port a byte counter, the port b interface byte count, the port a interface byte count, the record count register, and the port a end of transfer interrupt operate as in decompression mode. it is recommended that the port a interface be empty and the chip paused before switching between decompression output disabled and decompression modes. the following sequence is used to program the chip to decompress multiple records in output disabled mode: - program record count register - program interrupt disable register - enable port a end of transfer interrupt - program dclz control register dclz mode[2:0] decomp; output disabled mode comp ratio opt enable 0 reset dict after eor 0 reset dict 0 pause after eor 0 pause 0 - the port a end of transfer interrupt signals decompression output disabled completed figure 8: decompression output disabled mode port a byte counter port b byte counter port a dma state machine port a fifo port b dma state machine port b fifo single data bus arbiter record count register record length register processor interface state machine pass through controller interrupt logic processor interface dclz engine port a interface port b interface acsn dreqa dacka aoe awe dapty[1:0] da[15:0] a[4:0] portacsn csn rwn/iowrn dsn/iordn procmode tristaten test restn clk dtackn/ready d[7:0] intn/int dreqb dackb boe bwe dbpty[1:0] db[15:0] (8 bytes) (8 bytes) AHA3210B compression chip
ps3210b-1299 page 9 of 45 advanced hardware architectures, inc. 2.2.5 pass through a to b mode during pass through a to b mode, data enters port a, is transferred through the port a interface and the port b interface, and then transferred out of port b. the data is not altered as it passes through the chip. the record length register determines the number of bytes in a record. the record count register determines the number of records. multiply the values of these two registers to determine the total number of bytes that will be transferred through the chip. the pass through sequence has been completed after the last byte of the last record has been transferred out of port b. this event sets the port b end of transfer interrupt. the following sequence is used to program the chip to pass through data from port a to port b: - program record length register - program record count register - program interrupt disable register - enable port b end of transfer interrupt - program dclz control register dclz mode[2:0] pass through a to b comp ratio opt enable 0 reset dict after eor 0 reset dict 0 pause after eor 0 pause 0 - the port b end of transfer interrupt signals pass through a to b completed figure 9: pass through a to b mode port a byte counter port b byte counter port a dma state machine port a fifo port b dma state machine port b fifo single data bus arbiter record count register record length register processor interface state machine pass through controller interrupt logic processor interface dclz engine port a interface port b interface acsn dreqa dacka aoe awe dapty[1:0] da[15:0] a[4:0] portacsn csn rwn/iowrn dsn/iordn procmode tristaten test restn clk dtackn/ready d[7:0] intn/int dreqb dackb boe bwe dbpty[1:0] db[15:0] (8 bytes) (8 bytes) AHA3210B compression chip
page 10 of 45 ps3210b-1299 advanced hardware architectures, inc. 2.2.6 pass through b to a mode during pass through b to a mode, data enters port b, is transferred through the port b interface and port a interface, and is then transferred out of port a. the data is not altered as it passes through the chip. the record length register determines the number of bytes in a record. the record count register determines the number of records. multiply the values of these two registers to determine the total number of bytes that will be transferred through the chip. the pass through sequence has been completed after the last byte of the last record has been transferred out of port a. this event sets the port a end of transfer interrupt. the following sequence is used to program the chip to pass through data from port b to port a: - program record length register - program record count register - program interrupt disable register - enable port a end of transfer interrupt - program dclz control register dclz mode[2:0] pass through b to a comp ratio opt enable 0 reset dict after eor 0 reset dict 0 pause after eor 0 pause 0 - the port a end of transfer interrupt signals pass through b to a completed figure 10: pass through b to a mode port a byte counter port b byte counter port a dma state machine port a fifo port b dma state machine port b fifo single data bus arbiter record count register record length register processor interface state machine pass through controller interrupt logic processor interface dclz engine port a interface port b interface acsn dreqa dacka aoe awe dapty[1:0] da[15:0] a[4:0] portacsn csn rwn/iowrn dsn/iordn procmode tristaten test restn clk dtackn/ready d[7:0] intn/int dreqb dackb boe bwe dbpty[1:0] db[15:0] (8 bytes) (8 bytes) AHA3210B compression chip
ps3210b-1299 page 11 of 45 advanced hardware architectures, inc. 3.0 register description table 2: register address map notations: * these registers have one or more reserved bits set to 0. these registers read back 0 from these reserved bits. ** a soft reset is generated by writing a reset command to dclz mode[2:0]. u - these bits remain unchanged after a soft reset. x - indicates undefined bit. address read write hard reset soft** reset 0x00 dclz control dclz control 1110,0000 111u,uuuu 0x01 dclz status reserved 0000,0011 0000,0011 0x02 comp ratio optimization comp ratio optimization 0000,0000 unchanged 0x03 *dma configuration dma configuration 0000,0101 unchanged 0x04 port a control 0 port a control 0 0000,0000 unchanged 0x05 *port a control 1 port a control 1 x000,00xx unchanged 0x06 port a status reserved 0000,0000 0u00,0000 0x07 port a byte count [7:0] port a byte count [7:0] 0000,0000 unchanged 0x08 port a byte count [15:8] port a byte count [15:8] 0000,0000 unchanged 0x09 port a byte count [23:16] port a byte count [23:16] 0000,0000 unchanged 0x0a port b control 0 port b control 0 0000,0000 unchanged 0x0b *port b control 1 port b control 1 x000,00xx unchanged 0x0c port b status reserved 0000,0000 0u00,0000 0x0d port b byte count [7:0] port b byte count [7:0] 0000,0000 unchanged 0x0e port b byte count [15:8] port b byte count [15:8] 0000,0000 unchanged 0x0f port b byte count [23:16] port b byte count [23:16] 0000,0000 unchanged 0x10 port b byte comparator [7:0] port b byte comparator [7:0] undefined unchanged 0x11 port b byte comparator [15:8] port b byte comparator [15:8] undefined unchanged 0x12 port b byte comparator [23:16] port b byte comparator [23:16] undefined unchanged 0x13 record length [7:0] record length [7:0] undefined unchanged 0x14 record length [15:8] record length [15:8] undefined unchanged 0x15 record length [23:16] record length [23:16] undefined unchanged 0x16 record count [7:0] record count [7:0] undefined unchanged 0x17 record count [15:8] record count [15:8] undefined unchanged 0x18 record count [23:16] record count [23:16] undefined unchanged 0x19 interrupt status interrupt clear 0000,0000 unchanged 0x1a *interrupt disable interrupt disable 0011,1111 unchanged 0x1f identification reserved 0100,0001 0100,0001
page 12 of 45 ps3210b-1299 advanced hardware architectures, inc. 3.1 dclz control: address 00 hex - read/write dclz mode[2:0] = dclz control register [7:5]: the dclz mode bits determine how the chip will process data as follows. C pass through modes transfer data through the chip without any compression or decompression operation. pass through a to b transfers data into port a and out of port b. pass through b to a transfers data into port b and out of port a. C compression mode transfers uncompressed data into port a, compresses it, and transfers compressed data out of port b. C compression flush mode causes all data in the dclz engine to be compressed including an end of record codeword, and then flushed out of the chip through port b. C decompression mode transfers compressed data into port b, decompresses it, and transfers uncompressed data out of port a. C decompression output disabled mode transfers compressed data into port b, decompresses it and builds the decompression dictionary, but does not transfer any uncompressed data out of port a. C reset mode resets all state machines and data in port a, port b, single data bus arbiter, and the dclz engine. it also resets the dictionary. it resets the registers as shown in table 2. the dclz control bits should always be programmed to the reset mode, when switching between all modes, except between compression and compression flush modes and between decompression and decompression output disabled modes. it is recommended that the port a interface be empty and the chip paused before switching between decompression output disabled and decompression modes. the dclz mode bits are set to one when the chip is reset from the resetn pin. the dclz mode bits are decoded as shown below: table 3: dclz mode bit decode comp ratio opt enable: the compression ratio optimization enable bit enables the automatic compression ratio optimizer during compression. this bit enables the thresh[5:0] and period[1:0] bits in the comp ratio optimization register. a one enables optimization, and a zero disables optimization. this bit is cleared to zero when the chip is reset from the resetn pin. reset dict after eor: during compression, the reset dictionary after end of record bit causes the dclz engine to reset the compression dictionary after each end of record, and before the first subsequent byte which is not designated as an end of record. a one resets the dictionary after end of record, and a zero has no effect on the dictionary. this bit is cleared to zero when the chip is reset from the resetn pin. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 dclz mode[2:0] comp ratio opt enable reset dict after eor reset dict pause after eor pa use dclz mode[2] dclz mode[1] dclz mode[0] function 0 0 0 pass through a to b 0 0 1 pass through b to a 010compression 0 1 1 compression flush 1 0 0 decompression 1 0 1 decompression output disable 110reserved 111reset
ps3210b-1299 page 13 of 45 advanced hardware architectures, inc. reset dict the reset dictionary bit causes the compression dictionary to be reset after completing the current byte, and before the next byte which is not designated as an end of record. a one causes the dictionary to be reset, and a zero has no effect on the dictionary. the reset dict bit will be automatically cleared, once a dictionary reset has occurred. this bit is cleared to zero when the chip is reset from the resetn pin. pause after eor: writing a one to the pause after end of record bit causes the port a interface, the dclz engine and the port b interface to pause after each end of record has been processed. the paused status bit in the dclz status register is then set. to allow the chip to continue, a zero must be written to the pause bit. this bit is cleared to zero when the chip is reset from the resetn pin. pause: writing a one to the pause bit causes the port a interface, the dclz engine, and the port b interface to pause. the paused status bit in the dclz status register is then set. writing a zero to the pause bit allows the chip to resume operation after it has been paused or paused after end of record. pause bit operation is supported during processor write cycles which program the dclz control bits out of the reset state. this bit is cleared to zero when the chip is reset from the resetn pin. table 4: supported modes for dclz control register bits 3.2 dclz status: address 01 hex - read only res - reserved. bits read back zeros. dclz eor count: the dclz eor count bit shows the number of end of records contained in the dclz engine. this bit operates in compression, compression flush, decompression, and decompression output disabled mode. this bit is cleared to zero when the reset or pass through a to b or pass through b to a code is programmed to the dclz mode bits in the dclz control register, or when the chip is reset by the resetn pin. the dclz eor count bit can transition frequently when the dclz engine is actively processing data (i.e., when it is not paused). therefore, the dclz eor count bit should only be considered valid when the paused bit is one. dclz engine flushed: this bit operates in compression, compression flush, decompression, and decompression output disabled modes only. when the dclz engine flushed bit is a one, there is no data in the dclz engine. this occurs after an end of record has been processed through the dclz engine, and before the first byte of the next record has entered the dclz engine. once the first byte of the next record enters the dclz engine, the dclz engine flushed bit is cleared to zero. the dclz engine flushed bit is set to one when the dclz mode bits are programmed to pass through a to b, pass through b to a, or reset mode. also, the dclz engine flushed bit is set to one when the chip is reset by the resetn pin. the dclz engine flushed bit can transition frequently when the dclz engine is actively processing data (i.e., when it is not paused). therefore, the dclz engine flushed bit should only be considered valid when the paused bit is one. mode comp ratio opt enable reset dict after eor reset dict paus e after eor pau s e compression yes yes yes yes yes compression flush yes yes yes yes yes decompression no no no yes yes decompression output disabled no no no yes yes pass through a to b no no no yes yes pass through b to a no no no yes yes bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x01 res dclz eor count dclz engine flushed paused
page 14 of 45 ps3210b-1299 advanced hardware architectures, inc. paused: when the paused bit is one, the port a interface, the dclz engine, and the port b interface are paused. the port a byte count registers, the port b byte count registers, the port a status register, the port b status register, the record length registers, and the record count registers are stable at this time. this bit is set to one when the chip is reset from the resetn pin, or when the dclz control bits are programmed to the reset state. 3.3 comp ratio optimization: address 02 hex - read/write this register is used to control the compression ratio during compression mode, by automatically resetting the compression dictionary if the compression ratio is below the programmed threshold. if the compression dictionary is less than half full the optimization circuit will check the compression ratio and compare it to the compression ratio programmed in the threshold parameter every 1024 input bytes and reset the dictionary if the compression ratio does not meet or exceed this value. after the dictionary is greater than half full, the optimizer will check the compression ratio against a threshold every n bytes, where n is determined by the value of the period bits. the threshold is set by the value of the thresh bits. optimization is enabled by setting comp ratio opt enable bit in the dclz control register. the compression ratio is specified by the threshold bits according to the following formula: for example, if thresh is set at 32 the compression ratio is 2. this compression ratio is a target. after every n number of bytes as specified by the period field has been input, the actual compression ratio is checked against the target. if the actual is less than the target, the dictionary is automatically reset. the thresh[5:0] and period[1:0] bits are zero when the chip is reset by the resetn pin. 3.4 dma configuration: address 03 hex - read/write res - reserved. bits must always be written with zeros. they read back zeros. data bus mode [2:0]: the data bus mode bits determine the data configuration for the port a and port b dma buses. in dual data bus mode, port a and port b are independent, isolated data buses. data transfers on each bus may occur simultaneously. in this mode, port a and port b can be any combination of dma bus masters or slaves. this mode is intended for in line applications. in single bus mode, the port a and port b data buses are connected together on the pc board. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x02 thresh[5:0] period[1:0] period bit 1 bit 0 size 0 0 512 bytes 0 1 1024 bytes 1 0 2048 bytes 1 1 4096 bytes compression ranges compression ratio threshold value 1 ? 20 ? 32 2 ? 333 ? 42 3 ? 443 ? 48 4 ? 849 ? 56 8 ? 64 57 ? 63 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x03 res data bus mode[2:0] compression ratio 64 64 thresh C ---------------------------------- - =
ps3210b-1299 page 15 of 45 advanced hardware architectures, inc. both port a and port b are dma bus masters. the single data bus arbiter circuit inside the chip resolves all bus contention on this single data bus. port a and port b will never simultaneously request the data bus in this mode. this mode is intended for look aside applications. note that in single data bus mode, the dma port which is transferring data out of the chip has priority over the dma port which is transferring data into the chip. the port a interface supports register accesses to a peripheral chip on the port a data bus. register and dma accesses between the port a interface and the peripheral chip occur on a single data bus, da[7:0]. this mode is only supported when port a is a dma slave in dual data bus mode. data bus mode bits are set to 101 after the chip is reset by resetn. table 5: data bus mode bit decode the port a and port b dma control pins change direction, based on the master or slave mode. the following table shows the dma control pin direction for dma bus master and slave modes: port a dma bus master/slave pin configuration table 6: port a dma bus master/slave pin configuration table 7: port b dma bus master/slave pin configuration 3.5 port a control 0: address 04 hex - read/write enable da pullup: a one enables the pullups on the da[15:0] pins. a zero tristates the pullups on the da[15:0] pins. this bit is cleared to zero when the chip is reset by the resetn pin. data bus mode[2] data bus mode[1] data bus mode[0] function 0 0 0 dual data bus: port b slave, port a slave 0 0 1 dual data bus: port b slave, port a master 0 1 0 dual data bus: port b master, port a slave 0 1 1 dual data bus: port b master, port a master 1 0 0 dual data bus: port b slave, port a slave with peripheral access 101reserved 1 1 0 dual data bus: port b master, port a slave with peripheral access 1 1 1 single data bus: port b master, port a master pin name port a dma bus master port a dma bus slave dreqa output input dacka input output aoe input output awe input output pin name port b dma bus master port b dma bus slave dreqb output input dackb input output boe input output bwe input output bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x04 enable da pullup enable dapty pullup awe enable aoe enable awe polarity aoe polarity dreqa polarity dacka polarity
page 16 of 45 ps3210b-1299 advanced hardware architectures, inc. enable dapty pullup: a one enables the pullups on the dapty[1:0] pins. a zero tristates the pullups on the dapty[1:0] pins. this bit is cleared to zero when the chip is reset by the resetn pin. awe enable: a one enables the awe input when port a is a dma bus master, and enables the awe output when port a is a dma bus slave. a zero disables the awe input when port a is a dma bus master, and tristates the awe output when port a is a dma bus slave. this bit is cleared to zero when the chip is reset by the resetn pin. aoe enable: a one enables the aoe input when port a is a dma bus master, and enables the aoe output when port a is a dma bus slave. a zero disables the aoe input when port a is a dma bus master, and tristates the aoe output when port a is a dma bus slave. this bit is cleared to zero when the chip is reset by the resetn pin. awe polarity: a one makes awe high active. a zero makes awe low active. this bit is cleared to zero when the chip is reset by the resetn pin. aoe polarity: a one makes aoe high active. a zero makes aoe low active. this bit is cleared to zero when the chip is reset by the resetn pin. dreqa polarity: a one makes dreqa high active. a zero makes dreqa low active. this bit is cleared to zero when the chip is reset by the resetn pin. dacka polarity: a one makes dacka high active. a zero makes dacka low active. this bit is cleared to zero when the chip is reset by the resetn pin. 3.6 port a control 1: address 05 hex - read/write data bus width: a one makes the port a data bus 16 bits wide, with data transferred on the da[15:0] pins. a zero makes the port a data bus 8 bits wide, with data transferred on the da[7:0] pins. this bit should only be changed after the reset code has been programmed to the dclz control bits in the dclz control register. this bit is undefined when the chip is reset from the resetn pin. data15to8: the data15to8 bit causes one byte to be transferred on da[15:8] on the next dma cycle into or out of port a, when port a is in 16 bit mode. the intended use of this bit is to transfer a single byte on da[15:8] only during the first dma cycle of a contiguous data transfer sequence. the data15to8 bit only functions when port a is in 16 bit mode, and is ignored when port a is in 8 bit mode. the data15to8 bit should only be changed after the reset code has been programmed into the dclz control bits in the dclz control register, or after the chip has paused after end of record, or after the chip has paused because the port a or port b end of transfer interrupt has occurred. data15to8 takes effect only on the next dma cycle, which is defined as the next occurrence when dacka pulses active, and is supported when port a is a dma bus master or a dma bus slave. after the dma cycle occurs, the data15to8 bit is automatically cleared. data15to8 is cleared to zero when the chip is reset from the resetn pin. res - reserved. bit must always be written with a zero. it reads back a zero. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x05 data bus width data15to8 res port a disable clear interface clear byte counter enable parity odd parity
ps3210b-1299 page 17 of 45 advanced hardware architectures, inc. port a disable: a one disables the port a control and data buses. the port a output control signals are made hi- impedance. the port a input control signals are ignored. the da[15:0] and dapty[1:0] data pins are put into a hi-impedance state and any transitions on them are ignored. a zero in this bit position places port a into normal operational mode. this bit should only be changed while the chip is paused at an end of transfer condition. the contents of the dclz control register, the dma configuration register, and the port a control 0 register, should not be changed while this bit is a one. this bit is cleared to zero when the chip is reset from the resetn pin. clear interface: writing a one creates a pulse, which clears the port a interface. writing a zero has no effect on the port a interface. this bit is always a zero when it is read. the clear interface bit is intended to be used only when the chip has paused after end of record, or paused because the port a or port b end of transfer interrupt has occurred. clear byte counter: writing a one creates a pulse, which clears the port a byte count register. writing a zero has no effect on the port a byte count register. this bit is always a zero when it is read. enable parity: a one enables parity on dapty[1:0] when port a is in 16 bit mode, and on dapty[0] when port a is in 8 bit mode. writing a zero disables parity on port a. this bit is undefined when the chip is reset from the resetn pin. odd parity: a one selects odd parity on port a. a zero selects even parity on port a. this bit is undefined when the chip is reset from the resetn pin. 3.7 port a status: address 06 hex - read only res - reserved. bit reads back zero. data7to0: when port a is in 16 bit mode, the data7to0 bit shows whether the last dma cycle of a data transfer sequence out of port a contains one or two valid bytes. this occurs for the last byte of the last record, as determined by the record count register. if the last byte of the last record is the first byte in the sequence to output a word, that byte is output on da[7:0], the data on da[15:8] is undefined, and the data7to0 bit is set. if the last byte of the last record is the second byte in the sequence to output a word, the second to last byte is output on da[7:0], the last byte is output on da[15:8], and the data7to0 bit is cleared. the data7to0 bit is cleared during all dma cycles into port a, during all dma cycles when port a is in 8 bit mode, and when the chip is reset from the resetn pin. eor count[1:0]: the eor count[1:0] bits show the number of bytes with active end of record flags contained in the port a interface. these bits operate in compression, compression flush, decompression, decompression output disabled, pass through a to b, and pass through b to a modes. these bits are cleared to zero when a one is written to the clear interface bit in port a control 1 register, or when the reset code is programmed to the dclz mode bits in the dclz control register, or when the chip is reset by the resetn pin. during data transfers, these bits should only be read when the paused bit in the dclz status register is a one. interface byte count[3:0]: the interface byte count[3:0] bits show the number of bytes that are held in the port a interface. these bits are cleared to zero when a one is written to the clear interface bit in port a control 1 register, or when the reset code is programmed to the dclz mode bits in the dclz control register, or when the chip is reset by the resetn pin. during data transfers, these bits should only be read when the paused bit in the dclz status register is a one. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x06 res data7to0 eor count[1:0] interface byte count[3:0]
page 18 of 45 ps3210b-1299 advanced hardware architectures, inc. 3.8 port a byte count: address 07,08,09 hex - read/write least significant byte (address 07 hex): middle byte (address 08 hex) most significant byte (address 09 hex): the port a byte count register counts the number of bytes that are transferred by the port a dma state machine. this register counts in compression, compression flush, decompression, decompression output disabled, pass through a to b, and pass through b to a modes. the register is cleared to zero when a one is written to the clear byte counter bit in port a control 1 register, or when the chip is reset by the resetn pin. during data transfers, this register should only be written or read when the paused bit in the dclz status register is a one. the counter rolls over from ffffff hex to 000000 hex. 3.9 port b control 0: address 0a hex - read/write enable db pullup: a one enables the pullups on the db[15:0] pins. a zero tristates the pullups on the db[15:0] pins. this bit is cleared to zero when the chip is reset by the resetn pin. enable dbpty pullup: a one enables the pullups on the dbpty[1:0] pins. a zero tristates the pullups on the dbpty[1:0] pins. this bit is cleared to zero when the chip is reset by the resetn pin. bwe enable: a one enables the bwe input when port b is a dma bus master, and enables the bwe output when port b is a dma bus slave. a zero disables the bwe input when port b is a dma bus master, and tristates the bwe output when port b is a dma bus slave. this bit is cleared to zero when the chip is reset by the resetn pin. boe enable: a one enables the boe input when port b is a dma bus master, and enables the boe output when port b is a dma bus slave. a zero disables the boe input when port b is a dma bus master, and tristates the boe output when port b is a dma bus slave. this bit is cleared to zero when the chip is reset by the resetn pin. bwe polarity: a one makes bwe high active. a zero makes bwe low active. this bit is cleared to zero when the chip is reset by the resetn pin. boe polarity: a one makes boe high active. a zero makes boe low active. this bit is cleared to zero when the chip is reset by the resetn pin. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x07 [7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x08 [15:8] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x09 [23:16] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x0a enable db pullup enable dbpty pullup bwe enable boe enable bwe polarity boe polarity dreqb polarity dackb polarity
ps3210b-1299 page 19 of 45 advanced hardware architectures, inc. dreqb polarity: a one makes dreqb high active. a zero makes dreqb low active. this bit is cleared to zero when the chip is reset by the resetn pin. dackb polarity: a one makes dackb high active. a zero makes dackb low active. this bit is cleared to zero when the chip is reset by the resetn pin. 3.10 port b control 1: address 0b hex - read/write data bus width: a one makes the port b data bus 16 bits wide, with data transferred on the db[15:0] pins. a zero makes the port b data bus 8 bits wide, with data transferred on the db[7:0] pins. this bit should only be changed after the reset code has been programmed to the dclz control bits in the dclz control register. this bit is undefined when the chip is reset from the resetn pin. data15to8: the data15to8 bit causes one byte to be transferred on db[15:8] on the next dma cycle into or out of port b, when port b is in 16 bit mode. the intended use of this bit is to transfer a single byte on db[15:8] only during the first dma cycle of a contiguous data transfer sequence. the data15to8 bit only functions when port b is in 16 bit mode, and is ignored when port b is in 8 bit mode. the data15to8 bit should only be changed after the reset code has been programmed into the dclz control bits in the dclz control register, or after the chip has paused after end of record, or after the chip has paused because the port a or port b end of transfer interrupt has occurred. data15to8 takes effect only on the next dma cycle, which is defined as the next occurrence when dackb pulses active, and is supported when port b is a dma bus master or a dma bus slave. after the dma cycle occurs, the data15to8 bit is automatically cleared. data15to8 is cleared to zero when the chip is reset from the resetn pin. res - reserved. bit must always be written with a zero. it reads back a zero. enable port b comparator: a one enables the comparison of the port b byte count register with the port b byte comparator register, allowing the port b comparator interrupt to be set and the chip to pause. a zero disables the port b byte comparator register and prohibits the port b comparator interrupt. clear interface: writing a one creates a pulse, which clears the port b interface. writing a zero has no effect on the port b interface. this bit is always zero when it is read. this bit is intended to be used in port b slave input or output and master output modes. the clear interface bit is intended to be used only when the chip has paused after end of record, or paused because the port a or port b end of transfer has occurred. clear byte counter: writing a one creates a pulse, which clears the port b byte count register. writing a zero has no effect on the port b byte count register. this bit is always zero when it is read. enable parity: a one enables parity on dbpty[1:0] when port b is in 16 bit mode, and on dbpty[0] when port b is in 8 bit mode. writing a zero disables parity on port b. this bit is undefined when the chip is reset from the resetn pin. odd parity: a one selects odd parity on port b. a zero selects even parity on port b. this bit is undefined when the chip is reset from the resetn pin. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x0b data bus width data15to8 res enable port b comparator clear interface clear byte counter enable parity odd parity
page 20 of 45 ps3210b-1299 advanced hardware architectures, inc. 3.11 port b status: address 0c hex - read only res -reserved. bit must always be written with a zero. it reads back a zero. data7to0: when port b is in 16 bit mode, the data7to0 bit shows whether the last dma cycle of a data transfer sequence out of port b contains one or two valid bytes. this occurs for the last byte of the last record, as determined by the record count register. if the last byte of the last record is the first byte in the sequence to output a word, that byte is output on db[7:0], the data on db[15:8] is undefined, and the data7to0 bit is set. if the last byte of the last record is the second byte in the sequence to output a word, the second to last byte is output on db[7:0], the last byte is output on db[15:8], and the data7to0 bit is cleared. the data7to0 bit is cleared during all dma cycles into port b, during all dma cycles when port b is in 8 bit mode, and when the chip is reset from the resetn pin. eor count[1:0]: the eor count[1:0] bits show the number of bytes with active end of record flags contained in the port b interface. these bits operate in compression, compression flush, pass through a to b modes. these bits are cleared to zero when a one is written to the clear interface bit in port b control 1 register, or when the reset or decompression or decompression output disabled or pass through b to a code is programmed to the dclz mode bits in the dclz control register, or when the chip is reset by the resetn pin. during data transfers, these bits should only be read when the paused bit in the dclz status register is a one. interface byte count[3:0]: the interface byte count[3:0] bits show the number of bytes that are held in the port b interface. these bits are cleared to zero when a one is written to the clear interface bit in port b control 1 register, or when the reset code is programmed to the dclz mode bits in the dclz control register, or when the chip is reset by the resetn pin. during data transfers, these bits should only be read when the paused bit in the dclz status register is a one. 3.12 port b byte count: address 0d,0e,0f hex - read/write least significant byte (address 0d hex): middle byte (address 0e hex): most significant byte (address 0f hex): the port b byte count register counts the number of bytes that are transferred by the port b dma state machine. this register counts in compression, compression flush, decompression, decompression output disabled, pass through a to b, and pass through b to a modes. the register is cleared to zero when a one is written to the clear byte counter bit in port b control 1 register, or when the chip is reset by the resetn pin. during data transfers, this register should only be written or read when the paused bit in the dclz status register is a one. this counter rolls over from ffffff hex to 000000. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x0c res data7to0 eor count[1:0] interface byte count[3:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x0d [7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x0e [15:8] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x0f [23:16]
ps3210b-1299 page 21 of 45 advanced hardware architectures, inc. 3.13 port b byte comparator: address 10,11,12 hex - read/write least significant byte (address 10 hex): middle byte (address 11 hex): most significant byte (address 12 hex): the port b byte comparator register is used to pause the chip after a programmed amount of data has been transferred across the port b data bus pins, db[15:0]. this register operates in compression, compression flush, decompression, decompression output disabled, pass through a to b, and pass through b to a modes. when the port b dma state machine updates the 24 bit port b byte count register, this updated value is compared to the 24 bit port b byte comparator register. if the updated port b byte count value equals or exceeds the port b comparator value, the port b comparator interrupt is set, and the chip is immediately paused. this function is enabled by the enable port b comparator bit in port b control 1 register. if the enable port b comparator bit is zero (inactive), the port b byte comparator register is unused, and the port b comparator interrupt and pause functions are disabled. during data transfers, this register should only be written or read when the paused bit in the dclz status register is a one. 3.14 record length: address 13,14,15 hex - read/write least significant byte (address 13 hex): middle byte (address 14 hex): most significant byte (address 15 hex): the twenty four bit record length register is used to count the number of bytes of uncompressed data that comprise one record. the counter operates in compression, pass through a to b, and pass through b to a modes. note that in decompression, the end of record codewords in the compressed data stream determine where the end of records occur. the record length register contains a binary down counter. the initial value of the record length is written into the record length register. the current value of the down counter is transferred during read cycles from this register. this register is used in conjunction with the record count register. when the record length register reaches zero, the record count register is decremented. if the record count register is greater than zero, the record length register down counter is reloaded, to allow another record to be processed automatically. the three bytes of the record count register should be read from, or written to, only after the reset code has been written to the dclz control bits in the dclz control register, or when the paused bit in the dclz status register is one. the record length register is undefined when the chip is reset by the resetn pin. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x10 [7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x11 [15:8] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x12 [23:16] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x13 [7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x14 [15:8] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x15 [23:16]
page 22 of 45 ps3210b-1299 advanced hardware architectures, inc. 3.15 record count: address 16,17,18 hex - read/write least significant byte (address 16 hex): middle byte (address 17 hex): most significant byte (address 18 hex): the twenty four bit record count register is used to count the number of records in a multi-record transfer. this register is used in compression, compression flush, decompression, decompression output disabled, pass through a to b, and pass through b to a modes. the record count and record length registers allow multiple records to be processed without processor intervention. if only one record is to be compressed, then the record count register should be initialized to one. the initial value of the record count is written into the record count register. the record count register is a binary down counter. the current value of the down counter is transferred during read cycles from this register. the three bytes of the record count register should be read from, or written to, only after the reset code has been written to the dclz control bits in the dclz control register, or when the paused bit in the dclz status register is one. the record count register is undefined when the chip is reset by the resetn pin. 3.16 interrupt status: address 19 hex - read only res -reserved. bit reads back a zero. port b comparator int: the port b comparator interrupt bit is set after a byte is transferred over the port b data bus pins, when the port b byte count register is updated and then equals or exceeds the value in the port b byte comparator register. the port b comparator int bit is cleared to zero when the chip is reset from the resetn pin. note that the port b comparator interrupt bit can only be set when the enable port b comparator bit in port b control 1 register is one (active). dclz error int: the dclz error interrupt bit is set when any of the following errors occur during decompression or decompression output disabled modes: a grow codeword was read when the codeword size was already at the maximum 12 bits in length; an unknown codeword was read; a codeword was read which corresponded to greater than the maximum limit of 128 uncompressed bytes. once the dclz error int bit is set, the reset code should be written to the dclz mode bits in the dclz control register, followed by writing a one to the clear dclz error bit in the interrupt clear register. the dclz error int bit is cleared to zero when the chip is reset from the resetn pin. port b parity error int: the port b parity error interrupt is set when port b parity is enabled, and erroneous parity is detected when data is read into port b. once the port b parity error int bit is set, the reset code should be written to the dclz mode bits in the dclz control register, followed by writing a one to the clear port b parity error bit in the interrupt clear register. the port b parity error int bit is cleared to zero when the chip is reset from the resetn pin. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x16 [7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x17 [15:8] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x18 [23:16] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x19 res port b comparator int dclz error int port b par ity error int port a parity error int port b end of transfer int port a end of transfer int
ps3210b-1299 page 23 of 45 advanced hardware architectures, inc. port a parity error int: the port a parity error interrupt is set when port a parity is enabled, and erroneous parity is detected when data is read into port a. once the port a parity error int bit is set, the reset code should be written to the dclz mode bits in the dclz control register, followed by writing a one to the clear port a parity error bit in the interrupt clear register. the port a parity error int bit is cleared to zero when the chip is reset from the resetn pin. port b end of transfer int: the port b end of transfer interrupt is used in compression, compression flush, and pass through a to b modes. the interrupt occurs when the record count register and the record length register are both zero, and the last byte of the last record has been transferred through the port b interface. the port b end of transfer int bit is cleared to zero when the chip is reset from the resetn pin. port a end of transfer int: the port a end of transfer interrupt is used in decompression, decompression output disabled, and pass through b to a modes. the interrupt occurs in pass through b to a mode when the record count register and the record length register are both zero, and the last byte of the last record has been transferred through the port a interface. the interrupt occurs in decompression and decompression output disabled modes when the record count register is zero, and the last byte of the last record has been transferred through the port a interface. the port a end of transfer int bit is cleared to zero when the chip is reset from the resetn pin. 3.17 interrupt clear: address 19 hex - write only res -reserved. bit reads back a zero. all other bits in the register clear the interrupt bits in the interrupt status register. writing a one to a clear bit creates a pulse which clears the corresponding bit in the interrupt status register. writing a zero to a clear bit has no effect on the corresponding interrupt bit in the interrupt status register. 3.18 interrupt disable: address 1a hex - read/write res -reserved. bit reads back a zero. all other bits in the register gate the interrupts between the interrupt status register and the intn/int pin of the chip. writing a one to a disable bit disables the corresponding interrupt. writing a zero to a disable bit enables the corresponding interrupt. note that software polling is possible by disabling all the interrupts, and using the interrupt status register and interrupt clear registers. the disable bits are one when the chip is reset by the resetn pin. 3.19 identification: address 1f hex - read only this register provides an identification code for firmware to read. for the AHA3210B, the identification code is 0x41. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x19 res clear port b comparator int clear dclz error int clear port b par ity error int clear port a parity error int clear port b end of transfer int clear port a end of transfer int bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x1a res disable port b comparator int disable dclz error int disable port b parity error int disable port a pa ri ty error int disable port b end of transfer int disable port a end of transfer int
page 24 of 45 ps3210b-1299 advanced hardware architectures, inc. 4.0 pin description this section describes the function of the pins of the chip. a low active signal has an n appended to the end of the signal name. 4.1 processor interface name type description procmode i processor mode select pin. connect to vdd to select a processor interface controlled by a data strobe (dsn), a read/write signal (rwn), with an open drain data transfer acknowledge output (dtackn), and an open drain, low active interrupt (intn). connect to gnd to select processor interface controlled by an i/o read strobe (iordn), an i/o write strobe (iowrn), with a high active ready output (ready), and a high active interrupt (int). a[4:0] i address for registers accessed through the processor interface. rwn/iowrn i when the procmode pin is a high voltage this signal functions as readwriten. a high voltage denotes a processor read cycle. a low voltage denotes a write cycle. when the procmode pin is a low voltage, this signal functions as i/o writen. a low voltage denotes a processor i/o write cycle is occurring, and the rising edge denotes the end of the processor access. as iowrn, this signal is used as a strobe signal, and must not glitch. csn i chip selectn. when the procmode pin is a high voltage, a low voltage on this signal and on the dsn/iordn signal denotes the start of a processor access to a register internal to the chip. this signal can glitch when dsn/ iordn is a high voltage. it must not glitch once dsn/iordn is a low voltage. when the procmode pin is a low voltage, a low voltage on csn and either dsn/iordn or rwn/iowrn denotes the start of a processor access to a register internal to the chip. the csn signal can glitch when both dsn/iordn and rwn/iowrn are at high voltage. csn must not glitch once dsn/iordn or rwn/iowrn are at low voltage. csn is active low. portacsn i port a chip selectn. when the procmode pin is a high voltage, a low voltage on this signal and on the dsn/iordn signal denotes the start of a processor access to a peripheral chip on port a. this signal can glitch when dsn/iordn is a high voltage. it must not glitch once dsn/iordn is a low voltage. when the procmode pin is a low voltage, a low voltage on portacsn and either dsn/iordn or rwn/iowrn denotes the start of a processor access to a peripheral chip on port a. the portacsn signal can glitch when both dsn/iordn and rwn/iowrn are at high voltage. portacsn must not glitch once dsn/iordn or rwn/iowrn are at low voltage. portacsn is active low. dsn/iordn i when the procmode pin is a high voltage, this pin functions as datastroben. allow voltage on this signal and on the csn signal denotes the start of a processor access. the rising edge of dsn/iordn denotes the end of a processor access. this signal is used as a strobe signal. it must not glitch. dsn/ iordn is active low. when the procmode pin is a low voltage, this pin functions as i/o readn. a low voltage denotes a processor i/o read cycle is occurring, and the rising edge denotes the end of the processor access. as iordn, this signal is used as a strobe signal, and must not glitch.
ps3210b-1299 page 25 of 45 advanced hardware architectures, inc. dtackn/ready o when the procmode pin is a high voltage, this signal functions as a data transfer acknowledge open drain output. a low voltage indicates that processor data has been latched on processor write cycles. on read cycles, a low voltage indicates that data is valid on the d[7:0] bus for the processor to latch. when the procmode pin is a low voltage, this signal functions as a ready output. at the beginning of processor cycles, this output is driven to a low voltage, indicating that the chip is not ready. the pin is driven high when data is valid on the d[7:0] bus during read cycles, and after data has been internally latched during write cycles. this signal is tristated when processor cycles are inactive. the reset state of this pin is high impedance. d[7:0] i/o bidirectional processor data bus, to access all registers internal to the chip. the reset state of these pins is high impedance. intn/int o when the procmode pin is a high voltage, this signal functions as a low active interrupt, with an open drain output. a low voltage indicates that an internal interrupt is active. the reset state of the pin in this mode is tristate. when the procmode pin is a low voltage, this signal functions as a high active interrupt. a high voltage denotes that an internal interrupt is active. in this mode, the pin is never tristated. the reset state of the pin in this mode is low voltage. clk i input clock. resetn i a low voltage on this pin will reset the chip. tristaten i a low voltage on this pin will tristate all i/o and output signal drivers, and will disable the pad pullup resistors on all other pins. the tristaten pin has a pullup resistor on the pin. for normal operation, it should be left open circuited on the pc board. test[3:0] i test input pins. these pins should always be grounded on the pc board. name type description
page 26 of 45 ps3210b-1299 advanced hardware architectures, inc. 4.2 port a interface name type description dreqa i/o port a dma request pin, with programmable polarity. this pin is an output when port a is a dma bus master, and an input when port a is a dma bus slave. this signal pulses once for every dma transfer into or out of port a in master mode. this signal may be held active for multiple transfers in slave mode. the reset state of this pin is high impedance. dacka i/o port a dma channel dma acknowledge pin, with programmable polarity. this pin is an input when port a is a dma bus master, and an output when port a is a dma bus slave. this signal pulses once for every dma transfer into or out of port a. the reset state of this pin is high impedance. acsn o port a peripheral chip select pin. this signal pulses low during read and write accesses to registers to a peripheral chip connected to port a. the reset state of this pin is high voltage. awe i/o port a write enable pin, with programmable polarity. this pin pulses during each dma transfer into port a. awe is an input pin when port a is a dma bus master, and is used by an external dma bus slave to strobe data into port a. awe is an output pin when port a is a dma bus slave, and is used to enable an external dma bus master's data output drivers. this pin can be enabled/ disabled with the awe enable bit in port a control 0 register. the reset state of this pin is high impedance. aoe i/o port a output enable pin, with programmable polarity. this pin pulses during each dma transfer out of port a. aoe is an input pin when port a is a dma bus master, and is used by an external dma bus slave to enable port a data output drivers. aoe is an output pin when port a is a dma bus slave, and is used to latch data into an external dma bus master. this pin can be enabled/ disabled with the aoe enable bit in port a control 0 register. the reset state of this pin is high impedance. da[15:0] i/o port a bidirectional data bus. these pins have internal 10k ohm pullup resistors, which are enabled by the enable da pullup bit in port a control 0 register. when port a is in 16 bit mode, data is transferred on da[15:0]. in reference to a byte ordered data flow, the first byte is transferred on da[7:0] and the second byte on da[15:8]. when port a is in 8 bit mode, data is transferred on da[7:0]. the reset state of these pins has the output drivers tristated, and the internal pullup resistors disabled. dapty[1:0] i/o bidirectional parity bits for the da[15:0] bus. parity can be enabled/disabled, and odd/even parity programmed through port a control 1 register. dapty[1] provides parity for the da[15:8] bus. dapty[0] provides parity for the da[7:0] bus. if port a parity is disabled, these pins are always tristated. these pins have an internal 10k ohm pullup resistors, which are enabled with the enable dapty pullup bit in port a control 0 register. the reset state of these pins is high impedance, with the internal pullup resistors disabled.
ps3210b-1299 page 27 of 45 advanced hardware architectures, inc. 4.3 port b interface name type description dreqb i/o port b dma request pin, with programmable polarity. this pin is an output when port b is a dma bus master, and an input when port b is a dma bus slave. this signal pulses once for every dma transfer into or out of port b in master mode. this signal may be held active for multiple transfers in slave mode. the reset state of this pin is high impedance. dackb i/o port b dma channel dma acknowledge pin, with programmable polarity. this pin is an input when port b is a dma bus master, and an output when port b is a dma bus slave. this signal pulses once for every dma transfer into or out of port b. the reset state of this pin is high impedance. bwe i/o port b write enable pin, with programmable polarity. this pin pulses during each dma transfer into port b. bwe is an input pin when port b is a dma bus master, and is used by an external dma bus slave to strobe data into port b. bwe is an output pin when port b is a dma bus slave, and is used to enable an external dma bus master's data output drivers. this pin can be enabled/ disabled with the bwe enable bit in port b control 0 register. the reset state of this pin is high impedance. boe i/o port b output enable pin, with programmable polarity. this pin pulses during each dma transfer out of port b. boe is an input pin when port b is a dma bus master, and is used by an external dma bus slave to enable port b data output drivers. boe is an output pin when port b is a dma bus slave, and is used to latch data into an external dma bus master. this pin can be enabled/ disabled with the boe enable bit in port b control 0 register. the reset state of this pin is high impedance. db[15:0] i/o port b bidirectional data bus. these pins have internal 10k ohm pullup resistors, which are enabled by the enable db pullup bit in port b control 0 register. when port b is in 16 bit mode, data is transferred on db[15:0]. in reference to a byte ordered data flow, the first byte is transferred on db[7:0] and the second byte on db[15:8]. when port b is in 8 bit mode, data is transferred on db[7:0]. the reset state of these pins has the output drivers tristated, and the internal pullup resistors disabled. dbpty[1:0] i/o bidirectional parity bits for the db[15:0] bus. parity can be enabled/disabled, and odd/even parity programmed through port b control 1 register. dbpty[1] provides parity for the db[15:8] bus. dapty[0] provides parity for the db[7:0] bus. if port b parity is disabled, these pins are always tristated. these pins have an internal 10k ohm pullup resistors, which are enabled with the enable dbpty pullup bit in port b control 0 register. the reset state of these pins is high impedance, with the internal pullup resistors disabled.
page 28 of 45 ps3210b-1299 advanced hardware architectures, inc. 5.0 pinout figure 11: pinout diagram AHA3210B-020 pqc 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 31 tm 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 db[7] dbpty[0] gnd db[8] vdd gnd db[9] db[10] vdd db[11] gnd db[12] db[13] db[14] db[15] dbpty[1] vdd gnd dreqb dackb bwe boe vdd gnd a[0] a[1] a[2] a[3] a[4] csn gnd da[8] da[9] da[10] vdd vdd gnd da[11] gnd da[12] da[13] da[14] da[15] dapty[1] clk vdd vdd gnd gnd dreqa dacka awe aoe acsn gnd vdd d[7] d[6] d[5] d[4] d[3] d[2] d[1] gnd vdd d[0] intn/int dtackn/ready vdd gnd resetn test[3] test[2] test[1] test[0] tristaten procmode portacsn dsn/iordn rwn/iowrn dapty[0] da[7] da[6] vdd da[5] gnd da[4] da[3] da[2] da[1] da[0] db[0] db[1] db[2] db[3] db[4] gnd db[5] vdd db[6]
ps3210b-1299 page 29 of 45 advanced hardware architectures, inc. 6.0 electrical specifications 6.1 absolute maximum ratings absolute maximum voltage ratings are for voltage excursions which are transitory in nature. 6.2 recommended operating conditions 6.2.1 dc specifications 6.2.2 ac specifications symbol parameter min max units vdd power supply voltage 7.0 volts vpin voltage applied to any pin -0.5 7.0 volts symbol parameter min max units vdd power supply voltage 4.75 5.25 volts ta operating temperature 0 70 degrees c symbol parameter conditions min max units vil input low voltage clk all other inputs 0.8 volts vih input high voltage clk all other inputs 2.0 volts vol all output low voltage iol = 4.0 mamps 0.4 volts voh output high voltage ioh = 4.0 mamps 2.4 volts iil input low current vin = 0 volts -10 m amps iih input high current vin = vdd volts 10 m amps iozl output tristate low current vout 0 volts 10 m amps iozh output tristate high current vout vdd volts -10 m amps idd active idd current, compression compression, cr=1:1 200 mamps idd active idd current, decompression decompression, cr=1:1 150 mamps idd supply current (static) 1.0 mamps idd standby current chip paused, 20 mhz clock 20 mamps iol dtackn/ready, intn/int all other inputs 8 4 mamps ioh dtackn/ready, intn/int all other inputs 8 4 mamps pin names maximum capacitive load dtackn/ready, d[7:0], intn/int 50 pf dreqa, dacka, aoe, da[15:0], dapty[1:0], acsn, dreqb, dackb, boe, bwe, db[15:0], dbpty[1:0] 50 pf
page 30 of 45 ps3210b-1299 advanced hardware architectures, inc. 6.2.3 pin capacitance figure 12: dynamic current - idd vs. compression ratio symbol parameter max units cin input capacitance 10 pf cout output capacitance 10 pf cio i/o capacitance 10 pf 200.0 180.0 160.0 140.0 120.0 100.0 0.0 5.0 10.0 15.0 compression - 20 mhz clock, vdd = 5.0v idd (ma) comp ratio
ps3210b-1299 page 31 of 45 advanced hardware architectures, inc. 7.0 timing specifications figure 13: clock timing table 8: clock timing specification notes: 1) all ac timings are referenced to 1.4 volts. 2) rise and fall times are between 0.6 volts and 2.4 volts. 3) refer to aha application brief (abdc15-0798) AHA3210B clock specification clarification for rise/fall conditions. figure 14: reset timing - power up refer to table 9 for timing specification figure 15: reset timing table 9: reset timing specifications notes: 1) the resetn signal can be asynchronous to the clk signal. it is internally synchronized to the rising edge of clk. 2) resetn signal must stay low until a minimum of 5 clocks occur. see figure 14. number parameter min max units notes 1 clk period 50 nsec 1 2 clk low pulsewidth 20 nsec 1 3 clk high pulsewidth 20 nsec 1 4 clk rise time 5 nsec 2, 3 5 clk fall time 5 nsec 2, 3 number parameter min max units notes 1 resetn low pulsewidth 5 clocks 2 resetn setup to clk rise 10 nsec 1 3 resetn power up period 5 clocks 2 4 5 3 2 1 clock clk resetn 3 clk resetn 1 2 2
page 32 of 45 ps3210b-1299 advanced hardware architectures, inc. figure 16: processor read cycle - dsn, rwn controlled table 10: processor read cycle timings - dsn, rwn controlled notes: 1) csn, dsn/iordn and rwn/iowrn are assumed to be asynchronous with respect to the AHA3210B clock. these signals are synchronized internally to the AHA3210B clock to drive internal state machines. 2) csn may be held low during back-to-back register access cycles. 3) if a strobe to clock setup is missed at the beginning of an access cycle, then the access cycle begins on the following clock cycle at which the specification is met. 4) if a strobe to clock setup is missed at the end of an access cycle, then the access cycle terminator is delayed until the low to high transition of the strobe meets the specified setup time. number parameter min max units 1 csn, dsn/iordn, rwn/iowrn and a[4:0] setup to clk rise 10 ns 2 clk rise to d[7:0] valid and dtackn/ready low 0 20 ns 3 csn hold from dsn/iordn high 0 ns 4 rwn/iowrn hold from dsn/iordn high 0 ns 5 a[4:0] hold from dsn/iordn high 0 ns 6 dsn/iordn high to d[7:0] and dtackn/ready high-z 0 20 ns t5 t0 t1 t2 t3 t4 t5 1 3 1 1 1 4 1 5 2 6 2 6 clk csn dsn/iordn rwn/iowrn a[4:0] d[7:0] dtackn/ready tristate tristate tristate tristate
ps3210b-1299 page 33 of 45 advanced hardware architectures, inc. figure 17: processor write cycle - dsn, rwn controlled table 11: processor write cycle timings - dsn, rwn controlled notes: 1) csn, dsn/iordn and rwn/iowrn are assumed to be asynchronous with respect to the AHA3210B clock. these signals are synchronized internally to the AHA3210B clock to drive internal state machines. 2) csn may be held low during back-to-back register access cycles. 3) if a strobe to clock setup is missed at the beginning of an access cycle, then the access cycle begins on the following clock cycle at which the specification is met. 4) if a strobe to clock setup is missed at the end of an access cycle, then the access cycle terminator is delayed until the low to high transition of the strobe meets the specified setup time. number parameter min max units 1 csn, dsn/iordn, rwn/iowrn, a[4:0] and d[7:0] setup to clk rise 10 ns 2 clk rise to dtackn/ready low 0 20 ns 3 csn hold from dsn/iordn high 0 ns 4 rwn/iowrn hold from dsn/iordn high 0 ns 5 a[4:0] hold from dsn/iordn high 0 ns 6 dsn/iordn high to dtackn/ready high-z 0 20 ns 7 d[7:0] hold from dsn/iordn high 0 ns t5 t0 t1 t3 t4 t5 1 3 1 1 1 4 1 5 1 7 2 6 clk csn dsn/iordn rwn/iowrn a[4:0] d[7:0] dtackn/ready t2 tristate tristate tristate tristate
page 34 of 45 ps3210b-1299 advanced hardware architectures, inc. figure 18: processor read cycle - iordn controlled table 12: processor read cycle timings - iordn controlled notes: 1) csn and dsn/iordn are assumed to be asynchronous with respect to the AHA3210B clock. these signals are synchronized internally to the AHA3210B clock to drive internal state machines. 2) csn may be held low during back-to-back register access cycles. 3) if a strobe to clock setup is missed at the beginning of an access cycle, then the access cycle begins on the following clock cycle at which the specification is met. 4) if a strobe to clock setup is missed at the end of an access cycle, then the access cycle terminator is delayed until the low to high transition of the strobe meets the specified setup time. number parameter min max units 1 csn, dsn/iordn and a[4:0] setup to clk rise 10 ns 2 csn and dsn/iordn low to dtackn/ready low; clk rise to d[7:0] valid and dtackn/ready high 020ns 3 csn hold from dsn/iordn high 0 ns 4 a[4:0] hold from dsn/iordn high 0 ns 5 dsn/iordn high to d[7:0] and dtackn/ready high-z 0 20 ns t5 t0 t1 t2 t3 t4 t5 1 3 1 1 1 4 2 5 2 2 5 clk csn dsn/iordn rwn/iowrn a[4:0] d[7:0] dtackn/ready tristate tristate tristate tristate
ps3210b-1299 page 35 of 45 advanced hardware architectures, inc. figure 19: processor write cycle - iowrn controlled table 13: processor write cycle timings - iowrn controlled notes: 1) csn and rwn/iowrn are assumed to be asynchronous with respect to the AHA3210B clock. these signals are synchronized internally to the AHA3210B clock to drive internal state machines. 2) csn may be held low during back-to-back register access cycles. 3) if a strobe to clock setup is missed at the beginning of an access cycle, then the access cycle begins on the following clock cycle at which the specification is met. 4) if a strobe to clock setup is missed at the end of an access cycle, then the access cycle terminator is delayed until the low to high transition of the strobe meets the specified setup time. number parameter min max units 1 csn, rwn/iowrn, a[4:0] and d[7:0] setup to clk rise 10 ns 2 csn and rwn/iowrn low to dtackn/ready low; clk rise to dtackn/ready high 020ns 3 csn hold from rwn/iowrn high 0 ns 4 a[4:0] hold from rwn/iowrn high 0 ns 5 d[7:0] hold from rwn/iowrn high 0 ns 6 rwn/iowrn high to dtackn/ready high-z 0 20 ns t5 t0 t1 t3 t4 t5 1 3 1 1 1 4 1 5 2 2 6 clk csn dsn/iordn rwn/iowrn a[4:0] d[7:0] dtackn/ready t2 tristate tristate tristate tristate
page 36 of 45 ps3210b-1299 advanced hardware architectures, inc. figure 20: processor read cycle from port a peripheral - dsn, rwn controlled table 14: processor read cycle timings from port a peripheral - dsn, rwn controlled notes: 1) portacsn, dsn/iordn and rwn/iowrn are assumed to be asynchronous with respect to the AHA3210B clock. these signals are synchronized internally to the AHA3210B clock to drive internal state machines. 2) portacsn may be held low during back-to-back register access cycles. 3) if a strobe to clock setup is missed at the beginning of an access cycle, then the access cycle begins on the following clock cycle at which the specification is met. 4) if a strobe to clock setup is missed at the end of an access cycle, then the access cycle terminator is delayed until the low to high transition of the strobe meets the specified setup time. number parameter min max units 1 portacsn, dsn/iordn, rwn/iowrn and a[4:0] setup to clk rise 10 ns 2 clk rise to d[7:0] valid and dtackn/ready low 0 20 ns 3 portacsn hold from dsn/iordn high 0 ns 4 rwn/iowrn hold from dsn/iordn high 0 ns 5 a[4:0] hold from dsn/iordn high 0 ns 6 dsn/iordn high to d[7:0] and dtackn/ready high-z 0 20 ns 7 clk rise to acsn/awe valid 25 ns 8 da[7:0] setup to clk fall 5 ns 9 da[7:0] hold from clk fall 20 ns t6 t0 t1 t2 t3 t4 t5 t6 1 3 1 1 1 4 1 5 8 9 7 7 7 7 2 6 2 6 clk portacsn dsn/iordn rwn/iowrn a[4:0] acsn awe da[7:0] d[7:0] dtackn/ready tristate tristate tristate tristate tristate tristate
ps3210b-1299 page 37 of 45 advanced hardware architectures, inc. figure 21: processor write cycle to port a peripheral - dsn, rwn controlled table 15: processor write cycle to port a peripheral timings - dsn, rwn controlled notes: 1) portacsn, dsn/iordn and rwn/iowrn are assumed to be asynchronous with respect to the AHA3210B clock. these signals are synchronized internally to the AHA3210B clock to drive internal state machines. 2) portacsn may be held low during back-to-back register access cycles. 3) if a strobe to clock setup is missed at the beginning of an access cycle, then the access cycle begins on the following clock cycle at which the specification is met. 4) if a strobe to clock setup is missed at the end of an access cycle, then the access cycle terminator is delayed until the low to high transition of the strobe meets the specified setup time. number parameter min max units 1 portacsn, dsn/iordn, rwn/iowrn, a[4:0] and d[7:0] setup to clk rise 10 ns 2 clk rise to dtackn/ready low 0 20 ns 3 portacsn hold from dsn/iordn high 0 ns 4 rwn/iowrn hold from dsn/iordn high 0 ns 5 a[4:0] hold from dsn/iordn high 0 ns 6 dsn/iordn high to dtackn/ready high-z 0 20 ns 7 d[7:0] hold from dsn/iordn high 0 ns 8 clk rise to acsn/aoe, da[7:0] valid 0 25 ns t6 t0 t1 t2 t3 t4 t5 t6 1 3 1 1 1 4 1 5 1 7 2 6 8 8 8 8 8 8 clk portacsn dsn/iordn rwn/iowrn a[4:0] d[7:0] dtackn/ready acsn aoe da[7:0] tristate tristate tristate tristate tristate tristate
page 38 of 45 ps3210b-1299 advanced hardware architectures, inc. figure 22: processor read cycle from port a peripheral - iordn controlled table 16: processor read cycle from port a peripheral timings - iordn controlled notes: 1) portacsn, dsn/iordn and rwn/iowrn are assumed to be asynchronous with respect to the AHA3210B clock. these signals are synchronized internally to the AHA3210B clock to drive internal state machines. 2) portacsn may be held low during back-to-back register access cycles. 3) if a strobe to clock setup is missed at the beginning of an access cycle, then the access cycle begins on the following clock cycle at which the specification is met. 4) if a strobe to clock setup is missed at the end of an access cycle, then the access cycle terminator is delayed until the low to high transition of the strobe meets the specified setup time. number parameter min max units 1 portacsn, dsn/iordn, rwn/iowrn and a[4:0] setup to clk rise 10 ns 2 portacsn and dsn/iordn low to dtackn/ready low; clk rise to d[7:0] valid and dtackn/ready high 020ns 3 portacsn hold from dsn/iordn high 0 ns 4 rwn/iowrn hold from dsn/iordn high 0 ns 5 a[4:0] hold from dsn/iordn high 0 ns 6 dsn/iordn high to d[7:0] and dtackn/ready high-z 0 20 ns 7 clk rise to acsn/awe valid 25 ns 7 da[7:0] setup to clk fall 5 ns 9 da[7:0] hold from clk fall 20 ns t6 t0 t1 t2 t3 t4 t5 t6 1 3 1 1 1 4 1 5 8 9 7 7 7 7 2 6 2 2 6 clk portacsn dsn/iordn rwn/iowrn a[4:0] acsn awe da[7:0] d[7:0] dtackn/ready tristate tristate tristate tristate tristate tristate
ps3210b-1299 page 39 of 45 advanced hardware architectures, inc. figure 23: processor write cycle to port a peripheral - iowrn controlled table 17: processor write cycle to port a peripheral timings - iowrn controlled notes: 1) portacsn and rwn/iowrn are assumed to be asynchronous with respect to the AHA3210B clock. these signals are synchronized internally to the AHA3210B clock to drive internal state machines. 2) portacsn may be held low during back-to-back register access cycles. 3) if a strobe to clock setup is missed at the beginning of an access cycle, then the access cycle begins on the following clock cycle at which the specification is met. 4) if a strobe to clock setup is missed at the end of an access cycle, then the access cycle terminator is delayed until the low to high transition of the strobe meets the specified setup time. number parameter min max units 1 portacsn, rwn/iowrn, a[4:0] and d[7:0] setup to clk rise 10 ns 2 portacsn and rwn/iowrn low to dtackn/ready low; clk rise to dtackn/ready high 020ns 3 portacsn hold from rwn/iowrn high 0 ns 4 a[4:0] hold from rwn/iowrn high 0 ns 5 d[7:0] hold from rwn/iowrn high 0 ns 6 clk rise to acsn/aoe, da[7:0] valid 0 25 ns 7 rwn/iowrn high to dtackn/ready high-z 0 20 ns t6 t0 t1 t2 t3 t4 t5 t6 1 3 1 1 1 4 1 5 2 2 7 6 6 6 6 6 6 clk portacsn dsn/iordn rwn/iowrn a[4:0] d[7:0] dtackn/ready acsn aoe da[7:0] tristate tristate tristate tristate tristate tristate
page 40 of 45 ps3210b-1299 advanced hardware architectures, inc. figure 24: dma slave transfer timing for data into port a,b table 18: dma slave transfer timing for data into port a,b notes: 1) the dreqa signal can be asynchronous to the clk signal. it is internally synchronized to the rising edge of clk. the dreqa signal is polled at t1. if the setup time number 1 is met, the maximum data transfer rate will be achieved. 2) if the awe pin is programmed to be disabled, the pin will be tristated. port a and port b have the same timing for their dma interfaces. for port b specifications, substitute the port b name for the corresponding port a name. the timing diagram is for a transfer of two consecutive dma cycles. the signals dacka, and awe are chip outputs. dreqa, dapty[1:0] and da[15:0] are chip inputs. dreqa, dacka, awe are programmed to be active high. number parameter min max units notes 1 dreqa valid setup to clk rise 5 nsec 1 2 clk rise to dacka valid 0 25 nsec 3 clk rise to awe valid 0 25 nsec 2 4 da[15:0], dapty[1:0] setup to clk fall 5 nsec 5 da[15:0], dapty[1:0] hold from clk fall 20 nsec clk dreqa 4 t1 t2 t3 t4 t1 t2 t3 t4 t1 data0 data1 5 3 4 5 3 222 33 2 1 1 dacka awe da[15:0] dapty[1:0] clk dreqb dackb bwe db[15:0] dbpty[1:0] tristate tristate
ps3210b-1299 page 41 of 45 advanced hardware architectures, inc. figure 25: dma slave transfer timing for data out of port a,b table 19: dma slave transfer timing for data out of port a,b notes: 1) the dreqa signal can be asynchronous to the clk signal. it is internally synchronized to the rising edge of clk. the signal dreqa is polled at t1. if the setup time number 1 is met, the maximum data transfer rate will be achieved. 2) if the aoe pin is programmed to be disabled, the pin will be tristated. 3) if the enable parity bit in port a control 1 register is zero (inactive), the dapty[1:0] pins will always be tristated. 4) this specification has been proven by worst case timing simulations. it is not fully tested in production. port a and port b have the same timing for their dma interfaces. for port b specifications, substitute the port b name for the corresponding port a name. the timing diagram is for a transfer of two consecutive dma cycles. the signals dacka, aoe, dapty[1:0], and da[15:0] are chip outputs. dreqa is a chip input. dreqa, dacka, aoe are programmed to be active high. number parameter min max units notes 1 dreqa valid setup to clk rise 5 nsec 1 2 clk rise to dacka valid 0 25 nsec 3 clk rise to aoe valid 0 25 nsec 2 4 clk rise to da[15:0], dapty[1:0] valid 0 25 nsec 3 5 clk rise to da[15:0], dapty[1:0] tristate 0 25 nsec 3, 4 clk dreqa t1 t2 t3 t4 t1 t2 t3 t4 t1 data0 data1 3 3 222 33 2 1 1 dacka aoe da[15:0] dapty[1:0] clk dreqb dackb boe db[15:0] dbpty[1:0] 5 5 4 4 tristate
page 42 of 45 ps3210b-1299 advanced hardware architectures, inc. figure 26: dma master transfer timing for data into port a,b table 20: dma master transfer timing for data into port a,b notes: 1) the dacka signal can be asynchronous to the clk signal. it is internally synchronized to the rising edge of clk. if the setup time number 4 is met at t3, the maximum data transfer rate will be achieved. 2) if the awe pin is programmed to be disabled, substitute the dacka pin for the awe pin in the timing specifications. 3) if awe is used as an input to the AHA3210B part it may be valid only during dacka valid. this restriction also applies to bwe being valid during dackb. port a and port b have the same timing for their dma interfaces. for port b specifications, substitute the port b name for the corresponding port a name. the signal dreqa is a chip output. dacka, awe, dapty[1:0] and da[15:0] are chip inputs. dreqa, dacka, awe are programmed to be active high. number parameter min max units notes 1 clk rise to dreqa high 0 25 nsec 2 dreqa high to dacka high 0 nsec 3 dacka high to dreqa low 0 25 nsec 4 dacka low setup to clk rise 5 nsec 1 5 dacka high pulsewidth 25 nsec 6 dacka high to awe high 0 nsec 7 awe high pulsewidth 25 nsec 8 awe low to dacka low 0 nsec 9 da[15:0], dapty[1:0] setup to awe fall 10 nsec 2 10 da[15:0], dapty[1:0] hold from awe fall 10 nsec 2 clk dreqa t1 t2 t3 t4 valid dacka awe da[15:0] dapty[1:0] clk dreqb dackb bwe db[15:0] dbpty[1:0] 1 1 3 5 2 4 6 78 9 10 tristate tristate
ps3210b-1299 page 43 of 45 advanced hardware architectures, inc. figure 27: dma master transfer timing for data out of port a,b table 21: dma master transfer timing for data out of port a,b notes: 1) the dacka signal can be asynchronous to the clk signal. it is internally synchronized to the rising edge of clk. if the setup time number 4 is met at t3, the maximum data transfer rate will be achieved. 2) if the aoe pin is programmed to be disabled, substitute the dacka pin for the aoe pin in the timing specifications. port a and port b have the same timing for their dma interfaces. for port b specifications, substitute the port b name for the corresponding port a name. the signals dreqa, dapty[1:0], and da[15:0] are chip outputs. dacka, aoe, are chip inputs. dreqa, dacka, aoe are programmed to be active high. number parameter min max units notes 1 clk rise to dreqa high 0 25 nsec 2 dreqa high to dacka high 0 nsec 3 dacka high to dreqa low 0 25 nsec 4 dacka low setup to clk rise 5 nsec 1 5 dacka high pulsewidth 25 nsec 6 dacka high to aoe high 0 nsec 7 dacka low to aoe low 50 nsec 8 aoe high to da[15:0], dapty[1:0] valid 0 25 nsec 2 9 aoe low to da[15:0], dapty[1:0] tristate 0 25 nsec 2 clk dreqa t1 t2 t3 t4 valid dacka aoe da[15:0] dapty[1:0] clk dreqb dackb boe db[15:0] dbpty[1:0] 1 1 3 5 2 4 6 7 9 8 tristate tristate
page 44 of 45 ps3210b-1299 advanced hardware architectures, inc. 8.0 packaging figure 28: AHA3210B package specifications notes: all dimensions are in millimeters package type is 100 pin quad flat pack AHA3210B chip dimensions ab cd e f g h i j 12.35 14.00.1 17.90.4 18.85 20.00.1 23.90.4 0.650.12 0.150.050 0.30.1 2.750.10 AHA3210B-020 pqc tm a b c d e f g h i j
ps3210b-1299 page 45 of 45 advanced hardware architectures, inc. 9.0 ordering information 9.1 available parts 9.2 part numbering device number: 3210 revision letter: b package material codes: p plastic package type codes: q q - quad flat pack test specifications: ccommercial0 c to +70 c 10.0 aha related technical publications part number description AHA3210B-020 pqc 10 mbytes/sec dclz data compression coprocessor ic aha 3210 b- 020 p q c manufacturer device number revision level speed designation package material package type test specification document # description abdc02 aha application brief C dclz software licensing procedure abdc05 aha application brief C interfacing requirements to cmos devices abdc07 aha application brief C compression optimization in aha3101 and aha3210 systems abstd1 aha application brief C aha data compression and forward error correction standards andc01 aha application note C primer: data compression lempel ziv (dclz) andc04 aha application note C data management for the AHA3210B andc05 aha application note C AHA3210B designers guide andc07 aha application note C dclz evaluation software andc09 aha application note C error detection and recovery in data compression system using AHA3210B andc10 aha application note C compression performance: dclz algorithm on the calgary corpus glgen1 general glossary of terms pb3101 aha3101 product brief C dclz 2.5 mbytes/sec data compression coprocessor ic pb3210b AHA3210B product brief C dclz 10 mbytes/sec data compression coprocessor ic ps3101 aha3101 product specification C dclz 2.5 mbytes/sec data compression coprocessor ic raecma-0791 dclz emerges as an open data compression standard, article reprint computer technology review , summer 1991 dceval dclz evaluation software (windows ? 3.1)

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