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ps3520-1098 the data coding leader advanced hardware architectures tm advanced hardware architectures, inc. 2365 ne hopkins court pullman, wa 99163-5601 509.334.1000 fax: 509.334.9000 e-mail: sales@aha.com http://www.aha.com product specification AHA3520 20 mbytes/sec aldc data compression coprocessor ic
advanced hardware architectures, inc. ps3520-1098 i table of contents 1.0 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 conventions, notations and definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4.1 port a and port b interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4.2 fifo operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4.3 data expansion during compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.0 compression operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 compression pass through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.0 decompression operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 decompression pass through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.3 decompression output disabled mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.0 microprocessor interface and register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.1 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.1.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.1.2 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.2 register access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.3 pausing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.0 port a and port b configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.0 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.1 status 0 (stat0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 port a configuration 0 (acnf0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.3 port a configuration 1 (acnf1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.4 port b configuration 0 (bcnf0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.5 port b configuration 1 (bcnf1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.6 identification (id) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.7 port a polarity (apol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.8 port b polarity (bpol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.9 port a transfer count (atc0, atc1, atc2, atc3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.10 port b transfer count (btc0, btc1, btc2, btc3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.11 error status (errs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.12 interrupt status (ints) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.13 command (cmnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.14 transfer size (ts0, ts1, ts2, ts3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.15 data disabled count (ddc0, ddc1, ddc2, ddc3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.16 error mask (emsk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.17 interrupt mask (imsk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.0 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2 port a interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.3 port b interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.0 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.0 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.1 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.3 dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
advanced hardware architectures, inc. ii ps3520-1098 10.0 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11.0 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 12.0 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12.1 available parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12.2 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 13.0 aha related technical publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
advanced hardware architectures, inc. ps3520-1098 iii figures figure 1: functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2: pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 3: clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 4: reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 5: almost full/almost empty timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 6: processor read timing, mmode = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7: processor write timing, mmode = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8: processor read timing, mmode = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9: processor write timing, mmode = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10: port a/b timing, four edge, master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11: port a/b timing, four edge, slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 12: port a/b timing, burst, master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13: port a/b timing, burst, slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14: peripheral access read timing, mmode = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15: peripheral access write timing, mmode = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 16: peripheral access read timing, mmode = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 17: peripheral access write timing, mmode = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 18: AHA3520 pqfp package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
advanced hardware architectures, inc. iv ps3520-1098 ta b l e s table 1: microprocessor interface control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2: port a interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3: port b interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 4: clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 5: reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6: almost full/almost empty timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7: processor read timing, mmode = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8: processor write timing, mmode = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9: processor read timing, mmode = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10: processor write timing, mmode = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11: port a/b timing, four edge, master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12: port a/b timing, four edge, slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 13: port a/b timing, burst, master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 14: port a/b timing, burst, slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 15: peripheral access read timing, mmode = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 16: peripheral access write timing, mmode = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 17: peripheral access read timing, mmode = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 18: peripheral access write timing, mmode = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 19: pqfp (plastic quad flat pack) 14 mm 20 mm package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . 34
ps3520-1098 page 1 of 35 advanced hardware architectures, inc. 1.0 introduction AHA3520 is a single chip lossless compression and decompression integrated circuit implementing the industry standard adaptive lossless data compression algorithm, also known as aldc. the device compresses, decompresses or passes through data unchanged depending on the operating mode selected. this device achieves an average compression ratio of 2:1 on typical computer files. the flexible hardware interface makes this part suitable for many applications. aha 3520 is algorithm and pinout compatible to the ibm aldc device. compressed files between aha and ibms implementation of the algorithm do not always produce the same compressed code stream. however, the decompressed results are always the same. files compressed on either device can be interchanged and decompressed on either device. content addressable memory (cam) within the compression/decompression engine eliminates the need for external srams. this part connects directly to industry standard peripheral chips. included in this specification is a functional overview, operation modes, register descriptions, dc and ac electrical characteristics, ordering information, and a listing of related technical publications. it is intended for hardware and software engineers designing a compression system using AHA3520. aha designs and develops lossless compression, forward error correction and data storage formatter/controller ics. other aldc product offering includes aha3521. this is a pin and firmware compatible device that includes additional features. technical publications are available upon request. 1.1 conventions, notations and definitions - active low signals have an n appended to the end of the signal name. for example, csn and writen. - signal assertion means the output signal is logically true. - hex values are represented with a prefix of 0x, such as register 0x00. binary values do not contain a prefix, for example, mmode = 1. - a prefix or suffix of x indicates a letter missing in a register name or signal name. for example, xcnf0 refers to the acnf0 or bcnf0 register. - a range of signal names or register bits is denoted by a set of colons between the numbers. most significant bit is always shown first, followed by least significant bit. for example, mdata[7:0] indicates signal names mdata7 through mdata0. - mega bytes per second is referred to as mbytes/ sec or mb/sec. - reserved bits in registers are referred as res . 1.2 features performance: ? 20 mb/s data compression, decompression or pass-through rate with a single 40 mhz clock ? 2:1 average compression ratio ? a four byte transfer size register allows block transfers up to 4 gigabytes ? error checking in decompression mode reportable via an interrupt flexibility: ? in-line and look-aside architectures supported ? polled or interrupt driven i/o ? two independent dma ports programmable for 8 or 16-bit transfers, handshaking modes and master or slave operation ? programmable polarity for dma control signals system interface: ? single chip data compression solution ? two selectable microprocessor interfaces ? programmable interrupts ? interfaces directly with the aha5140 tape formatter and industry standard scsi chips others: ? open standard aldc adaptive lossless compression algorithm ? complies to qic-154, ecma 222, ansi x3.280-1996 and iso 15200 standard specifications ? compatible to ibm aldc1-20s-ha specification ? 100 pin package in 14 20 mm pqfp 1.3 applications ? qic or 8 mm tape drives 1.4 functional description AHA3520 is a compression/decompression device residing between the host interface, usually scsi, and the buffer manager asic. major blocks in this device are the microprocessor interface, port a interface, port b interface, and the compression/ decompression engine. the microprocessor interface provides status and control information by register access. port a and port b interfaces are dma ports configurable for bus width, polarity, handshaking modes, and other options. the
page 2 of 35 ps3520-1098 advanced hardware architectures, inc. operating mode establishes the direction of both the port a and port b interfaces. compression or compression pass through sets the port a interface as an input and the port b interface as an output. conversely decompression or decompression pass through sets the port a interface as an output and the port b interface as an input. decompression output disabled mode allows the device to decompress a block of data up to a predetermined point while dumping the uncompressed data, then automatically begin outputting the remaining uncompressed data in that block or record. a four byte transfer size counter allows the user to partition the data into blocks of four gigabytes or less to process. compression pass through mode and decompression pass through modes allow data transfers through the device without changing the data. both the port a interface and port b interface have a 16-byte fifo with almost empty and almost full signal pins and programmable thresholds. both dma interfaces, port a and port b, have programmable wait states in addition to four selectable dma transfer modes: asynchronous request/acknowledge pair, asynchronous burst mode, and two peripheral access modes that correlate with the two microprocessor modes. 1.4.1 port a and port b interfaces both port a and port b interfaces are independently configurable via the port a configuration registers (acnfx), the port a polarity register (apol), the port b configuration registers (bcnfx), and the port b polarity register (bpol). both operate in four dma modes. four-edge mode is an asynchronous data transfer requiring a request and acknowledge pulse for each transfer of one or two bytes, depending on the width configuration of the interface. a four edge transfer begins by asserting the request signal, followed by the acknowledge in response to the request, which causes the request to deassert, and finally this causes the acknowledge to deassert. data is transferred on the trailing edge of the acknowledge signal. burst mode is similar to four-edge mode except there may be many acknowledges while the request is held asserted. the advantage of this mode is that it requires fewer clocks per transfer. two peripheral access modes exist and are selected via the mmode pin. peripheral access allows the microprocessor to write to and read from a peripheral device connected to the port a interface or port b interface. this mode is a relatively slow, asynchronous transfer. this mode is not allowed during a data transfer operation. 1.4.2 fifo operation port a and port b interfaces both contain sixteen-byte fifos with programmable thresholds. AHA3520 has an almost full and an almost empty signal pin associated with each of the data interfaces. the fifo thresholds are programmed in the configuration registers (acnf0 and bcnf0). if the data interface is configured for either four-edge or burst mode of operation the fifo threshold determines when request gets asserted and deasserted. during an output transfer the request signal asserts when the number of bytes in the fifo is greater than or equal to the programmed fifo threshold. the interface continues to request data transfers until the fifo becomes empty. when transferring data into either the port a or port b interfaces, the request signal asserts when the number of empty byte locations in the fifo is greater than or equal to the programmed fifo threshold. the interface continues to request data transfers until the fifo is full. the almost full (xaf) and almost empty (xae) signals are always available to the user. almost full can be used as an early warning indicator to stop transferring data into the port b interface or port a interface. the xae signal can be used to stop transfers out of the port a interface or port b interface the xaf signal deasserts when a transfer operation begins. it asserts the clock after the number of empty byte locations in the fifo is less than or equal to the fifo threshold. the xaf signal deasserts the clock after the number of empty byte locations in the fifo is greater than the fifo threshold. the xae signal asserts when a transfer operation begins. it deasserts the clock after the number of available bytes in the fifo is greater than the fifo threshold. the xae signal asserts after the clock when the number of available bytes in the fifo is less than or equal to the fifo threshold. 1.4.3 data expansion during compression data expansion occurs when the size of the data increases during a compression operation. this typically occurs when the data is compressed prior to input into the chip.the expand status bit is set if the port b transfer count is larger than the transfer size register. if data expansion caused the port b transfer count to exceed its maximum 4-byte value then the btc overflow error status gets set. worst case expansion allowable by the algorithm is 12.5% or (9/8 times the uncompressed transfer size).
ps3520-1098 page 3 of 35 advanced hardware architectures, inc. figure 1: functional block diagram 2.0 compression operation 2.1 compression pass through compression pass through mode allows data to enter the port a interface, transfer through the device unchanged and exit through the port b interface. pass through mode uses the port a transfer counter, port b transfer counter and transfer size register. the done status bit and interrupt (if not masked) are set when the transfer completes. 2.2 compression during compression operation, uncompressed data flows into the port a interface, is compressed by the compression engine and the compressed data transferred out of the port b interface. the device contains a content addressable memory (cam). the cam is the history buffer during compression operation. the compressor appends an end marker control code to the end of the compressed data. it also pads the end of a transfer to a byte boundary with zeroes. end marker control codewords are monitored during decompression, to determine decompression end errors. the compression engine constantly monitors the performance of compression for expansion during compression operation. the expand bit is set if the port b transfer count is larger than the transfer size at the end of a compression operation. when the port b transfer count is higher than the port a transfer count the expand bit in the status 0 register is set indicating data expansion during compression operation. port a interface count increments with each byte received and when this count equals the transfer size, all bytes in this transfer have been received into port a. a compression operation is complete when the last byte transfers out of the port b interface and the port b interface count is zero, thus setting the done status bit and generating a done interrupt if it is not masked. port b transfer counter port a dma state port a transfer counter machine clock generation port b dma state machine interrupt logic processor interface state machine pa s s t h ro u g h controller processor interface aldc engine aparity[1:0] adata[15:0] clock mdata[7:0] port a interface port b interface AHA3520 compression chip acout ard apcs aaf bparity[1:0] bdata[15:0] bcout bcin bpcs baf mcin[1:0] waitn addr[4:0] mmode resetn ireqn ireq awr acin aae bae brd bwr
page 4 of 35 ps3520-1098 advanced hardware architectures, inc. 3.0 decompression operation 3.1 decompression pass through decompression pass through mode allows data to enter the port b interface, transfer through the device unchanged and exit through the port a interface. pass through mode uses the port a transfer counter, port b transfer counter and transfer size register. the done status bit and interrupt (if not masked) are set when the transfer completes. 3.2 decompression during decompression mode, compressed data flows into the port b interface and is decompressed. the resulting uncompressed data is transferred out of the port a interface. the number of compressed bytes in the transfer is programmed into the four byte transfer size register. a decompression operation is complete when the last byte transfers out of the port a interface, thus setting the done status bit and generating a done interrupt if it is not masked. two types of errors are detected and reported during decompression. decoder control coder errors are caused by detection of invalid control codes in the compressed data stream. decoder end errors are detected when either the decompressor encountered an end control code before the expected end of record indicated by the transfer size register, or the end of record was reached according to the transfer size register but no end control code was detected. these errors are reported in the error status register. 3.3 decompression output disabled mode decompressed output disabled mode allows the user to decompress to a point in the record or block and rebuild the history buffer while discarding the uncompressed data. after the point in the file is reached where the user wants the data (port a transfer count is equal or greater than the data disable count), the device switches to normal decompression mode and the remainder of that file is decompressed and transferred out of the port a interface. removal of cbg headers also applies to this mode. 4.0 microprocessor inter- face and register access 4.1 microprocessor interface microprocessor interface configuration is determined by the mmode pin. if mmode is tied high transfers are controlled by a chip select signal (csn) and a read/write signal (rwn), otherwise transfers are controlled by separate read (readn), write (writen) signals. refer to section 10.0 timing specifications for timing diagrams. 4.1.1 interrupts ireq and ireqn are two hardware interrupt signals. ireqn is a negative active open-drain output that requires a pull-up resistor if it is used. ireq is a standard ttl output. when active they indicate an interrupt is set in the device. the microprocessor can determine the cause of the interrupt by reading the interrupt status register. masking individual interrupts with the interrupt mask register disables particular interrupts from causing the interrupt signal pins to assert (ireq and ireqn). they do not disable bits in the interrupt status register. the interrupt signals are reset to their inactive state when either a hardware or software reset occurs, when a data transfer operation resumes, or when a data transfer operation begins. in addition, disabling interrupt mask bits after the interrupt pin is asserted, clears the interrupt and deasserts the interrupt pin. table 1: microprocessor interface control signals pin name mmode tied low mmode tied high mcin[0] readn csn mcin[1] writen rwn wa i t n wa i t n wa i t n addr[0] addr[0] = 0 selects register bits 7:0 addr[0] = 1 selects register bits 15:8 addr[0] = 0 selects register bits 15:8 addr[0] = 1 selects register bits 7:0
ps3520-1098 page 5 of 35 advanced hardware architectures, inc. 4.1.2 resets the AHA3520 has one hardware reset signal and a software reset. when the resetn signal is asserted all registers except the identification registers are reset, current operations are cancelled, and the history buffer is cleared. the software reset via the command register does not affect the configuration registers (acnfx or bcnfx), identification registers (idx), either of the polarity registers (apol or bpol), or the command register (cmnd). all other registers are reset, current operations cancelled and the history buffer cleared. 4.2 register access mmode determines whether addr[0] selects even or odd addressed registers. when mmode is high and addr[0]=0, odd addressed registers are accessible. mmode=1 causes addr[0] input signal to be inverted. the following registers may not be stable if busy is set: status 0 , status 1 , port a transfer count , port b transfer count , error status , interrupt status and fifo access . 4.3 pausing when a pause command is issued, the device pauses at the next break in the dma handshaking. when a port is in slave mode, it pauses after xcout (dackx) deasserts. when a port is in master mode and xcout (dreqx) is asserted, the port does not pause until xcin (dackx) is recieved from the external dma device. the AHA3520 waits until both ports are paused, at which time the busy status bit clears and the paused status bit and interrupt are set. 5.0 port a and port b configuration port a and port b operate identically. they both are 16-bit bidirectional data ports with parity checking and generation. there are three configuration registers associated with each port and a polarity register that determines the polarity of all of the control signals for that port. the function of the control pin is determined by either xcnf0[13, 12] bits or command register programmed for peripheral access. the polarity of control signals are controlled by specific bits in the polarity registers. table 2: port a interface signals table 3: port b interface signals signal name master slave=0 slave slave=1 apol bit direction acin dacka dreqa 7 i acout dreqa dacka 5 o awr deasserted awr 4 o ard deasserted ard 3 o apcs apcs apcs 2 o aaf aaf aaf 1 o aae aae aae 0 o signal name master slave=0 slave slave=1 bpol bit direction bcin dackb dreqb 7 i bcout dreqb dackb 5 o bwr deasserted bwr 4 o brd deasserted brd 3 o bpcs bpcs bpcs 2 o baf baf baf 1 o bae bae bae 0 o
page 6 of 35 ps3520-1098 advanced hardware architectures, inc. 6.0 register description notes: 1) when cmnd is not a selection command. 2) when cmnd is a select port a configuration command. 3) when cmnd is a select port b configuration command. 4) when cmnd is any transfer command or select port a configuration command. 5) when cmnd is any transfer command or select port b configuration command. addr[4:0] mnemonic register name r/w notes register reset value mmode=0 mmode=1 hardware reset reset command new transfer command 0x00 0x01 stat0 status 0 r 1 0x00 0x00 0x80 0x01 0x00 res reserved 0x00 0x01 acnf0 port a configuration 0 r/w 2 0x00 unchanged unchanged 0x01 0x00 acnf1 port a configuration 1 r/w 2 0x00 unchanged unchanged 0x00 0x01 bcnf0 port b configuration 0 r/w 3 0x00 unchanged unchanged 0x01 0x00 bcnf1 port b configuration 1 r/w 3 0x00 unchanged unchanged 0x02 0x03 id identification r 1 0xc1 0xc1 0xc1 0x03 0x02 res reserved 0x02 0x03 apol port a polarity r/w 2 0xff unchanged unchanged 0x03 0x02 res reserved 0x02 0x03 bpol port b polarity r/w 3 0xff unchanged unchanged 0x03 0x02 res reserved 0x04 0x05 atc2 port a transfer count, byte 2 r 4 0x00 0x00 0x00 0x05 0x04 atc3 port a transfer count, byte 3 r 4 0x00 0x00 0x00 0x06 0x07 atc0 port a transfer count, byte 0 r 4 0x00 0x00 0x00 0x07 0x06 atc1 port a transfer count, byte 1 r 4 0x00 0x00 0x00 0x08 0x09 btc2 port b transfer count, byte 2 r 5 0x00 0x00 0x00 0x09 0x08 btc3 port b transfer count, byte 3 r 5 0x00 0x00 0x00 0x0a 0x0b btc0 port b transfer count, byte 0 r 5 0x00 0x00 0x00 0x0b 0x0a btc1 port b transfer count, byte 1 r 5 0x00 0x00 0x00 0x0c 0x0d errs error status r 1 0x00 0x00 0x00 0x0d 0x0c res reserved 1 0x0e 0x0f ints interrupt status r 1 0x00 0x00 0x00 0x0f 0x0e res reserved 0x10 0x11 res reserved 0x11 0x10 cmnd command r/w 0x00 0x00 0x00 0x12 0x13 res reserved 0x13 0x12 res reserved 0x14 0x15 ts2 transfer size, byte 2 r/w 0x00 0x00 unchanged 0x15 0x14 ts3 transfer size, byte 3 r/w 0x00 0x00 unchanged 0x16 0x17 ts0 transfer size, byte 0 r/w 0x00 0x00 unchanged 0x17 0x16 ts1 transfer size, byte 1 r/w 0x00 0x00 unchanged 0x18 0x19 ddc2 data disabled count, byte 2 r/w 0x00 0x00 unchanged 0x19 0x18 ddc3 data disabled count, byte 3 r/w 0x00 0x00 unchanged 0x1a 0x1b ddc0 data disabled count, byte 0 r/w 0x00 0x00 unchanged 0x1b 0x1a ddc1 data disabled count, byte 1 r/w 0x00 0x00 unchanged 0x1c 0x1d emsk error mask r/w 0x00 0x00 unchanged 0x1d 0x1c res reserved 0x1e 0x1f imsk interrupt mask r/w 0x00 0x00 unchanged 0x1f 0x1e res reserved
ps3520-1098 page 7 of 35 advanced hardware architectures, inc. 6.1 status 0 (stat0) read only reset value = 0x00 software reset value = 0x00 busy - busy. this bit is set when a data transfer operation begins. it is cleared when the data transfer operation completes successfully, when an unmasked error occurs, when a reset occurs, or when a paused command is issued by the microprocessor. paused - paused. this bit is set when a data transfer operation is currently paused. it is cleared when a paused data transfer operation is resumed or when a reset occurs. outdis - output disabled. this bit is set when port a interface output is disabled. it is cleared when port a interface output is re-enabled or when a reset occurs. bypass - bypass. this bit is set after a start compression bypass or a start decompression bypass command is written to the command register. it is cleared after a start compression, start decompression or when a reset occurs. expand - expansion. this bit is set when the port b transfer count register is larger than the transfer size register at the end of a compression operation. it is cleared when another data transfer operation begins or when a reset occurs. anyint - any interrupt. this bit is set while an unmasked interrupt is active. this signal mirrors the interrupt signal pin. anyerr - any error. this bit is set when an unmasked error occurs. it is cleared when a data transfer operation begins or when a reset occurs. done - done. this bit is set when the current data transfer operation is complete. it is cleared when a data transfer operation begins or when a reset occurs. 6.2 port a configuration 0 (acnf0) read/write reset value = 0x00 software reset value = unchanged waitst[2:0] -wait state. these bits configure the number of wait states used during a port a interface peripheral access. the values 011 through 111 are valid. fifoth[3:0] -fifo threshold. these bits configure the port a fifo threshold value. values from 0000 through 1111 are valid. mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x00 0x01 busy paused outdis bypass expand anyint anyerr done mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x00 0x01 reserved waitst[2:0] fifoth[3:0]
page 8 of 35 ps3520-1098 advanced hardware architectures, inc. 6.3 port a configuration 1 (acnf1) read/write reset value = 0x00 software reset value = unchanged parity - parity. when set, parity checking is enabled for the adata[15:0] data bus. when cleared, parity checking is disabled for the adata[15:0] bus. odd - odd. setting this bit along with parity enables odd parity checking and generation on the adata[15:0] data bus. when cleared with parity set even parity checking and generation is enabled on the adata[15:0] data bus. slave - slave. when set, the port b interface acts as a slave device and generates acknowledges in response to requests. when cleared, the port b interface acts as a dma master, and generates requests and expects acknowledges. mode[1:0] -dma mode. these bits configure the interface dma mode of the port a interface with values as defined below. wide - two byte. when set, adata[15:0] and parity[1:0] are used. when cleared, ad[7:0] and parity[0] are used. 6.4 port b configuration 0 (bcnf0) read/write reset value = 0x00 software reset value = unchanged waitst[2:0] -wait state. these bits configure the number of wait states used during port a interface peripheral access. the values 001 through 111 are valid. values 000, 001, 010 result in two wait states. fifoth[3:0] -fifo threshold. these bits configure the port a fifo threshold value. values from 0001 through 1111 are valid. a value of 0000 results in the same operation as 0001. mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x01 0x00 parity odd slave mode[1:0] wide reserved mode[1:0] dma type 00 four edge 01 burst 10 reserved 11 reserved mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x00 0x01 reserved waitst[2:0] fifoth[3:0]
ps3520-1098 page 9 of 35 advanced hardware architectures, inc. 6.5 port b configuration 1 (bcnf1) read/write reset value = 0x00 software reset value = unchanged parity - parity. when set, parity checking is enabled for the bdata[15:0] data bus. when cleared, parity checking is disabled for the bdata[15:0] bus. odd - odd. when set, odd parity checking and generation is used on the bdata[15:0] data bus. when cleared, even parity checking and generation is used on the bdata[15:0] data bus. slave - slave. when set, the port b interface acts as a slave device and generates acknowledges in response to requests. when cleared, the port b interface acts as a dma master, and generates requests and expects acknowledges. mode[1:0] -dma mode. these bits configure the interface dma mode of the port b interface with values as defined below. wide - two byte. when set, bdata[15:0] and parity[1:0] are used. when cleared, bd[7:0] and parity[0] are used. 6.6 identification (id) read only value = contact aha applications engineering id[7:0] - the bits of this register correspond to the identification code of the chip. this register is accessible when cmnd is not a selection command. 6.7 port a polarity (apol) read/write reset value = 0xff software reset value = unchanged the bits of this register correspond to port a interface signals. a set bit programs the corresponding signal to be active low. a cleared bit programs the corresponding signal to be active high. this register is only accessible when cmnd is select port a configuration. mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x01 0x00 parity odd slave mode[1:0] wide reserved mode[1:0] dma type 00 four edge 01 burst 10 reserved 11 reserved mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x02 0x03 id[7:0] mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x02 0x03 acin reserved acout awr ard apcs aaf aae
page 10 of 35 ps3520-1098 advanced hardware architectures, inc. 6.8 port b polarity (bpol) read/write reset value = 0xff software reset value = unchanged the bits of this register correspond to port b interface signals. a set bit programs the corresponding signal to be active low. a cleared bit programs the corresponding signal to be active high.this register is only accessible when cmnd is select port b configuration. 6.9 port a transfer count (atc0, atc1, atc2, atc3) read only reset value = 0x00 software reset value = 0x00 atc[31:0] - port a transfer count. these registers provide status information on the number of bytes transferred for a current data transfer operation. during a compression operation, atc is incremented as each original data byte is received by the port a interface. when atc equals ts during compression, all bytes in the compression operation have been received by the AHA3520. during a decompression operation, atc is incremented as each decompressed data byte is sent by the port a interface. this register is only accessible when cmnd is not a selection command. 6.10 port b transfer count (btc0, btc1, btc2, btc3) read only reset value = 0x00 software reset value = 0x00 btc[31:0] -port b transfer count. these registers provide status information on the number of bytes transferred for a current data transfer operation. during a compression operation, btc is incremented as each compressed data byte is sent by the port b interface. during a decompression operation, btc is incremented as each compressed data byte is received by the port b interface. when btc equals ts during decompression, all bytes in the decompression operation have been received by the AHA3520 host interface.this register is only accessible when cmnd is not a selection command. mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x02 0x03 bcin reserved bcout bwr brd bpcs baf bae mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x06 0x07 atc[7:0] 0x07 0x06 atc[15:8] 0x04 0x05 atc[23:16] 0x05 0x04 atc[31:24] mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x00 0x01 btc[7:0] 0x01 0x00 btc[15:8] 0x00 0x01 btc[23:16] 0x01 0x00 btc[31:24]
ps3520-1098 page 11 of 35 advanced hardware architectures, inc. 6.11 error status (errs) read only reset value = 0x00 software reset value = 0x00 the error status register provides error status bits to the microprocessor. this register should only be read when cmnd is not a selection command. these bits are set regardless of the error mask settings. aperr - port a interface parity error. this bit is set when a parity error is detected during a transfer into adata[15:0] and the port a interface parity bit is set. it is cleared when a data transfer operation begins or when a reset occurs. bperr - port b interface parity error. this bit is set when a parity error is detected during a transfer into bdata[15:0] and the port b interface parity bit is set. it is cleared when a data transfer operation begins or when a reset occurs. btco - port b transfer count overflow error. this bit is set when a carry out is detected on the port b transfer count register. it is cleared when a data transfer operation begins or when a reset occurs. atco - port a transfer count overflow error. this bit is set when a carry out is detected on the port a transfer count register. it is cleared when a data transfer operation begins or when a reset occurs. adcc - aldc decoder control code error. this bit is set during decompression when an invalid control code is detected in the compressed data stream. it is cleared when a data transfer operation begins or when a reset occurs. ade - aldc decoder end error. this bit is set during decompression when an end control code is detected while port b transfer count is less than transfer size or when btc equals ts and no end control code is detected in the compressed data stream. it is cleared when a data transfer operation begins or when a reset occurs. 6.12 interrupt status (ints) read only reset value = 0x00 software reset value = 0x00 done - done interrupt. this bit is set when data transfer has completed on the port b interface during compression and when data transfer has completed on the port a interface during decompression. it is cleared when a data transfer operation begins or when a reset occurs. paused - paused interrupt. this bit is set when the current transfer step after the microprocessor issues a pause command is completed. it is cleared when the microprocessor issues a resume command, when a data transfer operation begins, or when a reset occurs. error - error interrupt. this bit is set when an error occurs. it is cleared when a data transfer operation begins or when a reset occurs. the error status register is used to determine the cause of the error. mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x0c 0x0d reserved aperr bperr reserved btco atco adcc ade mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x0e 0x0f done paused reserved error
page 12 of 35 ps3520-1098 advanced hardware architectures, inc. 6.13 command (cmnd) read/write reset value = 0x00 software reset value = 0x00 the command register is used to program the operation of the compression subsystem. cmnd[7:0] -command.this register provides for operation as described in the following table. mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x11 0x10 cmnd[7:0] cmnd[7:0] action selection commands 0xc1 select port a configuration. the port a configuration and port a polarity registers are enabled for reads and writes. 0xc2 select port b configuration. the port b configuration and port b polarity registers are enabled for reads and writes. 0xc4 select port a interface peripheral access. all peripheral access addresses are enabled for reads and writes to a port a interface attached peripheral. 0xc8 select port b interface peripheral access. all peripheral access addresses are enabled for reads and writes to a port b interface attached peripheral. transfer commands (described in sections 2.0 and 3.0) 0x50 start compression bypass. 0x58 start compression. 0x60 start decompression bypass. 0x68 start decompression. 0x6c start decompression output disabled. control commands 0x42 pause. when a data transfer operation is in progress, any current operation steps are completed and the port a interface and port b interface data busses are placed into a high impedance state. the paused interrupt and paused status bits are then set. all data currently being processed by the data transfer operation is preserved. 0x44 resume. a previously paused data transfer operation resumes processing. the paused interrupt and paused status bits are cleared and the busy status bit is set. 0xa0 software reset. the port a configuration , port b configuration , identification , port a polarity , port b polarity , and command registers are not affected by this command. all other registers are reset, current operations are cancelled, and the history buffer is cleared. miscellaneous commands 0x00 nop, no operation is performed.
ps3520-1098 page 13 of 35 advanced hardware architectures, inc. 6.14 transfer size (ts0, ts1, ts2, ts3) read/write reset value = 0x00 software reset value = 0x00 ts[31:0] - transfer size. the transfer size register provides the microprocessor control of the number of bytes transferred during a data transfer operation. the direction of the data transfer operation specifies whether the port a transfer count register or the port b transfer count register is used to determine when all data bytes have been received for the data transfer operation. during compression, atc is used. during decompression, btc is used. when the appropriate transfer count register (atc or btc) equals ts, all bytes in the current data transfer operation have been received by the compression module. 6.15 data disabled count (ddc0, ddc1, ddc2, ddc3) read/write reset value = 0x00 software reset value = 0x00 ddc[31:0] - data disabled count.the data disabled count register provides the microprocessor control of the number of bytes skipped during a start decompression output disabled operation. if the data disabled count is set to 0x00 during a start decompression output disabled operation or the ddc is greater than the transfer size (ts) during a start decompression output disabled operation, then the port a interface output is disabled for the entire transfer. mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x16 0x17 ts[7:0] 0x17 0x16 ts[15:8] 0x14 0x15 ts[23:16] 0x15 0x14 ts[31:24] mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x1a 0x1b ddc[7:0] 0x1b 0x1a ddc[15:8] 0x18 0x19 ddc[23:16] 0x19 0x18 ddc[31:24]
page 14 of 35 ps3520-1098 advanced hardware architectures, inc. 6.16 error mask (emsk) read/write reset value = 0x00 software reset value = 0x00 the error mask register provides error reporting configuration to the microprocessor. if an unmasked error status bit is active, anyerr status and error interrupts are set. aperrm -port a interface parity error mask. bperrm - port b interface parity error mask. btcom - port b transfer count overflow error mask. atcom - port a transfer count overflow error mask. adcom - aldc decoder control code error mask. adem - aldc decoder end error mask. 6.17 interrupt mask (imsk) read/write reset value = 0x00 software reset value = 0x00 the interrupt mask register masks the individual interrupts allowing the user to control which ones may cause the interrupt signal pins (ireq or ireqn) to assert. for example, if done and paused are set with error cleared, only an error interrupt will cause the interrupt signal pins to assert. donem - done interrupt mask. pausedm -paused interrupt mask. errorm -error interrupt mask. mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x1c 0x1d reserved aperrm bperrm reserved btcom atcom adcom adem mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x1e 0x1f donem pausedm reserved errorm
ps3520-1098 page 15 of 35 advanced hardware architectures, inc. 7.0 signal descriptions this section contains descriptions for all the pins. each signal has a type code associated with it. the type codes are described in the following table. 7.1 microprocessor interface type code description i input only pin o output only pin i/o input/output pin microprocessor interface signal type description default after reset mdata[7:0] i/o microprocessor data bus hi-z mcin[0] i microprocessor interface control pin [0]. if mmode is high this pin is csn. if mmode is low this pin is readn. input mcin[1] i microprocessor interface control pin [1]. if mmode is high this pin is rwn. if mmode is low this pin is writen. input wa i t n o microprocessor output signal. waitn is driven during csn and then goes to tristate with a resistive pullup. high (internal pullup) addr[4:0] i microprocessor interface address bus, used to select internal registers. input mmode i microprocessor interface mode selector pin. input resetn i hardware reset signal, resets all registers except the identification register. input ireqn o interrupt request output signal, open drain output. this signal requires a pull-up resistor if used by the system. hi-z ireq o interrupt request output signal, active high. low clock i clock input input testn[6:0] i active low test pins. these pins must be tied high in the system. input tristaten i active low testpin. tristates all pads input
page 16 of 35 ps3520-1098 advanced hardware architectures, inc. 7.2 port a interface note: refer to section 5.0 port a and port b configuration and table 2 for configuration of port a control signals. port a interface signal type description default after reset acin i port a interface control input signal. this signal functions as dacka or dreqa. polarity is programmed by apol[7]. input acout o port a interface control output signal. this signal functions as dacka or dreqa. polarity is programmed by apol[5]. high awr o port a interface control output signal. polarity is controlled by apol[4]. high ard o port a interface control output signal. polarity is controlled by apol[3]. high apcs o port a interface control output signal. polarity is controlled by apol[2]. high aaf o port a interface output signal. port a fifo almost full signal. polarity is programmed by apol[1]. exactly when this flag gets set depends on the threshold bits in the port a configuration 0 register. high aae o port a interface output signal. port a almost empty signal. polarity is programmed by apol[0]. exactly when this flag gets set depends on the threshold bits in the port a configuration 0 register. low aparity[1:0] i/o when enabled, this pin checks parity on input and generates parity for output for the ad bus. aparity[0] is used for ad[7:0], and aparity[1] is used for ad[15:8]. setting acnf[15]=1 enables aparity[0]. setting acnf[15]=1 and acnf[10]=1 enables aparity[1]. when disabled these pins may be tied high, tied low or not connected. hi-z adata[15:0] i/o port a interface data bus. the upper eight bits [15:8] are enabled by setting acnf[10]=1. when the upper eight bits are disabled they may be tied high, tied low, or not connected. hi-z
ps3520-1098 page 17 of 35 advanced hardware architectures, inc. 7.3 port b interface note: refer to section 5.0 port a and port b configuration and table 3 for configuration of port b control signals. port b interface signal type description default after reset bcin i port b interface control input signal. this signal functions as dackb or dreqb. polarity is programmed by bpol[7]. input bcout o port b interface control output signal. this signal functions as dackb or dreqb. polarity is programmed by bpol[5]. high bwr o port b interface control output signal. polarity is controlled by bpol[4]. high brd o port b interface control output signal. polarity is controlled by bpol[3]. high bpcs o port b interface control output signal. polarity is controlled by bpol[2]. high baf o port b interface output signal. port b fifo almost full signal. polarity is programmed by bpol[1]. exactly when this flag gets set depends on the threshold bits in the port b configuration 0 register. high bae o port b interface output signal. port b almost empty signal. polarity is programmed by bpol[0]. exactly when this flag gets set depends on the threshold bits in the port b configuration 0 register. low bparity[1:0] i/o when enabled, this pin checks parity on input and generates parity for output for the bd bus. bparity[0] is used for bd[7:0], and bparity[1] is used for bd[15:8]. setting bcnf[15]=1 enables bparity[0]. setting bcnf[15]=1 and bcnf[10]=1 enables bparity[1]. when disabled these pins may be tied high, tied low or not connected. hi-z bdata[15:0] i/o port b interface data bus. the upper eight bits [15:8] are enabled by setting bcnf[10]=1. when the upper eight bits are disabled they may be tied high, tied low, or not connected. hi-z
page 18 of 35 ps3520-1098 advanced hardware architectures, inc. 8.0 pinout pin signal pin signal 1 aae 51 acin 2 vdd 52 vdd 3 gnd 53 gnd 4 bdata[7] 54 adata[7] 5 bdata[6] 55 adata[6] 6 bdata[5] 56 testn[2] 7 bdata[4] 57 adata[5] 8 bdata[3] 58 adata[4] 9 bdata[2] 59 adata[3] 10 vdd 60 vdd 11 gnd 61 gnd 12 bdata[1] 62 adata[2] 13 baf 63 ard 14 bae 64 apcs 15 bdata[0] 65 adata[1] 16 bdata[15] 66 adata[0] 17 bdata[14] 67 adata[15] 18 bdata[13] 68 adata[14] 19 bdata[12] 69 adata[13] 20 vdd 70 vdd 21 gnd 71 gnd 22 bdata[11] 72 adata[12] 23 bdata[10] 73 adata[11] 24 bdata[9] 74 adata[10] 25 bdata[8] 75 adata[9] 26 bparity[0] 76 adata[8] 27 bparity[1] 77 aparity[0] 28 vdd 78 vdd 29 gnd 79 gnd 30 ireqn 80 aparity[1] 31 ireq 81 mdata[7] 32 bpcs 82 testn[3] 33 waitn 83 testn[4] 34 brd 84 mdata[6] 35 bwr 85 mdata[5] 36 bcout 86 mdata[4] 37 resetn 87 mdata[3] 38 tristaten 88 acout 39 clk 89 awr 40 gnd 90 gnd 41 vdd 91 vdd 42 addr[4] 92 mcin[0] 43 addr[3] 93 mcin[1] 44 testn[0] 94 mdata[2] 45 bcin 95 mdata[1] 46 gnd 96 mdata[0] 47 testn[1] 97 aaf 48 addr[2] 98 mmode 49 addr[1] 99 testn[5] 50 addr[0] 100 testn[6]
ps3520-1098 page 19 of 35 advanced hardware architectures, inc. figure 2: pinout AHA3520a-040 pqc 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 31 tm 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 aae vdd gnd bdata[7] bdata[6] bdata[5] bdata[4] bdata[3] bdata[2] vdd gnd bdata[1] baf bae bdata[0] bdata[15] bdata[14] bdata[13] bdata[12] vdd gnd bdata[11] bdata[10] bdata[9] bdata[8] bparity[0] bparity[1] vdd gnd ireqn aparity[1] gnd vdd aparity[0] adata[8] adata[9] adata[10] adata[11] adata[12] gnd vdd adata[13] adata[14] adata[15] adata[0] adata[1] apcs ard adata[2] gnd vdd adata[3] adata[4] adata[5] testn[2] adata[6] adata[7] gnd vdd acin addr[0] addr[1] addr[2] testn[1] gnd bcin testn[0] addr[3] addr[4] vdd gnd clk tristaten resetn bcout bwr brd waitn bpcs ireq mdata[7] testn[3] testn[4] mdata[6] mdata[5] mdata[4] mdata[3] acout awr gnd vdd mcin[0] mcin[1] mdata[2] mdata[1] mdata[0] aaf mmode testn[5] testn[6]
page 20 of 35 ps3520-1098 advanced hardware architectures, inc. 9.0 electrical specifications 9.1 absolute maximum ratings 9.2 recommended operating conditions 9.3 dc specifications notes: 1) test conditions: worst case compression current; 0ma loads. absolute maximum ratings symbol parameter min max units notes vdd power supply voltage 7.0 volts vpin voltage applied to any pin -0.5 7.0 volts recommended operating conditions symbol parameter min max units notes vdd power supply voltage 4.75 5.25 volts ta operating temperature 0 70 c dc specifications symbol parameter conditions min max units notes vil input low voltage 0.8 volts vih input high voltage 2.0 volts vol output low voltage iol = 4.0 mamps 0.4 volts voh output high voltage ioh = -0.4 mamps 2.4 volts iil input low current vin = 0 volts -10 m amps iih input high current vin = vdd volts 10 m amps iozl output tristate low current vout = 0 volts 10 m amps iozh output tristate high current vout = vdd volts -10 m amps idda active idd current vdd = 5.25 volts 250 mamps 1 idd supply current (static) 1 mamps iol low level output current (except ireqn) ireqn (open drain) 4 8 mamps ioh high level output current -4 mamps cin input capacitance 5 pf cout output capacitance 5 pf ci/o i/o capacitance 5 pf cl load capacitance 50 pf
ps3520-1098 page 21 of 35 advanced hardware architectures, inc. 10.0 timing specifications notes: 1) all ac timings are referenced to 1.4 volts. figure 3: clock timing table 4: clock timing notes: 1) all ac timings are referenced to 1.4 volts 2) rise and fall times are between 0.8 volts and 2.0 volts. figure 4: reset timing table 5: reset timing figure 5: almost full/almost empty timing table 6: almost full/almost empty timing notes: 1) these timings are valid for both port a and port b and inverted signal polarities. replace x with a for port a signals and b for port b signals. number parameter min max units notes 1 clk period 25 ns 1 2 clk low pulsewidth 10 ns 1 3 clk high pulsewidth 10 ns 1 4 clk rise time 3 ns 2 5 clk fall time 3 ns 2 number parameter min max units notes 1 resetn pulsewidth 5 clocks 2 resetn delay to csn, readn or writen 2clocks number parameter min max units notes 1 xaf or xae asserted from clock rise 3 26 ns 2 xaf or xae deasserted from clock rise 3 26 ns 4 5 3 2 1 clock resetn mcin[0] or mcin[1] 2 1 (csn, readn or writen) clock (input) xaf xae 1 2 2 1
page 22 of 35 ps3520-1098 advanced hardware architectures, inc. figure 6: processor read timing, mmode = 1 table 7: processor read timing, mmode = 1 note: 1) when waitn causes csn to deassert, ignore number 3, otherwise ignore number 6. 2) the device latches addr on the falling edge of csn. the user should latch mdata on the rising edge of csn. 3) waitn is pulled up internally with a 10k resistor when not active and not driven low. number parameter min max units notes 1 rwn setup to csn asserted 4 ns 2 rwn hold from csn asserted 4 ns 3 csn pulsewidth 3 clocks 1 4 delay from csn deasserted until next csn 1 clock+5 ns 5 csn asserted to waitn asserted 18 ns 6 csn hold from waitn deasserted 0 ns 1 7 waitn deasserted from csn asserted 2 clocks 3 clocks+18 ns 8 addr setup to csn asserted 2 ns 2 9 addr hold from csn asserted 6 ns 2 10 mdata valid from csn asserted 2 clocks+24 ns 11 mdata tristate from csn deasserted 3 20 ns 12 mdata hold from csn deasserted 3 20 ns 13 csn asserted to mdata driven 1 clock 14 csn deasserted to waitn tristate 10 ns mcin[1] (rwn) mcin[0] (csn) waitn mdata addr valid valid 12 3 4 5 6 8 9 7 10 11 12 tristate tristate (note 3) 14 13
ps3520-1098 page 23 of 35 advanced hardware architectures, inc. figure 7: processor write timing, mmode = 1 table 8: processor write timing, mmode = 1 notes: 1) when waitn causes csn to deassert, ignore number 3, otherwise ignore number 6. 2) when a read to a register immediately follows a write to that same register or to the command register, csn must deassert for a minimum of 3 clocks after the write. 3) the device latches addr on the falling edge of csn. 4) waitn is pulled up internally with a 10k resistor when not active and not driven low. number parameter min max units notes 1 rwn setup to csn asserted 4 ns 2 rwn hold from csn asserted 4 ns 3 csn pulsewidth 2 clocks 1 4 delay from csn deasserted until next csn 1 clock+5 ns 2 5 csn asserted to waitn asserted 18 ns 6 csn hold from waitn deasserted 0 ns 1 7 waitn deasserted from csn asserted 1 clock 2 clocks+18 ns 8 addr setup to csn asserted 2 ns 3 9 addr hold from csn asserted 6 ns 3 10 mdata valid before csn deasserted 4 ns 11 mdata hold from csn deasserted 4 ns 12 csn deasserted to waitn tristate 10 ns mcin[1] (rwn) mcin[0] (csn) waitn mdata addr valid valid 12 3 4 5 6 8 9 7 10 11 (note 4) 12
page 24 of 35 ps3520-1098 advanced hardware architectures, inc. figure 8: processor read timing, mmode = 0 table 9: processor read timing, mmode = 0 notes: 1) when waitn causes readn to deassert ignore number 1, otherwise ignore number 4. 2) the device latches addr on the falling edge of readn. the user should latch mdata on the rising edge of readn. 3) writen must be deasserted during register reads. 4) waitn is pulled up internally with a 10k resistor when not active and not driven low. number parameter min max units notes 1 readn pulsewidth 3 clocks 1 2 delay from readn deasserted until next readn 2clocks 3 readn asserted to waitn asserted 18 ns 4 readn hold from waitn deasserted 0 ns 1 5 waitn deasserted from readn asserted 2 clocks 3 clocks+18 ns 6 addr setup to readn asserted 2 ns 2 7 addr hold from readn asserted 6 ns 2 8 mdata valid from readn asserted 2 clocks+24 ns 9 mdata tristate from readn deasserted 20 ns 10 mdata hold from readn deasserted 3 ns 11 mdata asserted from readn asserted 1 clock 12 readn deasserted to waitn tristate 10 ns 7 mcin[0] (readn) waitn addr mdata valid valid 1 3 6 5 8 9 10 2 4 tristate tristate 11 12 (note 4) (note 3)
ps3520-1098 page 25 of 35 advanced hardware architectures, inc. figure 9: processor write timing, mmode = 0 table 10: processor write timing, mmode = 0 notes: 1) when waitn causes writen to deassert ignore number 1, otherwise ignore number 4. 2) the device latches addr on the falling edge of writen. 3) readn must be deasserted during register writes. 4) waitn is pulled up internally with a 10k resistor when not active and not driven low. number parameter min max units notes 1 writen pulsewidth 2 clocks 1 2 delay from writen deasserted until next writen 3clocks 3 writen asserted to waitn asserted 18 ns 4 writen hold from waitn deasserted 0 ns 1 5 waitn deasserted from writen asserted 1 clock 2 clocks+18 ns 6 addr setup to writen asserted 2 ns 2 7 addr hold from writen asserted 6 ns 2 8 mdata valid before writen deasserted 4 ns 9 mdata hold from writen deasserted 4 ns 10 writen deasserted to waitn tristate 10 ns mcin[1] (writen) waitn addr mdata valid valid 1 3 6 5 9 2 4 8 7 10 (note 4) (note 3)
page 26 of 35 ps3520-1098 advanced hardware architectures, inc. figure 10: port a/b timing, four edge, master mode table 11: port a/b timing, four edge, master mode notes: 1) these timings are valid for both port a and port b and inverted signal polarities. replace x with a for port a signals and b for port b signals. 2) internal bus keepers hold the xdata until overdriven. number parameter min max units notes 1 dackx asserted to dreqx deasserted 20 ns 1 2 delay from dreqx deasserted to next dreqx 2 clocks - 5 ns 1 3 dreqx asserted to dackx asserted 1 clocks 1 4 dackx pulsewidth 2 clocks 1 5 delay from dackx deasserted to next dreqx 1clocks1 6 xdata (output) driven from dackx asserted 2ns1 7 xdata (output) hold from dackx deasserted 2 23 ns 1, 2 8 xdata (input) valid before dackx deasserted 4ns1 9 xdata (input) hold from dackx deasserted 8 ns 1 10 xdata (output) valid from dackx asserted 23 ns 1 6 xcout (dreqx output) xcin (dackx input) xdata (output) xdata (input) valid 1 3 9 valid 2 5 4 8 tristate tristate tristate tristate 7 10
ps3520-1098 page 27 of 35 advanced hardware architectures, inc. figure 11: port a/b timing, four edge, slave mode table 12: port a/b timing, four edge, slave mode notes: 1) these timings are valid for both port a and port b and inverted signal polarities. replace x with a for port a signals and b for port b signals. 2) internal bus keepers hold the xdata until overdriven. number parameter min max units notes 1 dreqx pulsewidth 2 clocks 1 2 dackx deasserted from dreqx deasserted 1 clock 2 clocks+22 ns 1 3 delay from dackx deasserted to next dreqx 0ns1 4 dreqx asserted to dackx asserted 1 clocks 1 5 dackx pulsewidth 2 clocks - 8 ns 1 6 xdata (output) driven from dackx asserted 1 clock - 5 ns 1 7 xdata (output) hold from dackx deasserted 1 clock - 10 ns 1 clock+5 ns 1, 2 8 xdata (input) valid after dreqx deasserted 1 clock - 5 ns 1 9 xdata (input) hold from dackx deasserted 0 ns 1 10 xdata (output) valid from dackx asserted 1 clock+10 ns 1 xcin (dreqx input) xcout (dackx output) xwr or xrd (output) xdata (output) valid 1 23 4 5 6 7 valid xdata (input) 8 9 tristate tristate tristate tristate 10
page 28 of 35 ps3520-1098 advanced hardware architectures, inc. figure 12: port a/b timing, burst, master mode table 13: port a/b timing, burst, master mode notes: 1) these timings are valid for both port a and port b and inverted signal polarities. replace x with a for port a signals and b for port b signals. 2) internal bus keepers hold the xdata until overdriven. number parameter min max units notes 1 last dackx asserted to dreqx deasserted, end of burst 20 ns 1 2 dreqx asserted to first dackx asserted, start of burst 1clocks1 3 dackx pulsewidth 2 clocks - 10 ns 1 4 dackx deasserted to dackx asserted 2 clocks - 10 ns 1 5 last dackx deasserted to next dreqx asserted, next burst 2clocks1 6 xdata (output) driven from dackx asserted 2ns1 7 xdata (output) hold from dackx deasserted 2 23 ns 1, 2 8 xdata (input) valid before dackx deasserted 4ns1 9 xdata (input) hold from dackx deasserted 8 ns 1 10 dackx cycle time 4 clocks 1 11 xdata (output) valid from dackx asserted 23 ns 1 1 xcout (dreqx output) xcin (dackx input) xdata (output) xdata (input) 2 3 valid valid valid valid 5 7 6 9 8 tristate tristate tristate tristate 4 10 valid valid 11
ps3520-1098 page 29 of 35 advanced hardware architectures, inc. figure 13: port a/b timing, burst, slave mode table 14: port a/b timing, burst, slave mode notes: 1) these timings are valid for both port a and port b and inverted signal polarities. replace x with a for port a signals and b for port b signals. 2) internal bus keepers hold the xdata until overdriven. number parameter min max units notes 1 last dackx asserted to dreqx deasserted, end of burst 0 ns 3 clocks - 22 ns 1 2 dreqx asserted to first dackx asserted, start of burst 1clocks1 3 dackx pulsewidth 2 clocks - 8 ns 2 clocks+8 ns 1 4 dackx deasserted to dackx asserted 2 clocks - 8 ns 1 5 last dackx deasserted to next dreqx asserted, next burst 2clocks1 6 xdata (output) driven from dackx asserted 1 clock - 5 ns 1 7 xdata (output) hold from dackx deasserted 1 clock - 10 ns 1 clock+5 ns 1, 2 8 xdata (input) valid after dackx asserted 2 clocks - 18 ns 1 9 xdata (input) hold from dackx deasserted 0 ns 1 10 xdata (output) valid from dackx asserted 1 clock+10 ns ns 1 1 xcin (dreqx input) xcout (dackx output) xwr or xrd (output) xdata (output) 2 3 5 9 6 valid valid valid xdata (input) 7 tristate tristate tristate tristate 4 8 valid valid valid 10
page 30 of 35 ps3520-1098 advanced hardware architectures, inc. figure 14: peripheral access read timing, mmode = 1 table 15: peripheral access read timing, mmode = 1 notes: 1) when waitn causes csn to deassert ignore number 3, otherwise ignore number 6. 2) n is the number of wait states programmed into the xcnf registers. 3) the device latches addr on the falling edge of csn. the user should latch mdata on the rising edge of csn. 4) these timings are valid for both port a and port b and inverted signal polarities. replace x with a for port a signals and b for port b signals. 5) waitn is pulled up internally with a 10k resistor when not active and not driven low. number parameter min max units notes 1 rwn setup to csn asserted 4 ns 2 rwn hold from csn asserted 4 ns 3 csn pulsewidth (n+1) clocks 1, 2 4 delay from csn deasserted until next csn 2 clocks 5 csn asserted to waitn asserted 5 18 ns 6 csn hold from waitn deasserted 0 ns 1 7 waitn deasserted from csn asserted n clocks (n+1) clocks +18 ns 2 8 addr setup to csn asserted 4 ns 3 9 addr hold from csn asserted 4 ns 3 10 mdata (output) hold from csn deasserted 3 20 ns 11 mdata (output) valid from xdata (input) valid 19 ns 4 12 xrdn asserted from csn asserted 1 clock 2 clocks+21 ns 4 13 xrdn deasserted from csn deasserted 1 clock 2 clocks+21 ns 4 14 xpcsn asserted from csn asserted 1 clock 2 clocks+21 ns 4 15 xpcsn deasserted from csn deasserted 1 clock 2 clocks+21 ns 4 16 csn deasserted to waitn tristate 0 10 ns mcin[1] (rwn) mcin[0] (csn) waitn addr valid 3 1 valid mdata (output) 10 xrdn xpcsn xdata (input) valid 2 4 5 6 8 9 7 11 12 13 14 15 tristate tristate (note 5) 16
ps3520-1098 page 31 of 35 advanced hardware architectures, inc. figure 15: peripheral access write timing, mmode = 1 table 16: peripheral access write timing, mmode = 1 notes: 1) when waitn causes csn to deassert ignore number 3, otherwise ignore number 6. 2) n is the number of wait states programmed into the xcnf registers. 3) the device latches addr on the falling edge of csn. 4) these timings are valid for both port a and port b and inverted signal polarities. replace x with a for port a signals and b for port b signals. 5) waitn is pulled up internally with a 10k resistor when not active and not driven low. 6) this timing applies to before a write access as well as after. number parameter min max units notes 1 rwn setup to csn asserted 4 ns 2 rwn hold from csn asserted 4 ns 3 csn pulsewidth (n+1) clocks 1, 2 4 delay from csn deasserted until next csn 3 clocks 6 5 csn asserted to waitn asserted 5 18 ns 6 csn hold from waitn deasserted 0 ns 1 7 waitn deasserted from csn asserted n clocks (n+1) clocks+18 ns 2 8 addr setup to csn asserted 4 ns 3 9 addr hold from csn asserted 4 ns 3 10 mdata valid before csn deasserted 4 ns 11 mdata hold from csn deasserted 4 ns 12 xwrn asserted from csn asserted 1 clock 2 clocks+21 ns 4 13 xwrn deasserted from csn deasserted 1 clock 2 clocks+21 ns 4 14 xpcsn asserted from csn asserted 1 clock 2 clocks+21 ns 4 15 xpcsn deasserted from csn deasserted 1 clock 2 clocks+21 ns 4 16 xdata (output) tristated from csn deasserted 2 clocks 3 clocks+17 ns 4 17 xdata valid from csn deasserted 19 ns 4 18 csn asserted to xdata driven 1 clock 19 mcin[0] inactive to waitn tristate 0 10 ns mcin[1] (rwn) mcin[0] (csn) waitn addr valid 3 1 valid mdata 11 xwrn xpcsn xdata (output) 2 4 5 6 8 9 7 17 12 14 15 10 13 valid 16 tristate tristate tristate tristate (note 5) 19 18
page 32 of 35 ps3520-1098 advanced hardware architectures, inc. figure 16: peripheral access read timing, mmode = 0 table 17: peripheral access read timing, mmode = 0 notes: 1) when waitn causes readn to deassert ignore number 1, otherwise ignore number 4. 2) the device latches addr on the falling edge of readn. the user should latch mdata on the rising edge of readn. 3) writen must be deasserted during register reads. 4) n is the number of wait states programmed into the xcnf registers. 5) these timings are valid for both port a and port b and inverted signal polarities. replace x with a for port a signals and b for port b signals. 6) waitn is pulled up internally with a 10k resistor when not active and not driven low. number parameter min max units notes 1 readn pulsewidth (n+1) clocks 1, 2 2 delay from readn deasserted until next readn 2clocks 3 readn asserted to waitn asserted 5 18 ns 4 readn hold from waitn deasserted 0 ns 1 5 waitn deasserted from readn asserted n clocks (n+1) clocks+18 ns 2 6 addr setup from readn asserted 4 ns 2 7 addr hold from readn asserted 4 ns 2 8 mdata (output) hold from readn deasserted 320ns 9 mdata (output) valid from xdata (input) valid 19 ns 5 10 xrdn asserted from readn asserted 1 clock 2 clocks+21 ns 5 11 xrdn deasserted from readn deasserted 1 clock 2 clocks+21 ns 5 12 xpcsn asserted from readn asserted 1 clock 2 clocks+21 ns 5 13 xpcsn deasserted from readn deasserted 1 clock 2 clocks+21 ns 5 14 readn deasserted to waitn tristate 0 10 ns mcin[0] (readn) waitn addr valid 1 valid mdata (output) 8 xrdn xpcsn xdata (input) valid 2 3 4 6 7 5 9 10 11 12 13 tristate tristate 14 (note 6)
ps3520-1098 page 33 of 35 advanced hardware architectures, inc. figure 17: peripheral access write timing, mmode = 0 table 18: peripheral access write timing, mmode = 0 notes: 1) when waitn causes writen to deassert ignore number 1, otherwise ignore number 4. 2) the device latches addr on the falling edge of writen. 3) readn must be deasserted during register writes. 4) n is the number of wait states programmed into the xcnf registers. 5) these timings are valid for both port a and port b and inverted signal polarities. replace x with a for port a signals and b for port b signals. 6) waitn is pulled up internally with a 10k resistor when not active and not driven low. number parameter min max units notes 1 writen pulsewidth (n+1) clocks 1, 2 2 delay from writen deasserted until next writen 3clocks 3 writen asserted to waitn asserted 5 18 ns 4 writen hold from waitn deasserted 0 ns 1 5 waitn deasserted from writen asserted n clocks (n+1) clocks+18 ns 2 6 addr setup from writen asserted 4 ns 2 7 addr hold from writen asserted 4 ns 2 8 mdata valid before writen deasserted 4 ns 9 mdata hold from writen deasserted 4 ns 10 xwrn asserted from writen asserted 1 clock 2 clocks+21 ns 5 11 xwrn deasserted from writen deasserted 1 clock 2 clocks+21 ns 5 12 xpcsn asserted from writen asserted 1 clock 2 clocks+21 ns 5 13 xpcsn deasserted from writen deasserted 1 clock 2 clocks+21 ns 5 14 xdata (output) tristated from writen deasserted 2 clocks 3 clocks+17 ns 5 15 xdata valid from writen deasserted 19 ns 5 16 writen asserted to xdata driven 1 clock 5 17 writen inactive to waitn tristate 0 10 ns mcin[1] (writen) waitn addr valid 1 valid mdata (input) 9 xwrn xpcsn xdata (output) 2 3 4 6 7 5 15 10 12 13 8 11 valid 14 tristate tristate tristate tristate (note 6) 17 16
page 34 of 35 ps3520-1098 advanced hardware architectures, inc. 11.0 packaging figure 18: AHA3520 pqfp package specifications table 19: pqfp (plastic quad flat pack) 14 mm 20 mm package dimensions jedec outline mo-112 (all dimensions are in mm) symbol number of pin and specification dimension 100 rb min nom max (lca) 20 (lcb) 30 a3.1 a1 0.1 0.23 0.36 a2 2.57 2.71 2.87 d 23.65 23.9 24.15 d1 19.9 20 20.1 e 17.65 17.9 18.15 e1 13.9 14 14.1 l 0.73 0.88 1.03 p0.65 b 0.22 0.3 0.33 AHA3520a-040 pqc tm d1 p d b e1 p e (lca) (lcb) 81 82 83 84 85 96 97 98 99 100 30 29 28 27 26 l a a2 a1
ps3520-1098 page 35 of 35 advanced hardware architectures, inc. 12.0 ordering information 12.1 available parts 12.2 part numbering device number: 3520 revision letter: a package material codes: p plastic package type codes: q q - quad flat pack test specifications: c commercial 0 c to +70 c 13.0 aha related technical publications part number description AHA3520a-040 pqc 20 mbytes/sec aldc data compression coprocessor ic with enhanced features, pqfp aha 3520 a- 040 p q c manufacturer device number revision level speed designation package material package type test specification document # description pb3520 aha product brief C AHA3520 20 mbytes/sec aldc data compression coprocessor ic pb3521 aha product brief C aha3521 20 mbytes/sec aldc data compression coprocessor ic with enhanced features ps3521 aha product specification C aha3521 20 mbytes/sec aldc data compression coprocessor ic with enhanced features andc18 aha application note C differences between aha and ibm devices andc19 aha application note C designers guide for aldc compression/ decompression devices: AHA3520 and aha3521

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