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application note v.17 fax equipment replacing the r144efx with the st75c52/520 AN814/0695 by laurent claramond and jo?l huloux summary page i preliminary ..................................... ................... 2 ii introduction .................................... ................... 2 ii.1 overall . . . . . . . . . . . . . . . . . . . ......................................... 2 ii.2 a few modidifications in the software . . . . . . . . . . . . . . . . . . . . . . ....... 2 ii.3 hardware evolutions . . . . . ......................................... 2 iii comparison between r144efx and st75c52/520 ...................... 3 iv features required for fax communications ....................... 4 v data sheet and user's manual guide line .......................... 4 vi software guide line ............................................... 4 vi.1 user interface. . . . . . . . . . . . . . ....................... ................ 5 vi.2 interruptions. . . . . . . . . . . . . . . ....................................... 5 vi.3 parallel exchange in synchronous and in hdlc mode . . . . . . . . . . . . . . 7 vi.4 status report . . . . . . . . ...... .................... ................... 8 vi.5 g3 fax equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................... 8 vii flag detection ..................................................... 9 vii.1 v.21 channel 2 flag 7e detection . . . . . . . . . . . . . . . . ................... 9 vii.2 flag detection in v.21 channel 2 mode . .......... ................... 9 vii.3 flag detection in high speed mode . . . . . . . . . . . . . . ................... 9 vii.3.1 flag detection at the beginning of c phase or tcf reception . . . . . . . . . . . . . . . .... 9 vii.3.2 flag detection in c phase . . . . . . ......................................... 10 viii equalizer at reception side ....................................... 11 ix how to adjust the transmit level ................................. 12 x hardware guide line ............................................... 12 1/13
i - preliminary the st75c52/520 are a monolithic complete v.17 fax modem which is a superset of the r144efx. all functions found in the r144efx can be found in the st75c52/520, plus a few additional ones (class detection, 16 tone detectors, analog dac for eyediagram, etc) as you will see in the chapter iii table. although similar, the st75c52/520 are not a plug- in replacement for r144efx. you will need a few software and hardware adjustments, and with our help, it will cost you less than two man-months to do it. a small effort, compared to your benefits. if you are thinking about integrating the st75c52/520 with your prefered mcu and asic, call us immediately. ii - introduction ii.1 - overall this application note describes the way to replace the rockwell r144efx by the sgs-thomson st75c52/520 in a v.17 fax equipment system. this application note uses information detailed in the st75c52/520 data sheet and user's manual. first, you will find comparison on the features of the st75c52/520 and the r144efx. second, will be listed the features required to im- plement fax communications. third, will be presented to the user the different chapters in the st75c52/520 and user's manual where information was detailed. at the end of this application note is presented a software and hardware user's guide. ii.2 - a few modidifications in the software the user's fax software can be divided in two parts. the first part which is the main and the biggest is completly independent of the modem chip and is in charge of the following task : - user interface (keyboard, screen, printer). - ecm, t30, t4. - real time kernel. - control. - ... layers 2 and 3 are in this part of the software. this software can be reused in the final appli- cation without any modification and any pertur- bation when running in v.17 fax equipment including a st75c52/520 modem chip. the second part (which is the smallest ) is depend- ent of the modem chip and includes the driver routines needed to provide a complete list of serv- ices to the layer 2 and 3. we mainly find the following drivers : - interrupts driver. - modem configuration. - data transfer (emission/reception). - tone detection/generation. all the modifications will be easily done since : - the st75c52/520's software interface is based on command set using friendly mnemon- ics, - interrupts use dedicated registers clearly identified, - data transfer will use fifo principle to save cpu time. ii.3 - hardware evolutions performances and low cost are the two key pa- rameters that have been followed by sgs- thomson. the user can to remove the negative power supply (-5v) since the st75c52/520 needs only one power supply of +5v. the differential ana- log output and input will increase perform- ances at low level even on a two-layer printed circuit board. emi problems can be reduced using a crystal of 29.4912mhz instead 38.00053mhz. v.17 fax equipment replacing the r144efx 2/13
iii - comparison between r144efx and st75c52/520 features r144efx st75c52/520 package quip 64 and plcc68 pqfp64 power +5v 5%, -5v 5% +5v 5% supply current at 25 c 97ma and 14ma (555mw) 100ma (500mw, 5mw low power mode ) supply current at 0 c 105ma and 16ma (605mw) 130ma (650mw) operating range 0 to 70 c 0 to 70 c storage temperature -55 to 125 c -45 to 125 c frequency 38.000530mhz 29.4912mhz mcu bus 65xx/80xx bus motorola, intel bus interface with dsp 32 registers 60 registers interrupts 2 interrupts, one can be activated with a selectif mask from one of the 32 registers one interrupt. six sources with possible individual mask serial interface yes yes tx buffer 1 byte 2 x 8 bytes rx buffer 1 byte 2 x 8 bytes fax group 3 v.33 (14.4, 12kbps, 17000 and 1800hz) idem v.17 v.17 (14.4, 12, 9.6, 7.2kbps, 1700 and 1800hz) with short train v.29 (9.6, 7.2, 4.8kbps), no short train v.27ter (4.8, 2.4kbps) with short train v.33 (14.4, 12kbps, 17000 and 1800hz) idem v.17 v.17 (14.4, 12, 9.6, 7.2kbps, 1700 and 1800hz) with short train v.29 (9.6, 7.2, 4.8kbps), with short train v.27ter (4.8, 2.4kbps) withshort train short train v.27ter, v.17 v.27ter, v.29, v.17 hdlc yes yes tx level 0 to -15dbm 0 to -48dbm dynamic range 0 to -43dbm 0 to -43dbm turn on -10 to -47dbm -10 to -51dbm turn off -10 to -52dbm -15 to -55dbm reception timing 0.01% frequency error 0.01% frequency error tone generator 2 from 0 to 4800hz (step 0.15hz), attenuation if f > 300hz 4 from 0 to 3600hz (step 1hz) dtmf generation uses the 2 generators uses 2 of the 4 generators tone detector fr1, fr2 and fr3 from 400 to 3000hz (fr1 and fr2 not available in high speed reception) 2 to 16 detectors programmable from 0 to 3600hz : 2 if training fax high speed reception, else 8, 4 if dtmf detection, 16 if tone reception or audio transmission and reception dtmf detection gives the dtmf digit. twist (-8 to +4db) gives the dtmf digit. threshold -35dbm. t on > 40ms, twist ( 8db) flag detection available in high speed reception except in v.27 ter short train and tone detection available in high speed reception, and tone detection mode voice mode 7.2, 8 and 9.6khz on 8 bits till 10 to 16 bits 7.2, 8 and 9.6khz. a law on 8 bits equalizers (transmis- sion and reception) 44 input/output no no v.23 (full duplex) no yes eye monitoring yes with serial link yes with analog output analog interface mono differential max output level 3.3v 2.5v max input level 0dbm at rxa 2.5v bell 103-v.21 full duplex no yes class detection no yes v.17 fax equipment replacing the r144efx 3/13
iv - features required for fax communications in phase a (t.30 protocol) the modem chip must provide all features to establish or to answer a call. the user will use tone detectors for network tones detection (dialtone, busy tone, ring back tone), for answer tone detection (ced 2100hz tone) and for flag detection. in the calling unit, tone generators will be used to send dtmf digit, and the calling tone (cng tone at 1100hz). when on-hook, the modem chip can help the host make incoming call detection. in phase b, d and e (t.30 protocol) the modem chip must be able to send or receive : - in v.21 ch2, - hdlc frame over v.21 ch2 modulation, - tcf frame in high speed mode (only in phase b). in phase c the chip must be able to send or receive in high speed mode (v.27ter, v.29, v.17), and to detect v.21 flag (hdlc fanion) while in high speed mode reception. the user must be able to adjust level in transmis- sion (carrier, tone). complete hdlc (transmit and receive) function must also be available in high speed mode to allow ecm (error correcting mode). some others features such as dtmf detection, voice mode may be required in the final application. to use all the above features the user will initialize registers in the dsp and must read status. so, the chip must provide a friendly interface to a host microprocessor. all the above features included in the r144efx can be easily used with the st75c52/520. v - data sheet and user's manual guide line firstly the user has to read carefully the st75c52/520 data sheet and user's manual. secondly the user can use the following list which identifies the main chapters in the st75c52/520 documentation. these chapters detail the features introduced in the previous chapter. digital interface : - data sheet chapter iii - user's manual chapter ii.2 user interface : - data sheet chapter v analog interface : - data sheet chapter xii - user's manual chapter viii tone generator : - data sheet chapter iv.2.4 - data sheet chapter vi : ? deft, tone, tgen commands tone detector : - data sheet chapter viii - user's manual chapter v interruptions : - data sheet chapter v.i.2 configuration for g3 fax : - data sheet chapter vi : ? hshk, sync, conf, modc commands - data sheet chapter vii - user's manual chapter vii hdlc function : - data sheet chapter vi ? form, serial commands - data sheet chapter ix - user's manual chapter iv control in transmit mode : - user's manual chapter vi control in receive mode : - user's manual chapter vii pcb guide line : - user's manual chapter ix vi - software guide line as the main differencesbetween the r144efx and the st75c52/520 are found in the software man- agement, we suggest to the user the following steps to understand the st75c52/520 software interface : 1.study the user interface, the command set, the command acknowledge. 2.study the interruptions features. 3.study the parallel exchange in synchronous and in hdlc mode. 4.study the status report. 5.study the flow scharts for g3 fax configuration. v.17 fax equipment replacing the r144efx 4/13
vi.1 - user interface the host processor will be connected to the st75c52/520 using a dual port ram with dedicated memory addresses for : - command and parameters, - command acknowledge, - data tx buffer (transmission), - data rx buffer (reception), - status information, - interrupt registers. the address space within the host ram mapping is a 128 byte block requiring 7 address lines instead 5 for the rfx144efx. the host processor will use commands (with or without parameters) to initialized the modem chip and to start/stop a specific task such as : send a tone, a carrier or detect a tone, a dtmf, a car- rier, ... hereafter is described the syntax for each com- mand : opcode : hexadecimal value xxxxxxxx parameters : field byte pos value definition name x a..b xx* explanation of the parameter field : name of the addressed bit field. byte : index of the parameter byte (1 to 4). pos : bit field position inside the parameter byte. value : possible values for the bit (resp. bit field). a value followed by a star means a default value. each command will be acknowledge by the dsp. the host processormust not send a new command without waiting for the acknowledge of the previous command. figure 1 is summarized the command acknow- ledge. vi.2 - interruptions six sources of interruptions can be used by the software handler routine : error : it0, if errors have occured tx buffer : it2, the st75c52/520 frees one of the 2 tx buffers rx buffer : it3, the st75c52/520 has filled one of the 2 rx buffers status byte : it4 to signify that the modem status has changed low power mode : it5 when the st75c52/520 has been awakened command acknowledge : it6, the st75c52/520 is ready for a new command one 8 bit source register itsrcr located at ad- dress $50 in the dual port ram memory identifies the source : d0 = 1 it0 pending d1 not used d2 = 1 it2 pending d3 = 1 it3 pending d4 = 1 it4 pending d5 = 1 it5 pending d6 = 1 it6 pending write parameters (optional) mcu parameters dual port ram compar[0..3] write command command comsys comrep[0..1] (optional) must wait acknowledge before sending a new command comack raises interrupt (optional) AN814-01.eps figure 1 v.17 fax equipment replacing the r144efx 5/13
mcu interrupt read itsrcr dual port ram (dsp) raises it2 gives source register value acknowledge it2, writing 00 into itrst[2] clear it2 execute tx interrupt routine AN814-02.eps figure 2 the interrupt source will be reset and acknowledge by writing a $00 at one of the memory location $40 to $46 (reset interrupt registers itrest[0..6] )in the dual port ram memory. itrest[0] at address $40 is dedicated to it0. itrest[2] at address $42 is dedicated to it2. ... itrest[6] at address $46 is dedicated to it6. figure 2 is an example for it2. all sources of interrupt can be masked individually or globaly with the interrupt mask register itmask located at the address $4f in the dual port ram memory. itmask register definition : d7 = 0 all interrupts are masked (global mask) d6 = d7 = 1 it6 enable d5 = d7 = 1 it5 enable d4 = d7 = 1 it4 enable d3 = d7 = 1 it3 enable d2 = d7 = 1 it2 enable d1 not used must be equal to 0 d0 = d7 = 1 it0 enable even if an interrupt is masked, the dsp will always set the corresponding bit in the source register (itsrcr) to allow polling by the host processor. figure 3 illustrates for it2 and it3 the interruption principle, the user could easily transpose this prin- ciple to the other interrupts : - it2 and it3 are set by the dsp, - it2 and it3 are cleared and acknowledged by the host processor, - itsrcr is only read by the host processor, - itmask is read or write by the host processor. r s q itres2 (write only) r s q itres3 (write only) 3210 4 5 6 itsrcr (read only) from st75c52 buffer (tx buffer emptied) (rx buffer filled) 3210 4 5 6 itmask (read write) 7 sintr AN814-03.eps figure 3 v.17 fax equipment replacing the r144efx 6/13
vi.3 - parallel exchange in synchronous and in hdlc mode data tx buffer : the r144efx uses only one tx buffer of one byte in parallel transmission. this architecture is very simple since the dsp has to write succesive bytes at the same address. the drawback is that the r144efx will raise an interrupt every sent byte. to save mcu (host processor) time the principle is quite different with a st75c52/520. two tx buffers will be used in parallel transfer, tx_buffer_0 called dttbf0 and tx_buff- er_1 called dttbf1 . each tx buffer contains 8 bytes. the host processor can write one to eight bytes in the same buffer. the tx interrupt (it2) will only be raised when the complet tx buffer will be empty (e.g for tx buffers filled with 8 bytes the it2 will be activated every 8 bytes). as this principle save mcu time between two interrupts, the host processor could be more efficiency used for other main tasks such as error correcting mode (ecm), ... one status byte dttbs0 is dedicated to dttbf0 and another dttbs1 is associated with dttbf1. parallel transmission must be initialized with se- rial , form and xmit commands. in parallel transmission the two buffers must be used, always starting with buffer 0. the host processor must mcu step-1-mcu fill dttbf0 dual port ram (dsp) step-1-dsp reads dttbs0 reads dttbf0 clears dttbs0 write dttbs0 interrupt raises it2 step-2-mcu fill dttbf1 step-2-dsp reads dttbs1 reads dttbf1 clears dttbs1 write dttbs1 interrupt goto step-1-mcu raises it2 goto step-1-dsp AN814-04.eps figure 4 : data tx buffer flow chart send data alternatively into dttbf0, dttbf1, dttbf0, dttbf1, dttbf0, ... the host processorwrites data into a tx buffer then writes the number of bytes into the dedicated status. the dsp reads the tx buffer and clears the dedicated status, then raises it2. figure 4 is illustrated the exchange in transmit parallel mode (initialization with the form, se- rial and xmit was already done). complet and detailed information is given in chap- ter iv of the st75c52/520 user's manual. data rx buffers : the r144efx uses only one rx buffer of one byte in parallel reception. this architecture is very sim- ple since the dsp has to read succesive bytes at the same address. the drawback is that the r144efx will raise an interrupt every received byte. to save mcu (host processor) time the principle is quite different with a st75c52/520. two rx buffers will be used in parallel transfer, rx_buffer_0 called dtrbf0 and rx_buff- er_1 called dtrbf1 . each rx buffer contains 8 bytes. the host processor will generaly read eight bytes in the same buffer except if the modem chip detects a loss of carrier. one status byte dtrbs0 is dedicated to dtrbf0, and another dtrbs1 is dedicated to dtrbf1. v.17 fax equipment replacing the r144efx 7/13
mcu interrupt dual port ram (dsp) fill dtrbf0 step-1-dsp fill dtrbs0 raise it3 step-1-mcu read dtrbs0 dtrbf0 clear dtrbs0 interrupt fill dtrbf1 step-2-dsp fill dtrbs1 raise it3 goto step-1-dsp step-2-mcu read dtrbs1 dtrbf1 clear dtrbs1 goto step-1-mcu AN814-05.eps figure 5 : data rx buffer flow chart the rx interrupt (it3) will only be raised when the complet rx buffer will be full (it3 will be activated every 8 bytes). as this principle saves mcu time between two interrupts, the host processor could be more efficiency used for other main tasks such as ecm, ... parallel reception must be initialized with serial and form commands. in parallel reception the two buffers must always be used, starting with buffer 0. the dsp will alterna- tively fill dtrbf0, dtrbf1, dtrbf0, dtrbf1, ... the dsp will fill one rx buffer, then fill the dedi- cated status register and then raises it3. each time an rx buffer is filled the host processor must read it and then clear the dedicated status register. figure 5 is illustrated the exchange in receive par- allel mode (initialization with the form, serial already done). complet and detailed information is given in chap- ter iv of the st75c52/520 user's manual. vi.4 - status report the host processor needs some status information writen by the st75c52/520 to folllow tone detec- tion result, synchronisation in high speed mode, dtmf detection, ... for that purposethe st75c52/520 provides follow- ing status : error status (address $08) : provides information about error, can generate an interrupt it0 . status[0], status[1] (addresses $09, $0a) : contain all the modem signals, can generate an interrupt it4 . staqua (address $0b) : contains the quality of the received signal. staop[0], staop[1], staop[2] (addresses $0c, $0d, $0e) : optional status that contain additional information regarding the st75c52/520 operating mode. this default information can be changed to monitor any internal variables. vi.5 - g3 fax equipment all the information to set up the st75c52/520 in phase a,b,c,d and e (t.30 protocol) are described in chapter iii of the st75c52/520 user's manual. the user will find the command, status infor- mation required. a lot of flow charts detail the procedure to initialize low speed (v.21 ch2) and high speed (v.27ter, v.29 , v.17) transmission and reception. v.17 fax equipment replacing the r144efx 8/13
vii - flag detection this chapter describes the way to use the flag_de- tection provided by the st75c52/520 status report which will be used by a host micro-controller. vii.1 - v.21 chanel 2 flag 7e detection the st75c52/520 provides in the status1 (ad- dress $0a in the host interface) the sta_flag bit. status1 is an 8 bit register that can be read (only) by the host. bit position 7 corresponds to the msb and bit position 0 corresponds of the lsb. in this register bit 6 (position 6) is called sta_flag (valid only in fax modem and tone mode). sta_flag equal to 1 means that a v.21 ch2 flag is detected. three flags are necessary to validate v.21 flag. so minimum timing for v.21 flag detection is : 3.3ms x 8 x 3 = 79.2ms. at this optimum timing you have to add the re- sponse time for the filters and the time for synchro- nisation of state machine at the beginning of the flag. the overall detection of v.21 ch2 flag is be- tween 92 and 98ms . the overall time for loss of v.21 ch2 flag is between 17 and 25ms . vii.2 - flag detection in v.21 channel 2 mode if the st75c52/520 is set to receive in v.21 chan- nel 2 mode, the v.21 flag detector is always avail- able. the following flow chart shows how the host must used the st75c52/520 to detect v.21 ch2 flag while receiving in low speed mode (see figure 6). vii.3 - flag detection in high speed mode vii.3.1 - flag detection at the beginning of c phase or tcf reception in such a case the st75c52/520 is setting up to receive in v.27, v.29 or v.17. when the host starts the synchronisation of the reception sending the sync 1 command to the st75c52/520, the inter- nal dsp executes two tasks in which the v.21 ch2 flag detection is activated : - looking for v.21 ch2 signal, - looking for training in high speed mode. the v.21 ch2 flag detection is not available when the st75c52/520 is in data mode (the training is completed, the carrier detect signal and the sta_109 are true indicating a received high speed modulation). figure 7 shows when the flag detection is available. conf 0f 0d 00 00 sync 1 sta_109 sta_flag flag detected v.21 channel 2 carrier detect ? flag detected ? AN814-06.eps figure 6 flag detection available flag detection disabled training data in high speed mode conf sync 1 sta_109 carrier detect AN814-07.eps figure 7 : st75c52/520 high speed received sequence v.17 fax equipment replacing the r144efx 9/13
conf (v.27, v.29, v.17) sync 1 v.17 short train modc 40 00 sta_flag p2s no no yes yes no sync 00 conf 0f 0d 00 00 sync 1 waiting : sta_109 sta_flag sta_flag yes pndets wait sta_109 then receive data in high speed mode no no AN814-08.eps figure 8 figure 8 shows how the host can use the st75c52/520 for flag detection when receiving tcf frame or at the beginning of c phase. vii.3.2 - flag detection in c phase as said above the flag detection is not available while the st75c52/520 is receiving data in high speed mode (v.17, v.29, v.27) since the dsp disables it as soon as the carrier detect status ( sta_109 ) is true. it could be interesting for the host to have the sta_flag information available in c phase just after a loss of the high speed carrier because the next received signal could be a v.21 ch2 instead a high speed carrier without a training. figure 9 summarizes the two cases. in the first case the transmit unit has cut the high speed transmission (which causes the loss of the carrier) and start to send hdlc frames in v.21 ch2. in the second case the loss of the carrier may be due to a problem on the pstn network. training data in high speed mode start of reception reception sta_109 = 1 sta_109f = 1 loss of carrier (sta_109f = 0) v.21 channel 2 flag data in high speed or new received signal AN814-09.eps figure 9 : st75c52/520 received signal with loos of carrier v.17 fax equipment replacing the r144efx 10/13
conf (v.17, v.29, v.27) enb short sync 1 enable flag (1) sta_flag sync 0 conf 0f 0d 00 00 sta_109 staqua 3f no yes no yes no yes sta_109 no yes sta_109f yes no v.21 ch2 disable flag sta_109f yes no enable flag (2) AN814-10.eps figure 10 figure 10 gives to the user the way to be able to detect v.21 ch2 flag just after a loss of high speed carrier. to enable and disable the flag detection the host will performe a memory write (mw) command (see table 1 for addresses and parameters). as the short train is only used in c phase while receiving in v.17 mode the host can avoid to send the enb short sequence to the st75c52/520 in v.29 and v.27. this flow chart (figure 10) could be used in phase b but take care that the enb short sequence must only be sent in c phase. viii - equalizer at reception side the dsp provides an equalizer function in the reception section. it computes the coefficients of this equalizer firstly during the training and sec- ondly during the first seconds of the data mode (carrier detect signal and sta_109 are true). table 1 v.17 v.29 v.27 conf high speed conf 0f 09 00 04 conf 0f 08 00 01 conf 0f 07 40 00 enbl flag (1) mw 15 10 14 00 mw 15 10 12 00 mw 15 10 12 00 enbl flag (2) mw 15 10 14 00 mw 15 10 10 00 mw 15 10 10 00 disable flag mw 15 10 04 00 mw 15 10 00 00 mw 15 10 00 00 enb short modc 40 00 modc 00 00 modc 00 00 AN814-01.tbl in fax application the coefficients are firstly com- puted when receiving the tcf frame (continuous 0 during 1.5s) in phase b of the t.30 protocol. as the dsp rev 1.0 software takes more than 1.5s when in data mode to compute the coefficients of the equalizer the host must reduce these time sending to the dsp two memory write ( mw ) command. the two mw must be sent just after sta_109 equals 1 indicating a high speed modulation signal : first mw mw e3 16 01 00 second mw mw e3 16 b0 04 the dsp will take now 1.2s after the beginning of the data mode ( sta_109 = 1 ) to compute the coefficients of the equalizer. for dsp rev 1.1 software the problem is solved and the two mw need not be sent by the host. v.17 fax equipment replacing the r144efx 11/13
ring tip 1 3 2 4 11 220pf r' r3 u1a mc33174 22k w 22k w 680pf 13.2k w 13.2k w 22k w 220pf 22k w r3 r 1 3 2 4 11 u1b mc33174 u1a mc33174 u1a mc33174 r1 r2 1.2k w 1.2k w 2.2nf 2.2nf transformer rxa2 txa1 txa2 rxa1 4 11 7 5 6 4 11 2 3 1 r1 vcm r r' vcm v/2 -v/2 vt in this example the mc33174 is powered between 0va and +5va AN814-11.eps figure 11 ix - how adjust the transmit level as explained in the st75c52/520 user's manual in chapter vi.3 the user can adjust the level on the line using the setgn command. like that the user chooses an attenuation in the transmit section (no attenuation means a 0db value for the parameter of the setgn command). there is no limitation for the attenuation values. you can use different attenuationvalues with a step less than 1db between each value. the user's manual gives as example the value for attenu- ation between 0db and -14db with a step of 1db. how to compute the value of the parameter for the setgn command ? as the attenuation is provided by a gain in the transmit section you must know the value of the next gain which gives the wanted attenuation.0db attenuationmeans a unit gain (gt = 1). for 0db the value of the setgn parameter is 7fff (hexa decimal value) or 32768 (decimal value). suppose you would like a -10db attenuation, in such a case your attenuation gain will have a value of gt = 0.6065. the value of the setgn parameter will be equal to 32768 x 0.6065 (decimale value) or 287a (hexadecimal value). now the host has only to send setng 287a (command and parameter) to the dsp to set up the attenuation gain at the wanted value. x - hardware guide line the st75c52/520 can be connected to a host processor using intel or motorola bus. a synchronisation between the st75c52/520 and the host is provided with sdtack (for data ac- knowledge) and sintr (for interrupts) signals which are both open drain. the analog interface is detailed in chapter vi, vii, vii of the st75c52/520 user's manual. here, we briefly cover the basic schematics and hybrid interface tuning (see figure 11). v.17 fax equipment replacing the r144efx 12/13
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without noti ce. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system confo rms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. components : all resistors are 1% tolerance operational amplifier sgs-thomson : mc33174 tuning : return loss : r3 = r0 2 where r0 is the value for the best return loss versus the reference inpedance z0. and z0 = 600 w or complex impedance duplexor : vt = z0 ? v ( z0 + r0 ) coef = vt v = z0 z0 + r0 to have the best rejection : r' = r coef example 1: z0 = 600 w , r0 = 600 w coef = 0.5 r = 20k w and r' = 40k w example 2 : z0 = 600 w , r0 = 440 w coef = 0.577 r = 23.08k w and r' = 40k w transmit gain : tx_gain = 22k w /13.2k w today tuned to have -9dbm on the line. to transmit at 0dbm you must : - replace the two 13.2k w 1% by two 4.64k w 1%. - replace the two 220pf by 47pf. - power supply of the amplifier : +v and -v. receive gain : rx_gain = 1 + r1 ? ? ? r2 2 ? ? ? typical values r1 = 15k w , r2 = 82k w v.17 fax equipment replacing the r144efx 13/13

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