benefit from both, the unique, highly efficient and easy to program hyperstone risc/ dsp architecture combined with the most necessary interfaces and features required for network enabling and communications within the embedded applications world. together with available software solutions and a boot via the network option, HYNET? 32xs comprises a true system on a single chip. ? highly integrated system on chip including integrated phy helps to reduce application costs excellent risc and dsp performance of 220 mips and up to 880 mops versatile interface options powersaving features and efficient realization guarantee a highly energy- efficient chip easy programming of risc and dsp key data tfbga 256; 17 x 17 x 1.4 mm, 0.8mm ball pitch core-voltage: 1.8v i/o voltage supply: 3.3v temperature range: 0 to 85c (-40 to 125c selected by test) manufactured in a 0.18m process expected maximum power consumption at full speed (worst case): <1.7 watts max. targeted applications cost sensitive network-enabling and embedded web servers wireless lan and bluetooth access points remote service applications communication infrastructure bus bridges data and voice over ip (voip) residential gateways industrial automation, control and robotics power line communications . . . . and many more high performance hyperstone processor architecture hyperstone 32-bit risc/dsp processor (e1-32xsr) up to 220mhz, dynamic frequency scaling delivering 220 mips and up to 880 mops latency based parallelism of risc alu, load/store and dsp comprehensive dsp library . . . . and many more HYNET network processor 32xs
HYNET 32xs block diagram hyperstone ag line-eid-strasse 3 78467 konstanz, germany phone: +49 7531 98030 fax: +49 7531 51725 e-mail: info@hyperstone.de web: www.hyperstone.com hyperstone taiwan 11f, no.183, sec.2, tiding blvd. neihu district, taipei, taiwan, r.o.c. phone: +886 2 8751 0203 fax: +886 2 8797 2321 e-mail: taiwan@hyperstone.com web: www.hyperstone.com.tw content is subject to change without prior notice. HYNET, HYNET 32xs, hyrtk and hydsp are trademarks of hyperstone ag. other br and, product or company names are property of the respective holder. warranties, implied or expressed as well as liablities for any damage resulting from usi ng provided information in this document are excluded until part of a separate written contract. hs-mkt-am-005-04-01 internal memory-system 16kbyte ram, two 2kbyte instruction/data caches 8kbyte mask rom (boot loader) 128kbyte sram 32kbyte shared sram (ethernet) 32-bit data and address bus key features 4 internal busses with multi channel dma controller o peripheral bus with variable frequency, to reduce power consumption o multi-master/multi-slave high frequency system bus o ethernet bus o coprocessor bus direct memory access controller with 6 independent configurable channels memory management unit (mmu) time processor unit (tpu) programmable timer with one 32-bit counter and two 16 bit counters efficient power management management unit including reset manager, clock manager, configuration unit interrupt controller galois factory coprocessor: hardware calculation of galois field operations clock synchronization core according to ieee 1588 standard yuv interface ccir656-compliant video input interface reassembling raw video data out of a ccir656 ycrcb 4:2:2 8-bit data stream jtag (boundary scan) compliant to the ieee p1149.1 real time clock watchdog versatile interfaces dual 10/100 mbit/s ethernet mac with two mii and one ethernet phy supporting real-time standard (ieee 1588), also fully compliant with ethernet standards such as ieee 802.3, 802.3u, and ansi x3.263-1995 (fddi-tp- pmd) usb 1.1 device controller with integrated transceiver, supports up to 12mbit/s serial data transmission pcm interface connecting to an external iom-2 bus controller area network (can) interface, compatible to can 2.0 and extended format, and philips sja1000 asynchronous transfer mode (atm) ? utopia level-2 interface, for connection of up to 3 external atm physical layer controller (phys) multiplexed processor interface (mpi) configurable for cpu independent external transfers, accessible directly by the cpu or a dma, connects up to 15 external power line physical layer controllers for tdm transmission communication engine, programmable serial communication providing 16 i/o lines or software controlled general purpose i/os, providing eight communication channels and commands including uart, irda, i 2 c master and slave, synchronous communication and interface options to various devices such as a/d or d/a converters, codecs and serial memories development software and hardware support all necessary development software and hardware is available from hyperstone. available options include an inexpensive starter-kit option as well as the hyperstone real-time kernel (hyrtk), dsp software library (hydsp), macro assembler, c-compiler, debugger, file linker, library manager, and profiler. hyperstone risc / dsp e1 -32xsr? 16 kb ram mmu l1 cache l2 cache 128 kb sram boot rom system bus controller memory, i/o, sdram controller external bus interface bus bridge sp 64 kb sram shared bus bridge se ethernet sub -system: dma fifo mac 1 syn1588 miis dma fifo mac 0 mii mii phy bus con - troller mgmt. unit watch -dog ? com -engine uart 1,2 irda, i 2 c, 16 gpio can mpi pcm iom -2 atm utopia yuv usb 1.1 trans - ceiver hyperstone risc / dsp e1 -32xsr? 16 kb ram mmu l1 cache l2 cache risc / dsp e1 -32xsr? 16 kb ram mmu l1 cache l2 cache 16kb ram mmu l1 cache l2 cache l2 cache 128 kb sram 128kb sram boot rom boot rom system bus controller memory, i/o, sdram controller external bus interface memory, i/o, sdram controller external bus interface bus bridge sp 6 channel dma controller 64 kb sram shared bus bridge se 32kb sram shared ethernet sub -system: dma fifo mac 1 syn1588 miis dma fifo mac 0 mii mii phy bus con - troller ethernet sub-system dma fifo mac 1 syn1588 miis dma fifo mac 0 mii mii phy bus con - troller dma fifo mac 1 syn1588 miis dma fifo mac 0 mii mii phy dma fifo mac 1 syn1588 miis dma fifo mac 0 mii mii dma fifo mac 1 syn1588 miis dma fifo mac 0 dma fifo mac 1 dma dma fifo mac 0 dma fifo dma fifo mii mii bus controller interrupt controller mgmt. unit mgmt. unit watch- dog ? ? com -engine uart 1,2 irda, i 2 c, 16 gpio com -engine uart irda, i 2 c, 16 gpio can mpi mpi pcm iom -2 atm utopia yuv usb 1.1 trans - ceiver transceiver system bus rtc timer rtc timer peripheral bus galois factory coprocessor
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