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stpc ? industrial pc compatible embedded microprocessor 1/69 11/2/02 issue 2.4 isa i/f figure 1. logic diagram n powerful x86 processor n 64-bit bus architecture n 64-bit 66mhz dram controller n svga graphics controller n 135mhz ramdac n uma architecture n tft display controller n pci master / slave / arbiter n local bus interface n isa (master/slave) interface -including the ipc n pc-card interface - pcmcia - cardbus n i/o features - pc/at+ keyboard controller - ps/2 mouse controller - 2 serial ports - 1 parallel port n ipc - dma controller - interrupt controller - timer / counters n power management stpc industrial overview the stpc industrial integrates a fully static x86 processor, fully compatible with standard fifth gen- eration x86 processors, and combines it with pow- erful chipset, graphics, tft, pc-card, local bus, keyboard, mouse, serials and parallel interfaces to provide a single industrial oriented pc compatible subsystem on a single device. the performance of the device is comparable with the performance of a typical p5 generation system. the device is packaged in a 388 plastic ball grid array (pbga). tft ext x86 core host i/f serial2 // port serial1 kbd mouse dram i/f vga ge pci m/s local bus i/f pcmcia cardbus pci bus ipc 82c206 pci controller isa bus crtc hw cursor monitor tft output sync output tft i/f pbga388
stpc industrial 2/69 issue 2.4 - februar y 11, 2002 n x86 processor core n fully static 32-bit 5-stage pipeline, x86 processor fully pc compatible. n access up to 4gb of external memory. n 8kbyte unified instruction and data cache with write back capability. n parallel processing integral floating point unit, with automatic power down. n clock core speeds up to 100 mhz. n fully static design for dynamic clock control. n low power and system management modes. n optimized design for 3.3v operation. n dram controller n integrated system memory and graphic frame memory. n supports up to 128-mbyte system memory in 4 banks and down to as little as 2mbytes. n supports 4-mbyte, 8-mbyte, 16-mbyte, and 32-mbyte single-sided and double-sided dram simms. n four quad-word write buffers for cpu to dram and pci to dram cycles. n four quad-word read prefetch buffers for pci masters. n supports fast page mode & edo drams. n programmable timing for dram parameters including cas pulse width, cas pre-charge time, and ras to cas delay. n 60, 70, 80 & 100ns dram speeds. n memory hole between 1 mbyte & 8 mbyte supported for pci/isa busses. n hidden refresh. to check if your memory device is supported by the stpc, please refer to table 6-24 in the programming manual. n graphics controller n 64-bit windows accelerator. n complete backward compatibility to vga and svga standards. n hardware acceleration for text (generalized bit map expansion), bitblts, transparent blts and fills. n up to 64 x 64 bit graphics hardware cursor. n up to 4mb long linear frame buffer. n 8, 16, 24 and 32 bit pixels. n drivers for windows and other operating systems. n crt controller n integrated 135mhz triple ramdac allowing for 1280 x 1024 x 75hz display. n requires external frequency synthesizer and reference sources. n 8, 16, 24 and 32-bit pixels. n interlaced or non-interlaced output. n tft interface n programmable panel size up to 1024 by 1024 pixels. n support for 640 x 480, 800 x 600 & 1024 x 768 active matrix tft flat panels with 9, 12, 18-bit interface. n support 1 & 2 pixels per clock. n programmable image positionning. n programmable blank space insertion in text mode. n programmable horizontal and vertical image expansion in graphic mode. n a fully programmable pwm (pulse width modulator) signals to adjust the flat panel brightness and contrast. n supports panellink tm high speed serial transmitter externally for high resolution panel interface. n pci controller n fully compliant with pci version 2.1 specification. n integrated pci arbitration interface. up to 3 masters can connect directly. external pal allows for greater than 3 masters. n translation of pci cycles to isa bus. n translation of isa master initiated cycle to pci. n support for burst read/write from pci master. n 0.33x and 0.5x cpu clock pci clock. n local bus interface n 66mhz, low latency bus. n asynchronous / synchronous. n 22-bit address and 16-bit data busses. n 2 programmable flash eprom chip select. n 4 programmable i/o chip select. n separate memory and i/o address spaces. n memory prefetch (improved performances).
stpc industrial issue 2.4 - february 11, 2002 3/69 n isa master/slave n generation of the isa clock from either 14.318mhz oscillator clock or system clock n programmable extra wait state for isa cycles n supports i/o recovery time for back to back i/o cycles. n fast gate a20 and fast reset. n supports the single rom that c, d, or e. blocks shares with f block bios rom. n supports flash rom. n supports isa hidden refresh. n buffered dma & isa master cycles to reduce bandwidth utilization of the pci and host bus. nsp compliant. n pc-card interface n support one pcmcia 2.0 / jeida 4.1 68-pin standard pc card socket. n power management support. n support pcmcia/ata specifications. n support i/o pc card with pulse-mode interrupts. n provides an exca tm implementation to pcmcia 2.0 / jeida 4.1 standards. n dma support. n keyboard interface n fully pc/at& compatible n mouse interface n fully ps/2 compatible n serial interface n 16550a compatible n programmable word length, stop bits, parity. n 16-bit programmable baud rate generator. n interrupt generator. n loop-back mode. n 8-bit scratch register. n two 16-bit fifos. n two dma handshake lines. n parallel port n standard centronics mode supported. n nibble mode supported. n integrated peripheral controller n two 8237/at compatible 7-channel dma controllers. n two 8259/at compatible interrupt controller. 16 interrupt inputs - isa and pci. n three 8254 compatible timer/counters. n co-processor error support logic. n power management n four power saving modes: on, doze, standby, suspend. n programmable system activity detector n supports smm. n supports io trap & restart. n independent peripheral time-out timer to monitor hard disk, serial & parallel ports. n supports apm n supports rtc, interrupt and dma wake ups exca is a trademark of pcmcia / jeida. panellink is a trademark of siliconimage, inc
stpc industrial 4/69 issue 2.4 - februar y 11, 2002
general description issue 2.4 - february 11, 2002 5/69 1 general description at the heart of the stpc industrial is an advanced 64-bit processor block, dubbed the 5st86. the 5st86 includes a powerful x86 processor core along with a 64-bit dram controller, advanced 64-bit accelerated graphics and video controller, a high speed pci local-bus controller and industry standard pc chip set functions (interrupt controller, dma controller, interval timer and isa bus). the stpc industrial has in addition to the 5st86 a tft output, a local bus interface, pc card and super i/o features. the stpc industrial makes use of a tightly coupled unified memory architecture (uma), where the same memory array is used for cpu main memory and graphics frame-buffer. this means a reduction in total system memory for system performances that are equal to that of a comparable frame buffer and system memory based system, and generally much better, due to the higher memory bandwidth allowed by attaching the graphics engine directly to the 64-bit processor host interface running at the speed of the processor bus rather than the traditional pci bus. the 64-bit wide memory array provides the system with 320mb/s peak bandwidth, double that of an equivalent system using 32 bits. this allows for higher resolution screens and greater color depth. the processor bus runs at 66mhz further increasing standard bandwidth by at least a factor of two. the standard pc chipset functions (dma, interrupt controller, timers, power management logic) are integrated together with the x86 processor core; additional functions such as communication ports are accessed by the stpc industrial via an internal isa bus. the pci bus is the main data communication link to the stpc industrial chip. the stpc industrial translates appropriate host bus i/o and memory cycles onto the pci bus. it also supports the generation of configuration cycles on the pci bus. the stpc industrial, as a pci bus agent (host bridge class), fully complies with pci specification 2.1. the chip-set also implements the pci mandatory header registers in type 0 pci configuration space for easy porting of pci aware system bios. the device contains a pci arbitration function for three external pci devices. graphics functions are controlled through the on- chip svga controller and the monitor display is produced through the 2d graphics display engine. this graphics engine is tuned to work with the host cpu to provide a balanced graphics system with a low silicon area cost. it performs limited graphics drawing operations which include hardware acceleration of text, bitblts, transparent blts and fills. the results of these operations change the contents of the on-screen or off- screen frame buffer areas of dram memory. the frame buffer can occupy a space up to 4 mbytes anywhere in the physical main memory. the maximum graphics resolution supported is 1280x1024 in 65536 colours at 75hz refresh rate and is vga and svga compatible. horizontal timing fields are vga compatible while the vertical fields are extended by one bit to accommodate above display resolution. to generate the tft output, the stpc industrial extracts the digital video stream before the ramdac and reformats it to the tft format. the height and width of the flat panel are programmable through configuration registers up to a size of 1024 by 1024. by default, lower resolution images cover only a part of the larger tft panel. the stpc industrial allows to expand the image vertically and horizontally in text mode by inserting programmable blank pixels. it allows expantion of the image vertically and horizontally in graphics mode by replicating pixels. the replication of j times every k pixel is independently programmable in the vertical and horizontal directions. panellink tm is a proprietary interconnect protocol defined by silicon image, inc. it consists of a transmitter that takes parallel video/graphics data from the host lcd graphics controller and transmits it serially at high speed to the receiver which controls the tft panel. the tft interface is designed to support the connection of this control signal to the panellink tm transmitter. the stpc industrial cardbus / pcmcia controller has been specifically designed to provide the interface with pc-cards which contain additional memory or i/o and provides an exca tm implementation to pcmcia 2.0 / jeida 4.1 standards. the power management control facilities include socket power control, insertion/removal capability, power saving with windows inactivity, ncs controlled chip power down, together with further controls for 3.3v suspend with modem ring resume detection.
general description 6/69 issue 2.4 - februar y 11, 2002 the need for system configuration jumpers is eliminated by providing address mapping support for pcmcia 2.0 / jeida 4.1 pc-card memory together with address windowing support for i/o space. selectable interrupt steering from pc-card to internal system bus is also provided. the stpc industrial implements a multi-function parallel port. the standard pc/at compatible logical address assignments for lpt1, lpt2 and lpt3 are supported. the parallel port can be configured for any of the following 3 modes and supports the ieee standard 1284 parallel interface protocol standards as follow: -compatibility mode (forward channel, standard) -nibble mode (reverse channel, pc compatible) -byte mode (reverse channel, ps/2 compatible) the stpc industrial bga package has 388 balls, but this is not sufficient for all the integrated functions, therefore some features are sharing the same balls and can not be used at the same time. the stpc industrial configuration is done by strap options. it is a set of pull-up or pull-down resistors on the memory data bus, checked on reset, which auto-configure the stpc industrial. we can distinguish three main blocks independently configurables : the isa / local bus block, the serial 1 / tft block, and the pci / pc card block. from the first block, we can activate either the isa bus and some ipc additionnal features, or the local bus, the parallel port and the second serial interface. from the second block, we can activate either the first serial port, or the tft extension to get from 4 bit per colour to 6 bit per colour. from the third block, we can activate either the pci bus, or the pc card interface (cardbus/ pcmcia/zoomvideo). the stpc industrial core is compliant with the advanced power management (apm) specification to provide a standard method by which the bios can control the power used by personal computers. the power management unit module (pmu) controls the power consumption providing a comprehensive set of features that control the power usage and supports compliance with the united states environmental protection agency's energy star computer program. the pmu provides following hardware structures to assist the software in managing the power consumption by the system. - system activity detection. - 3 power-down timers detecting system inactivity: - doze timer (short durations). - stand-by timer (medium durations). - suspend timer (long durations). - house-keeping activity detection. - house-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand-by state. - peripheral activity detection. - peripheral timer detecting peripheral inactivity - susp# modulation to adjust the system performance in various power down states of the system including full power on state. - power control outputs to disable power from different planes of the board. lack of system activity for progressively longer periods of time is detected by the three power down timers. these timers can generate smi interrupts to cpu so that the smm software can put the system in decreasing states of power consumption. alternatively, system activity in a power down state can generate smi interrupt to allow the software to bring the system back up to full power on state. the chip-set supports up to three power down states described above, these correspond to decreasing levels of power savings. power down puts the stpc industrial into suspend mode. the processor completes execution of the current instruction, any pending decoded instructions and associated bus cycles. during the suspend mode, internal clocks are stopped. removing power down, the processor resumes instruction fetching and begins execution in the instruction stream at the point it had stopped. because of the static nature of the core, no internal data is lost..
general description issue 2.4 - february 11, 2002 7/69 figure 1.1. functionnal description. x86 core host i/f serial 2 // port serial 1 dram i/f vga ge pci m/s local bus i/f pcmcia cardbus pci bus isa m/s ipc 82c206 pci m/s isa bus crtc hw cursor monitor tft output sync output tft i/f tft extension kbd mouse
general description 8/69 issue 2.4 - februar y 11, 2002 figure 1.2. pci, pcmcia & cardbus modes: pci m/s pcmcia cardbus pci bus pci m/s pcmcia cardbus pci bus pci m/s pcmcia cardbus pci bus
general description issue 2.4 - february 11, 2002 9/69 figure 1.3. local bus and isa bus modes: figure 1.4. tft in normal (serial 1 available) and extended modes (serial 1 unavailable). serial 2 // port local bus i/f isa m/s ipc 82c206 isa bus serial 2 // port local bus i/f isa m/s ipc 82c206 isa bus serial 1 tft extension tft extension tft output tft i/f kbd mouse serial 1 kbd mouse tft output tft i/f 9-bit mode 12-bit mode 18-bit mode 2 x 9-bit mode
general description 10/69 issue 2.4 - februar y 11, 2002 figure 2. typical pc oriented application isa pci 4x 16-bit edo drams super i/o flash ide serial ports parallel port floppy monitor tft svga irq dma.req dma.ack dmux mux mux stpc industrial rtc mouse keyboard
general description issue 2.4 - february 11, 2002 11/69 figure 3. typical embedded application stpc industrial pc-card 4x 16-bit edo drams flash peripheral irq mux pcmcia cardbus monitor tft svga mouse keyboard serial ports parallel port stpc local bus i/o sram
pin description 12/69 issue 2.4 - februar y 11, 2002 2 pin description 2.1. introduction the stpc industrial integrates most of the func- tionalities of the pc architecture. therefore, many of the traditional interconnections between the host pc microprocessor and the peripheral devic- es are totally internal to the stpc industrial. this offers improved performance due to the tight cou- pling of the processor core and its peripherals. as a result many of the external pin connections are made directly to the on-chip peripheral functions. figure 2-1 shows the stpc industrial external in- terfaces. it defines the main buses and their func- tion. table 2-1 describes the physical implementa- tion listing signal types and their functionalities. table 2-2 provides a full pin listing and descrip- tion. table 2-4 provides a full listing of the stpc indus- trial package pin location physical connection. please refer to the pin allocation drawing for refer- ence. due to the number of pins available for the pack- age, and the number of functional i/os, some pins have several functions, selectable by strap option on reset. table 2-3 provides a summary of these pins and their functions. table 2-1. signal description group name qty basic clocks, reset & xtal (sys) 13 dram controller(dram) 89 pci controller 55 64 pc card interface 64 keyboard/mouse controller (sio) 4 local bus i/f, parallel i/f, serial 2 75 75 isa interface/ipc extensions 73 serial 1 (sio) 8 26 tft output 24 vga controller (vga) 10 grounds 74 v dd 16 analog specific v cc /v dd 16 reserved 1 total pin count 388 figure 2-1. stpc industrial external interfaces pci x86 core dram vga tft sys sio 89 10 24 12 55 13 75 38 stpc industrial card pc isa/ local bus north bridge south bridge
pin description issue 2.4 - february 11, 2002 13/69 table 2-2. definition of signal pins signal name dir description qty basic clocks and resets sysrsti#* i system reset / power good 1 sysrsto#* o reset output to system 1 xtali i 14.3 mhz crystal input 1 xtalo o 14.3 mhz crystal output 1 pci_clki* i 33 mhz pci/cardbus input clock 1 pci_clko o 33 mhz pci/cardbus output clock 1 isa_clk, isa_clk2x o isa clock x1 and x2 (also multiplexer select line for ipc) 2 clk14m o isa bus synchronisation clock 1 hclk* i/o 33 / 66 mhz host clock (test) 1 dev_clk* o 24 mhz peripheral clock 1 gclk2x i/o 80 mhz graphics clock 1 dclk i/o 135 mhz dot clock 1 v dd _xxx_pll power supply for pll clocks memory interface ma[11:0] o memory address 12 ras#[3:0] o row address strobe 4 cas#[7:0] o column address strobe 8 mwe# o write enable 1 md[63:0] i/o memory data 64 local bus interface (combined with isa bus ) pa[21:0]* o address bus [21:0] 22 pd[15:0]* i/o data bus [15:0] 16 prdy#* i ready 1 pwr#[1:0]* o memory and i/o write signals 2 prd#[1:0]* o memory and i/o read signals 2 fcs#[1:0]*, iocs#[3:0]* o flash memory and i/o chip select 6 isa bus interface (combined with local bus, parallel port, serial interface) la[23:17]* o unlatched address 7 sa[19:0]* o latched address 20 sd[15:0]* i/o data bus 16 iochrdy* i i/o channel ready 1 ale* o address latch enable 1 bhe#* o system bus high enable 1 memr#*, memw#* i/o memory read & write 2 smemr#*, smemw#* o system memory read and write 2 ior#*, iow#* i/o i/o read and write 2 master#* i add on card owns bus 1 mcs16#*, iocs16#* i memory chip select 16, i/o chip select 16 2 ref#* i refresh cycle 1 aen* o address enable 1 iochck#* i i/o channel check (isa) 1 rtcrw#* o rtc read / write# 1 rtcds#* o rtc data strobe 1 rtcas#* o rtc address strobe 1
pin description 14/69 issue 2.4 - februar y 11, 2002 rmrtccs#* o rom / rtc chip select 1 gpiocs#* i/o general purpose chip select 1 irq_mux[3:0]* i multiplexed interrupt request 4 dack_enc[2:0]* o dma acknowledge 3 dreq_mux[1:0]* i multiplexed dma request 2 tc* o isa terminal count 1 keyboard & mouse interface kbdata*, mdata* i keyboard & mouse data line 2 kbclk*, mclk* o keyboard & mouse clock line 2 serial interface (serial 1 combined with tft interface / serial 2 combined with ipc ) sin1*, sin2* i serial data in (serial 1, 2) 2 sout1*, sout2* o serial data out (serial 1, 2) 2 cts1#*, cts2#* i clear to send (serial 1, 2) 2 rts1#*, rts2#* o request to send (serial 1, 2) 2 dsr1#*, dsr2#* i data set ready (serial 1, 2) 2 dtr1#*, dtr2#* o data terminal ready (serial 1,2) 2 dcd1#*, dcd2#* i data carrier detect (serial 1, 2) 2 ri1#*, ri2#* i ring indicator (serial 1, 2) 2 parallel port (combined with isa bus and ipc) pe* i paper end 1 slct* i select 1 busy#* i busy 1 err#* i error 1 ack#* i acknowledge 1 pddir#* o parallel device direction 1 strobe#* o pcs / strobe# 1 init#* o init 1 autpfdx#* o automatic line feed 1 slctin#* o select in 1 ppd[7:0]* i/o data bus 8 pcmcia interface (combined with pci / cardbus) reset* o reset 1 a[25:0]* o address bus 26 d[15:0]* i/o data bus 16 iord#*, iowr#* o i/o read and write 2 dreq#* / wp* / iois16#* i dma request // write protect // i/o size is 16-bit 1 bvd1*, bvd2* i battery voltage detect 2 ready# */busy#*/ireq#* i ready / busy // interrupt request 1 wait#* i wait 1 inpack#* i input port acknowledge 1 oe#* / tcw* o output enable // dma terminal count 1 we#* / tcr* o write enable // dma terminal count 1 dack* / reg#* o dma acknowledge // register 1 cd1#*, cd2#* i card detect 2 table 2-2. definition of signal pins signal name dir description qty
pin description issue 2.4 - february 11, 2002 15/69 ce1#*, ce2#* o card enable 2 vs1#*, vs2#* i voltage sense 2 vcc5_en* o power switch control : 5 v power 1 vcc3_en* o power switch control : 3.3 v power 1 vpp_pgm* o power switch control : program power 1 vpp_vcc* o power switch control : vcc power 1 cardbus interface (combined with pci / pcmcia) cclkrun* i/o clock 1 crst#* o reset 1 cstschg#* i system change 1 cad[31:0]* i/o address / data 32 cbe[3:0]* i/o bus commands / byte enables 4 cframe#* i/o cycle frame 1 ctrdy#* i/o target ready 1 cirdy#* i/o initiator ready 1 cstop#* i/o stop transaction 1 cdevsel#* i/o device select 1 cpar* i/o parity signal transactions 1 cserr#* i system error 1 cperr#* i/o parity error 1 cblock#* i/o pci lock 1 ccd[2:1]* i card detect 2 cint#* i interrupt request 1 creq#* i request 1 cgnt#* o grant 1 pci interface (combined with pcmcia / cardbus) ad[31:0]* i/o address / data 32 be[3:0]* i/o bus commands / byte enables 4 frame#* i/o cycle frame 1 trdy#* i/o target ready 1 irdy#* i/o initiator ready 1 stop#* i/o stop transaction 1 devsel#* i/o device select 1 par* i/o parity signal transactions 1 serr#* o system error 1 lock#* i pci lock 1 pci_req#[2:0]* i pci request 3 pci_gnt#[2:0]* o pci grant 3 pci_int[3:0]* i pci interrupt request 4 table 2-2. definition of signal pins signal name dir description qty
pin description 16/69 issue 2.4 - februar y 11, 2002 note; * denotes that the pin is v 5t (see section 4 ) monitor interface red, green, blue o red, green, blue 3 vsync* i/o vertical sync 1 hsync* i/o horizontal sync 1 vref_dac i dac voltage reference 1 rset i resistor set 1 comp i compensation 1 ddc[1:0]* i/o display data channel serial link 2 scl / ddc[1]* i/o i2c interface - clock / can be used for vga ddc[1] signal 1 sda / ddc[0]* i/o i2c interface - data / can be used for vga ddc[0] signal 1 tft interface (combined with serial 1) r[5:0], g[5:0], b[5:0] o red, green, blue 18 fpline o horizontal sync 1 fpframe o vertical sync 1 de o data enable 1 enavdd o enable vdd of flat panel 1 envcc o enable vcc of flat panel 1 pwm o pwm back-light control 1 miscellaneous spkrd* o speaker device output 1 scan_enable i test pin - reserved 1 table 2-2. definition of signal pins signal name dir description qty
pin description issue 2.4 - february 11, 2002 17/69 2.2. signal descriptions 2.2.2 basic clocks and resets sysrsti# system reset/power good. this input is low when the reset switch is depressed. other- wise, it reflects the power supplys power good signal. pwgd is asynchronous to all clocks, and acts as a negative active reset. the reset circuit initiates a hard reset on the rising edge of pwgd. sysrsto# reset output to system. this is the system reset signal and is used to reset the rest of the components (not on host bus) in the system. the isa bus reset is an externally inverted buff- ered version of this output and the pci bus reset is an externally buffered version of this output. xtali 14.3 mhz crystal input xtalo 14.3 mhz crystal output. these pins are the 14.318 mhz crystal input; this clock is used as the reference clock for the internal frequency syn- thesizer to generate the hclk and clk24m. a 14.318 mhz series cut quartz crystal should be connected between these two pins. balance capacitors of 15 pf should also be added. in the event of an external oscillator providing the master clock signal to the stpc industrial device, the ttl signal should be provided on xtalo. pci_clki 33 mhz pci input clock this signal must be connected to a clock genera- tor and is usually connected to pci_clko. pci_clko 33 mhz pci output clock. this is the master pci bus clock output isa_clk isa clock output (also multiplexer se- lect line for ipc). this pin produces the clock signal for the isa bus. it is also used with isa_clk2x as the multiplexer control lines for the interrupt controller interrupt input lines. this is a divided down version of the pciclk or osc14m. isa_clkx2 isa clock output (also multiplexer select line for ipc). this pin produces a signal at twice the frequency of the isa bus clock signal. it is also used with isa_clk as the multiplexer con- trol lines for the interrupt controller interrupt input lines. clk14m isa bus synchronisation clock. this is the buffered 14.318 mhz clock to the isa bus. this clock also provides the reference clock to the frequency synthesizer that generates gclk2x and dclk. hclk host clock. this is the host 1x clock. its frequency can vary from 50 mhz to 75 mhz. all host transactions and pci transactions are syn- chronized to this clock. host transactions execut- ed by the dram controller are also driven by this clock. dev_clk 24 mhz peripheral clock (floppy drive). this 24 mhz signal is provided as a con- venience for the system integration of a floppy disk driver function in an external chip. gclk2x 80 mhz graphics clock. this is the graphics 2x clock, which drives the graphics en- gine and the dram controller to execute the graphics and display cycles. normally gclk2x is generated by the internal fre- quency synthesizer, and this pin is an output. by setting a bit in strap register 2, this pin can be made an input so that an external clock can re- place the internal frequency synthesizer. dclk 135 mhz dot clock. this is the dot clock, which drives graphics display cycles. its frequency can go from 8 mhz (using internal pll) up to 135 mhz, and it is required to have a worst case duty cycle of 60-40. the direction can be controlled by a strap option or an internal register bit. 2.2.3 memory interface ma[11:0] memory address. these 12 multiplexed memory address pins support external dram with up to 4k refresh. these include all 16m x n and some 4m x n dram modules. the address sig- nals must be externally buffered to support more than 16 dram chips. the timing of these signals can be adjusted by software to match the timings of most dram modules. md[63:0] memory data. this is the 64-bit memory data bus. if only half of a bank is populated, md63-32 is pulled high, data is on md31-0. md20-0 are also used as inputs at the rising edge of pwgd to latch in power-up configuration infor- mation into the adpc strap registers. ras#[3:0] row address strobe. there are four active low row address strobe outputs, one each for each bank of the memory. each bank contains 4 or 8 bytes of data. the memory controller allows half of a bank (4 bytes) to be populated to enable memory upgrade at finer granularity. the ras# signals drive the simms directly with- out any external buffering. these pins are always outputs, but they can also simultaneously be in- puts, to allow the memory controller to monitor the value of the ras# signals at the pins.
pin description 18/69 issue 2.4 - februar y 11, 2002 cas#[7:0] column address strobe. there are 8 active low column address strobe outputs, one each for each byte of the memory. the cas# signals drive the simms either directly or through external buffers. these pins are always outputs, but they can also simultaneously be inputs, to allow the memory controller to monitor the value of the cas# signals at the pins. mwe# write enable. write enable specifies whether the memory access is a read (mwe# = h) or a write (mwe# = l). this single write enable controls all drams. it can be externally buffered to boost the maximum number of loads (dram chips) supported. the mwe# signals drive the simms directly with- out any external buffering. 2.2.4 local bus interface (combined with isa bus) pa[21:0] memory address. this is the 22-bit lo- cal bus address pd[15:0] data bus. this is the 16-bit bidirectional local bus data bus. prdy# ready. this input signals the local bus ready state. pwr#1 memory and i/o write signal for ms byte pwr#0 memory and i/o write signal for ls byte . prd#1 memory and i/o read signals for ms byte . prd#0 memory and i/o read signals for ls byte . fcs#[1:0], iocs#[3:0] flash memory and i/o chip select. 2.2.5 isa bus interface la[23:17] unlatched address. these unlatched isa bus pins address bits 23-17 on 16-bit devices. when the isa bus is accessed by any cycle initiat- ed from the pci bus, these pins are in output mode. when an isa bus master owns the bus, these pins are tristated. sa[19:0] unlatched address. these are the 20 low bits of the system address bus of isa. these pins are used as an input when an isa bus master owns the bus and are outputs at all other times. sd[15:0] i/o data bus (isa). these are the exter- nal isa data bus pins. iochrdy io channel ready. iochrdy is the io channel ready signal of the isa bus and is driven as an output in response to an isa master cycle targeted to the host bus or an internal register of the stpc industrial. the stpc industrial moni- tors this signal as an input when performing an isa cycle on behalf of the host cpu, dma master or refresh. isa masters which do not monitor iochrdy are not guaranteed to work with the stpc industrial since the access to the system memory can be considerably delayed due to crt refresh or a write back cycle. ale address latch enable. this is the address latch enable output of the isa bus and is asserted by the stpc industrial to indicate that la23-17, sa19-0, aen and sbhe# signals are valid. the ale is driven high during refresh, dma master or an isa master cycles by the stpc industrial. ale is driven low after reset. bhe# system bus high enable. this signal, when asserted, indicates that a data byte is being trans- ferred on sd15-8 lines. it is used as an input when an isa master owns the bus and is an output at all other times. memr# memory read. this is the memory read command signal of the isa bus. it is used as an in- put when an isa master owns the bus and is an output at all other times. the memr# signal is active during refresh. memw# memory write. this is the memory write command signal of the isa bus. it is used as an in- put when an isa master owns the bus and is an output at all other times. smemr# system memory read. the stpc in- dustrial generates smemr# signal of the isa bus only when the address is below one mbyte or the cycle is a refresh cycle. smemw# system memory write. the stpc in- dustrial generates smemw# signal of the isa bus only when the address is below one mbyte. ior# i/o read. this is the io read command sig- nal of the isa bus. it is an input when an isa mas- ter owns the bus and is an output at all other times. iow# i/o write. this is the io write command sig- nal of the isa bus. it is an input when an isa mas- ter owns the bus and is an output at all other times. master# add on card owns bus. this signal is active when an isa device has been granted bus ownership. mcs16# memory chip select16. this is the de- code of la23-17 address pins of the isa address
pin description issue 2.4 - february 11, 2002 19/69 bus without any qualification of the command sig- nal lines. mcs16# is always an input. the stpc industrial ignores this signal during io and refresh cycles. iocs16# io chip select16. this signal is the de- code of sa15-0 address pins of the isa address bus without any qualification of the command sig- nals. the stpc industrial does not drive iocs16# (similar to pc-at design). an isa master access to an internal register of the stpc industrial is ex- ecuted as an extended 8-bit io cycle. ref# refresh cycle. this is the refresh command signal of the isa bus. it is driven as an output when the stpc industrial performs a refresh cycle on the isa bus. it is used as an input when an isa master owns the bus and is used to trigger a re- fresh cycle. the stpc industrial performs a pseudo hidden refresh. it requests the host bus for two host clocks to drive the refresh address and capture it in external buffers. the host bus is then relin- quished while the refresh cycle continues on the isa bus. aen address enable. address enable is enabled when the dma controller is the bus owner to indi- cate that a dma transfer will occur. the enabling of the signal indicates to io devices to ignore the ior#/iow# signal during dma transfers. iochck# io channel check. io channel check is enabled by any isa device to signal an error condition that can not be corrected. nmi signal be- comes active upon seeing iochck# active if the corresponding bit in port b is enabled. gpiocs# i/o general purpose chip select 1. this output signal is used by the external latch on isa bus to latch the data on the sd[7:0] bus. the latch can be use by pmu unit to control the exter- nal peripheral devices to power down or any other desired function. rtcrw# real time clock rw#. this pin is used as rtcrw#. this signal is asserted for any i/o write to port 71h. rtcds# real time clock ds . this pin is used as rtcds. this signal is asserted for any i/o read to port 71h. rtcas# real time clock address strobe. this sig- nal is asserted for any i/o write to port 70h. rmrtccs# rom/real time clock chip select. this pin is a multi-function pin. this signal is as- serted if a rom access is decoded during a mem- ory cycle. it should be combined with memr# or memw# signals to properly access the rom. during an io cycle, this signal is asserted if ac- cess to the real time clock (rtc) is decoded. it should be combined with ior# or iow# signals to properly access the real time clock. irq_mux[3:0] multiplexed interrupt request. these are the isa bus interrupt signals. they are to be encoded before connection to the stpc in- dustrial using isaclk and isaclkx2 as the input selection strobes. note that irq8b, which by convention is connect- ed to the rtc, is inverted before being sent to the interrupt controller, so that it may be connected di- rectly to the irq# pin of the rtc. 2.2.6 ipc (combined with serial interface) dack_enc[2:0] dma acknowledge. these are the isa bus dma acknowledge signals. they are encoded by the stpc industrial before output and should be decoded externally using isaclk and isaclkx2 as the control strobes. dreq_mux[1:0] isa bus multiplexed dma re- quest. these are the isa bus dma request sig- nals. they are to be encoded before connection to the stpc industrial using isaclk and isaclkx2 as the input selection strobes. tc isa terminal count. this is the terminal count output of the dma controller and is connected to the tc line of the isa bus. it is asserted during the last dma transfer, when the byte count expires. 2.2.7 keyboard/mouse interface kbclk, keyboard clock line. keyboard data is latched by the controller on each negative clock edge produced on this pin. the keyboard can be disabled by pulling this pin low by software control. kbdata, keyboard data line. 11 bits of data are shifted serially through this line when data is being transferred. data is synchronised to kbclk. mclk, mouse clock line. mouse data is latched by the controller on each negative clock edge pro- duced on this pin. the mouse can be disabled by pulling this pin low by software control. mdata, mouse data line. 11 bits of data are shifted serially through this line when data is being transferred. data is synchronised to mclk. note: mclk and mdata must be pulled when the stpc mouse interface is not used . 2.2.8 serial interface (serial 1 combined with tft interface) (serial 2 combined with ipc) sin1, sin2 input serial input. data is clocked in using rclk/16.
pin description 20/69 issue 2.4 - februar y 11, 2002 sout1, sout2 serial output. data is clocked out using tclk/16 (tclk=baud#). dcd1#, dcd2# input data carrier detect. ri1#, ri2# input ring indicator. dsr1#, dsr2# input data set ready. cts1#, cts2# input clear to send. rts1#, rts2# output request to send. dtr1#, dtr2# output data terminal read. 2.2.9 parallel port (combined with isa bus an ipc) pe paper end. input status signal from printer. slct printer select. printer selected input. busy# printer busy . input status signal from printer. err# error . input status signal from printer. ack# acknowledge. input status signal from printer. pddir# parallel device direction. bidirectional control line output. strobe# pcs/strobe#. data transfer strobe line to printer. init# initialize printer. this output sends an initial- ize command to the connected printer. autpfdx# automatic line feed. this output sends a command to the connected printer to au- tomatically generate line feed on received car- riage returns. slctin# select in. printer select output. ppd[7-0] printer data lines data transfer lines to printer. bidirectional depending on modes. important note: where the parallel port is not used, ppd[0], con- nected to device pin c25, must be pulled up to 1. this is to avoid memory access problems associ- ated with the mcs16 memory chip select line when in the isa bus mode. 2.2.10 pcmcia interface (combined with pci / cardbus) reset card reset. this output forces a hard reset to a pc card. a[25:0] address bus. these are the 25 low bits of the system address bus of the pcmcia bus. these pins are used as an input when an pcmcia bus owns the bus and are outputs at all other times. d[15:0] i/o data bus (pcmcia). these are the external pcmcia data bus pins. ca[25-0] card address . used with the lower 11 bits of the isa address bus to generate the card address. iord# i/o read. this output is used with reg# to gate i/o read data from the pc card, (only when reg# is asserted). iowr# i/o write . this output is used with reg# to gate i/o write data from the pc card, (only when reg# is asserted). wp write protect. this input indicates the status of the write protect switch (if fitted) on memory pc cards (asserted when the switch is set to write protect). bvd1, bvd2 battery voltage detect. these in- puts will be generated by memory pc cards that include batteries and are an indication of the con- dition of the batteries. bvd1 and bvd2 are kept asserted high when the battery is in good condi- tion. ready#/busy#/ireq# ready/busy/interrupt re- quest. this input is driven low by memory pc cards to signal that their circuits are busy processing a previous write command. wait# bus cycle wait. this input is driven by the pc card to delay completion of the memory or i/o cycle in progress. oe# output enable. oe# is an active low output which is driven to the pc card to gate memory read data from memory pc cards. we#/prgm# write enable. this output is used by the host for gating memory write data. we# is also used for memory pc cards that have pro- grammable memory. reg# attribute memory select. this output is in- active (high) for all normal accesses to the main memory of the pc card. i/o pc cards will only re- spond to iord# or iowr# when reg# is active (low). also see section 2.2.6 cd1#, cd2# card detect. these inputs provide for the detection of correct card insertion. cd#1 and cd#2 are positioned at opposite ends of the connector to assist in the detection process. these inputs are internally grounded on the pc
pin description issue 2.4 - february 11, 2002 21/69 card therefore they will be forced low whenever a card is inserted in a socket. ce1#, ce2# card enable . these are active low output signals provided from the pcic. ce#1 ena- bles even bytes, ce#2 odd bytes. enable# enable. this output is used to activate/ select a pc card socket. enable# controls the external address buffer logic.c card has been de- tected (cd#1 and cd#2 = '0'). enif# enif . this output is used to activate/select a pc card socket. ext_dir external transceivers direction con- trol. this output is high during a read and low dur- ing a write. the default power up condition is write (low). used for both low and high bytes of the data bus. vcc_en#, vpp1_en0, vpp1_en1, vpp 2_en0, vpp2_en1 power control. five output signals used to control voltages (vpp1, vpp2 and vcc) to a pc card socket. also see section 13.7.5. gpi# general purpose input. this signal is hard- wired to 1. 2.2.11 cardbus interface (combined with pci / pcmcia) for card bus pinouts, refer to the pci pinout. 2.2.12 pci interface ad[31:0] pci address/data. this is the 32-bit multiplexed address and data bus of the pci. this bus is driven by the master during the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. be[3:0]# bus commands/byte enables. these are the multiplexed command and byte enable signals of the pci bus. during the address phase they define the command and during the data phase they carry the byte enable information. these pins are inputs when a pci master other than the stpc industrial owns the bus and out- puts when the stpc industrial owns the bus. frame# cycle frame. this is the frame signal of the pci bus. it is an input when a pci master owns the bus and is an output when stpc industrial owns the pci bus. trdy# target ready. this is the target ready sig- nal of the pci bus. it is driven as an output when the stpc industrial is the target of the current bus transaction. it is used as an input when stpc in- dustrial initiates a cycle on the pci bus. irdy# initiator ready. this is the initiator ready signal of the pci bus. it is used as an output when the stpc industrial initiates a bus cycle on the pci bus. it is used as an input during the pci cy- cles targeted to the stpc industrial to determine when the current pci master is ready to complete the current transaction. stop# stop transaction. stop# is used to im- plement the disconnect, retry and abort protocol of the pci bus. it is used as an input for the bus cy- cles initiated by the stpc industrial and is used as an output when a pci master cycle is targeted to the stpc industrial. devsel# i/o device select. this signal is used as an input when the stpc industrial initiates a bus cycle on the pci bus to determine if a pci slave device has decoded itself to be the target of the current transaction. it is asserted as an output either when the stpc industrial is the target of the current pci transaction or when no other device asserts devsel# prior to the subtractive decode phase of the current pci transaction. par parity signal transactions. this is the parity signal of the pci bus. this signal is used to guar- antee even parity across ad[31:0], cbe[3:0]#, and par. this signal is driven by the master dur- ing the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. (its assertion is identi- cal to that of the ad bus delayed by one pci clock cycle) serr# system error. this is the system error sig- nal of the pci bus. it may, if enabled, be asserted for one pci clock cycle if target aborts a stpc in- dustrial initiated pci transaction. its assertion by either the stpc industrial or by another pci bus agent will trigger the assertion of nmi to the host cpu. this is an open drain output. lock# pci lock. this is the lock signal of the pci bus and is used to implement the exclusive bus operations when acting as a pci target agent. pci_req#[2:0] pci request. these pins are the three external pci master request pins. they indi- cates to the pci arbiter that the external agents desire use of the bus. pci_gnt#[2:0] pci grant. these pins indicate that the pci bus has been granted to the master requesting it on its pci_req#. pci_int[3:0] pci interrupt request. these are the pci bus interrupt signals. they are to be en- coded before connection to the stpc industrial using isaclk and isaclkx2 as the input selec- tion strobes.
pin description 22/69 issue 2.4 - februar y 11, 2002 2.2.13 monitor interface red, green, blue rgb video outputs. these are the three analog color outputs from the ram- dacs. these signals are sensitive to interference, therefore they need to be properly shielded. vsync vertical synchronisation pulse. this is the vertical synchronization signal from the vga controller. hsync horizontal synchronisation pulse. this is the horizontal synchronization signal from the vga controller. vref_dac dac voltage reference. this pin is an input driving the digital to analog converters. this allows an external voltage reference source to be used. rset resistor current set. this is the reference current input to the ramdac. used to set the full- scale output of the ramdac. comp compensation. this is the ramdac com- pensation pin. normally, an external capacitor (typically 10nf) is connected between this pin and v dd to damp oscillations. ddc[1:0] direct data channel serial link. these bidirectional pins are connected to crtc register 3fh to implement ddc capabilities. they conform to i 2 c electrical specifications, they have open- collector output drivers which are internally con- nected to v dd through pull-up resistors. they can instead be used for accessing i2c devic- es on board. ddc1 and ddc0 correspond to scl and sda respectively. 2.2.14 flat panel interface signals (combined with serial 1) fpframe, vertical sync. pulse output. fpline, horizontal sync. pulse output. de, data enable. r5-0, red output. g5-0, green output. b5-0, blue output . enavdd enable vdd of flat panel. envcc enable vcc of flat panel. pwm pwm back-light control. 2.2.15 miscellaneous spkrd speaker drive. this is the output to the speaker and is the and of the counter 2 output with bit 1 of port 61h and drives an external speak- er driver. this output should be connected to a 7407 type high voltage driver. scan_enable reserved . this pin is reserved for test and miscellaneous functions. it has to be set to 0 or connected to ground in normal opera- tion.
pin description issue 2.4 - february 11, 2002 23/69 table 2-3. signals sharing the same pin isa bus / ipc local bus parallel port serial interface la[23:22] fcs#[0], prd#[1] la[21:20] pa[21:20] la[19:17] prd#[0], pwr#[1:0] sa[19:1] pa[19:1] sa[0] prdy# sd[15:0] pd[15:0] bhe# fcs#[1] memr#, memw# iocs[3:2] smemr#, smemw# iocs[1:0] gpiocs# pe iochrdy slct ior# busy# iow# err# master# ack# mcs16# pddir# iocs16# init# ref# autpfdx# aen slctin# iochck# ppd[7] rtcrw# ppd[5] rtcds# ppd[4] rtcas# ppd[3] rmrtccs# ppd[2] ale ppd[1] dack_enc[0:2] dcd2#, dsr2#, sin2 dreq_mux[0:1] cts2#, rts2# tc sout2 tft interface serial 1 b[0,1] dcd1#, cts1# g[0,1] dsr1#, rts1# r[0,1] sin1, sout1 pci cardbus pcmcia cclk a[16] crst# reset ad[31:27] cad[31:27] d[10,9,1,8,0] ad[26:20] cad[26:20] a[0:6]
pin description 24/69 issue 2.4 - februar y 11, 2002 pci cardbus pcmcia ad[19] cad[19] a[25] ad[18] cad[18] a[7] ad[17] cad[17] a[24] ad[16] cad[16] a[17] ad[15] cad[15] iowr# ad[14] cad[14] a[9] ad[13] cad[13] iord# ad[12] cad[12] a[11] ad[11] cad[11] oe# / tcw ad[10] cad[10] ce[2] ad[9] cad[9] a[10] ad[8:0] cad[8:0] d[15,7,13,6,12,5,11,4,3] be[3] cbe[3] dack/reg# be[2] cbe[2] a[12] be[1] cbe[1] a[8] be[0] cbe[0] ce[1] frame# cframe# a[23] trdy# ctrdy# a[22] irdy# cirdy# a[15] stop# cstop# a[20] devsel# cdevsel# a[21] pa r c pa r a [ 1 3 ] serr# cserr# wait lock# cblock# a[19] pcireq#[2] creq# inpack# pcireq#[1] ccd1 cd1# pcireq#[0] cstschg# bvd1 pcignt#[2] cgnt# we# / tcr pcignt#[1] ccd2 cd2# pcignt#[0] bvd2 pci_int[3] vcc3_en pci_int[2] vcc5_en pci_int[1] vpp_pgm pci_int[0] cint# ready# clkrun dreq# / wp / iois16#
pin description issue 2.4 - february 11, 2002 25/69 table 2-4. pinout. pin # pin name c4 sysrsti# a3 sysrsto# ab25 xtali ab23 xtalo g25 pci_clki h23 pci_clko b20 isa_clk a20 isa_clk2x ac26 clk14m h26 hclk j26 dev_clk ac15 gclk2x ad16 dclk ae13 ma[0] ac12 ma[1] af13 ma[2] ad12 ma[3] ae14 ma[4] ac14 ma[5] af14 ma[6] ad13 ma[7] ae15 ma[8] ad14 ma[9] af15 ma[10] ae16 ma[11] ad15 ras#[0] af16 ras#[1] ac17 ras#[2] ae18 ras#[3] ad17 cas#[0] af18 cas#[1] ae19 cas#[2] af19 cas#[3] ad18 cas#[4] ae20 cas#[5] ac19 cas#[6] af20 cas#[7] ad19 mwe# ae21 md[0] ac20 md[1] af21 md[2] ad20 md[3] ae22 md[4] af22 md[5] ad21 md[6] ae23 md[7] ac22 md[8] af23 md[9] ad22 md[10] ae24 md[11] ad23 md[12] af24 md[13] ae26 md[14] ad25 md[15] ad26 md[16] ac25 md[17] ac24 md[18] ab24 md[19] ab26 md[20] aa25 md[21] y23 md[22] aa24 md[23] aa26 md[24] y25 md[25] y26 md[26] y24 md[27] w25 md[28] v23 md[29] w26 md[30] w24 md[31] v25 md[32] v26 md[33] u25 md[34] v24 md[35] u26 md[36] u23 md[37] t25 md[38] u24 md[39] t26 md[40] r25 md[41] r26 md[42] t24 md[43] p25 md[44] r23 md[45] p26 md[46] r24 md[47] pin # pin name n25 md[48] n23 md[49] n26 md[50] p24 md[51] m25 md[52] n24 md[53] m26 md[54] l25 md[55] m24 md[56] l26 md[57] m23 md[58] k25 md[59] l24 md[60] k26 md[61] k23 md[62] j25 md[63] b1 pa[0] p1 la[17] / pwr#[0] n3 la[18] / pwr#[1] r2 la[19] / prd#[0] c1 la[20] / pa[20] c2 la[21] / pa[21] p3 la[22] / prd#[1] r1 la[23] / fcs#[0] p4 sa[0] / prdy# j2 sa[1] / pa[1] h3 sa[2] / pa[2] h1 sa[3] / pa[3] j4 sa[4] / pa[4] h2 sa[5] / pa[5] g3 sa[6] / pa[6] g1 sa[7] / pa[7] g2 sa[8] / pa[8] f1 sa[9] / pa[9] f3 sa[10] / pa[10] g4 sa[11] / pa[11] f2 sa[12] / pa[12] e1 sa[13] / pa[13] e3 sa[14] / pa[14] e4 sa[15] / pa[15] e2 sa[16] / pa[16] d1 sa[17] / pa[17] pin # pin name
pin description 26/69 issue 2.4 - februar y 11, 2002 d3 sa[18] / pa[18] d2 sa[19] / pa[19] p2 sd[0] / pd[0] m3 sd[1] / pd[1] n1 sd[2] / pd[2] m4 sd[3] / pd[3] n2 sd[4] / pd[4] l3 sd[5] / pd[5] m1 sd[6] / pd[6] m2 sd[7] / pd[7] l1 sd[8] / pd[8] k3 sd[9] / pd[9] l2 sd[10] / pd[10] k4 sd[11] / pd[11] k1 sd[12] / pd[12] j3 sd[13] / pd[13] k2 sd[14] / pd[14] j1 sd[15] / pd[15] t2 bhe# / fcs#[1] r3 memr# / iocs#[3] t1 memw# / iocs#[2] r4 smemr# / iocs#[1] u2 smemw# / iocs#[0] ab2 iochrdy / slct ab1 ior# / busy# y3 gpiocs# / pe aa3 iow# / err# ac2 master# / ack# ab4 mcs16# / pddir# ab3 iocs16# / init# ad2 ref# / autpfdx# ac3 aen / slctin# e25 iochck# / ppd[7] e26 ppd[6] f24 rtcrw# / ppd[5] d25 rtcds# / ppd[4] e23 rtcas# / ppd[3] d26 rmrtccs# / ppd[2] e24 ale / ppd[1] c25 ppd[0] ac1 strobe# d5 irq_mux[0] a4 irq_mux[1] pin # pin name c5 irq_mux[2] b3 irq_mux[3] ad1 spkrd v3 dack_enc[0]/dcd2# y2 dack_enc[1]/dsr2# w4 dack_enc[2] / sin2 y1 dreq_mux[0]/cts2# w3 dreq_mux[1]/rts2# aa2 tc / sout2 y4 dtr2# aa1 ri2# u4 sin1 / r[0] v1 sout1 / r[1] v2 cts1 / b[1] u3 rts1# / g[1] u1 dsr1# / g[0] w2 dtr1# t3 dcd1# / b[0] w1 ri1# f25 kbclk f26 kbdata g24 mclk g23 mdata d18 reset c18 a[0] a17 a[1] d17 a[2] b16 a[3] c17 a[4] a16 a[5] b15 a[6] a15 a[7] c16 a[8] b14 a[9] d15 a[10] a14 a[11] c15 a[12] b13 a[13] d13 a[14] a13 a[15] c14 a[16] pin # pin name b12 a[17] c13 a[18] a12 a[19] b11 a[20] a11 a[21] d12 a[22] b10 a[23] c11 a[24] a10 a[25] d10 d[0] b9 d[1] c10 d[2] a9 d[3] b8 d[4] c9 d[5] b7 d[6] d8 d[7] a7 d[8] b6 d[9] d7 d[10] a6 d[11] c7 d[12] a5 d[13] c6 d[14] b4 d[15] b22 iord# d22 iowr# d24 wp a18 bvd1 c26 bvd2 a21 ready# c19 wait# a25 inpack# c22 oe# b18 we# b19 reg# b24 cd1# a24 cd2# b23 ce1# c23 ce2# c20 vs1# a19 vs2# d20 vcc5_en c21 vcc3_en pin # pin name
pin description issue 2.4 - february 11, 2002 27/69 b21 vpp_pgm a22 vpp_vcc ad4 red af4 green ae5 blue af3 vsync ae4 hsync af5 vref_dac ae6 rset af6 comp ae3 sda / ddc[1] af2 scl / ddc[0] ae7 b[2] af7 g[2] ad7 r[2] ae8 b[3] ac9 g[3] af8 r[3] ad8 b[4] ae9 g[4] af9 r[4] ae10 b[5] ad9 g[5] af10 r[5] ac10 reserved ad10 fpline ae11 fpframe af11 de ae12 enavdd af12 envcc ad11 pwm c8 scan_enable ad5 vdd_dac1 ac5 vdd_dac2 ae17 vdd_gclk_pll af17 vdd_dclk_pll k24 vdd_zclk_pll h25 vdd_devclk_pll j24 vdd_hclk_pll pin # pin name a8 reserved a23 reserved b5 reserved b17 reserved c12 reserved d6 vdd d11 vdd d16 vdd d21 vdd f4 vdd f23 vdd l4 vdd l23 vdd t4 vdd t23 vdd aa4 vdd aa23 vdd ac6 vdd ac11 vdd ac16 vdd ac21 vdd ac7 vss_dac1 ad6 vss_dac2 g26 vss_dll h24 vss_dll a1 vss a2 vss a26 vss b2 vss b25 vss b26 vss c3 vss c24 vss d4 vss d9 vss d14 vss d19 vss d23 vss h4 vss j23 vss l11:16 vss m11:16 vss pin # pin name n4 vss n11:16 vss p11:16 vss p23 vss r11:16 vss t11:16 vss v4 vss w23 vss ac4 vss ac8 vss ac13 vss ac18 vss ac23 vss ad3 vss ad24 vss ae1 vss ae2 vss ae25 vss af1 vss af25 vss af26 vss pin # pin name
pin description 28/69 issue 2.4 - februar y 11, 2002
strap option issue 2.4 - february 11, 2002 29/69 3. strap option this chapter defines the stpc industrial strap options and their location. memory data lines refer to designation location actual settings set to 0 set to 1 md16 reserved index 4c,bit 0 pull up md17 pci clock pci_clko divisor index 4c,bit 1 user defined hclk / 2 hclk / 3 md18 host clock hclk pad direction index 4c,bit 2 pull up external internal md19 graphics clock gclk2x pad direction index 4c,bit 3 pull up external internal md20 dot clock dclk pad direction index 4c,bit 4 user defined external internal md21 reserved pull up md22 reserved index 5f,bit 1 pull up md23 reserved index 5f,bit 2 pull up md24 hclk hclk pll speed index 5f,bit 3 user defined see section 3.1.6. md25 index 5f,bit 4 md26 index 5f,bit 5 md27 reserved pull down md28 reserved pull down md29 reserved pull down md30 reserved pull down md31 reserved pull down md32 reserved pull down md33 reserved pull up md34 reserved pull down md35 reserved pull up md 36 reserved pull up md 37 reserved pull up md 38 reserved pull up md 39 reserved pull up md 40 pcmcia or pci i/f 3c,bit 0 user defined pci pcmcia md 41 local bus or isa i/f 3c,bit 1 user defined isa local bus md 42 keyboard & mouse 3c,bit 2 user defined external internal md 43 parallel port 3c,bit 3 user defined external internal md 44 serial port uart1 3c,bit 4 user defined external internal md 45 uart2 3c,bit 5 user defined external internal md 46 reserved 3c,bit 6 pull down md 47 reserved 3c,bit 7 pull down md 48 tft tft interface 3d,bit 0 user defined disable enable md 49 cardbus socket 5v availability 3d,bit 1 user defined unavailable available md 50 3.3v availability 3d,bit 2 user defined unavailable available md 51 x.xv available 3d,bit 3 user defined unavailable available md 52 y.yv available 3d,bit 4 user defined unavailable available md 53 reserved pull up md 56 reserved pull up md 57 reserved pull down md 58 reserved pull up md 59 cpu clock speed factor user defined x1 x2
strap option 30/69 issue 2.4 - february 11, 2002 3.1. strap option register description 3.1.1. strap register 0 this register reflect the status of pins md[7:0] respectively. they are expected to be connected on the system board to the simm configuration pins as follows: strap0 access = 0022h/0023h regoffset = 04ah 76543210 md7 md6 md5 md4 md3 md2 rsv this register defaults to the values sampled on md[7:0] pins after reset bit number sampled mnemonic description bit 7-2 md[7:2] user defined bits 1-0 rsv reserved.
strap option issue 2.4 - february 11, 2002 31/69 3.1.2. strap register 1 this register reflect the status of pins md[15:8] respectively. they are expected to be connected on the system board to the simm configuration pins as follows: strap1 access = 0022h/0023h regoffset = 04bh 76543210 md15 md14 md13 md12 mb11 md10 rsv this register defaults to the values sampled on md[15:8] pins after reset bit number sampled mnemonic description bit 7-2 md[7:2] user defined bits 1-0 rsv reserved.
strap option 32/69 issue 2.4 - february 11, 2002 3.1.3. strap register 2 bits 4-0 of this register reflect the status of pins md[20:16] respectively. bit 5 of this register reflect the sta- tus of pin md[23]. bit 4 is writeable, writes to other bits in this register have no effect. strap2 access = 0022h/0023h regoffset = 04ch 76543210 rsv md20 md19 md18 md17 rsv this register defaults to the values sampled on md[23] and md[20:16] pins after reset bit number sampled mnemonic description bits 7-5 rsv reserved. bit 4 md20 this bit reflects the value sampled on md[20] pin and controls the dot clock (dclk) source. note this bit is writeable as well as readable. bit 3 md19 this bit reflects the value sampled on md[19] pin and controls the graphics clock source. bit 2 md18 this bit reflects the value sampled on md[18] pin and controls the host/cpu clock source as follows: settin g to 0: external. hclk pin is an input, settin g to 1: internal. hclk pin is an output and is connected to the internal frequenc y s y nthesizer output. bit 1 md17 this bit reflects the value sampled on md[17] pin and controls the pci clock output as follows: settin g to 0, the pci clock output = hclk / 3 settin g to 1, the pci clock output = hclk / 2. bit 0 rsv reserved.
strap option issue 2.4 - february 11, 2002 33/69 3.1.4. strap register 3 bits 7-0 of this register reflect the status of pins md[47:40] respectively. strap3 access = 0022h/0023h regoffset = 03ch 76543210 rsv md45 md44 md43 md42 md41 md40 this register defaults to the values sampled on md[47:40] pins after reset bit number sampled mnemonic description bits 7-6 rsv reserved. bit 5 md45 uart2 internal or external. this bit reflects the value sampled on md[45] pin and controls the uart2 i/f as follows: setting to 0, uart2 is external. setting to 1, uart2 is internal. bit 4 md44 uart1 internal or external and additional tft outputs. this bit reflects the value sampled on md[44] pin and controls the uart1 i/f and the additional tft i/f as follows: setting to 0, uart1 is external and an additional 6 tft outputs (lowest bits - 2 red, 2 green and 2 blue) are enabled. setting to 1, uart1 is internal. bit 3 md43 parallel port internal or external. this bit reflects the value sampled on md[43] pin and controls the parallel port i/f as follows: setting to 0, the parallel port is external. setting to 1, the parallel port is internal. bit 2 md42 kb/mouse internal or external. this bit reflects the value sampled on md[42] pin and controls the kb/mouse controller i/f as follows: setting to 0, the kb/mouse controller is external. setting to 1, the kb/mouse controller is internal. bit 1 md41 local bus i/f or isa i/f. this bit reflects the value sampled on md[41] pin and sets whether the local bus i/f or the isa i/f is available at the device i/f as follows: setting to 0, selects the isa i/f. setting to 1, selects the local bus i/f. bit 0 md40 pcmcia i/f or pci i/f. this bit reflects the value sampled on md[40] pin and sets whether the pcmcia i/f or the pci i/f is available at the device i/f as follows: setting to 0, selects the pci i/f. setting to 1, selects the pcmcia i/f.
strap option 34/69 issue 2.4 - february 11, 2002 3.1.5. strap register 4 bits 5-0 of this register reflect the status of pins md[53:48] respectively. strap4 access = 0022h/0023h regoffset = 03dh 76543210 rsv md52 md51 md50 md49 md48 this register defaults to the values sampled on md[53:48] pins after reset bit number sampled mnemonic description bits 7-5 rsv reserved. bit 4 md52 y . y v present on board. this bit reflects the value sampled on md[52] pin and is used to notif y the cardbus socket mana g ement unit if the y . y v vcc volta g e (where y . y is less than x.x) is present on board as follows settin g to 0, y . y v vcc volta g e is not available. settin g to 1: y . y v vcc volta g e is available. bit 3 md51 x.x v present on board. this bit reflects the value sampled on md[51] pin and is used to notif y the cardbus socket mana g ement unit if the x.x v vcc volta g e (where x.x is less than 3.3) is present on board as follows: settin g to 0, x.x v vcc volta g e is not available. settin g to 1: x.x v vcc volta g e is available. bit 2 md50 3.3 v present on board. this bit reflects the value sampled on md[50] pin and is used to notif y the cardbus socket mana g ement unit if the 3.3 v vcc volta g e is present on board as follows: settin g to 0, 3.3 v vcc volta g e is not available. settin g to 1, 3.3 v vcc volta g e is available. bit 1 md49 5 v present on board. this bit reflects the value sampled on md[49] pin and is used to notif y the cardbus socket mana g ement unit if the 5 v vcc volta g e is present on board as follows: settin g to 0, 5 v vcc volta g e is not available. settin g to 1, 5 v vcc volta g e is available. bit 0 md48 this bit reflects the value sampled on md[48] pin and is used to enable the tft controller outputs.
strap option issue 2.4 - february 11, 2002 35/69 3.1.6. hclk pll strap register 0 bits 5-0 of this register reflect the status of pins md[26:21] respectively. hclk_strap0 access = 0022h/0023h regoffset = 05fh 76543210 rsv md26 md25 md24 rsv rsv this register defaults to the values sampled on pins described below after reset bit number sampled mnemonic description bits 7-6 rsv reserved. bits 5-3 md[26:24] these pins reflect the value sampled on md[26:24] pins respectively and control the host clock frequency synthesizer: 000 25 mhz 001 33 mhz 010 40 mhz 011 50 mhz 100 60 mhz 101 66 mhz 110 75 mhz 111 80 mhz bits 2-0 rsv reserved.
strap option 36/69 issue 2.4 - february 11, 2002
electrical specifications issue 2.4 - february 11, 2002 37/69 4 electrical specifications 4.1 introduction the electrical specifications in this chapter are valid for the stpc industrial. 4.2 electrical connections 4.2.1 power/ground connections/decoupling due to the high frequency of operation of the stpc industrial, it is necessary to install and test this device using standard high frequency techniques. the high clock frequencies used in the stpc industrial and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. these effects can be minimized by filtering the dc power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the vss and vdd pins. 4.2.2 unused input pins all inputs not used by the designer and not listed in the table of pin connections in section 2 should be connected either to vdd or to vss. connect active-high inputs to vdd through a 20 k w (10%) pull-down resistor and active-low inputs to vss and connect active-low inputs to vcc through a 20 k w (10%) pull-up resistor to prevent spurious operation. 4.2.3 reserved designated pins pins designated reserved should be left disconnected. connecting a reserved pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. 4.3 absolute maximum ratings the following table lists the absolute maximum ratings for the stpc industrial device. stresses beyond those listed under table 4-1 limits may cause permanent damage to the device. these are stress ratings only and do not imply that operation under any conditions other than those specified in section "operating conditions". exposure to conditions beyond those outlined in table 4-1 may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. prolonged exposure to conditions at or near the absolute maximum ratings ( table 4-1 ) may also result in reduced useful life and reliability. table 4-1. absolute maximum ratings symbol parameter minimum maximum units v ddx dc supply voltage -0.3 4.0 v v i , v o digital input and output voltage -0.3 vdd + 0.3 v v 5t 5volt tolerance 2.5 5.5 v v esd esd capacity (human body mode) 1500 v t stg storage temperature -40 +150 c t oper operating temperature -40 +115 c p tot maximum power dissipation - 4.8 w
electrical specifications 38/69 issue 2.4 - february 11, 2002 4.3.1 5v tolerance the stpc is capable of running with i/o systems that operate at 5v such as pci and isa devices. certain pins of the stpc tolerate inputs up to 5.5v. above this limit the component is likely to sustain permanent damage. all the pin that are v 5t have been denoted with a * besides the signal name in table 2-1 . 4.4 dc characteristics notes: 1. mhz ratings refer to cpu clock frequency. 2. not yet released. table 4-2. dc characteristics recommended operating conditions: vdd = 3.3v 0.3v, tcase = 0 to 100 c unless otherwise specified symbol parameter test conditions min typ max unit v dd operating voltage 3.0 3.3 3.6 v p dd supply power v dd = 3.3v, h clk = 66mhz 3.2 3.9 w h clk internal clock (note 1) 80 mhz v dac dac voltage reference 1.215 1.235 1.255 v v ol output low voltage i load =1.5 to 8ma depending of the pin 0.5 v v oh output high voltage i load =-0.5 to -8ma depending of the pin 2.4 v v ild input low voltage except xtali -0.3 0.8 v xtali -0.3 0.5 v v ihd input high voltage except xtali 2.1 v dd +0.3 v xtali 2.35 v dd +0.3 v i lk input leakage current input, i/o -5 5 m a c in input capacitance (note 2) pf c out output capacitance (note 2) pf c clk clock capacitance (note 2) pf table 4-3. ramdac dc specification symbol parameter min nom max vref voltage reference 1.00v 1.12v 1.24v inl integrated non linear error - - 2 lsb dnl differentiated non linear error - - 1lsb fs full scale - - 20ma fsr full scale range 14.00 ma 16.50ma 19.00 ma lsb least significant byte size 54ua 63ua 72ua zero zero scale @ 7.5ire mode 0.95ma 1.44ma 1.90ma compare dac to dac matching - - +/- 5%
electrical specifications issue 2.4 - february 11, 2002 39/69 4.5 ac characteristics table 4-5 through table 4-22 list the ac characteristics including output delays, input setup requirements, input hold requirements and output float delays. these measurements are based on the measurement points identified in figure 4-1 . the rising clock edge reference level vref, and other reference levels are shown in table 4-4 below for the stpc industrial. input or output signals must cross these levels during testing. figure 4-1 shows output delay (a and b) and input setup and hold times (c and d). input setup and hold times (c and d) are specified minimums, defining the smallest acceptable sampling window a synchronous input signal must be stable for correct operation. note: refer to figure 4-1 . table 4-4. drive level and measurement points for switching characteristics symbol value units v ref 1.5 v v ihd 3.0 v v ild 0.0 v figure 4-1. drive level and measurement points for switching characteristics clk: v ref v ild v ihd tx legend: a - maximum output delay specification b - minimum output delay specification c - minimum input setup specification d - minimum input hold specification v ref valid valid valid outputs: inputs: output n output n+1 input max min a b cd v ref v ild v ihd
electrical specifications 40/69 issue 2.4 - february 11, 2002 4.5.1 power on sequence sysrsti# has no constraint on its rising time but needs to be set to high at least 10 m s after power supply is stable. strap options are continuously sampled during sysrsti# low and should be stable. once sysrsti# is high, they must not change un- til sysrsto# is high. strap options 3.3v suppl y sysrsti# sysrsto# 14mhz 1.6v valid configuration > 10 us hclk pci_clk 2.3 ms frame#
electrical specifications issue 2.4 - february 11, 2002 41/69 4.5.2 pci ac timing characteristics 4.5.3 dram controller ac timing characteristics table 4-5. pci bus ac timing name parameter min max unit t1 pci_clki to ad[31:0] valid 2 13 ns t2 pci_clki to frame# valid 2 11 ns t3 pci_clki to cbe#[3:0] valid 2 12 ns t4 pci_clki to par valid 2 12 ns t5 pci_clki to trdy# valid 2 13 ns t6 pci_clki to irdy# valid 2 11 ns t7 pci_clki to stop# valid 2 14 ns t8 pci_clki to devsel# valid 2 11 ns t9 pci_clki to pci_gnt# valid 2 14 ns t10 ad[31:0] bus setup to pci_clki 7 ns t11 ad[31:0] bus hold from pci_clki 3 ns t12 pci_req#[2:0] setup to pci_clki 10 ns t13 pci_req#[2:0] hold from pci_clki 1 ns t14 cbe#[3:0] setup to pci_clki 7 ns t15 cbe#[3:0] hold to pci_clki 5 ns t16 irdy# setup to pci_clki 7 ns t17 irdy# hold to pci_clki 4 ns t18 frame# setup to pci_clki 7 ns t19 frame# hold from pci_clki 3 ns figure 4-2 edo write mode (ref table table 4-6 ) row column row valid data tcpn tcwl tcpn twcs twrh twch tcpn tds tcah tcpn tcrw trwl twch tral tras trc twcr twrp tdhr tcsh trah trad tar trcd tcrp tras trp trp trc tccas tcma tcras clk ras# cas# ma mwe# md
electrical specifications 42/69 issue 2.4 - february 11, 2002 figure 4-3 memory early write mode (ref table table 4-6 ) figure 4-4 edo read mode (ref table table 4-6 ) row column data valid tcpn tcpn tcwl trch tchr twrh tcpn tds twch twcs trcs tcah tcpn trp trc tcrw trwl tras tral trp tdhr twcr trad tras trah tchr trcd trc tcrp tccas tcras tcma clk ras# cas# ma mwe# md row column row open valid data open tcpn tcpn tcpn tcoh trcs tcah tcpn trch tral tras trc trah trad tar trcd tcrp tcsr tchr tras trp trp trc tcmd tcmwe tccas tcras tcma clk ras# cas# ma mwe# md
electrical specifications issue 2.4 - february 11, 2002 43/69 figure 4-5 fast page mode read (ref table table 4-6 ) figure 4-6 fast page mode write (ref table table 4-6 ) ro w column 1 column 2 column n dout 1 dout 2 dout n tcpn tcoh tcah tcpn tcpn tcoh tcah tcpn tcpn tcoh tcah tcpn tcrp trp tral trp tar trah tcsh trad trcd tcrp tcmd tcras tcmd tcma tccas tcmd tcma tccas tcma tccas tcras clk ras# cas# ma mwe# md row column 1 column 2 column n dout 1 dout 2 dout n tral trch tcpn tds tcah tcpn tcpn tds trc tcah tcpn tcwl tcpn tds twcs trc tcah tcpn tcrp trp tcrw trwl tras tral trp tdhr twcr tar tras trah tcsh trad trcd tcrp tcmd tccas tcma tcras clk ras# cas# ma mwe# oe md
electrical specifications 44/69 issue 2.4 - february 11, 2002 figure 4-7 refresh cycle (ref table table 4-6 ) tcpn tcpn tcpn tcpn tcsr trp trpc tras trp tchr tcrs tcsr tras trp trpc trp tcras tccas clk ma[11:0] ras#[3:0] cas#[7:0] table 4-6. ac memory timing characteristics parameter min max units tcras hclk (or gclk2x) to ras#[3:0] valid (see note 3) 17 ns tccas hclk (or gclk2x) to cas#[7:0] bus valid (see note 3) 17 ns tcma hclk (or gclk2x) to ma[11:0] bus valid (see note 3) 17 ns tcmwe hclk (or gclk2x) to mwe# valid (see note 3) 17 ns tcmd hclk to md[63:0] bus valid (see note 3) 25 ns tgcmd gclk2x to md[63:0] bus valid (see note 3) 23 ns tmdg md[63:0] generic hold 0 ns tcah column address hold time 3 1t cycles ns tchr cas hold time 3 1t cycles ns tcoh data hold time from cas low note 1 ns tcpn cas precharge time 1t cycles ns tcrp cas to ras precharge time 1t cycles ns tcrw cas low to ras high (write only) 3 1t cycles ns tcsr cas setup time 3 1t cycles ns tds data in setup time 3 1t cycles ns trah row address hold time 3 1t cycles ns tras ras pulse width 3 3t cycles ns trc random read or write time cycle 3 6t cycles ns trcd ras to cas delay time 3 1t cycles ns note 1; t cycle x n cas + (t data off - t cas out ) where t cycle is the number of clock cycles. n cas is the number of cas cycles (see section 6.7. ) t dataoff is the generic datahold t cas out the clk (either hclk or gclk2x) to cas low. t dataoff and t cas out are used to refine the timing programming. note 2; value to be derived from cas pulse width which is programmable (see section 6.7. ). note 3; for all chronograms, clk refers to the clock signal that the program is using. it can be either hclk or gclk2x
electrical specifications issue 2.4 - february 11, 2002 45/69 trch read command hold time 3 1t cycles ns trcs read command setup time 3 1t cycles ns trp ras precharge time 3 2t cycles ns twch write command hold time 3 1t cycles ns twcs we command setup time 3 1t cycles ns twrh we hold time note 2 ns twrp we setup time 3 1t cycles ns tar column address hold time from ras 3 1t cycles ns trad ras to valid column address delay 3 1t cycles ns tral column address to ras setup time 3 2t cycles ns twcr write command hold reference to ras 3 1t cycles ns trwl write command to ras setup time (note 2) 3 1t cycles ns tcwl write command to cas setup time (note 2) 3 1t cycles ns tdhr data hold reference to ras 3 3t cycles ns trpc ras high to cas low precharge 3 1t cycles ns tcrs cas before ras setup time 3 1t cycles ns tchr cas before ras hold time 3 1t cycles ns tcsh cas hold time after ras 3 1t cycles ns table 4-6. ac memory timing characteristics parameter min max units note 1; t cycle x n cas + (t data off - t cas out ) where t cycle is the number of clock cycles. n cas is the number of cas cycles (see section 6.7. ) t dataoff is the generic datahold t cas out the clk (either hclk or gclk2x) to cas low. t dataoff and t cas out are used to refine the timing programming. note 2; value to be derived from cas pulse width which is programmable (see section 6.7. ). note 3; for all chronograms, clk refers to the clock signal that the program is using. it can be either hclk or gclk2x table 4-7. graphics adapter (vga) ac timing name parameter min max unit t18 dclk to vsync valid 27 ns t19 dclk to hsync valid 27 ns
electrical specifications 46/69 issue 2.4 - february 11, 2002 4.5.4 isa interface ac timing characteristics figure 4-8 isa cycle (ref table table 4-8 ) note 1; stands for smemr#, smemw#, memr#, memw#, ior# & iow#. note; the clock has not been represented as it cannot be accurately represented depending on the isa slave mode. table 4-8. isa bus ac timing name parameter min max units 2 la[23:17] valid before ale# negated 5t cycles 3 la[23:17] valid before memr#, memw# asserted 3a memory access to 16 bit isa slave 5t cycles 3b memory access to 8 bit isa slave 5t cycles 9 sa[19:0] & sbhe valid before ale# negated 1t cycles 10 sa[19:0] & sbhe valid before memr#, memw# asserted 10a memory access to 16 bit isa slave 2t cycles 10b memory access to 8 bit isa slave 2t cycles 10 sa[19:0] & shbe valid before smemr#, smemw# asserted 10c memory access to 16 bit isa slave 2t cycle 10d memory access to 8 bit isa slave 2t cycle 10e sa[19:0] & sbhe valid before ior#, iow# asserted 2t cycles 11 xtalo to iow# valid note; the si g nal numberin g refers to table 4-8 valid aenx valid address valid address, sbhe* v.dat a valid data 54 28 26 64 59 58 55 28 23 61 48 47 26 23 57 27 24 42 41 10 11 34 33 3 22 56 29 25 9 18 2 12 38 37 15 14 13 12 ale aen la [23:17] sa [19:0] control (note 1) iocs16# mcs16# iochrdy read data write data
electrical specifications issue 2.4 - february 11, 2002 47/69 11a memory access to 16 bit isa slave - 2bclk 2t cycles 11b memory access to 16 bit isa slave - standard 3bclk 2t cycles 11c memory access to 16 bit isa slave - 4bclk 2t cycles 11d memory access to 8 bit isa slave - 2bclk 2t cycles 11e memory access to 8 bit isa slave - standard 3bclk 2t cycles 12 ale# asserted before ale# negated 1t cycles 13 ale# asserted before memr#, memw# asserted 13a memory access to 16 bit isa slave 2t cycles 13b memory access to 8 bit isa slave 2t cycles 13 ale# asserted before smemr#, smemw# asserted 13c memory access to 16 bit isa slave 2t cycles 13d memory access to 8 bit isa slave 2t cycles 13e ale# asserted before ior#, iow# asserted 2t cycles 14 ale# asserted before al[23:17] 14a non compressed 15t cycles 14b compressed 15t cycles 15 ale# asserted before memr#, memw#, smemr#, smemw# negated 15a memory access to 16 bit isa slave- 4 bclk 11t cycles 15e memory access to 8 bit isa slave- standard cycle 11t cycles 18a ale# negated before la[23:17] invalid (non compressed) 14t cycles 18a ale# negated before la[23:17] invalid (compressed) 14t cycles 22 memr#, memw# asserted before la[23:17] 22a memory access to 16 bit isa slave. 13t cycles 22b memory access to 8 bit isa slave. 13t cycles 23 memr#, memw# asserted before memr#, memw# negated 23b memory access to 16 bit isa slave standard cycle 9t cycles 23e memory access to 8 bit isa slave standard cycle 9t cycles 23 smemr#, smemw# asserted before smemr#, smemw# negated 23h memory access to 16 bit isa slave standard cycle 9t cycles 23l memory access to 16 bit isa slave standard cycle 9t cycles 23 ior#, iow# asserted before ior#, iow# negated 23o memory access to 16 bit isa slave standard cycle 9t cycles 23r memory access to 8 bit isa slave standard cycle 9t cycles 24 memr#, memw# asserted before sa[19:0] 24b memory access to 16 bit isa slave standard cycle 10t cycles 24d memory access to 8 bit isa slave - 3blck 10t cycles 24e memory access to 8 bit isa slave standard cycle 10t cycles 24f memory access to 8 bit isa slave - 7bclk 10t cycles 24 smemr#, smemw# asserted before sa[19:0] 24h memory access to 16 bit isa slave standard cycle 10t cycles 24i memory access to 16 bit isa slave - 4bclk 10t cycles 24k memory access to 8 bit isa slave - 3bclk 10t cycles 24l memory access to 8 bit isa slave standard cycle 10t cycles 24 ior#, iow# asserted before sa[19:0] 24o i/o access to 16 bit isa slave standard cycle 19t cycles 24r i/o access to 16 bit isa slave standard cycle 19t cycles table 4-8. isa bus ac timing name parameter min max units note; the si g nal numberin g refers to table 4-8
electrical specifications 48/69 issue 2.4 - february 11, 2002 25 memr#, memw# asserted before next ale# asserted 25b memory access to 16 bit isa slave standard cycle 10t cycles 25d memory access to 8 bit isa slave standard cycle 10t cycles 25 smemr#, smemw# asserted before next ale# asserted 25e memory access to 16 bit isa slave - 2bclk 10t cycles 25f memory access to 16 bit isa slave standard cycle 10t cycles 25h memory access to 8 bit isa slave standard cycle 10t cycles 25 ior#, iow# asserted before next ale# asserted 25i i/o access to 16 bit isa slave standard cycle 10t cycles 25k i/o access to 16 bit isa slave standard cycle 10t cycles 26 memr#, memw# asserted before next memr#, memw# asserted 26b memory access to 16 bit isa slave standard cycle 12t cycles 26d memory access to 8 bit isa slave standard cycle 12t cycles 26 smemr#, smemw# asserted before next smemr#, smemw# asserted 26f memory access to 16 bit isa slave standard cycle 12t cycles 26h memory access to 8 bit isa slave standard cycle 12t cycles 26 ior#, iow# asserted before next ior#, iow# asserted 26i i/o access to 16 bit isa slave standard cycle 12t cycles 26k i/o access to 8 bit isa slave standard cycle 12t cycles 28 any command negated to memr#, smemr#, memr#, smemw# asserted 28a memory access to 16 bit isa slave 3t cycles 28b memory access to 8 bit isa slave 3t cycles 28 any command negated to ior#, iow# asserted 28c i/o access to isa slave 3t cycles 29a memr#, memw# negated before next ale# asserted 1t cycles 29b smemr#, smemw# negated before next ale# asserted 1t cycles 29c ior#, iow# negated before next ale# asserted 1t cycles 33 la[23:17] valid to iochrdy negated 33a memory access to 16 bit isa slave - 4 bclk 8t cycles 33b memory access to 8 bit isa slave - 7 bclk 14t cycles 34 la[23:17] valid to read data valid 34b memory access to 16 bit isa slave standard cycle 8t cycles 34e memory access to 8 bit isa slave standard cycle 14t cycles 37 ale# asserted to iochrdy# negated 37a memory access to 16 bit isa slave - 4 bclk 6t cycles 37b memory access to 8 bit isa slave - 7 bclk 12t cycles 37c i/o access to 16 bit isa slave - 4 bclk 6t cycles 37d i/o access to 8 bit isa slave - 7 bclk 12t cycles 38 ale# asserted to read data valid 38b memory access to 16 bit isa slave standard cycle 4t cycles 38e memory access to 8 bit isa slave standard cycle 10t cycles 38h i/o access to 16 bit isa slave standard cycle 4t cycles 38l i/o access to 8 bit isa slave standard cycle 10t cycles 41 sa[19:0] sbhe valid to iochrdy negated 41a memory access to 16 bit isa slave 6t cycles 41b memory access to 8 bit isa slave 12t cycles table 4-8. isa bus ac timing name parameter min max units note; the si g nal numberin g refers to table 4-8
electrical specifications issue 2.4 - february 11, 2002 49/69 41c i/o access to 16 bit isa slave 6t cycles 41d i/o access to 8 bit isa slave 12t cycles 42 sa[19:0] sbhe valid to read data valid 42b memory access to 16 bit isa slave standard cycle 4t cycles 42e memory access to 8 bit isa slave standard cycle 10t cycles 42h i/o access to 16 bit isa slave standard cycle 4t cycles 42l i/o access to 8 bit isa slave standard cycle 10t cycles 47 memr#, memw#, smemr#, smemw#, ior#, iow# asserted to iochrdy negated 47a memory access to 16 bit isa slave 2t cycles 47b memory access to 8 bit isa slave 5t cycles 47c i/o access to 16 bit isa slave 2t cycles 47d i/o access to 8 bit isa slave 5t cycles 48 memr#, smemr#, ior# asserted to read data valid 48b memory access to 16 bit isa slave standard cycle 2t cycles 48e memory access to 8 bit isa slave standard cycle 5t cycles 48h i/o access to 16 bit isa slave standard cycle 2t cycles 48l i/o access to 8 bit isa slave standard cycle 5t cycles 54 iochrdy asserted to read data valid 54a memory access to 16 bit isa slave 1t(r)/2t(w) cycles 54b memory access to 8 bit isa slave 1t(r)/2t(w) cycles 54c i/o access to 16 bit isa slave 1t(r)/2t(w) cycles 54d i/o access to 8 bit isa slave 1t(r)/2t(w) cycles 55a iochrdy asserted to memr#, memw#, smemr#, smemw#, ior#, iow# negated 1t cycles 55b iochry asserted to memr#, smemr# negated (refresh) 1t cycles 56 iochrdy asserted to next ale# asserted 2t cycles 57 iochrdy asserted to sa[19:0], sbhe invalid 2t cycles 58 memr#, ior#, smemr# negated to read data invalid 0t cycles 59 memr#, ior#, smemr# negated to databus float 0t cycles 61 write data before memw# asserted 61a memory access to 16 bit isa slave 2t cycles 61b memory access to 8 bit isa slave (byte copy at end of start) 2t cycles 61 write data before smemw# asserted 61c memory access to 16 bit isa slave 2t cycles 61d memory access to 8 bit isa slave 2t cycles 61 write data valid before iow# asserted 61e i/o access to 16 bit isa slave 2t cycles 61f i/o access to 8 bit isa slave 2t cycles 64a memw# negated to write data invalid - 16 bit 1t cycles 64b memw# negated to write data invalid - 8 bit 1t cycles 64c smemw# negated to write data invalid - 16 bit 1t cycles 64d smemw# negated to write data invalid - 8 bit 1t cycles 64e iow# negated to write data invalid 1t cycles table 4-8. isa bus ac timing name parameter min max units note; the si g nal numberin g refers to table 4-8
electrical specifications 50/69 issue 2.4 - february 11, 2002 4.5.5 ipc interface ac timing characteristics 4.5.6 pcmcia interface ac timing characteristics 4.5.7 parallel interface ac timing characteristics 64f memw# negated to copy data float, 8 bit isa slave, odd byte by isa master 1t cycles 64g iow# negated to copy data float, 8 bit isa slave, odd byte by isa master 1t cycles table 4-8. isa bus ac timing name parameter min max units note; the si g nal numberin g refers to table 4-8 table 4-9. ipc interface ac timings name parameter min max unit t20 xtalo to dack_en[2:0] valid 71 ns t21 xtalo to tc valid 68 ns t22 irq_mux input setup to isaclk2x 0 - ns t23 dreq_mux[1:0] input setup to isaclk2x 0 - ns table 4-10. pcmcia interface ac timing name parameters min max units t24 input setup to isaclk2x 24 ns t25 input hold from isaclk2x 5 ns t28 isaclk2x to iord - 55 ns t29 isaclk2x to iorw - 55 ns t30 isaclk2x to ad[25:0] - 25 ns t31 isaclk2x to oe# 2 55 ns t32 isaclk2x to we# 2 55 ns t33 isaclk2x to data[15:0] 0 35 ns t34 isaclk2x to inpack 2 55 ns t35 isaclk2x to ce1# 7 65 ns t36 isaclk2x to ce2# 7 65 ns t37 isaclk2x to reset 2 55 ns table 4-11. parallel interface ac timing name parameters min max units t37 strobe# to busy setup 0 - ns t38 pd bus to autpfd# hold 0 - ns t39 pb bus to busy setup 0 - ns
electrical specifications issue 2.4 - february 11, 2002 51/69 4.5.8 keyboard interface ac timing characteristics 4.5.9 mouse interface ac timing characteristics table 4-12. keyboard interface ac timing name parameters min max units t40 input setup to kbclk 5 - ns t41 input hold to kbclk 1 - ns t42 kbclk to kbdata - 12 ns table 4-13. mouse interface ac timing name parameters min max units t43 input setup to mclk 5 - ns t44 input hold to mclk 1 - ns t45 mclk to mdata - 12 ns
electrical specifications 52/69 issue 2.4 - february 11, 2002 4.5.10 local bus interface ac timing characteristics table 4-14. 16 bit memory write @ data active* active* hold* setup* t50 t51 t53 t52 t58 hclk pa pd iocs#[3:0] pwr#0 pwr#1 prd#0 prd#1 table 4-15. 16 bit memory read @ data active* active* hold* setup* t50 t51 t55 t54 t58 hclk pa pd iocs#[3:0] pwr#0 pwr#1 prd#0 prd#1 table 4-16. 16 bit i/o write @ data active* active* hold* setup* t50 t51 t53 t52 t58 hclk pa pd iocs#[3:0] pwr#0 pwr#1 prd#0 prd#1
electrical specifications issue 2.4 - february 11, 2002 53/69 table 4-17. 16 bit i/o read @ data active* active* hold* setup* t50 t51 t55 t54 t58 hclk pa pd iocs#[3:0] pwr#0 pwr#1 prd#0 prd#1 table 4-18. 8 bit i/o write at even addresses with iowidth=0 or 1 @ data active* active* hold* setup* t51 t50 t52 t58 hclk pa pd[7:0] pd[15:8] iocs#[3:0] pwr#0 pwr#1 prd#0 prd#1 table 4-19. 8 bit i/o write at odd addresses with iowidth=0 (8 bit peripheral) @ data active* active* hold* setup* t51 t50 t53 t58 hclk pa pd[7:0] pd[15:8] iocs#[3:0] pwr#0 pwr#1 prd#0 prd#1
electrical specifications 54/69 issue 2.4 - february 11, 2002 4.5.11 tft interface ac timing characteristics table 4-20. 8 bit i/o write at odd addresses with iowidth=1 (16 bit peripheral) @ data active* active* hold* setup* t51 t50 t53 t58 hclk pa pd[7:0] pd[15:8] iocs#[3:0] pwr#0 pwr#1 prd#0 prd#1 table 4-21. local bus interface ac timing name parameters min max units t46 prdy# input hold to hclk 2 ns t47 pd[15:0] input hold to hclk 2 ns t48 prdy# input setup to hclk 1 - ns t49 pd[15:0] input setup to hclk 2 4 ns t50 hclk to pa bus - 15 ns t51 hclk to pd bus - 15 ns t52 hclk to pwr0# - 15 ns t53 hclk to pwr1# - 15 ns t54 hclk to prd0# - 15 ns t55 hclk to prd1# - 15 ns t56 hclk to fcs0# - 15 ns t57 hclk to fcs1# - 15 ns t58 hclk to iocs#[3:0] - 15 ns note; to program the values of setup, active and hold timings, refer to section 14.4.3. table 4-22. tft interface timing name parameters min max units t59 dclk to fpline 15 ns t60 dclk to r[2] 15 ns t61 dclk to r[3] 15 ns t62 dclk to r[4] 15 ns t63 dclk to r[5] 15 ns t64 dclk to g[2] 15 ns t65 dclk to g[3] 15 ns t66 dclk to g[4] 15 ns t67 dclk to g[5] 15 ns t68 dclk to b[2] 15 ns t68 dclk to b[3] 15 ns t69 dclk to b[4] 15 ns
electrical specifications issue 2.4 - february 11, 2002 55/69 t70 dclk to b[5] 15 ns t71 dclk to fpframe 15 ns table 4-22. tft interface timing name parameters min max units
electrical specifications 56/69 issue 2.4 - february 11, 2002
mechanical data issue 2.4 - february 11, 2002 57/69 5. mechanical data 5.1. 388-pin package dimension the pin numbering for the stpc 388-pin plastic bga package is shown in figure 5-1 . dimensions are shown in figure 5-2 , table 5-1 and figure 5-3 , table 5-2 . figure 5-1. 388-pin pbga package - top view a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 135791113151719212325 2 4 6 8 10 12 14 16 18 20 22 24 26 a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 135791113151719212325 2468101214161820222426
mechanical data 58/69 issue 2.4 - februar y 11, 2002 figure 5-2. 388-pin pbga package - pcb dimensions table 5-1. 388-pin pbga package - pcb dimensions symbols mm inches min typ max min typ max a 34.95 35.00 35.05 1.375 1.378 1.380 b 1.22 1.27 1.32 0.048 0.050 0.052 c 0.58 0.63 0.68 0.023 0.025 0.027 d 1.57 1.62 1.67 0.062 0.064 0.066 e 0.15 0.20 0.25 0.006 0.008 0.001 f 0.05 0.10 0.15 0.002 0.004 0.006 g 0.75 0.80 0.85 0.030 0.032 0.034 a a b detail a1 ball pad corner d f e g c
mechanical data issue 2.4 - february 11, 2002 59/69 figure 5-3. 388-pin pbga package - dimensions table 5-2. 388-pin pbga package - dimensions symbols mm inches min typ max min typ max a 0.50 0.56 0.62 0.020 0.022 0.024 b 1.12 1.17 1.22 0.044 0.046 0.048 c 0.60 0.76 0.92 0.024 0.030 0.036 d 0.52 0.53 0.54 0.020 0.021 0.022 e 0.63 0.78 0.93 0.025 0.031 0.037 f 0.60 0.63 0.66 0.024 0.025 0.026 g 30.0 11.8 a b c solderball solderball after collapse d e f g
mechanical data 60/69 issue 2.4 - februar y 11, 2002 5.2. 388-pin package thermal data the 388-pin pbga package has a power dissipation capability of 4.5w. this increases to 6w when used with a heatsink. the structure in shown in fi g ure 5-4 . thermal dissipation options are illustrated in fi g ure 5-5 and fi g ure 5-6 . figure 5-4. 388-pin pbga structure thermal balls power & ground layers signal layers figure 5-5. thermal dissipation without heatsink ambient board case junction board ambient ambient case junction board rca rjc rjb rba 66 125 8.5 rja = 13 c/w airflow = 0 board dimensions: the pbga is centred on board copper thickness: - 17m for internal layers - 34m for external layers - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 gnd, 1vcc) there are no other devices 1 via pad per ground ball (8-mil wire) 40% copper on signal layers board temperature taken at the centrecentre b a
mechanical data issue 2.4 - february 11, 2002 61/69 figure 5-6. thermal dissipation with heatsink board ambient case junction board ambient ambient case junction board rca rjc rjb rba 36 50 8.5 rja = 9.5 c/w airflow = 0 board dimensions: the pbga is centred on board copper thickness: - 17m for internal layers - 34m for external layers - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 gnd, 1vcc) there are no other devices heat sink is 11.1c/w 1 via pad per ground ball (8-mil wire) 40% copper on signal layers board temperature taken at the centre balls
mechanical data 62/69 issue 2.4 - februar y 11, 2002 5.3. soldering recommendations high quality, low defect soldering requires identifying the optimum temperature profile for reflowing the solder paste, therefore optimizing the process. the heating and cooling rise rates must be compatible with the solder paste and components. a typical profile consists of a preheat, dryout, reflow and cooling sections. the most critical parameter in the preheat section is to minimize the rate of temperature rise to less than 2 c / second, in order to minimize thermal shock on the semi-conductor components. dryout section is used primarily to ensure that the solder paste is fully dried before hitting reflow temperatures. solder reflow is accomplished in the reflow zone , where the solder paste is elevated to a temperature greater than the melting point of the solder. melting temperature must be exceeded by approximately 20 c to ensure quality reflow. in reality the profile is not a line, but rather a range of temperatures all solder joints must be exposed. the total temperature deviation from component thermal mismatch, oven loading and oven uniformity must be within the band. figure 5-7. reflow soldering temperature range temperature ( c ) time ( s ) preheat dryout reflow cooling 240 0 250 200 150 100 50 0
board layout issue 2.4 - february 11, 2002 63/69 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6. board layout 6.1. thermal dissipation thermal dissipation of the stpc depends mainly on supply voltage. when the system does not need to work at 3.3 v, it may be beneficial to reduce the voltage to, for example, 3.15 v. this may save a few 100s of mw. a further area to consider is unused interfaces and functions. depending on the application, some input signals can be grounded, some blocks left un- powered, other blocks shutdown. clock speed dynamic adjustment offers a further solution, together with the integrated power management unit. the standard way to route the thermal balls to the internal ground layer uses one via for each ball pad, connected using 8-mil wire. with such a configuration, the plastic bga 388 package provides 90% of the thermal dissipation through the ground balls, in particular the central thermal balls, as these are directly connected to the die. the remaining 10% of heat is dissipated through the case. adding a heat sink can reduce this value by 85%. to avoid thermal problems when routing to the stpc, some basic rules must be applied. firstly, the ground balls must be directly connected to the ground layer, which acts as a heat sink. this is illustrated in figure 6-1 . if one ground layer is not enough, a second ground plane may be added on the solder side. figure 6-1. ground routing pad for ground ball thru hole to ground layer t o p l a y e r : s i g n a l s g r o u n d l a y e r p o w e r l a y e r b o t t o m l a y e r : s i g n a l s + l o c a l g r o u n d l a y e r ( i f n e e d e d ) note: for better visibility, ground balls are not all routed.
board layout 64/69 issue 2.4 - february 11, 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. when considering thermal dissipation, the most important - if not the most obvious - part of the layout is the connection between the ground balls and the ground layer. a 1-wire connection is shown in figure 6-2 . the use of 8-mil wire results in a thermal resistance of 105c/w assuming copper is used (418 w/m.k). this high value is due to the thickness (34 m) of the copper on the external side of the pcb. considering only the central matrix of 36 thermal balls and one via for each ball, the global thermal resistance is 2.9c/w. this can be improved by using four 10 mil wires to connect to the four vias around the ground pad link, as in figure 6-3 . this gives a total of 49 vias and a global resistance for the 36 thermal balls of 0.6c/w. the use of a ground plane, as shown in figure 6- 4 , is even better. to avoid solder wicking over to the via pads during soldering, it is important to have a solder mask of 4 mil around the pad (nsmd pad). this gives a diameter of 33 mil for a 25 mil ground pad. to obtain the optimum ground layout, place the vias directly under the ball pads. in this case, no local board distortion can be tolerated. the thickness of the copper on pcb layers is typically 34 m for external layers and 17 m for internal layers. the resulting thermal dissipation is not good, with areas of high temperature being concentrated around the devices, falling off quickly with increased distance. where possible, place a metal layer inside the pcb. this will improve dramatically the spread of heat and hence improve the thermal dissipation of the board.. figure 6-2. recommended 1-wire ground pad layout figure 6-3. recommended 4-wire ground pad layout solder mask (4 mil) pad for ground ball (diameter = 25 mil) hole to ground layer (diameter = 12 mil) connection wire (width = 10 mil) via (diameter = 24 mil) 3 4 .5 m il 1 mil = 0.0254 mm 4 via pads for each ground ball
board layout issue 2.4 - february 11, 2002 65/69 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. the pbga package also dissipates heat through the peripheral ground balls. when a heat sink is placed on the device, heat is more uniformly spread throughout the moulding, increasing the dissipation of heat through the peripheral ground balls. the higher the number of via pads connected to each ground ball, the higher the amount of heat dissipated. the only limitation is the risk of losing routing channels. figure 6-1 shows a routing with a good trade off between thermal dissipation and the number of routing channels. a local ground plane on the opposite side of the board, as shown in figure 6-2 , improves thermal dissipation. it is used to connect decoupling capacitors but can also be used for connection to a heat sink or to the system metal box for better dissipation. this possibility of using the whole system box for thermal dissipation can be very useful in cases of high internal temperature and low external temperature. in such cases, both sides of the pbga should be thermally connected to the metal chassis in order to propagate the heat flow through the metal. figure 6-3 illustrates a typical example. figure 6-4. optimum layout for central ground ball via to ground layer pad for ground ball clearance = 6mil diameter = 25 mil hole diameter = 14 mil solder mask diameter = 33 mil external diameter = 37 mil connections = 10 mil
board layout 66/69 issue 2.4 - february 11, 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. figure 6-1. global ground layout for good thermal dissipation figure 6-2. bottom side layout and decoupling ground pad via to ground layer ground plane for thermal dissipation via to ground layer
board layout issue 2.4 - february 11, 2002 67/69 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. figure 6-3. use of metal plate for thermal dissipation metal planes thermal conductor board die
board layout 68/69 issue 2.4 - february 11, 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6.2. high speed signals as some stpc interfaces (listed below in decreasing speed order) run at high speeds, they must be carefully routed or even shielded. 1) memory interface. 2) graphics and video interfaces. 3) pci bus. 4) 14 mhz oscillator stage. all clock signals must be routed first and shielded for speeds of 27 mhz or higher. all high-speed signals, such as memory control signals and pci control signals, require the same constraints. all analog noise-sensitive signals should be routed in a separate area and hence can be routed indepedently. figure 6-5. shielding signals ground ring ground pad shielded signal line ground pad shielded signal lines
ordering data issue 2.4 - february 11, 2002 69/69 7 ordering data 7.1 ordering codes st pc i01 66 bt c 3 stmicroelectronics prefix product family pc: pc compatible product id i01: industrial core speed 66: 66mhz 80: 80mhz package bt: 388 overmoulded bga temperature range c: commercial tcase = 0 to +100c i: industrial tcase = -40 to +100c operating voltage 3 : 3.3v 0.3v
ordering data 70/69 issue 2.4 - februar y 11, 2002 7.2 available part numbers part number core frequency (mhz) cpu mode tcase range (c) operating voltage (v) STPCI0166btc3 66 dx 0c to +100c 3.3v 0.3v STPCI0180btc3 80 dx STPCI0166bti3 66 dx -40c to +100c STPCI0180bti3 80 dx
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? 2000 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 71 issue 2.4

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