publication number 30613 revision a amendment 0 issue date september 10, 2003 mirrorbit tm and mirrorflash tm status bits and erase suspend timing application note introduction as new microprocessors achieve faster and faster speeds, the response time of flash memory has become increasingly important. when working with mirrorbit/ mirrorflash devices, which are typically used with high-end microprocessors, knowing how to address the response time limitations is even more important. two of the most common instances that engineers are faced with response time issues are when checking the status of a program operation or when performing multiple erase/suspend operations. checking status bits during program operations with the addition of write buffers in mirrorbit/mirrorflash devices, the response time of the dq status bits has changed slightly. when checking the program sta- tus, the dq status bits are not guaranteed to be valid until 4 s after the program command (see figure 1) is issued. note that all program operations on mirrorbit/ mirrorflash parts take more than 4 s to complete. in other words, the only sta- tus information expected within the first 4 s would be ?program in progress? or ?write to buffer operation aborted?.
2 mirrorbit tm and mirrorflash tm status bits and erase suspend timing 30613a0 september 10, 2003 application note figure 1. program operation if the write-buffer page boundary is crossed while programming the write buffer, mirrorbit/mirrorflash devices will return the abort condition status (dq1 = 1, dq7 = data for the last address loaded, dq6 = toggle, and dq5 = 0) on the next read and will not be affected by the 4 s status bit delay. program status can be checked using the dq6 toggle-bit for ?busy/programming in progress?, independent of the address being read; however, polling for ?done/ successful operation? should be performed on the address being programmed or on the last word in the program buffer. reading status bits without waiting 4 s to read the program status without waiting 4 s, the output enable (oe#) control must be permanently tied low. in some systems, this may cause interference on the data bus; however, no issue should be present in systems that use the ce# signal to control access to the flash. in addition, if a write buffer operation is aborted, there is no 4 s delay in reading the status bits. reading status bit when using program suspend/resume if the suspend command is issued less then 4 s after the program command, the system must wait 4 s after programming is resumed before the status bits are valid. if the suspend command is issued more than 4 s after the program command, there will be no delay when reading the status bits after programming is resumed. oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h 4 s t cs program command sequence (last two cycles) ry/by# t rb t busy t ch pa status d out
september 10, 2003 30613a0 mirrorbit tm and mirrorflash tm status bits and erase suspend timing 3 application note sector erase/suspend/resume timing spansion devices allow the user to suspend an erase and resume at a later time. during an erase operation, the flash device performs multiple internal operations, which are invisible to the system. when an erase operation is suspended, any of the internal operations that were not fully completed must be restarted. as such, if a flash device is continually issued suspend/resume commands in rapid succes- sion, erase progress will be impeded as a function of the number of suspends. the result will be a longer overall erase time than without suspends. note that the additional suspends will not affect device reliability or future performance. in most systems rapid erase/suspend activity occurs only briefly. in this example, erase performance will not be significantly impacted.
4 mirrorbit tm and mirrorflash tm status bits and erase suspend timing 30613a0 september 10, 2003 application note revision summary revision a (september 10, 2003) initial release. trademarks and notice this document contains fasl confidential information. the contents of this document may not be copied nor duplicated in any for m, in whole or in part, without prior written consent from fasl. the information in this document is subject to change without notice. product and comp any names are trademarks or registered trademarks of their respective owners copyright 2003 fasl llc. all rights reserved.
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