1 sar control serial
interface d out comparator s/h amp cs/shdn dclock +in v ref ?n cdac
1 short cycling the 8-pin ads78xx family by bonnie c. baker 3 ? 1997 burr-brown corporation AB-117 printed in u.s.a. june, 1997 the most recent 8-pin, 12-bit a/d converters that burr- brown has introduced to the market are advertised as high speed, micro power, low priced sampling sar devices. during product development and the initial introduction period, the engineering effort was placed on optimizing the combination of 12 bits with high speed, low power and low cost. burr-brown applications has revisited these converters to find that the claims of high speed and micro power at 12 bits are only part of the story. if power savings is a priority and fewer bits are tolerable in the application, these parts can be operated at much higher speeds and with considerably lower power dissipation. the products that are discussed in this application note are the ads7816, ads7817 and ads7822 (figure 1). the data sheet key specifications for these products are shown in table i. the maximum through-put rate stated in table i assumes that the devices operate at that speed with less error than stated in the maximum linearity error speci- fications. this is, of course, in a 12-bit system. the differen- tiating specifications between these three products are speed, power, and supply voltage. as shown in table i, the power dissipation of the ads7816 at a 200khz continuous sam- pling rate is 1.9mw. if the application allows for a conser- vative 16 clock cycles to complete the conversion, the clock rate for the ads7816 and ads7817 would be 3.2mhz and for the ads7822, 1.2mhz. table i. published specifications of three of the 12-bit, micro-power, sampling a/d converters. ads7817c ads7816c ads7822c (v ref = 2.5v) (v ref = 5v) (v ref = 3v) maximum through-put rate, 1/t cyc 200khz 200khz 75khz maximum system clock rate assuming 16 3.2mhz 3.2mhz 1.2mhz clocks for one conversion plus data transfer typical power dissipation at specified 2.3mw 1.9mw 0.54mw through-put rate maximum integral linearity error 1lsb 1lsb 0.75lsb maximum differential linearity error 1lsb 0.75lsb 0.75lsb power supply for above specifications 5.0v 5.0v 2.7v input structure fully differential single-ended with single-ended with sampled ground sense sampled ground sense 4 figure 1. the basic topology of the ads7816, ads7817, and ads7822 is shown in this figure. all three devices are 12-bit, 8-pin, sar converters with serial outputs.
2 all three devices communicate with a processor by way of a synchronous 3-wire interface. the basic timing diagrams for these a/d converters is shown in figures 2 and 3. as shown in figure 2, a falling cs signal initiates the conver- sion process. this is usually synchronized with the falling edge of the system clock (dclock). the first 1.5 to 2 clock periods after cs falls are used to sample the analog input signal. following this sampling time, the converter transmits one null bit and then the 12 bits of the conversion, starting with the msb. at the end of the transmission of these 12 bits and with the falling edge of the system clock, cs is brought high. a high cs also puts the dout pin into high imped- ance mode. cs must be kept high for at least one clock cycle, thus completing one conversion/data transfer cycle. the power down mode is initiated by the converter with the transmission of the last bit or the lsb. if cs is kept high, the device will remain in the power down mode until cs goes low, as described above. the power down mode can be used to conserve over all power. to illustrate this point the ads7816 is used as an example. if the desired conversion rate for the application is 20khz, the clock rate can be set to a minimum of 320khz (for 12-bit operation) or a maximum of 3.2mhz. in the case where the clock is set to 320khz, the converter is powered for most of the conversion cycle (1/t cyc ). in this case, the power dissipation of a typical ads7816 would be 1.425mw. in contrast, the clock can be set at its maximum rate of 3.2mhz. a 20khz conversion rate is obtained by sending bursts of 16 clock cycles to the converter every 50 m s. these bursts put the a/d converter in its fully powered state for 5 m s and in the power down mode for 45 m s (assuming that cs is kept high during the 45 m s). now the power dissipation of the ads7816 will be a typical of 210 m w. this improve- ment in power dissipation is very effective in battery power applications. short cycling using output data truncation techniques the timing process described above should be implemented if a full 12 bits of the serial data out is required. in instances where fewer bits are acceptable, such as 10 bits or 8 bits, the transmission of the data on the d out pin can be terminated by prematurely by bringing cs high. when cs is brought high prematurely, the transmission of the serial data from the a/d converter will stop and d out will go into a high impedance mode. an example of the timing for 8-bit d out 1.4v test point 3k w 100pf
c load load circuit for t ddo , t r , and t f voltage waveforms for d out delay times, t ddo
t ddo t hdo d out dclock v oh v ol v il figure 3. the timing relationship between dclock and the serial data output at d out of the converters is shown here. v il and v ol is defined at 10% above logic low, v oh is defined at 10% below logic high. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or omissions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. cs/shdn d out dclock t data t sucs t csd t cyc t conv power
down t smpl note: (1) after completing the data transfer, if further clocks are applied with cs
low, the adc will output lsb-first data then followed with zeroes indefinitely.
b11
(msb) b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (1) null
bit hi-z hi-z b11 b10 b9 b8 null
bit figure 2. the standard timing diagram for the ads7816, ads7817, and ads7822 is shown here. in this figure cs and the transfer of the d out to the processor is initiated by the falling edge of dclock.
3 operation is shown in figure 4. this technique, known as short cycling, can be used to increase the through-put rate or reduce the average power dissipation. a comparison of data rate versus power dissipation of the ads7817 is shown in figure 5. in this diagram, the clock rate is kept constant at 3.2mhz. the data rate of the converter is adjusted by extending the amount of time that the device is in its power down mode, implemented by making cs high. this simple technique of short cycling does not compromise the 12-bit performance of the converter, it simply terminates the trans- mission of bits. consequently, performance specifications such as inl, dnl, thd and snr are not degraded. this technique is briefly discussed in the data sheet for each product. the limiting factor for the maximum data rate of these converters (regardless of the number of bits actually latched) is the set-up and hold times of d out . this is most effectively shown in the timing diagram in figure 3. the specification of particular interest is t ddo , the dclock falling to next d out valid specification. in the case of the ads7816 and ads7817, the maximum (over full temperature range) t ddo is equal to 150ns. given that the processor will latch the data in on the rising edge of the clock, the output data of the converter must be valid at the time of the clock rising edge. this limits the maximum clock rate to (1 / (2 ? t ddo )) or 3.33mhz. for these devices, 3.2mhz was conservatively specified as the clock rate. table ii shows the difference in these specifications for the ads7816, ads7817 and ads7822. conclusion if only 8 or 10 bits are required from the a/d converter the ads7822, ads7816 and ads7817 serial output data can be truncated to the desired number of bits. this allows for a lower overall conversion time because fewer clock cycles are used to produce the desired number of output bits. in the case of a 10-bit conversion 14 clock cycles are required for the conversion. in the case of 8 bits, 12 clock cycles are required. this technique offers an opportunity to lower the overall power dissipation by approximately 12.5% for 10 bits and 25% for 8 bits for the same throughput rate. figure 5. using the ads7817 as a example, the timing technique illustrated in figure 4 is used to short cycle the device to 10 bits and 8 bits. note that in all examples the system clock, dclock, is kept at 3.2mhz. figure 4. these a/d converters can be short cycled by bringing cs high prematurely. all serial output data is halted at that time. this timing diagram illustrates the performance of the ads7816, ads7817, and ads7822 being utilized as 8-bit converters. ads7817 3.2mhz clock short cycle
trigger on falling edge
unit #1 2.5
2
1.5
1
0.5
0 power (mw) 0 50 100 150 200 250 300 data rate (khz) 8 bits: 3.2mhz clk
10-bit: 3.2mhz clk
12 bits: 3.2mhz clk cs/shdn d out dclock t sucs t csd t cyc t conv power
down t smpl note: (1) after completing the data transfer, if further clocks are applied with cs
low, the adc will output lsb-first data then followed with zeroes indefinitely.
b11
(msb) b10 b9 b8 b7 b6 b5 b4 null
bit hi-z hi-z b11 b10 b9 b8 null
bit
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