View AD9833_985026.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. prh a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 preliminary technical data AD9833 2.3 v to 5.5 v, 25 mhz low power cmos complete dds features 2.3 v to 5.5 v power supply 25 mhz speed tiny 10-lead msop package serial loading sinusoidal/triangular dac output extended temperature range: ?0 c to +105 c power-down option narrow-band sfdr >72 db 20 mw power consumption at 3 v applications digital modulation portable equipment test equipment dds tuning functional block diagram phase0 reg phase1 reg 12 10-bit dac sin rom phase accumulator (28-bit) mux freq0 reg freq1 reg mux on-board reference full-scale control mux mux div by 2 msb cap/2.5v vdd dgnd agnd mclk AD9833 fsync sclk sdata serial register control register 14-bit data register comp vout regulator avdd/ dvdd 2.5v general description this low power dds device is a numerically controlled oscilla- tor em ploying a phase accumulator, a sin rom, and a 10-bit d/a converter integrated on a single cmos chip. clock rates up to 25 mhz are supported with a power supply from 2.3 v to 5.5 v. capability for phase modulation and frequency modulation is provided. frequency accuracy can be controlled to one part in 0.25 billion. modulation is affected by loading registers through the serial interface. the AD9833 offers a variety of output waveforms from the vout pin. the sin rom can be bypassed so that a linear up/down ramp is output from the dac. if the sin rom is not byp assed, a sinusoidal output is available. also, if a clock output is required, the msb of the dac data can be output. the digital section is internally operated at 2.5 v, irrespective of the value of vdd, by an on-board regulator that steps down vdd to 2.5 v when vdd exceeds 2.7 v. the AD9833 has a power-down function (sleep). this allows sections of the device that are not being used to be powered down, thus minimizing the current consumption of the part, e.g., the dac can be powered down when a clock out put is being generated. the AD9833 is available in a 10-lead msop package.
rev. prh e2e AD9833especifications * (v dd = 2.3 v to 5.5 v, agnd = dgnd = 0 v, t a = t min to t max , r set = 6.8 k for vout, unless otherwise noted.) parameter min typ max unit test conditions/comments signal dac specifications resolution 10 bits update rate 25 msps v out max 0.65 v v out min 38 mv v out tc 200 ppm/ c dc accuracy integral nonlinearity 1.0 lsb differential nonlinearity 0.5 lsb dds specifications dynamic specifications signal-to-noise ratio 55 60 db f mclk = 25 mhz, f out = f mclk /4096 total harmonic distortion 56 66 dbc f mclk = 25 mhz, f out = f mclk /4096 spurious-free dynamic range (sfdr) wideband (0 to nyquist) 60 dbc f mclk = 25 mhz, f out = f mclk /50 narrow band ( 200 khz) 78 dbc f mclk = 25 mhz, f out = f mclk /50 clock feedthrough dbc wake-up time 1 ms logic inputs v inh , input high voltage 1.7 v 2.3 v to 2.7 v power supply 2.0 v 2.7 v to 3.6 v power supply 2.8 v 4.5 v to 5.5 v power supply v inl , input low voltage 0.5 v 2.3 v to 2.7 v power supply 0.7 v 2.7 v to 3.6 v power supply 0.8 v 4.5 v to 5.5 v power supply i inh /i inl , input current 10 a c in , input capacitance 3 pf power supplies f mclk = 25 mhz, f out = f mclk /4096 vdd 2.3 5.5 v i dd 4.5 5.5 ma i dd code dependent. see tpc 2. low power sleep mode 0.5 ma dac powered down, mclk running * operating temperature range is as follows: b version: ?0 c to +105 c; typical specifications are at 25 c. specifications subject to change without notice.
rev. prh AD9833 e3e vout comp 12 AD9833 10-bit dac sin rom 20pf 10nf vdd regulator 100nf cap/2.5v figure 1. test circuit with which specifications are tested timing characteristics * parameter limit at t min to t max unit test conditions/comments t 1 40 ns min mclk period t 2 16 ns min mclk high duration t 3 16 ns min mclk low duration t 4 25 ns min sclk period t 5 10 ns min sclk high duration t 6 10 ns min sclk low duration t 7 5 ns min fsync sclk fs fsyncsclk s sclkfsyncfs clk f c sclk fsync s f s nn
rev. prh e4e AD9833 absolute maximum ratings * (t a = 25 c, unless otherwise noted.) vdd to agnd . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +6 v vdd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +6 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . e0.3 v to +0.3 v cap/2.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75 v digital i/o voltage to dgnd . . . . . . e0.3 v to vdd + 0.3 v analog i/o voltage to agnd . . . . . . e0.3 v to vdd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . . . e40 c to +105 c storage temperature range . . . . . . . . . . . . e65 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . . 150 c ms op package
rev. prh AD9833 ? pin function descriptions pin number mnemonic function power supply 2 vdd positive power supply for the analog and the digital interface sections. the on- board 2.5 v regulator is also supplied from vdd. vdd can have a value from 2.3 v to 5.5 v. a 0.1 f and 10 f decoupling capacitor should be con- nected between vdd and agnd. 3 cap/2.5 v the digital circuitry operates from a 2.5 v power supply. this 2.5 v is gener- ated from vdd using an on-board regulator (when vdd exceeds 2.7 v). the regulator requires a decoupling capacitor of typically 100 nf, which is conn ected from cap/2.5 v to dgnd. if vdd is equal to or less than 2.7 v, cap/2.5 v should be tied directly to vdd. 4 dgnd digital ground 9 agnd analog ground analog signal and reference 1 comp a dac bias pin. this pin is used for decoupling the dac bias voltage. 10 vout voltage output. the analog and digital output from the AD9833 is available at this pin. an external load resistor is not required as the device has a 200 resistor on-board. digital interface and control 5 mclk digital clock input. dds output frequencies are expressed as a binary fraction of the frequency of mclk. the output frequency accuracy and phase noise are determined by this clock. 6 sdata serial data input. the 16-bit serial data-word is applied to this input. 7 sclk serial clock input. data is clocked into the AD9833 on each falling sclk edge. 8 fsync active low control input. this is the frame synchronization signal for the input data. when fsync is taken low, the internal logic is informed that a new word is being loaded into the device.
rev. prh e6e AD9833?ypical performance characteristics mclk ?mhz i dd ?ma 5.5 5.0 3.0 3.5 4.0 4.5 030 5101 52025 5v 3v t a = 25 c tpc 1. typical current consump- tion vs. mclk frequency mclk frequency ?mhz ?0 ?0 ?5 ?0 ?5 ?0 ?5 030 51015 sfdr ?db 20 25 sfdr db imhz sfdr db mclk/7 av d d = dvdd = 3v t a = 25 c tpc 4. wideband sfdr vs. mclk frequency temperature ? c 400 ?0 w ake-up time ? s 900 ?0 ?0 0 20 40 60 80 100 120 450 500 550 600 650 700 750 800 850 2.3v 5.5v tpc 7. wake-up time vs. temperature f out ?hz 5.5 3.0 4.0 4.5 5.0 100 1m 1k 10k 100k i dd ?ma 3.5 3v 5v t a = 25 c tpc 2. typical i dd vs. f out for f mclk = 25 mhz f out ?mhz ?0 ?0 ?0 ?0 ?0 ?0 ?0 0.001 0.01 0.1 1 sfdr ?db 10 100 0 ?0 ?0 mclk 1mhz mclk 10mhz mclk 18mhz mclk 25mhz av d d = dvdd = 3v t a = 25 c tpc 5. wideband sfdr vs. f out /f mclk for various mclk frequencies temperature ? c 1.200 1.100 1.125 1.150 1.175 ?0 vrefout ?v 1.250 1.225 25 105 upper range lower range tpc 8. wake-up time vs. temperature mclk frequency ?mhz ?0 ?0 ?0 ?0 ?0 0 80 20 40 60 sfdr ?db sfdr db mclk/7 sfdr db mclk/50 av d d = dvdd = 3v t a = 25 c tpc 3. narrow-band sfdr vs. mclk frequency mclk ?frequency ?0 ?0 ?5 ?0 ?5 1.0 snr ?db ?0 ?5 5.0 10.0 12.5 25.0 50.0 t a = 25 c tpc 6. snr vs. mclk frequency frequency ?hz 10db/div 0 ?0 ?0 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 0 100k rwb 100 st 100 sec vwb 30 tpc 9. f mclk = 10 mhz, f out = 2.4 khz, frequency word = 000fba9
rev. prh AD9833 e7e frequency ?hz 10db/div 0 ?0 ?0 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 0 5m rwb 1k st 50 sec vwb 300 tpc 10. f mclk = 10 mhz, f out = 1.43 mhz = f mclk /7, frequency word = 2492492 frequency ?hz 10db/div 0 ?0 ?0 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 0 1m rwb 300 st 100 sec vwb 100 tpc 13. f mclk = 25 mhz, f out = 60 khz, frequency word = 009d495 frequency ?hz 10db/div 0 ?0 ?0 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 0 10m rwb 1k st 100 sec vwb 300 tpc 16. f mclk = 25 mhz, f out = 3.857 mhz = f mclk /7, frequency word = 2492492 frequency ?hz 10db/div 0 ?0 ?0 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 0 5m rwb 1k st 50 sec vwb 300 tpc 11. f mclk = 10 mhz, f out = 3.33 mhz = f mclk /3, frequency word = 5555555 frequency ?mhz 10db/div 0 ?0 ?0 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 0 10m rwb 1k st 100 sec vwb 300 tpc 14. f mclk = 25 mhz, f out = 600 khz, frequency word = 0624dd3 frequency ?hz 10db/div 0 ?0 ?0 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 0 10m rwb 1k st 100 sec vwb 300 tpc 17. f mclk = 25 mhz, f out = 8.333 mhz = f mclk /3, frequency word = 5555555 frequency ?hz 10db/div 0 ?0 ?0 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 0 100k rwb 100 st 100 sec vwb 30 tpc 12. f mclk = 25 mhz, f out = 6 khz, frequency word = 000fba9 frequency ?hz 10db/div 0 ?0 ?0 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 0 10m rwb 1k st 100 sec vwb 300 tpc 15. f mclk = 25 mhz, f out = 2.4 mhz, frequency word = 189374d
rev. prh e8e AD9833 terminology integral nonlinearity this is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the end- points of the transfer function are zero scale, a point 0.5 lsb below the first code transition (000 . . . 00 to 000 . . . 01), and full scale, a point 0.5 lsb above the last code transition (111 . . . 10 to 111 . . . 11). the error is expressed in lsbs. differential nonlinearity this is the difference between the measured and ideal 1 lsb change between two adjacent codes in the dac. a specified differ- ential nonlinearity of 1 lsb maximum ensures monotonicity. output compliance the output compliance refers to the maximum voltage that can be generated at the output of the dac to meet the specifica tions. when voltages greater than that specified for the output compli- ance are generated, the AD9833 may not meet the specifications listed in the data sheet. spurious-free dynamic range along with the frequency of interest, harmonics of the fundamental frequency and images of these frequencies are present at the output of a dds device. the spurious-free dynamic range (s fdr) refers to the largest spur or harmonic present in the band of interest. the wideband sfdr gives the magnitude of the largest harm onic or spur relative to the magnitude of the fundamental frequency in the ??to nyquist bandwidth. the narrow band sfdr gives the attenuation of the largest spur or harmonic in a bandwidth of 200 khz about the fundamental frequency. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the rms value of the fundamental. for the ad9834, thd is defined as: thd v v v v v v =++++ () 20 2 2 2 3 4 2 5 2 6 2 1 log where v 1 is the rms amplitude of the fundamental and v 2, v 3, v 4, v 5, and v 6 are the rms amplitudes of the second through sixth harmonic. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the n yquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. clock feedthrough there will be feedthrough from the mclk input to the analog output. clock feedthrough refers to the magnitude of the mclk signal relative to the fundamental frequency in the ad9834? output spectrum. theory of operation sine waves are typically thought of in terms of their magnitude form a(t) = sin( t). however, these are nonlinear and not easy to generate except through piecewise construction. on the other hand, the angular information is linear in nature. that is, the phase angle rotates through a fixed angle for each unit of time. the angular rate depends on the frequency of the signal by the traditional rate of = 2 f . magnitude phase +1 0 ? 2p 0 figure 4. sine wave knowing that the phase of a sine wave is linear and given a refer- ence interval (clock period), the phase rotation for that period can be determined. ? phase t =? solving for ?? == ? phase t f /2 solving for f and substituting the reference clock frequency for the reference period 1/ ft mclk = () f phase f mclk = ? /2 the AD9833 builds the output based on this simple equation. a simple dds chip can implement this equation with three major subcircuits: numerical controlled oscillator + phase modulator, sin rom, and digital-to-analog converter. each of these subcircuits are discussed in the following section. circuit description the AD9833 is a fully integrated direct digital synthesis ( dds) chip. the chip requires one reference clock, one low precision resistor, and decoupling capacitors to provide digitally cre ated sine waves up to 12.5 mhz. in addition to the generation of this rf signal, the chip is fully capable of a broad range of simple and complex modulation schemes. these modulation schemes are fully implemented in the digital domain allowing accurate and simple realization of complex modulation algorithms using dsp techniques. the internal circuitry of the AD9833 consists of the following main sections: a numerical controlled oscillator (nco), fre- quency and phase modulators, sin rom, a digital-to-analog converter, and a regulator.
rev. prh AD9833 ? numerical controlled oscillator plus phase modulator this consists of two frequency select registers, a phase accumulator, two phase offset registers, and a phase offset adder. the main component of the nco is a 28-bit phase accumu lator. continuous time signals have a phase range of 0 to 2 . out side this range of numbers, the sinusoid functions repeat them selves in a periodic manner. the digital implementation is no different. the accumulator simply scales the range of phase numbers into a multibit digital word. the phase accumulator in the AD9833 is implemented with 28 bits. therefore, in the AD9833, 2 = 2 28 . likewise, the phase term is scaled into this range of num- bers 0 < phase < 2 28 e 1, making these substitutions into the equation above f phase f mclk = ? phase < 2 28 e 1. the input to the phase accumulator can be selected either from the freq0 register or freq1 register, and is controlled by the fselect bit. ncos inherently generate continuous phase signals, thus avoiding any output dis continuity when switching between frequencies. following the nco, a phase offset can be added to perform phase modulation using the 12-bit phase registers. the contents of one of these phase registers is added to the most significant bits of the nco. the AD9833 has two phase registers, the resolu- tion of these registers being 2 /4096. sin rom to make the output from the nco useful, it must be converted from phase information into a sinusoidal value. since phase information maps directly into amplitude, the sin rom uses the digital phase information as an address to a look-up table and c onverts the phase information into amplitude. although the nco contains a 28-bit phase accumulator, the output of the nco is truncated to 12 bits. using the full resolution of the phase accumulator is impractical and unnecessary, as this would require a look-up table of 228 entries. it is necessary only to have sufficient phase resolution such that the errors due to t runcation are smaller than the resolution of the 10-bit dac. this requires the sin rom to have 2 bits of phase resolution more than the 10-bit dac. the sin rom is enabled using the mode bit (d1) in the control register. this is explained further in table xi. digital-to-analog converter the AD9833 includes a high-impedance current source 10-bit dac. the dac receives the digital words from the sin rom and converts them into the corresponding analog voltages. the dac is configured for single-ended operation. an external load resistor is not required since the device has a 200 ? ( )
rev. prh e10e AD9833 the control register the AD9833 contains a 16-bit control register that sets up the AD9833 as the user wishes to operate it. all control bits, except mode, are sampled on the internal negative edge of mclk. table ii describes the individual bits of the control register. the different functions and the various output options from the AD9833 are des cribed in more detail in the section follow ing table ii. sin rom phase accumulator (28-bit) AD9833 (low power) 10-bit dac 0 mux 1 sleep12 sleep1 reset mode + opbiten i opbiten ot iit otot enbe ib b b b b b b b eet b peet b b eet b eep b eep b opbiten b b i b b oe b b tii b b n b t bt bbt tit t b b btb btbb tbbb b tbb tb btb bbb bb bb b b eet teete e peet tpeetpepe t eet eeteet eettti eep eep no eep t t ti ontobit
rev. prh AD9833 ?1 table ii. description of bits in the control register (continued) bit name function d6 sleep12 sleep12 = 1 powers down the on-chip dac. this is useful when the AD9833 is used to output the msb of the dac data. sleep12 = 0 implies that the dac is active. this function is explained further in table x. d5 opbiten the function of this bit, in association with d1 (mode), is to control what is output at the vout pin. this is explained further in table xi. when opbiten = 1, the output of the dac is no longer available at the vout pin. instead, the msb (or msb/ 2) of the dac data is connected to the vout pin. this is useful as a coarse clock source. the bit div2 controls whether it is the msb or msb/2 that is output. when opbiten = 0, the dac is connected to vout. the mode bit determines whether it is a sinusoidal or a ramp output that is available. d4 reserved this bit must be set to ?. d3 div2 div2 is used in association with d5 (opbiten). this is explained further in table xi. when div2 = 1, the msb of the dac data is passed directly to the vout pin. when div2 = 0, the msb/2 of the dac data is output at the vout pin. d2 reserved this bit must always be set to ?. d1 mode this bit is used in association with opbiten (d5). the function of this bit is to control what is output at the vout pin when the on-chip dac is connected to vout. this bit should be set to ??if the control bit opbiten = 1. this is explained further in table xi. when mode = 1, the sin rom is bypassed, resulting in a ramp output from the dac. when mode = 0, the sin rom is used to convert the phase information into amplitude information, which results in a sinusoidal signal at the output. d0 reserved this bit must always be set to ?. the frequency and phase registers the AD9833 contains two frequency registers and two phase registers. these are described in table iii. table iii. frequency/phase registers register size description freq0 28 bits frequency register ?.?when the fselect bit = 0, this register defines the output frequency as a fraction of the mclk frequency. freq1 28 bits frequency register ?.?when the fselect bit = 1, this register defines the output frequency as a fraction of the mclk frequency. phase0 12 bits phase offset register ?.?when the pselect bit = 0, the contents of this register are added to the output of the phase accumulator. phase1 12 bits phase offset register ?.?when the pselect bit = 1, the contents of this register are added to the output of the phase accumulator. the analog output from the AD9833 is: f freqreg mclk /2 28 where freqreg is the value loaded into the selected fre quency register. this signal will be phase shifted by 2 4096 / phasereg where phasereg is the value contained in the selected phase register. c onsideration must be given to the relationship of the selected output frequency and the reference clock fre- quency to avoid unwanted output anomalies. the flow chart in figure 9 shows the routine for writing to the frequency and phase registers of the AD9833. writing to a frequency register when writing to a frequency register, bits d15 and d14 give the address of the frequency register. table iv. frequency register bits d15 d14 d13 d0 01 msb 14 freq0 reg bits lsb 10 msb 14 freq1 reg bits lsb
rev. prh ?2 AD9833 the reset function the reset function resets appropriate internal registers to ? to provide an analog output of midscale. reset does not reset the phase, frequency, or control registers. when the AD9833 is powered up, the part should be reset. to reset the AD9833, set the reset bit to ?.?to take the part out of reset, set the bit to ?.?a signal will appear at the dac to output eight mclk cycles after reset is set to ?. table ix. applying reset reset bit result 0n o reset applied 1 internal registers reset the sleep function sections of the AD9833, which are not in use, can be powered down to minimize power consumption. this is done using the sleep function. the parts of the chip that can be powered down are the internal clock and the dac. the bits required for the sleep fun ction are outlined in table x. table x. applying the sleep function sleep1 bit sleep12 bit result 00 no power-down 01 dac powered down 10 internal clock disabled 11 both the dac powered down and the internal clock disabled dac powered down this is useful when the AD9833 is used to output the msb of the dac data only. in this case, the dac is not required so it can be powered down to reduce power consumption. internal clock disabled when the internal clock of the AD9833 is disabled, the dac output will remain at its present value as the nco is no longer accumulating. new frequency, phase, and control words can be written to the part when the sleep1 control bit is active. the synchronizing clock is still active, which means that the selected frequency and phase registers can also be changed using the control bits. setting the sleep1 bit equal to 0 enables the mclk. any changes made to the registers while sleep1 was active will be seen at the output after a certain latency. the vout pin the AD9833 offers a variety of outputs from the chip, all of w hich are available from the vout pin. the choice of outputs are: the msb of the dac data, a sinusoidal output, or a ramp output. the bits opbiten (d5) and mode (d1) in the control regis- ter are used to decide which output is available from the ad 9833. this is explained further below and also in table xi. msb of the dac data the msb of the dac data can be output from the AD9833. by setting the opbiten (d5) control bit to 1, the msb of the dac data is available at the vout pin. this is useful as a coarse clock source. this square wave can also be divided by two before being output. the bit div2 (d3) in the control register controls the frequency of this output from the vout pin. if the user wishes to alter the entire contents of a frequency register, two consecutive writes to the same address must be performed since the frequency registers are 28 bits wide. the first write will contain the 14 lsbs, while the second write will con tain the 14 msbs. for this mode of operation, the control bit b28 (d 13) should be set to 1. an example of a 28-bit write is shown in table v. table v. writing 3fff0000 to freq0 reg sdata input result of input word 0010 0000 0000 0000 control word write (d15, d14 = 00), b28 (d13) = 1, hlb (d12) = x 0100 0000 0000 0000 freq0 reg write (d15, d14 = 01), 14 lsbs = 0000 0111 1111 1111 1111 freq0 reg write (d15, d14 = 01), 14 msbs = 3fff in some applications, the user does not need to alter all 28 bits of the frequency register. with coarse tuning, only the 14 msbs are altered while with fine tuning, only the 14 lsbs are altered. by setting the control bit b28 (d13) to 0, the 28-bit fre quency register operates as two, 14-bit registers, one containing the 14 msbs and the other containing the 14 lsbs. this means that the 14 msbs of the frequency word can be altered independent of the 14 lsbs, and vice versa. bit hlb (d12) in the control register identifies which 14 bits are being altered. examples of this are shown in tables vi and vii. table vi. writing 3fff to the 14 lsbs of freq1 reg sdata input result of input word 0000 0000 0000 0000 control word write (d15, d14 = 00), b28 (d13) = 0; hlb (d12) = 0, i.e. lsbs 1011 1111 1111 1111 freq1 reg write (d15, d14 = 10), 14 lsbs = 3fff table vii. writing 0011 to the 14 msbs of freq0 reg sdata input result of input word 0001 0000 0000 0000 control word write (d15, d14 = 00), b28 (d13) = 0, hlb (d12) = 1, i.e. msbs 0100 0000 1111 1111 freq0 reg write (d15, d14 = 01), 14 msbs = 0011 writing to a phase register when writing to a phase register, bits d15 and d14 are set to 11. bit d13 identifies which phase register is being loaded. table viii. phase register bits d15 d14 d13 d12 d11 d0 110 x msb 12 phase0 bits lsb 111 x msb 12 phase1 bits lsb
rev. prh AD9833 ?3 sinusoidal output the sin rom is used to convert the phase information from the frequency and phase registers into amplitude information that results in a sinusoidal signal at the output. to have a sinusoidal output from the vout pin, set the bit mode (d1) = 0 and the opbiten (d5) bit to ?. up/down ramp output the sin rom can be bypassed so that the truncated digital output from the nco is sent to the dac. in this case, the output is no longer sinusoidal. the dac will produce a ramp up/down function. to have a ramp output from the vout pin, set the bit mode (d1) = 1. note that the sleep12 bit must be ??(i.e. the dac is en abled) when using this pin. table xi. various outputs from vout opbiten bit mode bit div2 bit vout pin 00 x sinusoid 01xu p/down ramp 10 0 dac data msb/2 10 1 dac data msb 11 xr eserved figure 6. ramp output applications because of the various output options available from the part, the AD9833 can be configured to suit a wide variety of applications. one of the areas where the AD9833 is suitable is in modulation applications. the part can be used to perform simple modu- la tion, such as fsk. more complex modulation schemes, such as gmsk and qpsk, can also be implemented using the AD9833. in an fsk application, the two frequency registers of the ad 9833 are loaded with different values. one frequency will represent the space frequency, while the other will represent the mark frequency. using the fselect bit in the control register of the AD9833, the user can modulate the carrier frequency between the two values. the AD9833 has two phase registers; this enables the part to perform psk. with phase shift keying, the carrier frequency is phase shifted, the phase being altered by an amount that is related to the bit stream being input to the modulator. the AD9833 is also suitable for signal generator applica tions. because the msb of the dac data is available at the vout pin, the device can be used to generate a square wave. with its low current consumption, the part is suitable for appli- cations in which it can be used as a local oscillator. grounding and layout the printed circuit board that houses the AD9833 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be separated easily. a minimum etch technique is generally best for ground planes since it gives the best shielding. digital and analog ground planes should only be joined in one place. if the AD9833 is the only device requiring an agnd to dgnd connection, then the ground planes should be connected at the agnd and dgnd pins of the AD9833. if the AD9833 is in a system where multiple devices require agnd to dgnd connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD9833. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the AD9833 to avoid noise coupling. the power supply lines to the AD9833 should use as large a track as is possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals, such as clocks, should be shielded with digital ground to avoid radiat- ing noise to other sections of the board. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip tech nique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is d edi- cated to ground planes, while signals are placed on the other side. good decoupling is important. the AD9833 should have supply bypassing of 0.1 f ceramic capacitors in parallel with 10 f tantalum capacitors. to achieve the best from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. proper operation of the comparator requires good layout strategy. the strategy must minimize through proper layout of the pcb the parasitic capacitance between v in and the sign bit out pin by adding isolation using a ground plane. for example, in a four layer board, the c in signal could be con- nected to the top layer and the sign bit out connected to the bottom layer, so that isolation is provided by the power and ground planes between.
rev. prh e14e AD9833 data write see figure 9 select data sources wait 8/9 mclk cycles v out = v ref 18 r load /r set (1+ (sin(2 (freqreg f mclk t /228 + phasereg /212 )))) dac output change phase? change frequency? change dac output from sin to ramp? change output to a digital signal? change pselect? change phase register? change fselect? change frequency register? control register write (see table xi) initialization see figure 8 below no no no no yes no yes yes no yes yes yes yes yes figure 7. flow chart for AD9833 initialization and operation initialization apply reset (control register write) reset = 1 write to frequency and phase registers freq0 reg = f out0 /f mclk 2 28 freq1 reg = f out1 /f mclk 2 28 phase0 and phase1 reg = (phaseshift 2 12 ) / 2 (see figure 9) set reset = 0 select frequency registers select phase registers (control register write) reset bit = 0 fselect = selected frequency register pselect = selected phase register figure 8. initialization
rev. prh AD9833 ?5 no write 14 msbs or lsbs to a frequency register? (control register write) b28 (d13) = 0 hlb (d12) = 0/1 write a 16-bit word (see tables vi and vii for examples) write 14msbs or lsbs to a frequency register? write to phase register? (16-bit write) d15, d14 = 11 d13 = 0/1 (choose the phase register) d12 = x d11 ... d0 = phase data write to another phase register? yes write another full 28-bit to a frequency register? write two consecutive 16-bit words (see table v for example) (control register write) b28 (d13) = 1 write a full 28-bit word to a frequency register? data write no yes yes no yes no no yes yes figure 9. data writes interfacing to microprocessors the AD9833 has a standard serial interface that allows the part to interface directly with several microprocessors. the device uses an external serial clock to write the data/control information into the device. the serial clock can have a frequency of 40 mhz maxi- mum. the serial clock can be continuous, or it can idle high or low between write operations. when data/control information is being written to the AD9833, fsync is taken low and is held low while the 16 bits of data are being written into the AD9833. the fsync signal frames the 16 bits of information being loaded into the AD9833. AD9833 to adsp-21xx interface figure 10 shows the serial interface between the AD9833 and the adsp-21xx. the adsp-21xx should be set up to operate in the sport transmit alternate framing mode (tfsw = 1). the adsp-21xx is programmed through the sport control register and should be configured as follows: internal clock operation (isclk = 1) active low framing (invtfs = 1) 16-bit word length (slen = 15) internal frame sync signal (itfs = 1) generate a frame sync for each write (tfsr = 1) transmission is initiated by writing a word to the tx register after the sport has been enabled. the data is clocked out on each rising edge of the serial clock and clocked into the AD9833 on the sclk falling edge. * additional pins omitted for clarity AD9833 * fsync sdata sclk adsp-2101/ adsp-2103 * tfs dt sclk figure 10. adsp-2101/adsp-2103 to AD9833 interface AD9833 to 68hc11/68l11 interface figure 11 shows the serial interface between the AD9833 and the 68hc11/68l11 microcontroller. the microcontroller is configured as the master by setting bit mstr in the spcr to 1. this provides a serial clock on sck while the mosi output d rives the serial data line sdata. since the microcontroller does not have a dedicated frame sync pin, the fsync signal is derived from a port line (pc7). the setup conditions for correct operation of the interface are as follows: sck idles high between write operations (cpol = 0). data is valid on the sck falling edge (cpha = 1). when data is being transmitted to the AD9833, the fsync line is taken low (pc7). serial data from the 68hc11/68l11 is transmit- ted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. in order to load data into the AD9833, pc7 is held low after the first 8 bits are transferred, and a second serial write operation is performed to the AD9833. only after the second 8 bits have been transferred should fsync be taken high again.
rev. prh ?6 AD9833 * additional pins omitted for clarity AD9833 * fsync sdata sclk 68hc11/68l11 * pc7 mosi sck figure 11. 68hc11/68l11 to AD9833 interface AD9833 to 80c51/80l51 interface figure 12 shows the serial interface between the AD9833 and the 80c51/80l51 microcontroller. the microcontroller is operated in mode ??so that txd of the 80c51/80l51 drives sclk of the AD9833, while rxd drives the serial data line sdata. the fsync signal is again derived from a bit programmable pin on the port (p3.3 being used in the diagram). when data is to be transmitted to the AD9833, p3.3 is taken low. the 80c51/80l51 transmits data in 8-bit bytes, thus only eight falling sclk edges occur in each cycle. to load the remaining 8 bits to the AD9833, p3.3 is held low after the first 8 bits have been transmitted, and a second write operation is initiated to transmit the second byte of data. p3.3 is taken high following the comple tion of the second write operation. sclk should idle high between the two write operations. the 80c51/80l51 outputs the serial data in a format t hat has the lsb first. the AD9833 accepts the msb first (the 4 msbs being the control information, the n ext 4 b its being the address, while the 8 lsbs contain the data when writing to a destination register). therefore, the transmit routine of the 80c51/80l51 must take this into account and rearrange the bits so that the msb is output first. * additional pins omitted for clarity fsync sdata sclk p3.3 rxd txd AD9833 * 80c51-80l51 * figure 12. 80c51/80l51 to AD9833 interface AD9833 to dsp56002 interface figure 13 shows the interface between the AD9833 and the dsp56002. the dsp56002 is configured for normal mode asynchronous operation with a gated internal clock (syn = 0, gck = 1, sckd = 1). the frame sync pin is generated inter nally (sc2 = 1), the transfers are 16 bits wide (wl1 = 1, wl0 = 0), and the frame sync signal will frame the 16 bits (fsl = 0). the frame sync signal is available on pin sc2, but it needs to be in verted before being applied to the AD9833. the interface to the dsp56000/dsp56001 is similar to that of the dsp56002. * additional pins omitted for clarity fsync sdata sclk sc2 std sck AD9833 * dsp56002 * figure 13. AD9833 to dsp56002 interface AD9833 evaluation board the AD9833 evaluation board allows designers to evaluate the high-performance AD9833 dds modulator with a minimum of effort. to prove that this device will meet the user? waveform synthe- sis requirements, the user only requires a power supply, an ibm-compatible pc, and a spectrum analyzer along with the evaluation board. the dds evaluation kit incl udes a populated, teste d AD9833 printed circuit board. the evaluation board interfaces to the parallel port of an ibm-compatible pc. software is available with the evaluation board that allows the user to easily pro gram the AD9833. a schematic of the evaluation board is shown in figure 14. the software will run on any ibm-compatible pc that has microsoft win 95 , win 98 , windows me , or windows 2000 nt installed. using the AD9833 evaluation board the AD9833 evaluation kit is a test system designed to simplify the evaluation of the AD9833. an application note is also avail- able with the evaluation board and gives full information on operating the evaluation board. prototyping area an area is available on the evaluation board for the user to add additional circuits to the evaluation test set. users may want to build custom analog filters for the output or add buffers and operational amplifiers to be used in the final application. xo vs. external clock the AD9833 can operate with master clocks up to 25 mhz. a 25 mhz oscillator is included on the evaluation board. how ever, this oscillator can be removed and, if required, an external cmos clock connected to the part. power supply power to the AD9833 evaluation board must be provided ex ter- nally through pin connections. the power leads should be tw isted to reduce ground loops.
rev. prh AD9833 ?7 mclk r1 50r dgnd dvdd out dvdd c5 0.1 f lk2 u3 18 16 14 1 6 4 2 dvdd c6 0.1 f u2 j1 sclk sdata fsync dvdd c6 0.1 f c8 10 f c7 0.1 f c9 0.1 f c10 10 f j2 j3 dvdd vdd vout c4 vdd c3 0.01 f c2 0.1 f vdd c11 10 f c1 0.1 f lk1 2 vdd cap 3 1 10 comp dgnd agnd 49 5 8 6 7 mclk fsync sdata sclk u1 AD9833 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 sclk fsync sdata vout figure 14. evaluation board layout integrated circuits u1 AD9833bru u2 74hct244 u3 osc xtal 25 mhz capacitors c1, c2 100 nf ceramic capacitor 0805 c3 10 nf ceramic capacitor c4 option for extra decoupling capacitor c5, c6, c7, c9 100 nf ceramic capacitor c8, c10, c11 10 f tantalum capacitor resistor r1 51 ? resistor links lk1, lk2 2-pin sil header sockets mclk vout subminiature bnc connector connectors j1 36-pin edge connector j2, j3 pcb mounting terminal block
rev. prh e18e AD9833 outline dimensions 10-lead msop package [msop] (rm-10) dimensions shown in millimeters 0.23 0.08 0.80 0.40 8 0 0.15 0 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 compliant to jedec standards mo-187ba coplanarity 0.10

▲Up To Search▲

Price & Availability of AD9833

	To Download AD9833 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .