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revision 3.0, 31-may-06 page 1 of 123 1. key features - precision single-phase, one or two current input energy measurement front-end including sigma- delta modulators for a/d-conversion and digital signal processor (dsp). - low current consumption of 5ma, depending on mcu activity. - digital phase correction and selectable gain on both current channels for use with two current transformers (ct) or one ct and one shunt. - power-supply monitor (psm) for power-on reset and reset when the supply voltage falls below a defined threshold. - customer programmable 8-bit 8051 compatible microcontroller (mcu). - programmable mcu clock with optional low power operating conditions. - 2 x universal asynchronous receiver / transmitters (uart) for external communications such as programme download and debugging. - programmable watchdog timer (wdt) and external system reset pin. - real-time clock/calendar (rtc) with on-chip digital calibration and separate battery supply pin. - on-chip voltage reference (vref) with small temperature coefficient. - low power 3.0 ? 4.0mhz crystal oscillator. - spi compatible interface for external eeprom memory. - standard on-chip lcd driver (lcdd) interface. - programmable multi-purpose i/os (mpio) with selectable data direction, pull-up or pull-down resistors and drive strength. - mains current lead/lag status indication for reactive energy measurement. - low power battery operating mode for meter reading when mains voltage is not present. - the AS8218 and as8228 ics offer the following options: AS8218: 20 x 4 segment lcdd 9 x multi-purpose i/o (mpio) as8228: 24 x 4 segment lcdd 12 x multi-purpose i/o (mpio) 2. general description the AS8218 / as8228 are highly integrated cmos single-phase energy metering devices for fully electronic lcd meter systems. the AS8218 / as8228 have been designed to ensure the meters full compliance with the international standards iec62052 and ansi. the AS8218 / as8228 ics include all the functions required for conventional 1 current or 2-current anti-tamper meters. the functions include precision energy measurement, an 8-bit microcontroller unit (mcu), an on-chip liquid crystal display driver (lcdd), programmable multi-purpose inputs/outputs (mpio), a real time clock/calendar (rtc) for complex tariff functions such as time-of- use or maximum demand billing and a serial peripheral interface (spi) for reading data from and writing data to an external non-volatile memory (eeprom). the AS8218 / as8228 ics have a dedicated energy measurement front-end, which includes an analog front-end and programmable digital signal processor (dsp) from which active energy, mains voltage and mains current are provided. reactive and apparent energy can also be calculated. the on-chip 8-bit 8051 compatible microcontroller is freely programmable and provides user access to the various functional blocks. the dedicated universal asynchronous receiver / transmitter (uart1) in the system control block provides access to various system functions and blocks. a second uart (uart2) is also provided, which may for example be used for debugging. the on-chip memory includes 24kbyte program memory and 1kbyte data memory. the meter system designer can select the size of the external eeprom memory from 1kbyte to 32kbyte (in binary steps). AS8218 / as8228 highly integrated single phase 2-current energy metering integrated circuits with microcontroller, rtc, programmable multi-purpose i/os and lcd driver data sheet
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 2 of 123 an on-chip programmable watchdog timer (wdt) is available to automatically initiate a system reset if a regular ?hold-off? signal is not detected. the system timing and real time clock (rtc) has a dedicated external battery supply pin (vdd_bat), enabling the oscillator and rtc to continue during ?power-down?. the rtc may be digitally calibrated for oscillator frequency accuracy. the lcd driver (lcdd) block enables the display of information provided by the microcontroller, directly to the lcd. two dedicated data register banks are provided to simplify programming, particularly in the case where the display data needs to be scrolled. the programmable multi-purpose i/o pins (mpio) may be independently configured as inputs or outputs. all the i/o pins are programmable for data direction, pull-up/pull-down resistors and drive strength (4ma/8ma). typical functions may include led energy consumption pulse output, energy direction and fault condition indication depending on current 1 or current 2 being active for the energy calculation, push button for display scrolling, mains isolation relay control for prepayment meters, optical interface etc. an on-chip analog ground buffer (abuf) and voltage reference (vref) ensures that no external circuitry is required. a power-supply monitor (psm) provides a reset, when vdd falls below a safe operating threshold. a reset pin (res_n) is available for external system reset. the AS8218 / as8228 ics are available in lqfp64 plastic packages.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 3 of 123 3. typical application circuit analog front end system timing & rtc system control i/os lcd driver spi dsp mcu uart1 sdm rtc low power divider low power oscillator lsd0 lsd5 lsd6 lsd4 lsd3 lsd2 lsd1 io0 lsd19 lsd18 lsd17 lsd16 lsd15 lsd14 lsd13 lsd12 lsd11 lsd10 lsd9 lsd8 lsd7 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 9 10 11 12 15 16 17 19 18 23 20 lcd led fault diro 24 25 io5 io4 io3 io2 io1 io6 io7 io8 reference pulses for calibration examples only s_n si sc so 40 22 37 38 39 7 lbp3 lbp0 lbp1 lbp2 vddd 3.3v vdda 33 xout 32 xin 3.3v i1p i1n 31 3 4 sdm i2p i2n 6 5 sdm vp vn 1 2 29 30 txd rxd 8 vssa 14 vssd 3.3v vdd_bat kwh vrms irms multi- purpose i/os push-button 13 21 vssd lsd23 lsd22 lsd21 lsd20 61 62 63 64 26 28 27 io9 io10 io11 load vi vo gnd 3.3v nl + as8228 only vss 3.3v 3.3v 3.3v 1 3 2 4 8 6 7 5 eeprom q hold vcc c d w s as8228 only + + res_n wdt 34 figure 1: typical application circuit of the AS8218 / as8228
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 4 of 123 4. pin out vp vn i1p i1n i2p i2n vdda vssa io0 io1 io2 io3 io5 io6 io7 io8 si s_n vddd vssd so sc io9 rxd vdd_bat xin 1 2 3 4 5 6 7 8 9 10 11 12 13 17 xout res_n lbp0 lbp1 lbp2 lbp3 lsd0 lsd1 lsd2 lsd3 lsd4 lsd5 lsd6 lsd8 lsd9 lsd10 lsd11 lsd12 lsd13 lsd14 lsd15 lsd16 lsd17 lsd18 lsd19 as8228 lqfp64 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 vddd vssd io10 io11 txd lsd7 lsd20 lsd21 lsd22 lsd23 io4 n.c. n.c. vp vn i1p i1n i2p i2n vdda vssa io0 io1 io2 io3 io5 io6 io7 io8 si s_n vddd vssd so sc n.c. rxd vdd_bat xin 1 2 3 4 5 6 7 8 9 10 11 12 13 17 xout res_n lbp0 lbp1 lbp2 lbp3 lsd0 lsd1 lsd2 lsd3 lsd4 lsd5 lsd6 lsd8 lsd9 lsd10 lsd11 lsd12 lsd13 lsd14 lsd15 lsd16 lsd17 lsd18 lsd19 AS8218 lqfp64 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 vddd vssd txd lsd7 n.c. io4 n.c. n.c. n.c. n.c. n.c. n.c. n.c. 5. pin description pin no. pin name AS8218 pin name as8228 type description 1 vp vp ai positive input for the voltage channel. vp is a differential input with vn. the typical differential voltage is 100mv peak. 2 vn vn ai negative input for the voltage ch annel. vn is a differential input with vp. 3 i1p i1p ai positive input for the first current channel. i1p is a differential input with i1n. the input gain is programmable depending on the desired current sensor. the typical differential voltage is 150mv peak (gain = 4). 4 i1n i1n ai negative input for the first current c hannel. i1n is a differential input with i1p. the input gain is programmable depending on the desired current sensor. the typical differential voltage is 150mv peak (gain = 4). 5 i2p i2p ai positive input for the second current channel. i2p is a differential input with i2n. the input gain is programmable depending on the desired current sensor. the typical differential voltage is 150mv peak (gain = 4). 6 i2n i2n ai negative input for the second current channel. i2n is a differential input with i2p. the input gain is programmable depending on the desired current sensor. the typical differential voltage is 150mv peak (gain = 4). 7 vdda vdda s positive analog supply. vdda provides the positive supply voltage for the analog circuitry. the required supply voltage is 3.3v 10%. 8 vssa vssa s negative analog supply. vssa is the ground reference for the analog circuitry. 9 io0 io0 dio programmable multi-purpose input/out put, with selectable pull-up or pull-down resistors and selectable drive strength.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 5 of 123 pin no. pin name AS8218 pin name as8228 type description 10 io1 io1 dio programmable multi-purpose input/out put, with selectable pull-up or pull-down resistors and selectable drive strength. 11 io2 io2 dio programmable multi-purpose input/out put, with selectable pull-up or pull-down resistors and selectable drive strength. 12 io3 io3 dio programmable multi-purpose input/out put, with selectable pull-up or pull-down resistors and selectable drive strength. 13 vddd vddd s positive digital supply. vddd provides the positive supply voltage to the digital circuitry and is internally connected to pin 22. the required supply voltage is 3.3v 10%. 14 vssd vssd s negative digital supply. vssd is the ground reference for the digital circuitry. 15 io4 io4 dio programmable multi-purpose input/output, with selectable pull-up or pull-down resistors and selectable drive strength. 16 io5 io5 dio programmable multi-purpose input/out put, with selectable pull-up or pull-down resistors and selectable drive strength. 17 io6 io6 dio programmable multi-purpose input/out put, with selectable pull-up or pull-down resistors and selectable drive strength. 18 io7 io7 dio programmable multi-purpose input/output, with selectable pull-up or pull-down resistors and selectable drive strength. 19 io8 io8 dio programmable multi-purpose input/out put, with selectable pull-up or pull-down resistors and selectable drive strength. 20 si si dipd serial peripheral interface (spi) for external eeprom: serial data input. si is a digital input with an on-chip pull-down resistor. 21 vssd vssd s negative digital supply. vssd is the ground reference for the digital circuitry. 22 vddd vddd s positive digital supply. vddd provides the positive supply voltage to the digital circuitry and is internally connected to pin 13. the required supply voltage is 3.3v 10%. 23 s_n s_n do serial peripheral interface (spi) fo r external eeprom: chip select (active low). 24 so so do serial peripheral interface (spi) fo r external eeprom: serial data output 25 sc sc do serial peripheral interface (spi) for external eeprom: serial clock 26 n.c. io9 dio programmable multi-purpose input/out put, with selectable pull-up or pull-down resistors and selectable drive strength. 27 n.c. io10 dio programmable multi-purpose input/out put, with selectable pull-up or pull-down resistors and selectable drive strength. 28 n.c. io11 dio programmable multi-purpose input/out put, with selectable pull-up or pull-down resistors and selectable drive strength. 29 txd txd do universal asynchronous receiver/t ransmitter (uart1) serial transmit data output. 30 rxd rxd dipu universal asynchronous receiver/transmitter (uart1) serial receive data input. rxd is a digital input with an on-chip pull-up resistor. 31 vdd_bat vdd_bat s battery backup supply voltage input fo r the system timing and real time clock (rtc). 32 xin xin ai a 3.0 to 4.0mhz crystal may be connected across xin and xout without the requirement for external load capacitors. alternatively, an external clock signal may be applied to xin.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 6 of 123 pin no. pin name AS8218 pin name as8228 type description 33 xout xout ao see xin above, for the connection of a crystal. when an external clock is applied to xin, xout is not connected. 34 res_n res_n system reset active low. 35 n.c. n.c. not connected 36 n.c. n.c. not connected 37 lbp0 lbp0 ao lcd back-plane driver output signal. 38 lbp1 lbp1 ao lcd back-plane driver output signal. 39 lbp2 lbp2 ao lcd back-plane driver output signal. 40 lbp3 lbp3 ao lcd back-plane driver output signal. 41 lsd0 lsd0 ao lcd segment driver output signal. 42 lsd1 lsd1 ao lcd segment driver output signal. 43 lsd2 lsd2 ao lcd segment driver output signal. 44 lsd3 lsd3 ao lcd segment driver output signal. 45 lsd4 lsd4 ao lcd segment driver output signal. 46 lsd5 lsd5 ao lcd segment driver output signal. 47 lsd6 lsd6 ao lcd segment driver output signal. 48 lsd7 lsd7 ao lcd segment driver output signal. 49 lsd8 lsd8 ao lcd segment driver output signal. 50 lsd9 lsd9 ao lcd segment driver output signal. 51 lsd10 lsd10 ao lcd segment driver output signal. 52 lsd11 lsd11 ao lcd segment driver output signal. 53 lsd12 lsd12 ao lcd segment driver output signal. 54 lsd13 lsd13 ao lcd segment driver output signal. 55 lsd14 lsd14 ao lcd segment driver output signal. 56 lsd15 lsd15 ao lcd segment driver output signal. 57 lsd16 lsd16 ao lcd segment driver output signal. 58 lsd17 lsd17 ao lcd segment driver output signal. 59 lsd18 lsd18 ao lcd segment driver output signal. 60 lsd19 lsd19 ao lcd segment driver output signal. 61 n.c. lsd20 ao lcd segment driver output signal. 62 n.c. lsd21 ao lcd segment driver output signal. 63 n.c. lsd22 ao lcd segment driver output signal. 64 n.c. lsd23 ao lcd segment driver output signal. note: shaded pins above only available with as8228 ic
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 7 of 123 pin types: s supply pin ai analog input pin ao analog output pin dipd digital input pin with pull-down resistor dipu digital input pin with pull-up resistor do digital output pin dio programmable digital input or output pin
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 8 of 123 table of contents 1. key features ................................................................................................................... ......................1 2. general description ........ ............. ............. .............. ............. ............. .............. .......... .......... ...................1 3. typical application circuit .................................................................................................... ..................3 4. pin out........................................................................................................................ ..........................4 5. pin description ................................................................................................................ ......................4 6. electrical characteristics..................................................................................................... ...................9 6.1 absolute maximum ratings (non-operating) ......................................................................................9 6.2 operating conditions ........................................................................................................... .............9 6.3 dc/ac characteristics for digital inputs and outputs... ............. ............. .............. .......... ........... ........ 10 6.4 electrical system specification ................................................................................................ ........ 11 7. performance graphs ............................................................................................................. ............... 12 8. detailed functional description ................................................................................................ ............ 14 8.1 energy measurement front end (including dsp) .............................................................................. 16 8.2 lcd driver (lcdd) .............................................................................................................. ........... 48 8.3 programmable multi-purpose i/os (mpio)........................................................................................ 5 4 8.4 serial peripheral interface (spi) .............................................................................................. ........ 64 8.5 external eeprom requirements ................................................................................................... .. 70 8.6 8051 microcontroller (mcu)..... ............. .............. ............. ............. ........... ........... .......... ........... ........ 77 8.7 system control (sct) ........................................................................................................... .......... 98 8.8 serial interface ? uart1....................................................................................................... ........ 105 9. circuit diagram................................................................................................................ .................. 114 10. parts list..................................................................................................................... ...................... 115 11. packaging ...................................................................................................................... ................... 117 12. product ordering guide ......................................................................................................... ............ 117 13. collection of formulae ......................................................................................................... .............. 118 14. terminology .................................................................................................................... .................. 121 15. revision ....................................................................................................................... ..................... 122 16. copyright ...................................................................................................................... .................... 122 17. disclaimer ..................................................................................................................... .................... 122 18. contact ........................................................................................................................ ..................... 123
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 9 of 123 6. electrical characteristics 6.1 absolute maximum ratings (non-operating) stresses beyond the ?absolute maximum ratings? may cause permanent damage to the AS8218 / as8228 ics. these are stress ratings only. functional operation of th e device at these or any other conditions beyond those indicated under ?operating conditions? is not implied. caution: exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol min max unit notes dc supply voltage vdd -0.3 +5.0 v input pin voltage v in -0.3 vdd+0.3 v electrostatic discharge esd 1000 v norm: mil 883 e method 3015 storage temperature t strg -55 125 c lead temperature profile t lead norm: ipc/jedec-020c humidity non-condensing 5 85 % 6.2 operating conditions parameter symbol min typ max unit notes positive analog supply voltage vdda 3.0 3.6 v negative analog supply voltage vssa 0 0 v difference of supplies a - d -0.1 0.1 v vdda ? vddd vssa ? vssd positive digital supply voltage vddd 3.0 3.3 3.6 v referring to vssd, typical 10 % negative digital supply voltage vssd 0 0 v battery supply voltage vdd_bat 2.0 3.3 3.6 v ambient temperature t amb -40 25 85 c supply current i supp 5 ma depending on mcu activity system clock frequency f osc 3.0 3.579545 4.0 mhz
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 10 of 123 6.3 dc/ac characteristics for digital inputs and outputs cmos input with schmitt trigger and pull-up resistor (rxd) parameter symbol min typ max unit notes high level input voltage v ih 0.7 x vdd v low level input voltage v il 0.3 x vdd v low level input current i il -100 -15 a tested at vdd=3.6v and vin=0v cmos input (si) parameter symbol min typ max unit notes high level input voltage v ih 0.7 x vdd v low level input voltage v il 0.3 x vdd v high level input current i ih 15 100 a tested at vdd=3.6v and vin=3.6v cmos outputs (txd, so, sc, s_n) parameter symbol min typ max unit notes high level output voltage v oh 2.5 v tested at vdd=3.0v low level output voltage v ol 0.4 v tested at vdd=3.0v high level output current i oh 4 ma tested at vdd=3.0v and vout=voh low level output current i ol -4 ma tested at vdd=3.0v and vout=vol mpio inputs with schmitt trigger and selectable pull-up/pull-down parameter symbol min typ max unit notes high level input voltage v ih 0.7 x vdd v low level input voltage v il 0.3 x vdd v high level input current i ih 15 100 a tested at vdd=3.6v and vin=3.6v; ?pull-down? low level input current i il -100 -15 a tested at vdd=3.6v and vin=0v; ?pull-up? mpio outputs with programmable drive strength parameter symbol min typ max unit notes high level output current v oh 2.5 v tested at vdd=3.0v low level output current v ol 0.4 v tested at vdd=3.0v high level output current i oh 4 ma if ?4ma? is selected. tested at vdd=3.0v and vout=voh low level output current i ol -4 ma if ?4ma? is selected. tested at vdd=3.0v and vout=vol
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 11 of 123 parameter symbol min typ max unit notes high level output current i oh 8 ma if ?8ma? is selected. tested at vdd=3.0v and vout=voh low level output current i ol -8 ma if ?8ma? is selected. tested at vdd=3.0v and vout=vol lcdd outputs the liquid crystal display driver (lcdd) outputs are specified in the lcd driver section of this data sheet. 6.4 electrical system specification parameter symbol min typ max unit notes input signals voltage channel input voltage |v vp | 100 212 mvp referenced to vssa current channel input voltage (gain=4) |v i1p |, |v i2p | 150 212 mvp referenced to vssa current channel input voltage (gain=16) |v i1p |, |v i2p | 38 54 mvp referenced to vssa current channel input voltage (gain=20) |v i1p |, |v i2p | 30 42 mvp referenced to vssa mains frequency f mains 45 65 hz dynamic range current dr(i) 600:1 dynamic range power dr(p) 2000:1 accuracy 0.1 % reading error variation over dyn. range err(dr) 0.2 % 1) error variation over temperature err(temp) 0.5 % within operating temperature range, 1) error variation over cos(phi) err(co sphi) 0.5 % from 1 to 0.5, 1) error variation with vdd err(vdd) 0.2 % 1) output pulse jitter j 0.1 % 2) mains voltage v mains 264 v(rms) 240v + 10%, 3) measured current i max 120 a(rms) 3) measurement bandwidth bw 1.75 khz notes: 1) errors determined during energy measurement using a demoboard and a reference meter with high accuracy (0.05%), which calculates the actual error. 2) difference between largest and smallest error of 20 successive error samples; maximum meter constant: 1,600i/kwh; reference meter: 10,000 x dut-m eter-constant; measured at 5% ib, ib and i max . 3) what is used for system considerations/calculations.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 12 of 123 7. performance graphs -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 0,01 0,1 1 10 100 i [a] error [% ] vdd 3v0 vdd 3v3 vdd 3v6 graph 1: error as a % of reading for gain setting 4 at 25c -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 0,01 0,1 1 10 100 i [a] error [% ] vdd 3v0 vdd 3v6 vdd 3v3 graph 2: error as a % of reading for gain setting 16 at 25c -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 0,01 0,1 1 10 100 i [a] error [% ] vdd 3v6 vdd 3v3 vdd 3v0 graph 3: error as a % of reading for gain setting 20 at 25c -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 0,01 0,1 1 10 100 i [a] error [%] pf=1.0 pf=0.8 pf=0.5 graph 4: error as a % of reading for pf=1, pf=0.8, pf=0.5 at 25c -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 0,01 0,1 1 10 100 i [a] error [% ] pf=1.0 pf=0.8 pf=0.5 graph 5: error as a % of reading for pf=1, pf=0.8, pf=0.5 at -40c -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 0,01 0,1 1 10 100 i [a] error [%] pf=1.0 pf=0.8 pf=0.5 graph 6: error as a % of reading for pf=1, pf=0.8, pf=0.5 at 85c
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 13 of 123 -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 0,01 0,1 1 10 100 i [a] error [% ] 3v6 3v3 3v0 graph 7: error as a % of reading with variation in vdd -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 0,01 0,1 1 10 100 i [a] error [% ] 290v 230 v 170v graph 8: error as a % of reading with mains voltage variation -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 45 55 65 f [hz] error [% ] graph 9: error as a % of reading with mains frequency variation -2 -1,5 -1 -0,5 0 0,5 1 1,5 2 0,01 0,1 1 10 100 i [a] error [%] gain16 gain 4 gain 20 graph 10: error as a % of reading using vconst for mains voltage value
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 14 of 123 8. detailed functional description the AS8218 / as8228 integrated circuits have a dedicated measurement front end, which is capable of measuring active and reactive energy, rms mains voltage, rms mains current as well as power factor. there are two completely separate differential current channel inputs, for measurement of both the live and neutral currents. the two current inputs may be connected to a s hunt resistor (i1) and a current transformer (i2); of which the secondary winding is terminated with a burden resistor. both current channels have programmable gains; thus it is possible to connect the shunt resistor to any of the two differential current inputs. the option to use two current transformers is also available. the AS8218 / as8228 ics may be programmed to accept either of the two measured currents for the energy calculation, or may be programmed to accept the larger of the two currents for the energy calculation. the AS8218 / as8228 ics may also be used for conventional 1-phase single current measurement applications, where only the live current is measured. in this case, the i2p and i2n pins are left unconnected and the second current channel modulator can be powered down. the voltage channel input for measurement of the line volta ge is also differential and is connected to a tap of a resistive divider of the line voltage. the resistive divider can be set to accommodate any line voltage standard (v mains ) including 100v, 110v, 220v, 230v and 240v. a 3.0 to 4.0mhz low power oscillator generates the sy stem clock for the AS8218 / as8228 ics. the absolute clock frequency may be calibrated on-chip. a low power divider is used to generate a 1hz clock for the on-chip real time clock/calendar (rtc). the supply voltage to the low power oscillator, the low power divider and the rtc may be buffered with an external battery in case of mains power dips or failures, which results in the AS8218 / as8228 ics power supply being interrupted. the lcd driver (lcdd) signals lsd0 ? lsd23 and lbp0 ? lbp3 can be directly connected to a liquid crystal display (lcd), which is used to display the various measured parameters. a total of 80 lcd segments may be driven by the AS8218 ic and 96 lcd segments may be driven by the as8228 ic. the measurement data and display annunciators are fully programmable. the meter system designer should define the annunciators so that the end customer?s specific me ter system requirements are met. a maximum of twelve programmable multi-purpose input/o utput (mpio) pins are available for various meter functions, for example light-emitting diodes (led) to signal energy consumption, energy direction, fault condition, etc. these i/o pins may also be programmed for use as bi-directional communication channels such as an optical interface or an additional universal asynchronous receiver/transmitter (uart2) interface, should it so be required. the AS8218 has 9 x mpio pins, while the as8228 has 12 x mpio pins. a dedicated serial peripheral interface (spi) is also provided for the direct connection to an external eeprom memory with a compatible serial peripheral interface. depending on the meter system requirements, the external eeprom memory capacity may be selected from 1kb up to 32kb, in binary steps. the on-chip 8051 compatible microcontroller performs a ll the required calculations and enables the user to customize the input and output configuration of the me ter. the microcontroller has 24kb of program memory, 1kb data memory, a square root calculation facility and a second uart (uart2) for debugging purposes. a programmable watchdog timer is provided to automatically initiate a system reset when a regular hold-off signal is not detected by the watchdog timer. the watchd og timer is an optional function which is software enabled.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 15 of 123 a dedicated serial universal asynchronous receiver/transmitter (uart1) interface within the system control is provided to communicate with the AS8218 / as8228 ics and perform all the required programming and reading of data, especially during the meter production process. the AS8218 / as8228 ics supply voltages (2 x vddd and vdda) are typically 3.3 volts. these supply voltages should be derived from the v mains with the use of a standard voltage regulated power supply circuit. a typical 3.3 volt power supply circuit is described later. an on-chip power supply monitor (psm) ensures that a reset is generated independently of the supply voltage rise and fall times. monitoring of the v mains is provided to ensure early power-down detection. a reset pin (res_n) is also available for external system reset, which is active low. the res_n pin can be left unconnected if not required. the individual functional elements of the AS8218 / as8228 ics, as well as the relationships between the various functional blocks are shown in the following block diagram. a detailed description of the AS8218 / as8228 ics system and the flexibility available to the kwh meter designer, through the system programmability is also described below: system timing & real time clock energy measurement front end system control 8051 micro- controller lcd driver multi-purpose i/os spi analog front end dsp lbp3 ... 0 sc io11 ... 0 lsd23 ... 0 txd si so s_n rxd i2n i2p i1n i1p vn vp vdd_bat xin xout uart1 wdt res_n figure 2: AS8218 / as8228 block diagram
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 16 of 123 8.1 energy measurement front end (including dsp) the energy measurement front end is made up of the analog front end and the digital signal processing block (dsp), which performs the active energy measur ement calculations for the microcontroller. the analog front end comprises of the three sigma-delta modulators for the sampling of the mains voltage, line current and a second current channel, for the optional measurement of the neutral current. also included in the analog front end is the voltage reference, which provides the temperature stability to the sigma-delta modulators. setting up for the optimum input conditions for the voltage and current channels is also described in this section. the digital signal processing block (dsp) provides the filtering and processing of the output data from the sigma-delta modulators and ensures that the specified measurement accuracy is provided by the AS8218 / as8228. the dsp offers programming flexibility and provid es for fast and efficient meter production calibration procedures. a power supply monitor (psm) is also described in this section. the psm ensures that a reset is generated independently of the rise and fall times of the supply voltage (vdd). analog front end the analog front end comprises of three identical sigma-delta modulators, which convert the differentially connected analog voltage and current inputs into digital signals. the two current inputs are gain adjustable to accommodate both directly connected or galvanically isolated current sensors. the on-chip voltage reference (vref) is the most important contributor to the accuracy of the AS8218 / as8228 ics due to it providing temperature stability to the circuit. considering th at the voltage and current signals are multiplied to derive the energy value, errors introduced prior to multiplication function results in errors being multiplied. thus the introduction of errors into the voltage and the current channel inputs will result in a doubling of the percentage error after multiplication at the energy output. the temperature coefficient of the vref is specified at 30 ppm/k typical. voltage reference specifications parameter symbol min typ max unit notes output voltage v ref 1.217 1.219 1.221 v temperature coefficient tk 30 ppm/k current inputs for energy calculation the AS8218 / as8228 ics have 2 identical mains current inputs, i1p/i1n and i2p/i2n, for measurement of both the live and neutral currents. either of the two current inputs may be selected for calculating the energy value. these two differential current inputs are second order sigma-delta modulators, with each of the inputs being provided with selectable gains of 4, 16 and 20. the selectable gains are provided so that the AS8218 / as8228 ics may be easily adapted for use with either 2 current transformers or alternatively a shunt resistor and a current transformer for current sensing. the AS8218 / as8228 ics may also be used in a conventional single current configuration with either a current transformer or shunt resistor being used for current sensing.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 17 of 123 the current input signal levels may be programmed by means of on-chip programmable gain settings. the required gain setting is selected as follows: current input gain settings gain input voltage comments current inputs i1p, i1n 20 -30mv v i1p 30mv shunt mode; default setting 16 -38mv v i1p 38mv ct mode or shunt mode 4 -150mv v i1p 150mv ct mode current inputs i2p, i2n 20 -30mv v i2p 30mv shunt mode 16 -38mv v i2p 38mv ct mode or shunt mode 4 -150mv v i2p 150mv ct mode; default setting notes: 1) v i1n and v i2n are connected to vssa. 2) refer to the settings register (sreg) in the dsp section for programming of the gain settings. for optimum operating conditions, the in put signal at the maximum current (i max ) condition should be set at 30mvp, when the gain = 20, or 150mvp, when the gain = 4. the default gain, the AS8218 / as8228 ics current input gain settings without any programming required, is gain = 20 for the i1 input and gain = 4 for the i2 input. the value of an ideal shunt resistor, may be calculated as follows: assuming an i max rating of 60a (rms) 84.85a (peak), then a shunt value of 350 would be suitable. = = 354 a 85 . 84 mv 30 r p p shunt thus a standard 300 shunt resistor may be selected. the mains currents are sampled at 3.4956khz, assuming that the recommended crystal oscillator frequency of 3.5795mhz, is used. the current transformer(s) must be terminated with a voltage setting resistor (r vs ) to ensure the optimum voltage input level to the current input(s) of the AS8218 / as8228 ics. the value of r vs is calculated as follows: 2 i v r l ) p ( in vs = where i l = ct rms secondary current at rated conditions (v mains ; i max ) v in(p) = the peak input voltage to the ic at rated conditions (v mains ; i max ). for example, if gain = 4, v in(p) should be set at 150mvpeak. example: a current transformer is specified at 60a/24ma and the gain = 4:
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 18 of 123 ? = = = 3 . 4 42 . 4 2 ma 24 mv 150 2 i v r l ) p ( in vs voltage input for energy calculation the voltage channel input consisting of inputs vp and vn is differential, with vp connected to the tap of a resistor divider circuit of the line voltage and vn connected to vssa. for optimum operating conditions, the input signal at vp should be set at 100mvp for the rated voltage condition. the resistor values for an ideal voltage divider may be calculated as follows: assuming a v mains of 230v (rms) 325v (peak) and r2 = 470 (according to the voltage divider shown below), the value of r1a+r1b may be calculated as follows: v mains r1a+r1b r2 v in = ? = ? = + m 53 . 1 mv 100 mv 100 v 325 470 v ) v v ( 2 r b 1 r a 1 r ) p ( in ) p ( in mains thus r1a = 820k and r1b = 750k resistors may be selected. the mains voltage is also sampled at 3.4956khz, assuming that the recommended crystal oscillator frequency of 3.5795mhz is used. digital signal processing block (dsp) the digital signal processing (dsp) block provides the si gnal processing required to ensure that the specified measured accuracy is performed and that the microcontroller (mcu) is provided with the appropriate data and protocol to perform all the required meter functions. for the description below, please refer to the following block diagram (figure 3). the dsp makes allowance for phase correction of the two current channels (i1 and i2) within the sinc 3 decimation filters in the phase correc tion block. the applicable phase correction setting (pcorr_i1 or pcorr_i2) is selected (sel_i), depending upon which current (i1 or i2) is being used for the power calculation. the equalization filters on the voltage and current chann els which may be by-passed (sel_equ), correct for the attenuation introduced by the decimation filters at the edge of the input frequency band, while the high pass filters, which may also be by-passed (sel_hp), elim inate any dc offsets introduced into the input channels.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 19 of 123 independent calibration of the voltage (cal_v) and current signals (cal_i1 and cal_i2) is done after the voltage and current signals are provided for power calculation. this ensures that calibration of the voltage (sos_v), current channel 1 (sos_i1), current channel 2 (sos_i2) has no influence on the power (np) calibration. the imux (current multiplexer) allows the selection of th e applicable current for power calculation (sel_i), while the vmux (voltage multiplexer) allows the selection of either the mains voltage data, or a constant voltage value, vconst (sel_v). the multiplication of the appropr iately selected voltage and current signals is then performed. after multiplication, the next multiplexer (sel_p) enable s the selection of either instantaneous power or real power, which is filtered through a lo w pass filter, plp. the direction indica tor output (diro) is derived from the output of the power low pass filter (plp). the following multiplexer (creep) allows the select ion of the power signal, or blocks the power signal, depending on the required anti-creep and starting current thresholds, which may be set in the microcontroller. only when constant voltage value (vconst) is selected by the vmux (voltage multiplexer) or when diro=1, it is necessary to derive the absolute power value, for measurement (abs). the first pulse generator (fast pulse gen) produces fa st internal pulses, with the number of pulses being proportional to the measured energy. the multiplexer en ables the selection of the appropriate pulse level (pulselev_i1 or pulselev_i2) depending on the current bei ng used for energy measurement (sel_i). the output of the fast pulse gen is always directly proportional to the led pulse output, generated in the led pulse gen. the led output pulse rate is selectable (mconst). the polarity of the led output pulses is also selectable (ledpol). to ensure that the power data transferred to the microc ontroller (mcu) is identical to that of the led pulses, the power accumulator (p_accu) counts the pulses generated by the fast pulse gen. after a defined number of sampling periods (nsamp), an interrupt is sent to the mcu, for the mcu to collect the accumulated energy data.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 20 of 123 phase correction adc v adc i2 adc i1 equ filter equ filter equ filter hp filter hp filter hp filter x cal_v square accu sos_v x cal_i1 square accu sos_i1 x cal_i2 square accu sos_i2 imux vmux sel_hp sel_equ mux sel_i pcorr_i1 pcorr_i2 sel_i sel_v vconst x mux mux plp <0? abs "0" diro sel_p creep p_accu fast pulse gen mux pulselev_i1 pulselev_i2 sel_i mconst ledpol np nsamp sel_v led pulse gen led registers pd_det alarm pddeton figure 3: afe block diagram
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 21 of 123 phase correction the dsp provides phase correction of the two current channels (i1 and i2) by means of the sinc 3 decimation filters in the phase correction block. on ly one of the phase correction settings (pcorr_i1 or pcorr_i2) is valid at a time, depending on which current (i1 or i2) has been selected for the power calculation (sel_i). the phase correction step size is dependent upon the main oscillator frequency selected (f osc ) and the mains frequency (f mains ). assuming a 3.579545mhz crystal oscillator frequency and 50hz mains frequency, the phase can be corrected in steps of 2.41? or 0.04 degrees, which is equal to one oversampling sample, or one ?unit? in the table below: pcorr phase correction [unit(s)] bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 1 1 1 1 1 1 1 1 255 0 1 1 1 1 1 1 1 0 254 ? 0 0 1 1 1 1 1 1 1 127 0 0 1 1 1 1 1 1 0 126 ? 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 -1 1 1 1 1 1 1 1 1 0 -2 ? 1 1 0 0 0 0 0 0 1 -127 1 1 0 0 0 0 0 0 0 -128 ? 1 0 0 0 0 0 0 0 1 -255 1 0 0 0 0 0 0 0 0 -256 one ?unit? equals a certain phase shift related to the mains frequency: 8 360 360 360 1 / f f f f t t unit osc mains ovs mains mains ovs = = = 8 360 / f f unit # phase osc mains = example: 8 360 1 / f f unit osc mains = 255 units = 255 x 2.41? = 10.26 where f mains is the mains frequency and f osc is the oscillator frequency.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 22 of 123 calculating phase correction factors the measured phase_error in percentage is defined by the following formula [] % 100 ) 60 cos( ) 60 cos( ) shift _ phase 60 cos( error _ phase ? + = while the phase_shift in degrees, is calculated as follows: [ ] ? ? ? ? ? ? ? ? ? ? ? ? ? + = 60 ) 60 cos( 100 % error _ phase 1 arccos shift _ phase shift _ phase correction _ phase ? = the required phase correction factor can be determined fr om error measurements with a power factor (pf) less than 1. assuming that at pf = 1 the meter has been calibrated and the error is approximately 0 for i cal (calibration current), the pf is reduced and the effect of phase differences results in an increased error (?phase_error?). example: the phase_error at pf = 0.5 ( ? = 60) is measured to be 9.2 %. the related phase shift can be calculated using the following formula: [ ] ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = 60 60 cos 100 % error _ phase 1 cos arc shift _ phase where the phase_error is the measured error in percentage and cos is the phase angle. for phase_error = 9.2[%] the phase_shift is -3.0 and the phase correction is 3.0. if f osc = 3.579545mhz and f mains = 50hz, one phase correction unit represents 2.41?, which is 0.04023. thus the phase correction factor must be set to units . . . 57 74 04023 0 0 3 = = 75 units. the pcorr register has to be set to 4bh. equalization filters the equalization filters in the voltage and current channels correct for the attenuation effects introduced by the decimation filters around the frequency band limit. the re sulting transfer curve after the equalization filter has approximately 0db attenuation over the entire frequency band. the equalization filters may be by-passed (sel_equ), if required.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 23 of 123 high-pass filters the high pass filters in the voltage and current channe ls, with corner frequencies of <10hz, correct for dc offsets introduced into the input channels. each of the voltage and current channels has a separate high pass filter in order to avoid any phase shift being introduced between the voltage and the two current channels. the high pass filters may also be by-passed (sel_hp), if so desired. corner frequency: <10hz rms calculations the dsp provides the voltage and current channel data in ?sum-of-squares? format. to calculate rms values from the voltage (sos_v) and current (sos_i1 and sos_i2), the following formula should be applied for the voltage and current respectively: = = nsamp 1 i 2 i rms v nsamp 1 v , where = nsamp 1 i 2 i v is the sos_v value = = nsamp 1 i 2 i rms i nsamp 1 i , where = nsamp 1 i 2 i i is the sos_i value nsamp should be selected in order to achieve coherent sampling as close as possible: e.g. f s = 3.4956khz (f osc = 3.579545mhz) ? nsamp = 3496 should be selected if the mcu has to be interrupted every 1 second. when f mains = 50hz, 70 mains periods are monitored. refer to squareroot block (sqrt) for a detailed descrip tion of the programming sequence of the squareroot input operand.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 24 of 123 calibration of v and i channels the single channel data may be corrected with a 16-bit calibration value. the calibration range is [1 lsb; 2 ? 1 lsb], step size (1 lsb): 3.052 x 10 -5 . calibration register setting value 0000h 0 0001h 0.00003052 (= 1 lsb) ? ? 2000h 0.25 ? ? 4000h 0.5 ? ? 8000h 1.0 ? ? ffffh 1.99996948 (2 ? 1lsb) the v and i channel rms calculation and calibration is described below (v and i channel are identical, thus only the i channel is shown): the ideal values after rms calculations of voltage and current are: rms_v(ideal) = 479(rms) rms_i(ideal) = 292,110(rms) these values assume ideal input conditions with v in = 100mvp at rated conditions and i in = 30mvp (gain = 20) at rated conditions. e.g: i max = 60a 292,110 ? 60a i cal = 10a a 10 685 , 48 6 110 , 292 ) ideal ( i _ rms ? = = due to non-ideal components a different rms value is calculated: rms_i(actual). from this, the required calibration factor is calculated using the following formula: ) actual ( i _ rms ) ideal ( i _ rms i _ cal = the following formula calculates the actual value to be programmed into the calibration registers (cal_v; cal_i1; cal_i2): )) 768 , 32 i _ cal ( round ( hex ) reg ( i _ cal = constant voltage register (vconst) the vconst registers (9334h and 9335h) provide a predefined voltage value that can be used for calculating energy when the v mains is not available.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 25 of 123 the default value of vconst is 2877 (0b3dh) which translates into an equivalent v mains value of 311v. the energy is calculated using vconst and the selected current (i1 or i2) when sel_v in the sreg/select register is set to ?1?. the vconst value may be calculated according to the formula: = 2 v _ rms vconst example: rms_v = 479 ? = 2 479 vconst = 2,128 note: when vconst is used for the calculation of energy, sel_p must be set to ?0?. low pass filter for real power (plp) when the instantaneous power is low pass filtered the resu lt is practically a dc value for the power, which is termed real power. it is generally preferred to use real power to generate pulses for the calibration, as the duration between pulses is more constant (pulse jitter). corner frequency: 18.6hz the low pass filter ensures that the po wer output pulse jitter is minimised. direction indicator (diro) the direction indicator (diro) situated in the status register (bit 4) defines the direction of the measured power. the direction is determined by the phase relationship between the mains voltage and selected mains current (i1 or i2). when bit 4 in the status register is ?0?, the mains voltage and selected mains current are in phase, thus indicating positive energy flow. when bit 4 in the status register is ?1?, the mains voltage and the selected mains current have a phase reversal, indicating negative energy flow. the energy calculation (np) is generated from positive energy, thus when diro = 1, the negative energy is converted to positive energy by the ?abs? block shown in figure 3: afe block diagram. should the meter application require unidirectional energy measurement, the mcu can separately derive both the positive and negative energy values, depending on the status of the diro bit. accumulator for real power (p_accu) to ensure that the power information transferred to the mcu is identical to that of the led pulses, the p_accu counts the pulses generated by fast pulse gen. after ?nsamp? (nyquist) sampling periods an interrupt is sent to the mcu requesting to fetch the new energy information. (i nterrupt line ?ie.0? goes high and the ?data available interrupt? (dai) flag in the sreg/status register is set). th e ?ack? bit in the sreg/status register is also set to 1. if the mcu takes the energy information, it has to reset the ?ack? bit signalling that the energy information (once the voltage channel has been calibrated, 479 is the typical value when v mains = 230v)
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 26 of 123 has been taken. if the ?ack? bit is not reset the p_accu will add the ?old? energy information to the ?new? energy information accumulated in the following cycle. in any event, the mcu must reset the dai flag in order to clear the interrupt. wait for fast pulse increment p_accu np = 0 y n new fast pulse? y np = p_accu + np (old) p_accu = 0 nsamp reached? y ie.0 = 1 dai = 1 ack = 1 y ack = 0? n n note: the above flow chart assumes that the dai flag is always reset in time before the next interrupt is generated. pulse generation two pulse generators are provided to ensure that virtually any led pulse rate output can be programmed for display and calibration purposes. the first pulse generator (fast pulse gen) produces fast internal pulses. these fast pulses are accumulated in the power accumulator (p_accu) for energy data transfer to the mcu. the second pulse generator (led pulse gen) produces th e led output pulses (meter constant) from the fast internal pulses. this type of data interface ensures that the mcu receives exactly the same energy information as is displayed by the led pulses. in case of ?creep?, the power samples to be added will be set to 0. this has the advantage that previously recorded energy is not lost and remains exactly the same. the following flow chart shows the basic flow diagram for pulse generation:
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 27 of 123 wait for next power samples add power sample to accu generate pulse accu> threshold defined by pulse_lev? y n the fast pulse gen output pulse rate always has the same relationship with the led pulse rate defined by mconst. only if led is calibrated to a meter constant di fferent from those provided in the mconst table, will the fast internal pulse rate be different. formula for fast internal pulse rate (pr int ): [] kwh / i mconst rate pulse et arg t 800 , 204 pr int = where mconst is the meter constant. [] ws pr 600 , 3 000 , 1 i 1 int = when 1i is one impulse representing an energy equivalent. active power calibration (pulse_lev) this paragraph describes how the active power measurement within the AS8218 / as8228 ics is calibrated. the parameter pulse_lev is the main parameter which determines the output frequency of the fast pulse gen. this frequency relates to the measured power and is the basis from which the output pulse rate is derived. prior to system calibration, the appropriate value for the parameter pulse_lev must be calculated to produce the required output pulse rate. the calibration exercise must accommodate all non-idealities that are present in the meter system. the pulse_lev is specified such that a typical pulse rate of 204,800i/kwh can be achieved. during energy pulse calibration the correct pulse_lev is determined in order to get the desired pulse rate. the default value for pulse_lev is defined for i max =40a and v mains =230v. default pulse_lev: 570,950 example for pulse_lev calculations: ) default ( lev _ pulse i a 40 v v 230 ) ideal ( lev _ pulse max mains =
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 28 of 123 v mains (v) i max (a) pulse_lev (ideal) notes 230 100 228,380 230 80 285,475 230 60 380,633 230 40 570,950 default setting 230 20 1,141,900 230 10 2,283,800 240 100 218,864 240 80 273,580 240 60 364,774 240 40 547,160 240 20 1,094,321 240 10 2,188,642 pulse_lev(ideal) = 230/v mains x 40/i max x 570,950 comparison calibration method the most common calibration method is the comparison of energy reading of the meter under test against a standard or reference meter. normally, the standard, or reference meter has a considerably higher pulse rate than the meter under calibration. reference meter outp ut pulses are then counted between consecutive led pulses. to facilitate the calibration procedure, a pulse c ounter is provided in the mpio block. in this case, the absolute calibration time and the calibration current are not relevant for the calibration cycle. the basic calibration setup is shown below: reference meter as82xx i pulse counter led io1 pc figure 4: basic setup for comparison calibration method (using io1 as example input) note: an i/o used as push-button input can be used for the input of the reference meter pulses during calibration. the standard or reference meter pulses are counted between two pulses from the meter to be calibrated. ideally the sum of the pulses would exactly be the ratio between standard meter or reference pulse rate and the pulse rate of the meter under test. from the de viation the corrected pulse_lev may be calculated. na ni ) ideal ( lev _ pulse ) corrected ( lev _ pulse = , where ni is the ideal number of pulses and na is the actual number of pulses (pcnt register in mpio).
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 29 of 123 the ideal number of pulses ni is the ratio between the pulse rates, which is always >1. the formula for ni is as follows: ) mconst ( rate pulse led ) ref ( pr ni = , where pr(ref) is the reference meter constant. the pulse_lev (ideal) is calculated using the following formula: ) default ( lev _ pulse i a 40 v v 230 ) ideal ( lev _ pulse max mains = example the reference meter has a pulse rate, which is 10,000 times greater than the pulse rate of the AS8218 / as8228 led output. during a calibration cycle we measure 11,000 pulses between two led pulses. therefore the ideal pulse_lev has to be changed by a factor of 10,000/11,000 = 0.909. led meter constant selection (mconst, 9330h) the led pulses are derived directly from the fast internal pulses (204,800i/kwh). the ?mconst? register in sreg specifies the led pulse rate: msb lsb - - - - mconst[3] mconst[2] mconst[1] mconst[0] bit symbol function 7 - not used 6 - not used 5 - not used 4 - not used bit3 bit2 bit1 bit0 led pulse rate 0 0 0 0 204,800 0 0 0 1 102,400 3 mconst[3] 0 0 1 0 51,200 0 0 1 1 25,600 0 1 0 0 12,800 0 1 0 1 6,400 2 mconst[2] 0 1 1 0 3,200 0 1 1 1 1,600 1 0 0 0 800 1 mconst[1] 1 0 0 1 400 1 0 1 0 200 1 0 1 1 100 0 mconst[0] 1 1 x x 100
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 30 of 123 if the target meter constant is different from one of the selectable (mconst) meter constants defined above: e.g. 1,000i/kwh (target pulse rate) the same formula ) mconst ( rate pulse led ) ref ( pr ni = can be used, but ni is calculated using the target pulse rate: rate pulse et arg t ) ref ( pr ni = (important: select a pulse rate which is close to mconst, for the target pulse rate, so that the pulse_lev stays within reasonable limits.) after this calibration the energy equivale nt of 1 fast pulse (1i) is different! standard: internal pulse rate: 204,800i/klwh [] ws 58 . 17 800 , 204 ws 600 , 3 000 , 1 i 1 = = ? when a special pulse rate is requir ed, the following formula applies: [] ws e etpulserat arg t pulserate led 800 , 204 600 , 3 000 , 1 i 1 = ? example: assuming a pulse rate of 1,000 is required: 1,600 204,800 1,000 204,800 x 1,000/1,600 [ ] ws 13 . 28 600 , 1 / 000 , 1 800 , 204 ws 600 , 3 000 , 1 i 1 = = ? mains current leads/lags mains voltage the i_lead flag in the sreg /status register determines if the mains current leads the mains voltage or lags the mains voltage. the data is provided for reactive power calculation, to establish if the measured power is capacitive or inductive.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 31 of 123 led output timing the pulses on the led output indicate the amount of energy that has been consumed over a certain period of time. each pulse has an equivalent that can be set in the sreg/mconst register exactly. the unit is impulses per kwh (i/kwh). this output may be used for calibration. the polarity of the led pulses may be selected via the ledpol bit in the sreg/select register for either positive or negative going pulses. timing diagram timing parameters parameter symbol min typ max unit notes pulse width t1 80 ms 50% duty cycle is enabled when the led period is less than 160ms. for mconst=0, t1 will be 17.9s. register interface to mcu one register block contains the data for the meter da ta register (mdr) and the settings register (sreg), hence only one interface to the mcu is required. meter data register (mdr) the meter data register is updated after ?nsamp? samples. then an interrupt is issued to the mcu, which may take the energy data and process them further on. when an interrupt is generated the ?ack? bit in the sreg/status register is set. if the mcu takes the data, it has to reset the ?ack? bit. if the ?ack? bit has not been reset by the mcu when a new set of data is ready, the previous np value will be added to the new one. in any case the dai flag in the sreg/status regist er must be reset in order to clear the interrupt.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 32 of 123 the following table shows the data which is available in the mdr: register name address reset value description samptoend[7:0] 9300h ffh samptoend[15:8] 9301h ffh indicates how many samples are left (until nsamp), before the next interrupt is generated. using this information the mcu can determine if it still has time to transfer the mdr data to the mcu memory. np[7:0] 9302h 00h np[15:8] 9303h 00h np[23:16] 9304h 00h np[31:24] 9305h 00h number of fast pulses, equivalent to energy information accumulated during nsamp samples sos_v[7:0] 9306h 00h sos_v[15:8] 9307h 00h sos_v[23:16] 9308h 00h sos_v[31:24] 9309h 00h sos_v[35:32] 930ah 00h sum of squares of voltage channel samples sos_i1[7:0] 930bh 00h sos_i1[15:8] 930ch 00h sos_i1[23:16] 930dh 00h sos_i1[31:24] 930eh 00h sos_i1[39:32] 930fh 00h sos_i1[47:40] 9310h 00h sos_i1[53:48] 9311h 00h sum of squares of current channel 1 samples sos_i2[7:0] 9312h 00h sos_i2[15:8] 9313h 00h sos_i2[23:16] 9314h 00h sos_i2[31:24] 9315h 00h sos_i2[39:32] 9316h 00h sos_i2[47:40] 9317h 00h sos_i2[53:48] 9318h 00h sum of squares of current channel 2 samples notes: 1) mdr is read-only for mcu. (except for ?mcu debug mode?, then you can set the register values as described.) 2) unused addresses will simply be ignored. the following flowchart describes how accumulators and registers work together:
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 33 of 123 accumulate fast pulses (np); accumulate squares (sos) nsamp reached? add p_accu to np-register transfer sos- accus to registers (mdr/sos) clear sos accus and p_accu ack reset by mcu? reset np-register (mdr) n y y n
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 34 of 123 settings register (sreg) the settings register contains data stored by the mcu, which are used, for example, for calibration purposes, but also for general settings like input gain. register name address reset value description pcorr_i1[7:0] 9320h 00h pcorr_i1[8] 9321h 00h sets the phase correction for current channel i1. pcorr_i2[7:0] 9322h 00h pcorr_i2[8] 9323h 00h sets the phase correction for current channel i2. cal_v[7:0] 9324h 00h cal_v[15:8] 9325h 80h calibration factor for voltage channel. only acts on sos_v data. cal_i1[7:0] 9326h 00h cal_i1[15:8] 9327h 80h calibration factor for current channel i1. only acts on sos_i1 data. cal_i2[7:0] 9328h 00h cal_i2[15:8] 9329h 80h calibration factor for current channel i2. only acts on sos_i2 data. pulselev_i1[7:0] 932ah 46h pulselev_i1[15:8] 932bh b6h pulselev_i1[23:16] 932ch 08h pulse_lev for fast pulse genera tion if current channel i1 is selected (sel_i). pulselev_i2[7:0] 932dh 46h pulselev_i2[15:8] 932eh b6h pulselev_i2[23:16] 932fh 08h pulse_lev for fast pulse genera tion if current channel i2 is selected (sel_i). mconst[3:0] 9330h 06h meter constant for led pulse generation - 9331h - not used nsamp[7:0] 9332h ach nsamp[15:8] 9333h 0dh sets number of samples before next update of mdr. vconst[7:0] 9334h 3dh vconst[13:8] 9335h 0bh a predefined voltage value which may be used for energy calculation in the event of v mains not being available. select 9336h 80h select register gains 9337h 03h gain settings register status 9338h 00h status register note: unused addresses will simply be igno red. unspecified bits will also be ignored.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 35 of 123 select register (select, 9336h) msb lsb ledpol - - sel_p sel_i sel_v sel_hp sel_equ bit symbol function 7 ledpol selects polarity of led pulses: 0: negative going pulses 1: positive going pulses (default) 6 - not used 5 - not used 4 sel_p select between instantaneous and real power for pulse generation 0: instantaneous power 1: real power (low-pass filtered instantaneous power) 3 sel_i select current channel for power calculation (fast pulse gen) 0: i1 1: i2 2 sel_v select voltage channel data 0: selects voltage channel analog input 1: selects the predefined constant ?vconst? 1 sel_hp select high-pass filter 0: high-pass 1: no high-pass 0 sel_equ select equalisation filter 0: equalizer 1: no equalizer gain settings register (gains, 9337h) msb lsb - - - - gain_i2[1] gain_i2[0] gain_i1[1] gain_i1[0] bit symbol function 7 - not used 6 - not used 5 - not used 4 - not used bit1 bit0 gain 0 0 4 3 gain_i2[1] 0 1 16 1 0 16 1 1 20 2 gain_i2[0] gain setting for current channel 2 modulator bit1 bit0 gain 0 0 4 1 gain_i1[1] 0 1 16 1 0 16 1 1 20 0 gain_i1[0] gain setting for current channel 1 modulator
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 36 of 123 status register (status, 9338h) msb lsb creep mdm i_lead diro pddeton alarm dai ack bit symbol function 7 creep indicator for creep situation, used as disable signal for led pulse generation 0: no creep 1: creep 6 mdm mcu debug mode flag enables the mdr to be written by the mcu. this is useful for debugging when the programmer wants to know exactly what is received from the dsp block. 0: normal mode 1: debug mode as described later in the data sheet. 5 i_lead indicates if the mains current leads or lags the mains voltage. 0: mains current lags (inductive) 1: mains current leads (capacitive) 4 diro diro indicator, signals when voltage and current are out of phase by 180 0: 0 phase difference 1: 180 phase difference can only be read by mcu. 3 pddeton enables the power-down detector functionality 0: no pd_det functionality 1: pd_det on 2 alarm indicates when the v mains is falling below a predefined threshold. if this happens an interrupt is generated and the alarm flag is set. the interrupt will be reset only when the alarm flag is reset. 0: no alarm 1: alarm that v mains is low 1 dai data available interrupt flag indicates that an interrupt has been generated because new meter data are available. 0: no interrupt 1: interrupt due to new data set only by dsp. resetable only by software (mcu). a clear of ?dai? means that the irq is set back to 0. 0 ack acknowledge bit, indicates if mcu has transferred newly available data to its memory 1: set by dsp, when data are ready on mdr. (not settable by mcu!) 0: reset by mcu, when data have been taken. when ack gets reset the contents of mdr-np is set to zero. the ?p_accu? always adds the contents of mdr-np to the last value just before it transfers new data to the mdr. thus, if ack=0 the mdr-np is reset and nothing is added to the p_accu. if ack has not been cleared the np data is still available and is added to the p_accu. current channel comparison the two current channels can be compared by the microc ontroller (mcu), if the greater of the two currents is required for energy calculation. this is done by comparing the calculated rms values of the two currents. the threshold for changing from i1 to i2 (or visa versa) can also be set in the mcu. creep detection the standards specify that no pulses must be generated when there is no current flow (?creep?). additionally there is a threshold for current when the meter must gener ate pulses in any case (?starting current?). therefore a detection circuit must guarantee that these two situations are under control. the AS8218 / as8228 current channel data are evaluated in the mcu to find out if there is a ?creep? situation. the related signal is used to stop the pulse generation if required.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 37 of 123 mcu debug mode when mdm flag of sreg/status register is set, the d sp block enters the mcu debug mode. here the mdr can be written through the mcu interface. in this mode the dsp block is not allowed to write to the mdr. special functionality: 1) ack set to 0 np is set to 0 (i.e. must be set again by mcu) 2) when ack is not reset by the mcu the np value is doubled, i.e. a shift left is done. note: also in debug mode an interrupt is generated after nsamp samples. power supply monitor (psm) the AS8218 / as8228 ics have an on-chip power supp ly monitor (psm) that ensures a reset is generated independently of the supply voltage (vdd) rise and fall times. a built in hysteresis is provided to accommodate slow changes on the vdd, to ensure clean signal switching. parameter symbol min typ max unit notes threshold positive edge v th,pos 2.6 2.9 v threshold negative edge v th,neg 2.2 2.6 v hysteresis hyst 100 mv table 1: power supply monitor: power-on reset specifications to ensure sufficient time is available to store the meter data in the eeprom during power-down, it is necessary to detect the falling supply voltage as fast as possible. should only the vdd be monitored, an external capacitor in the 3.3v power supply could sustain the vdd supply voltage even after the v mains has begun to fall. for this reason, the AS8218 / as8228 ics allow the monitoring of the v mains to ensure early power-down detection. the power-down detector function (pd_det) is enabled in the sreg/status register. an alarm signal is generated, when the v mains falls below a specified mains voltage threshold, which enables the mcu to react with sufficient time. it is also possib le to calculate energy during power-down detection, taking a constant voltage value for calculation of the energy value. the mains voltage threshold is calculated as follows: 2 ) ideal ( v _ rms 512 v ) alarm ( v mains mains = 2 479 512 230 = = 173.8 vac external system reset (res_n) an external reset pin (res_n) is provided for system rese t. res_n is active low (i.e. logic ?0? will initiate a system reset). a system reset via the res_n pin is or-ed with the main system power-on reset generated by the power supply monitor psm. res_n is internally pulled high. if not used, res_n should be left unconnected.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 38 of 123 system timing and real time clock (rtc) a low power crystal oscillator using a 3.0 to 4.0mhz crystal provides the AS8218 / as8228 system timing. the low power oscillator is internally connected to a low power divider, which provides a 1hz signal to the real time clock, which may be precision trimmed. low power oscillator low power divider rtc register interface 1hz div[19:0] mcu mclk xin xout vdd_bat clk_1hz figure 5: system timing and rtc block diagram low power oscillator (lp_osc) the low power oscillator is connected to an external 3.0 to 4.0mhz crystal. the oscillator can be operated in two modes, namely normal mode or low power mode. the low power mode is operational when the remainder of the circuit is off (not operational). should a suitable external clock signal be preferred, this may be directly connected to the xin pin, which is fed through to output ?mclk?. in this case, xout is left unconnected. parameter symbol min typ max unit notes current consumption, normal mode i osc,norm 20 50 a current consumption, low power mode i osc,bat 7 a vdd_bat = 2vdc @ 25c frequency range f osc 3.0 3.579545 4.0 mhz supply voltage range vdd_bat 2.0 3.3 3.6 v duty cycle duty_cyc 45 55 % low power divider (lp_div, 9130h ? 9132h) the main oscillator output frequency (mclk) is divided down to 1hz for the real time clock (rtc). the option to use alternative crystal frequencies and still derive a 1hz clock signal for the real time clock (rtc), is provided through this internally programmable divider. for power-saving reasons, the fast oscillator clock is firs t divided down by a fixed ratio (divide by 5) and then the programmable divider follows.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 39 of 123 div5 programmable divider mclk clk_1hz div[19:0] parameter symbol min typ max unit notes input frequency range f mclk 3.0 3.579545 4.0 mhz supply voltage range vdd_bat 2.0 3.3 3.6 v division factor n 1,048,575 1) the setting of div[19:0] is located in the rtc registers (addresses: 9132h ? 9130h) note: 1) the division factor n is effective on the frequency mclk/5. it represents the actual division factor minus 1. example: calculate n for oscillator frequency 3,579, 545hz. the frequency after the div5 is 715,909hz. therefore, n must be 715,909 ? 1 = 715,908. (setting n = 1 means a division factor of 2) 2) n = 0 stops the clock. real-time clock (rtc) the rtc can be directly accessed from the mcu via a dedicated interface register. two alarm registers are provided to indicate a certain time instance, such as the start of a new month. in that case an interrupt is sent to the mcu. constant frequency deviations of the crystal that is used can be trimmed to an accuracy of better than +/-1.4ppm. a seconds counter is provided which may be used for certain meter calculations. there is only one interrupt output. the source of the interrupt is indicated in the control/status 2 register. register interface time/ calendar registers alarm registers lp_div setting frequency trim seconds counter mcu lp_div rtc
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 40 of 123 rtc registers register name address reset value notes seconds / vl 9100h 80h minutes 9101h 00h hours 9102h 00h days 9103h 01h day of the week 9104h 00h month / century 9105h 01h years 9106h 00h control / status 1 9110h 10h control / status 2 9111h 00h seconds timer byte 0 9112h 01h seconds timer byte 1 9113h 00h minute alarm 1 9114h 00h hour alarm 1 9115h 00h day alarm 1 9116h 01h month alarm 1 9117h 01h years alarm 1 9118h 00h minute alarm 2 9119h 00h hour alarm 2 911ah 00h day alarm 2 911bh 01h month alarm 2 911ch 01h years alarm 2 911dh 00h divider register byte 0 9130h 84h [7:0] = div [7:0] (lp_div) divider register byte 1 9131h ech [7:0] = div [15:8] (lp_div) divider register byte 2 9132h 0ah [3:0] = div [19:16] (lp_div) frequency trim 9133h 00h notes: 1) if illegal values (i.e. not defined in the following tables , e.g. ?0?, no bcd code, not correct last day of month, not correct leap year) are wr itten to the time/date registers (00h ? 06h), they are corrected to the first valid number (?automatic corr ection?)! then an interrupt is generated and the tsa flag in the control/status 2 register is set. 2) all other registers are not corrected (e.g. alarm info incorrect ? alarm is not met). 3) after power-up of vdd_bat the time/date registers ar e stopped, the wait flag (con trol/status 1) is set. 4) unused addresses will simply be ignored.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 41 of 123 control / status 1 register (9110h) msb lsb - - - wait - - - - bit symbol function 7 - not used 6 - not used 5 - not used 4 wait indicates that rtc is waiting for a start signal. the start signal is wait being reset to 0. wait = 0 ? rtc running normally. (clear by mcu.) wait = 1 ? is set when time/calendar information is c hanged (access to registers 9100h to 9106h). while rtc is waiting for a start signal, 1hz clock is still gated to the mpios. 3 - not used 2 - not used 1 - not used 0 - not used register bit assignment: (unassigned bits in the registers are marked with ?-?. if these bits are read they will return zero value. writing these bits has no effect.) control / status 2 register (9111h) msb lsb tsa - a2f a1f stf aie2 aie1 sie bit symbol function 7 tsa time setting alarm: indicates when an impossible time/date has been set and it has been corrected by the rtc automatically, e.g. 31 st february ? 1 st february. an interrupt will be generated and tsa is set to 1. the interrupt is cleared by setting tsa=0 (done by mcu (software)). 6 - not used 5 a2f set to logic 1 when an alarm 2 occurs and maintains this value until software clears it. indicates the source of the interrupt. cannot be se t by software. when the flag is clea red, also the interrupt is cleared. 4 a1f set to logic 1 when an alarm 1 occurs and maintains this value until software clears it. indicates the source of the interrupt. cannot be se t by software. when the flag is clea red, also the interrupt is cleared. 3 stf set to logic 1 when a seconds timer interrupt occurs and maintains this value until software clears it. indicates the source of the interrupt. cannot be set by software. when the flag is cleared, also the interrupt is cleared. 2 aie2 aie2 = 0; alarm 2 interrupt disabled aie2 = 1; alarm 2 interrupt enabled 1 aie1 aie1 = 0; alarm 1 interrupt disabled aie1 = 1; alarm 1 interrupt enabled 0 sie sie = 0; seconds counter interrupt disabled sie = 1; seconds counter interrupt enabled
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 42 of 123 note: alarm interrupts are only generated on rising clk_1hz edges (using system clock for detection). this means that enabling an alarm after that will not generate an interrupt. seconds / vl register (9100h) msb lsb vl sec.6 sec.5 sec.4 sec.3 sec.2 sec.1 sec.0 bit symbol function 7 vl vl = 0; reliable clock / calendar information guaranteed. vl = 1; clock / calendar information is not guaranteed. this bit is set after power-up of vdd_bat. it can be cleared by software only. 6 sec.6 5 sec.5 4 sec.4 3 sec.3 2 sec.2 1 sec.1 0 sec.0 these bits represent current seconds value encoded in bcd format (values from 0 to 59). minutes register (9101h) msb lsb 0 min.6 min.5 min.4 mi n.3 min.2 min.1 min.0 these bits represent current minute value encoded in bcd format (values from 0 to 59). hours register (9102h) msb lsb 0 0 hour.5 hour.4 hour.3 hour.2 hour.1 hour.0 these bits represent the current hours value encoded in bcd format (values from 0 to 23). days register (9103h) msb lsb 0 0 day.5 day.4 day.3 day.2 day.1 day.0 these bits represent current day value encoded in bcd format (values from 1 to 31). note on leap years: ?00? years in general are no leap years unless the complete year can be divided by 400 (e.g. 2000). since the year 2000 has passed already, this chip will not consider a leap year for ?00? years.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 43 of 123 day of the week register (9104h) msb lsb 0 0 0 0 0 weekd.2 weekd.1 weekd.0 bit symbol function 7 - not used 6 - not used 5 - not used 4 - not used 3 - not used bit2 bit1 bit0 day 0 0 0 sunday 2 weekd.2 0 0 1 monday 0 1 0 tuesday 0 1 1 wednesday 1 weekd.1 1 0 0 thursday 1 0 1 friday 1 1 0 saturday 0 weekd.0 these bits represent the current weekday value. month / century register (9105h) msb lsb c 0 0 month.4 month.3 month.2 month.1 month.0 bit symbol function 7 c century bit. c = 0; indicates the year is 20xx c = 1; indicates the year is 21xx ?xx? indicates the value held in years register. this bit is modified when years register overflows from 99 to 00. 6 - not used 5 - not used bit4 bit3 bit2 bit1 bit0 month 0 0 0 0 1 january 4 month.4 0 0 0 1 0 february 0 0 0 1 1 march 0 0 1 0 0 april 3 month.3 these bits represent the current month value encoded in bcd format. 0 0 1 0 1 may
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 44 of 123 bit symbol function 0 0 1 1 0 june 0 0 1 1 1 july 2 month.2 0 1 0 0 0 august 0 1 0 0 1 september 1 month.1 1 0 0 0 0 october 1 0 0 0 1 november 0 month.0 1 0 0 1 0 december year register (9106h) msb lsb year.7 year.6 year.5 year.4 year.3 year.2 year.1 year.0 these bits represent current year value encoded in bcd format (value from 0 to 99). the alarm 1 or 2 is generated when the programmed time has been reached (seconds = 0!). minute alarm register (1/2) (9114h/9119h) msb lsb 0 mina.6 mina.5 mina.4 mi na.3 mina.2 mina.1 mina.0 these bits represent minute alarm information encoded in bcd format (values from 0 to 59). hour alarm register (1/2) (9115h/911ah) msb lsb 0 0 houra.5 houra.4 houra.3 houra.2 houra.1 houra.0 these bits represent hour alarm information encoded in bcd format (values from 0 to 23). day alarm register (1/2) (9116h/911bh) msb lsb 0 0 daya.5 daya.4 daya.3 daya.2 daya.1 daya.0 these bits represent day alarm information encoded in bcd format (values from 1 to 31). month / century alarm register (1/2) (9117h/911ch) msb lsb c 0 0 mona.4 mona.3 mona.2 mona.1 mona.0 these bits represent current month alarm value encoded in bcd format (value from 1 to 12). please see also the ?month assignments? table above.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 45 of 123 year alarm register (1/2) (9118h/911dh) msb lsb yeara.7 yeara.6 yeara.5 yeara.4 yeara.3 yeara.2 yeara.1 yeara.0 these bits represent the year alarm value encoded in bcd format (value from 0 to 99). setting the time the time can be set by writing to the respective time an d calendar registers. when this is done the clock stops, the wait bit is set and the control waits for the wait bi t to be reset (by the mcu or through system control). when the wait bit is reset the clock gate will be opened and the rtc starts running. alarms when time and one of the alarm registers match (seconds = 0), an interrupt is generated. the source of the interrupt is indicated in the a[1|2]f regist er bits in the control/status 2 register. the alarm generation can be disabled using the aie1/2 bits. when the rest of the chip is off, there is no clock for the mcu interface, hence no alarm will be generated. the mcu interface is reset with the ?res? signal which is coming from the psm, i.e. all status 2 bits are reset to default, which means that after mcu power-up it has to set the appropriate alarms again. (after power-up the mcu has to check what the time is, and has to decide what the next appropriate alarms will be.) seconds timer (9112h, 9113h) the seconds counter block, if enabled (sie bit of cont rol/status 2 register), generates an interrupt every n seconds. ?n? is the number of seconds specified in the seconds timer registers 9112h (byte 0) and 9113h (byte 1). when an interrupt is sent, the flag stf is set. the seconds timer register is not bcd coded. seconds counter start value: 0000h seconds counter count direction: up condition for interrupt generation: seconds counter register value = seconds timer register value note: 0000h in the timer register means that no interrupt must be generated. rtc calibration (clk_1hz) when using the real-time clock (rtc) it is essential that the 1hz signal to the real-time clock is accurate. there are many possible external influences on the crystal o scillator frequency including the absolute crystal frequency itself and the parasitic and oscillator capacitor values. these influences alone can contribute to a significant change in the oscillator frequency. in this case, it is necessary to perform a calibration of the 1hz signal through the ?programmable divider? located in the 'low power divider'. the procedure for trimming the rtc via the 'pr ogrammable divider' is explained below: assuming a crystal frequency of 3.579545 mhz
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 46 of 123 the programmable divider follows a fixed 'divide by 5' divider, thus the default value to the programmable divider is: 3.579545 / 5 = 715909 (default value to programmable divider) therefore: a change of 1hz in this default value is equal to: 1 / 715909 = 1.397 ppm measure the deviation in the clk_1hz frequency output provided by the AS8218 / as8228 ics assuming an error of +690 ppm is measured (faster than real-time) thus +690 / 1.397 = 493.915 = 494 therefore 494 must be added to the default value: 715909 + 494 = 716403 (dec) = 0a ee 73 (hex) divider register byte 2 = 0a divider register byte 1 = ee divider register byte 0 = 73 the rtc is then calibrated to within +/- 1.4 ppm frequency trimming (9133h) a further option for clk_1hz frequency trimming is available. in this case only the 5 lower bits of register ?frequency trim? (9133h) are used as defined in the following table. freq_trim[4:0] correction [ppm] seconds per day 1 seconds per day 2 0 1 1 1 1 87.0 7 8 0 1 1 1 0 81.2 7 7 0 1 1 0 1 75.4 6 7 0 1 1 0 0 69.6 6 6 0 1 0 1 1 63.8 5 6 0 1 0 1 0 58.0 5 5 0 1 0 0 1 52.2 4 5 0 1 0 0 0 46.4 4 4 0 0 1 1 1 40.6 3 4 0 0 1 1 0 34.8 3 3 0 0 1 0 1 29.0 2 3 0 0 1 0 0 23.2 2 2 0 0 0 1 1 17.4 1 2 0 0 0 1 0 11.6 1 1 0 0 0 0 1 5.8 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 -5.8 0 -1 1 1 1 1 0 -11.6 -1 -1 1 1 1 0 1 -17.4 -1 -2 1 1 1 0 0 -23.2 -2 -2 1 1 0 1 1 -29.0 -2 -3
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 47 of 123 freq_trim[4:0] correction [ppm] seconds per day 1 seconds per day 2 1 1 0 1 0 -34.8 -3 -3 1 1 0 0 1 -40.6 -3 -4 1 1 0 0 0 -46.4 -4 -4 1 0 1 1 1 -52.2 -4 -5 1 0 1 1 0 -58.0 -5 -5 1 0 1 0 1 -63.8 -5 -6 1 0 1 0 0 -69.6 -6 -6 1 0 0 1 1 -75.4 -6 -7 1 0 0 1 0 -81.2 -7 -7 1 0 0 0 1 -87.0 -7 -8 1 0 0 0 0 -92.8 -8 -8 the table specifies 2 successive days with (possibly) a different number of seconds that have to be added or subtracted per day. ?day1/day2? are repeated continuously. the rtc is always adjusted at the same time: 00:00 a.m. and 30 seconds . (the 30 seconds is required to avoid conflicts with alarm settings, which are defined to occur at 0 seconds.) subtraction means that the specified number of 1hz pulses is ignored. this has the effect that the clock stands still for the specified number of seconds. example: a crystal has a frequency that is 30ppm higher than specified. therefore the rtc will run faster. thus, the rtc has to correct in the negative direction, by subtracting seconds. value ?11011? (-29.0) will be chosen which means that on day1, 2 seconds are subtracted, then on the next day 3 seconds are subtracted, then 2 seconds again and so on. battery backup operation the AS8218 / as8228 ics contain a real-time clock (rtc) circuit, which must continue to operate even when the mains supply voltage (v mains ) is interrupted. a battery backup facility is provided for this purpose at pin vdd_bat. the low power oscillator (lp_osc), low power divider (lp_ div) and the real time clock (rtc) are all supplied from the vdd_bat pin. the recommended battery backup circuit is shown below. the battery is connected to the vdd_bat pin via one or two diodes. the external vdd is also connected to the vdd_bat pin via a diode, with the battery backup only providing supply to the AS8218 / as8228 ics when the external vdd is interrupted. external vdd vdd_bat +
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 48 of 123 8.2 lcd driver (lcdd) lcd drive voltage level generation vreg lbp0 lbp1 lbp2 lbp3 lsd0 lsd23 selvlcd vdd vss mcu lcdd control data register1 data register2 lcdd_pd figure 6: lcd driver block diagram the on-chip lcd driver (lcdd) is a peripheral block, which interfaces to almost any liquid crystal display (lcd) having a multiplex rate of 4. it generates the drive signals to directly drive multiplexed lcds containing up to four backplanes and up to 24 segments per backplane. the AS8218 has a 20 x 4 lcdd, while the as8228 has a 24 x 4 lcdd. the data registers receive and store the display information, which is to be sent to the display. the lcdd control block decodes the information into the select lines for the single segments using a specific timing. the lcd voltage can be selected to adjust the contrast of the display, as required. the selvlcd[2:0] register bits enable the setting of the lcd contrast by selecting one of the defined lcd voltage levels. the contrast can be improved with a higher voltage, however the contrast is also dependent upon the crystal frequency.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 49 of 123 typical display the lcd above is a typical example of those used in elec tricity meter applications and consists of a number of digits (generally up to 8 digits) including decimal poin ts. typically, annunciators (?kwh?, ?volt?, etc.) are also included to signify the type of data on display. lcd drive (lcd_drive) - lcd drive mode is 1/4duty, 1/3bias. - 4 back planes - 24 segment drives (maximum) all other parameters are listed in the table below: parameter symbol min typ max unit notes lcd frame frequency f lcd 33 39.4 44 hz 1) lcd voltage v lcd 2.3 2.5 2.75 v for selvlcd=?000? v 3 0.95 x v lcd v lcd 1.05 x v lcd v v 2 0.95 x 2/3v lcd 2/3v lcd 1.05 x 2/3v lcd v v 1 0.95 x 1/3v lcd 1/3v lcd 1.05 x 1/3v lcd v lcd segment and back plane drive voltages v 0 vss lcd dc component v dclcd -20 0 20 mv lcd drive impedance r lcd 100 k lcd load on each driver pin c load 300 pf note: 1) these frequencies are derived from the master clock (3mhz; 3.58mhz; 4mhz) using a divider of 90,909.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 50 of 123 lcdd control (lcdd_ctrl) including input and config registers in the control block of the lcd driver there are two registers. each of these registers may contain data to be displayed. with a special bit (921eh, bit 0), it is possi ble to select one of the two register banks for display. each register defines the settings for the different segment and plane select lines. the following table specifies the allocation of the register bits: lsd0 lsd1 lsd2 lsd3 lsd4 lsd5 lsd6 lsd7 lsd8 lsd9 lbp0 reg[0] reg[4] reg[8] reg[12] reg[16] reg[20] reg[24] reg[28] reg[32] reg[36] lbp1 reg[1] reg[5] reg[9] reg[13] reg[17] reg[21] reg[25] reg[29] reg[33] reg[37] lbp2 reg[2] reg[6] reg[10] reg[14] reg[18] reg[22] reg[26] reg[30] reg[34] reg[38] lbp3 reg[3] reg[7] reg[11] reg[15] reg[19] reg[23] reg[27] reg[31] reg[35] reg[39] lsd10 lsd11 lsd12 lsd13 lsd14 lsd15 lsd16 lsd17 lsd18 lsd19 lbp0 reg[40] reg[44] reg[48] reg[52] reg[56] reg[60] reg[64] reg[68] reg[72] reg[76] lbp1 reg[41] reg[45] reg[49] reg[53] reg[57] reg[61] reg[65] reg[69] reg[73] reg[77] lbp2 reg[42] reg[46] reg[50] reg[54] reg[58] reg[62] reg[66] reg[70] reg[74] reg[78] lbp3 reg[43] reg[47] reg[51] reg[55] reg[59] reg[63] reg[67] reg[71] reg[75] reg[79] lsd20 lsd21 lsd22 lsd23 lbp0 reg[80] reg[84] reg[88] reg[92] lbp1 reg[81] reg[85] reg[89] reg[93] lbp2 reg[82] reg[86] reg[90] reg[94] lbp3 reg[83] reg[87] reg[91] reg[95] as8228 only notes: 1) each of the register bits represents one of the segments of the digits or a decimal point or one of the annunciators. 2) reg[x]=0: segment is turned off; reg[x]=1: segment is turned on.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 51 of 123 the complete register is organized in bytes according to following table: register name address reset value description reg1[7:0] 9200h 00h reg1[15:8] 9201h 00h reg1[23:16] 9202h 00h reg1[31:24] 9203h 00h reg1[39:32] 9204h 00h reg1[47:40] 9205h 00h reg1[55:48] 9206h 00h reg1[63:56] 9207h 00h reg1[71:64] 9208h 00h reg1[79:72] 9209h 00h reg1[87:80] 920ah 00h reg1[95:88] 920bh 00h as8228 only reg2[7:0] 9210h 00h reg2[15:8] 9211h 00h reg2[23:16] 9212h 00h reg2[31:24] 9213h 00h reg2[39:32] 9214h 00h reg2[47:40] 9215h 00h reg2[55:48] 9216h 00h reg2[63:56] 9217h 00h reg2[71:64] 9218h 00h reg2[79:72] 9219h 00h reg2[87:80] 921ah 00h reg2[95:88] 921bh 00h as8228 only use_reg 921eh 00h bit 0: selects register to be used. 0: data register 1 1: data register 2 selvlcd[2:0] 921fh 00h select v lcd level. see table in lcd voltage select register. lcdd_pd 9220h 01h bit 0: power-down of the lcdd analog part. 0: display on 1: display off notes: 1) unused registers will simply be ignored. 2) all the registers are write only. read operations always return 0.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 52 of 123 lcd display data select register (use_reg, 921eh) the use_reg register selects either data register 1 or da ta register 2 for display on the lcd. select ?0? for data register 1 and ?1? for data register 2. msb lsb - - - - - - - use_reg lcd voltage select register (selvlcd, 921fh) the lcd voltage select register, selvlcd enables variation of the lcd contrast by selecting on of the 8 pre- set voltage levels. msb lsb - - - - - selvlcd.2 selvlcd.1 selvlcd.0 bit symbol function 7 - not used 6 - not used 5 - not used 4 - not used 3 - not used bit2 bit1 bit0 vlcd 0 0 0 2.5v 2 selvlcd.2 0 0 1 2.5714v 0 1 0 2.6428v 0 1 1 2.7142v 1 selvlcd.1 1 0 0 2.7856v 1 0 1 2.8570v 1 1 0 2.9284v 0 selvlcd.0 these bits set the lcd voltage level for the lcd contract setting. 1 1 1 3.0v lcd power-down (lcdd_pd, 9220h) the lcdd_pd register enables the analog part of the lcdd to be powered-down. select ?0? for lcd display on and ?1? for lcd display off. msb lsb - - - - - - - lcdd_pd
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 53 of 123 drive signals: timing and levels the following graphic shows examples of the timing of the drive signals. clk lcd frame lbp0 lbp1 lbp2 lbp3 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 lbp0 lbp3 lbp2 lbp1 lsd0 lsd5 lsd4 lsd3 lsd2 lsd1 v 3 v 2 v 1 v 0 lsd0 lsd1 v 3 v 2 v 1 v 0 lsd2 v 3 v 2 v 1 v 0 lsd3 v 3 v 2 v 1 v 0 lsd4 v 3 v 2 v 1 v 0 lsd5 v 3 v 2 v 1 v 0 figure 7: lcd multiplexing waveform
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 54 of 123 8.3 programmable multi-purpose i/os (mpio) data registers output multiplexer [11:0] input register [11:0] config register output register [11:0] led pulse counter sel_drv clk_1hz input- multiplexer [11:0] io0 io11 register[x] led txd2 clk_1hz sel1_io[x] sel0_io[x] out_io[x] en_io0 out_io0 in_io0 en_io sel_pupd mcu sel_in out_mux sel_refp [11:0] uart2 rxd2 txd2 figure 8: mpio block diagram a total of 9 bidirectional multi-purpose i/o pins (mpio) are provided with the AS8218 and 12 bidirectional multi- purpose i/o pins with the as8228, which may be used for a variety of purposes. all the i/os can be freely programmed as inputs or outputs, with the option of either a pull-up or pull-down resistor. the drive strength of the individual i/o pins may also be programmed. on start-up all the i/o pins are disabled. furthermore, a pulse counter is available, which can be used for calibration purposes (?comparison calibration method?: between two led pulses the pulses from a reference meter with much higher pulse rate are counted. the result is used to calcul ate the calibration factor.). mpio registers all the mpio registers are listed in the table below. th e individual register functions are then described in detail. register name address reset value notes config make_irq0 9500h 00h make_irq1 9501h 00h out_mux0 9502h 00h out_mux1 9503h 00h
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 55 of 123 register name address reset value notes out_mux2 9504h 00h set_en0 9505h 00h set_en1 9506h 00h sel_drv0 9507h 00h sel_drv1 9508h 00h sel_pupd0 9509h 00h sel_pupd1 950ah 00h sel_in_rxd2 950bh 04h sel_in_refp 950ch 03h input in0 950dh 00h in1 950eh 00h output out0 950fh 00h out1 9510h 00h out2 9511h 00h out3 9512h 00h out4 9513h 00h out5 9514h 00h out6 9515h 00h out7 9516h 00h out8 9517h 00h out9 9518h 00h out10 9519h 00h out11 951ah 00h as8228 only pulse counter pcnt0 951bh 00h pcnt1 951ch 00h pcnt2 951dh 00h status status0 951eh 00h status1 951fh 00h note: unused addresses are ignored.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 56 of 123 make_irq0/make_irq1 (9500h/9501h) the make_irq registers specify if an interrupt should be generated after the related i/o input has changed. the i/o pin, which caused the interrupt, will be in dicated in the status0/status1 flag registers. iox: 0: no interrupt on signal change 1: generate an interrupt on signal change make_irq0 msb lsb io7 io6 io5 io4 io3 io2 io1 io0 make_irq1 msb lsb 0 0 0 0 io11 io10 io9 io8 as8228 only out_mux0/out_mux1/out_mux2 (9502h/9503h/9504h) the out_mux registers specify the source signal for each of the i/o outputs. every 2 bits are used as select signals for the 4-way output multiplexer of the designated i/o. out_mux0 msb lsb io3: sel1 io3: sel0 io2: sel1 io2: sel0 io1: sel1 io1: sel0 io0: sel1 io0: sel0 out_mux1 msb lsb io7: sel1 io7: sel0 io6: sel1 io6: sel0 io5: sel1 io5: sel0 io4: sel1 io4: sel0 out_mux2 msb lsb io11: sel1 io11: sel0 io10: sel1 io10: sel0 io9: sel1 io9: sel0 io8: sel1 io8: sel0 as8228 only the following table shows the settings for the output signal options: sel1 sel0 output signal notes 0 0 register[x] 0 1 led 80ms pulse width 1 0 txd2 1 1 clk_1hz
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 57 of 123 set_en0/set_en1 (9505h/9506h) the set_en registers set the en_io signal of the related i/ o pin. the en_io enables the tri-state output buffer so that the i/o pins operate as outputs. iox: 0: disable output (i/o used as input) 1: enable output set_en0 msb lsb io7 io6 io5 io4 io3 io2 io1 io0 set_en1 msb lsb 0 0 0 0 io11 io10 io9 io8 as8228 only sel_drv0/sel_drv1 (9507h/9508h) the sel_drv registers select the current drive strength for all the i/os that have been selected as outputs: iox: 0: 4ma 1: 8ma sel_drv0 msb lsb io7 io6 io5 io4 io3 io2 io1 io0 sel_drv1 msb lsb 0 0 0 0 io11 io10 io9 io8 as8228 only sel_pupd0/sel_pupd1 (9509h/950ah) the sel_pupd registers select either a pull-up or pull-down resistor for each of the i/o pins: iox: 0: pull-down 1: pull-up sel_pupd0 msb lsb io7 io6 io5 io4 io3 io2 io1 io0 sel_pupd1 msb lsb 0 0 0 0 io11 io10 io9 io8 as8228 only
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 58 of 123 sel_in_rxd2 (950bh) the sel_in_rxd2 register selects which i/o input is used for the special input signal ?rxd2? (uart2 receive input). any one of the i/os from io0 to io11 may be selected for this purpose. the select bits are defined in the following table: msb lsb 0 0 0 0 sel3 sel2 sel1 sel0 msb lsb input 0 0 0 0 0 0 0 0 io0 0 0 0 0 0 0 0 1 io1 0 0 0 0 0 0 1 0 io2 0 0 0 0 0 0 1 1 io3 0 0 0 0 0 1 0 0 io4 0 0 0 0 0 1 0 1 io5 0 0 0 0 0 1 1 0 io6 0 0 0 0 0 1 1 1 io7 0 0 0 0 1 0 0 0 io8 0 0 0 0 1 0 0 1 io9 0 0 0 0 1 0 1 0 io10 0 0 0 0 1 0 1 1 io11 as8228 only sel_in_refp (950ch) the sel_in_refp register selects which i/o input is to be used for reference pulses. any one of the i/os from io0 to io11 may be selected for this purpose. the select bits are defined in the following table: msb lsb 0 0 0 0 sel3 sel2 sel1 sel0 msb lsb input 0 0 0 0 0 0 0 0 io0 0 0 0 0 0 0 0 1 io1 0 0 0 0 0 0 1 0 io2 0 0 0 0 0 0 1 1 io3 0 0 0 0 0 1 0 0 io4 0 0 0 0 0 1 0 1 io5 0 0 0 0 0 1 1 0 io6
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 59 of 123 msb lsb input 0 0 0 0 0 1 1 1 io7 0 0 0 0 1 0 0 0 io8 0 0 0 0 1 0 0 1 io9 0 0 0 0 1 0 1 0 io10 0 0 0 0 1 0 1 1 io11 as8228 only in0/in1 (950dh/950eh) the in registers (input registers) store the input da ta from the i/o pins. these registers are continuously updated by the ?mclk? (main clock). in0 msb lsb io7 io6 io5 io4 io3 io2 io1 io0 in1 msb lsb 0 0 0 0 io11 io10 io9 io8 as8228 only out0 ? out11 (950fh ? 951ah) the out registers (output registers) contain the out put data to be sent to the i/o pins (through the multiplexers). out0 msb lsb 0 0 0 0 0 0 0 io0 out1 msb lsb 0 0 0 0 0 0 0 io1 out2 msb lsb 0 0 0 0 0 0 0 io2 out3 msb lsb 0 0 0 0 0 0 0 io3
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 60 of 123 out4 msb lsb 0 0 0 0 0 0 0 io4 out5 msb lsb 0 0 0 0 0 0 0 io5 out6 msb lsb 0 0 0 0 0 0 0 io6 out7 msb lsb 0 0 0 0 0 0 0 io7 out8 msb lsb 0 0 0 0 0 0 0 io8 out9 msb lsb 0 0 0 0 0 0 0 io9 as8228 only out10 msb lsb 0 0 0 0 0 0 0 io10 as8228 only out11 msb lsb 0 0 0 0 0 0 0 io11 as8228 only pcnt0/pcnt1/pcnt2 (951bh/951ch/951dh) the pcnt registers (pulse counter regi sters) contain the result of the pu lse counting for calibration purposes. pcnt0 msb lsb b7 b6 b5 b4 b3 b2 b1 b0
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 61 of 123 pcnt1 msb lsb b15 b14 b13 b12 b11 b10 b9 b8 pcnt2 msb lsb b23 b22 b21 b20 b19 b18 b17 b16 the maximum reference pulse frequency is defined below: parameter symbol min typ max unit notes reference pulse frequency f refp 120 khz status0/status1 (951eh/951fh) the status registers contain the irq flag register bi ts for each of the i/os, the count register bit which signals when a pulse counting should be started and the cint flag bit which indicates when pulse counting has been completed. the irq flag registers are cleared by software only (mcu), but they cannot be set by software. the count register bit can be set and reset by software (mcu). the count register bit is cleared, when the pulse counter is finished and an interrupt has been generated. status0 msb lsb io7 io6 io5 io4 io3 io2 io1 io0 status1 msb lsb count cint 0 0 io11 io10 io9 io8 as8228 only notes: 1) iox: 0: no change on input x 1: input x has changed 2) when an interrupt on an io change has been generated, the signal irq is reset after the related flag has been cleared. 3) cint is a flag, which indicates that the pulse counting has finished. when cint is cleared, the irq is cleared. pulse counter a synchronous pulse counter is used. it is started after the count bit has been set. the first led pulse is used for synchronisation. the second led pulse starts countin g the reference pulses from the specified i/o input.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 62 of 123 timing: count led gate refp counted refp cint notes: 1) the count signal is synchronized with ?led?. 2) count is reset and cint is set using clk and checking for falling edge on gate. 3) the pcnt register is only updated when counting is finished. example: select io3 as the pulse reference input. meter is 220v mains ; i max = 20a meter constant: 1,600imp/kwh reference meter constant: 16 million imp/kwh register settings: mpio set_en0 (9505h): io3 bit = 0 (output disabled) sel_in_refp (950ch): 02h dsp mconst (9330h): 07h (ideal) pulse_lev (932ch ? 932ah) = a 20 a 40 v 220 v 230 950 , 570 = 1,193,804 ? 12374ch ? 932ah: 4ch 932bh: 37h 932ch: 12h procedure: status1 (951fh): 80h starts pulse counting. when pulse counting is completed cint bit in status1 = 1. the status of the cint bit in status1 may be checked to confirm that the pulse counting is complete. alternatively, the time between 2 pulses may be calculated to determine the count cycle time (the first pulse is used for synchronization and the second pulse starts the count cycle). following the pulse counting cycle, the number of pulses counted can be read from pcnt0/pcnt1/pcnt2 (951bh/951ch/951dh).
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 63 of 123 the ideal number of pulses counted assuming the meter is perfectly calibrated would be: 000 10 600 1 000 000 16 , , , , ni = = assuming that we count 11,000 pulses, the (ideal) pulse_lev must be changed by the factor: 10,000/11,000 = 0.909 the new pulse_lev = 1,193,804 x 0.909 = 1,085,168 ? 108ef0h ? 932ah: f0h 932bh: 8eh 932ch: 10h
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 64 of 123 8.4 serial peripheral interface (spi) the serial peripheral interface (spi) represents a synchronous, bit serial 4-wire interface for full-duplex data transfer. it?s primarily used here to communicate with an external eeprom memory, which must fulfil the requirements described below. the eeprom is selectable in size from 1kbyte to 32kbyte in binary steps. the spi always operates in master mode, whereas the eeprom works in slave mode. the bootloader controls the spi during system start up. after that it is available to the mcu for free programming. spi signals name type description si input serial input from slave device so output serial output to slave sc output clock output to slave device s_n output chip select output to slave device (low active) spi master eeprom s_n si so sc eep_s_n eep_wp_n eep_hold_n eep_so eep_si eep_sc AS8218/ as8228 3.3v figure 9: typical spi connection to an eeprom many eeproms provide a hold_n (hold protocol) pin and a wp_n pin (write protect), which must be held ?1?, otherwise the operation is blocked. during startup phase, the bootloader takes control over the spi and generates the read out sequence automatically. key features - standard 4 wire synchronous serial interface (si, so, sc, s_n) - master mode operation only - 8-bit word length (variable transmit/receive word optional) - shift clock sc high when idle - msb is always transmitted first - four selectable clocking schemes (clock idle state / clock phase) - selectable spi clock rate divider (from mcu_clk/2 to mcu_clk/65536) - three maskable interrupts (transmission complete, overrun, collision)
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 65 of 123 each protocol starts by putting s_n to low level and ends by putting s_n to high again. if s_n goes high before the normal end of the protocol, the current protocol is te rminated, the internal spi state control logic is reset. the so line state is x (don?t care). when operating (s_n = 0), the data is shifted out on the falling edge of sc and incoming data is sampled on the rising edge of sc. s_n (out) sc (out) so (out) t s_n_setup 18 7 6 5 4 3 215 4 3 28 7 6 1/f sc =t sc t byte_to_byte t s_n_hold do7 do6 do5 do4 do3 do2 do1 do0 do7 do6 do5 do4 do3 do2 do1 do0 x x shift out data at so with falling edge of sc si (in) di7 di6 di5 di4 di3 di2 di1 di0 di7 di6 di5 di4 di3 di2 di1 di0 x x sample input data si on rising edge of sc transfer of 1 st data byte transfer of 2 nd data byte figure 10: spi timing diagram note: so is shifted out on the falling edge of sc and si is sampled on the rising edge (clock scheme: cpha=1, cidle=1). for mcu_clk = 4 mhz (max) parameter description mcu_clk cycles min units t s_n_setup time between s_n going low and first sc falling edge 36 9 s t s_n_hold time between last sc rising edge and s_n going high 6 1.5 s t byte_to_byte time between two data bytes (lsb last to msb next) 12 3 s t sc sc serial clock period (= 1/f sc ) 4 1 s t sc_low sc serial clock minimum low time 2 0.5 s t sc_high sc serial clock minimum high time 2 0.5 s spi registers register name address description sspcon 9400h control register sspclkdiv 9401h clock divider register sspstat 9402h status register sspbuf 9403h data register
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 66 of 123 control register (sspcon, 9400h) the control register is used for enabling the spi-interrupts and to control the chip select of the spi. msb lsb ietr ieov ieco iecs cso - auto - bit symbol function 7 ietr transmit interrupt enable issued after data register has be en serially loaded with new data (slave mode) or if data has been shifted out after writ e access (master mode) 0: disable 1: enable 6 ieov overrun interrupt enable issued if itra still set and new data seri ally arrived 0: disable 1: enable 5 ieco write collision interrupt enable issued if data register is written during transmission 0: disable 1: enable 4 iecs chip select interrupt enable issued if chip-select pin is activated during master/slave mode 0: disable 1: enable 3 cso chip select output state in master mode if auto = 0 inverted state of output signal s_n 0: s_n = ?1? 1: s_n = ?0? (active) 2 - not used 1 auto 1: automatically activates the s_n (= ?0?) after data has been written to the data register and deactivates s_n (= ?1?) after transfer completed 0: s_n depends on the cso bit ( manual s_n setting) 0 - not used recommended programming for sspcon with no interrupts enabled: mode sspcon s_n auto mode 02h manual s_n=1 (inactive) 00h manual s_n=0 (active) 08h
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 67 of 123 clock divider register (sspclkdiv, 9401h) the clock divider register contains control bits to confi gure the clock-divider, to set-up the serial-clock sc, to enable the spi and to select master or slave mode. msb lsb enbl cidle cpha m/s clkdiv.3 clkdiv.2 clkdiv.1 clkdiv.0 bit symbol function 7 enbl spi enable. enables the spi interface 1: enable 0: disable cidle bit6 cpha bit5 sc idle data shifted out on sc input sampled on sc 0 0 0 falling rising 0 1 0 rising falling 6 cidle serial clock sc idle state 1: sc idles high 0: sc idles low 1 0 1 rising falling 1 1 1 falling rising 5 cpha serial clock sc phase data is samples and shifted out according to cidle/cpha note: the cidle/cpha set at 1 1 is used internally by most standard available eeproms 4 m/s master/slave mode 1: master mode, must be ?1? 0: slave mode (stops spi operation), there is no slave mode available bit3 bit2 bit1 bit0 sc-rate 0 0 0 0 1 : 2 0 0 0 1 1 : 4 0 0 1 0 1 : 8 3 clkdiv.3 0 0 1 1 1 : 16 0 1 0 0 1 : 32 0 1 0 1 1 : 64 0 1 1 0 1 : 128 2 clkdiv.2 0 1 1 1 1 : 256 1 0 0 0 1 : 512 1 0 0 1 1 : 1,024 1 0 1 0 1 : 2,048 1 clkdiv.1 1 0 1 1 1 : 4,096 1 1 0 0 1 : 8,192 1 1 0 1 1 : 16,384 1 1 1 0 1 : 32,768 0 clkdiv.0 clock divider exponent in master mode, spi output clock sc is mcu_clk / 2 clkdiv+1 1 1 1 1 1 : 65,536 the spi output clock sc, which is derived from the mcu clock (mcu_clk) may be divided down as shown in the table above.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 68 of 123 it is important to note, that the mcu_clk may also be divided down as described under mcuclkdiv register (?mcu_clk?). therefore the spi output clock sc is also dependent on the programming of the mcu_clk frequency. recommended programming for 3.579545mhz mcu clock rate, spi enabled, sc clock phase = ?11?, master: value sc clock rate 1.74mhz f0h 0.895mhz f1h 0.447mhz f2h status register (sspstat, 9402h) msb lsb itra iovr icol - csi - - - bit symbol function 7 itra 1 transmission complete interrupt issued. issued after ne w data word is available in data-register (slave configuration), or if data-register has been shift ed out after write access (master configuration) 6 iovr 1 overrun interrupt issued. issued if itra is still se t from previous transmission and new data arrives (master and slave configuration) 5 icol 1 write-collision interrupt issued. issued if data-register is written during receive (slave configuration) or transmit (master configuration) 4 - not used 3 csi always ?0?, has no effect 2 - not used 1 - not used 0 - not used note: 1) flag-bits change state independent of the state of the corresponding interrupt-enable bit of the control register.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 69 of 123 the spi interrupt status is captured in the sspstat register. each interrupt status bit can be masked by the sspcon register, which is or-ed to a single spi interrupt request signal (spi_irq). ie.espi (=ie.3) or itra iovr icol ietr, ieov, ieco spi_irq sspstat sspcon ie mcu register figure 11: block diagram data register (sspbuf, 9403h) the data-register is an 8-bits wide shift-register with parallel load input and parallel output. it is written and read by the mcu in normal operation and by the bootloader during startup phase. 7 6 5 4 3 2 1 0 bit parallel spi_datain from mcu/bootloader parallel out spi_dataout to mcu/bootloader serial in si serial out so
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 70 of 123 8.5 external eeprom requirements an external eeprom with spi bus serial interface is used for non-volatile program and data storage. the spi master block that communicates with the eeprom is specified above. this section explains the requirement for serial eeproms. it shows the most important figures and tables as a reference. for the details please turn to the data sheet of your specifically applied eeprom. the following minimum requirements must be fulfilled: pins there must be at least the typical spi pins like serial data input (eep_si), serial data output (eep_so) serial clock input (eep_sc), chip select input (eep_s_n) clock rate the applicable clock rate pin eep_sc must be 1mhz to allow correct bootloading for maximum mcu_clk = 4mhz. status register must look like this: don?t care for AS8218 / as8228 bootloader/sct bit 0 must be the wip bit, indicating that a write operat ion is in progress. only this bit is polled during the eeprom upload, means programming of the eeprom. the status register can be accessed via the rdsr instruction. data protection the write protection block size is given in the table below: status register bits bp1 bp0 protected block array addresses protected example only 0 0 none none 0 1 upper quarter 6000h ? 7fffh 1 0 upper half 4000h ? 7fffh 1 1 whole memory 0000h ? 7fffh note: the array addresses must be referenced from the data sheet of the specific eeprom used.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 71 of 123 bp1, bp0 allows the selection of one out of 4 protection schemes. in order to protect against inadvertent programming the user can see these bits. please note that the protected range of eeprom cannot be overwritten via an sct command there anymore. reprogramming must be done with a dedicated program then. instruction set there must be at least 4 instructions with the coding s hown in the table for they are deployed by the bootloader to download the user program and by the sct unit to upload the user program to the eeprom. instruction name instruction format description read 03h read data from memory starting with selected address write 02h write data to memory beginning at selected address. most eeproms allow page writing of pages 16, 32, 64 or even more bytes for faster device programming. before every page write operation a wren instructio n must be applied ? see also bootloading and uploading sequence for details. wren 06h write enable eeprom, enables write operation rdsr 05h read eeprom status register, bi t 0 = wip required for AS8218 / as8228 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: - cpol = 0, cpha = 0 - cpol = 1, cpha = 1 (it is recommended to set cpol = 1, cpha = 1 in your program: the build-in bootloader uses this setting as well.) for these two modes, input data is latched in on the rising edge of serial clock (sc), and output data is issued on the falling edge of serial clock (sc). the recommended mode is shown in figure 12. the clock polarity sc is ?1? when the bus master is in stand-by mode and not transferring data (idle state): - sc remains at 1 for (cpol = 1, cpha = 1) figure 12: spi modes recommended eep_sc(in) eep_si(in) eep_so(out ) 1 1
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 72 of 123 address roll over when the highest address on the eeprom is reached, e.g. 7fffh for a 32kb device, then the address counter must roll over to 0000h. unused upper address bits unused upper address bits must be ignored in any case. e.g. an 8kb device has a maximum address of 1fffh must interpret 7fffh as 1fffh, ignoring the higher bits. program length the program length is stored at the 2 topmost locations, means for a 32kb eeprom at 7ffeh and 7fffh. it is possible to use any smaller eeprom as long as it is guaranteed that a) the upper unused address bits are ignored b) an address roll over is performed after the highest address timing of AS8218 / as8228 boot sequence detailed spi timing generated by the AS8218 / as8228 ? see spi section. figure 13: timing diagram the diagram shows the sequence applied to the eeprom after device reset. on the eep_si line you see: 03h (read) 7fh (address high) feh (address low) on the eep_so line you see the answer of the eeprom. in this case the first two values 22h and 00h are forming the program length, means 0022h = 34 bytes are to be fetched and stored to the program memory (p_ram). the next values are 02h, 00h, 16h (ljmp 001 6h) representing the first bytes of the program code. 03h feh 00h 00h 75h 22h 02h 16h 90h 7fh
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 73 of 123 example pin list pin name type functionality description eep_s_n input chip select, active low when this input signal is high, the device is deselected and serial data output (so) is at high impedance. unless an internal write cycle is in progress, the device will be in the standby mode. driving chip select (s_n) low enables the device, placing it in the active power mode. eep_so output serial data output this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (sc). eep_si input serial data input this input signal is used to transfer data serially into the device. it receives instructions, addresses and the data to be written. values are latched on the rising edge of serial clock (sc). eep_sc input serial clock this input signal provides the timing of the serial interface. instructions, addresses or data present at serial data input (si) are latched on the rising edge of serial clock (sc). da ta on serial data output (so) changes after the falling edge of serial clock (sc). eep_wp_n 1) input write protect, active low the main purpose of this input signal is to freeze the size of the area of memory that is protected against write instructions (as specified by the values in the bp1 and bp0 bits of the status register). this pin must be driven either high or low and must be stable during all write operations. eep_hold_n 1) input hold, active low the hold (hold_n) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (so) is high impedance, and serial data input (si) and serial clock (sc) are don?t care. to start the hold condition, the device must be selected, with chip select (s_n) driven low. eep_vcc supply positive supply voltage eep_vss supply negative supply voltage note: 1) no write protect (eep_wp_n) and hold (eep_hold_n) pins are available on the AS8218 / as8228 ics. these pins must be tied ?high? directly at the eeprom device. instructions timings write enable (wren) figure 14: write enable (wren) sequence eep_s_n(in) eep_sc(in) eep_si(in) eep_so(out )
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 74 of 123 read status register (rdsr) figure 15: read status register (rdsr) sequence read from memory array (read) figure 16: read from memory array (read) sequence write to memory array (write) figure 17: byte write (write) sequence eep_s_n(in) eep_sc(in) eep_si(in) eep_so(out ) eep_s_n(in) eep_sc(in) eep_si(in) eep_so(out ) eep_s_n(in) eep_sc(in) eep_si(in) eep_so(out )
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 75 of 123 figure 18: page write (write) sequence uploading programs using the sct in order to allow direct access to the eeprom via a standard rs232 interface the AS8218 / as8228 ics provide a uart to spi protocol converter. the two system control (sct) instructions involved are called read_p (f3h) and write_p (f4h), which may be used to upload user software or user data to the eeprom. doing a read_p allows the verification of the written data, respectively. example write eeprom via uart to spi converter: uart write_p address block length data1 data2 wait prog.time ackn rxd f4 1f f0 00 02 21 42 - - txd - - - - - - - - fa spi wren write rdsr eep_si 06 02 1f f0 00 00 21 42 05 - eep_so x x x x x x x x loop until wip=0 ?xxxx xxx0? - eep_s_n(in) eep_sc(in) eep_si(in) eep_s_n(in) eep_sc(in) eep_si(in)
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 76 of 123 figure 19: timing diagram after having finished the write sequence, the eeprom goes to programming state for about 5ms to 10ms (depending on the eeprom type). the AS8218 / as8228 read out the status register in a loop until bit0 = wip (write in progress) goes low. then the uart transmits the acknowledge instruction fah. example read eeprom locations 1ff0 and 1ff1: on eep_so the expected 21h and 42h are transmitted. uart read_p address block length data1 data2 rxd f3 1f f0 00 02 - - txd - - - - - 21 42 spi read eep_si 03 1f f0 00 00 00 00 eep_so x x x x x 21 42 x......... don?t care - ......... no activity, idle = ?1? figure 20: timing diagram s......... stop bit f4 1f f0 00 02 21 42 06 03 42 21 f0 1f write_p address data1 block length data2 read status register 00 f3 1f f0 02 21 42 read_p address data1 block length data2 1 1 0 0 1 1 1 1 s 1 1 1 1 1 0 0 0 s 0 0 0 0 0 1 1 1 1 s (03) (f0) (1f) (42) (21) 0 0 0 0 0 0 0 0 s 0 1 0 0 0 0 0 0 s 1 0 0 0 0 1 0 0 s 0 1 0 0 0 0 1 0
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 77 of 123 8.6 8051 microcontroller (mcu) the mcu is a derivative of the well-known 8051 microcontroller. the mcu block consists of an 8051 compatible microprocessor core, program memory (p_ram), data memory (x_ram), squareroot calculation unit and two uarts for debugging and communication purposes. the special function registers (sfr) section enfolds the standard blocks like the 16 bit timer (timer 0), 128 bytes of internal data memory (i_ram) and a serial interface (uart1). furthermore, a squareroot block and a second serial interface (uart2) are also provided. timer 1, port 0 to 3 and the uart are not implemented ex actly the same as in the original 8051. instead, the bus extension (port 0, 2 on single chip 8051) provides access to on-chip periphery, which comprises a serial peripheral interface (spi), a real time clock (rtc), nine general purpose i/os (mpio), the lcd driver (lcdd), the dsp block that interfaces to the analog front end and system control registers (sct). the mcu block is configured as von neumann architecture with the pr ogram memory (p_ram) section staring from 0000h and the data memory (x_ram) and periphery section starting from 8000h up to ffffh. all 64kb of memory can be accessed with both, the movc instruction (for program fetches and data read) and the movx instruction (for data read/store). the interrupt controller enfolds 7 internal interrupt sources, for having all necessary peripherals already on chip. mcu internal interrupt sources interrupt control cpu clock divider 128 bytes i_ram timer 0 24kb p_ram sqrt uart2 1kb x_ram uart1 mclk rxd txd boot load lcdd rtc sct mpio dsp i/os spi afe serial eeprom lc display rxd2 txd2 figure 21: mcu block diagram legend cpu ................8051 compatible microcontroller core i_ram .............128 bytes static ram, range 00h to 7fh of 8051 x_ram............1024 bytes static ram, (extended) memory for data storage p_ram............24kb static ram, primarily fo r program storage, maybe used also for data timer 0............16 bit timer (due to 8051 standard) uart1 ............serial interface rs232 (due to 80 51 standard) with extended baudrate generator
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 78 of 123 uart2 ............serial interface rs23 2 with extended baudrate generator sqrt ..............square root calculation out of 5 bytes (40 bits) input, 2.5 bytes (20 bits) output spi..................serial peripheral interface, used to access an external eeprom bootload..........downloads program data after reset, combined with the spi lcdd ..............lcd driver block rtc ................real time clock, time/data may be set via uart1 (sct) mpio...............multi-purpose i/o pins, configurable inputs and outputs dsp .............. ..digital signal processing unit interfaces to analog front end (afe) afe.................analog front end, includes amplifiers and a to d converters sct ................system control unit, combined with uart1 used for debugging/programming of the device key features - 8051 compatible 8 bit oriented microcontroller core - 128 bytes of internal data memory (i_ram) - 24kb program memory (p_ram) - 1kb data memory (x_ram) - von neumann architecture, shared program and data memory - cycle optimized compared to standard 8051, some instructions are executed in a single clock cycle - 128 bytes of sfr range - standard sfrs: timer 0, uart1 (with 16 baudrate reg.) - specific sfrs: uart2 (with 16 bit baudrate reg.), sqrt block - fully compatible 8051 instruction set including da, mul and div instruction - 7 internal interrupt sources - ports p0, p1, p2, p3 are not implemented - p0 and p2 are accessible as registers - register pcon is not implemented - no idle mode via pcon - automatic bootload of application program after power-on reset - 6 clock cycles per instruction (12 cycles in standard 8051) - 1 data pointer dptr
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 79 of 123 instruction set the instruction set is fully compatible to the 8051 standard. this allows the use of commonly available software development tools for a51 assembler, c-compiler and code simulators. the instructions marked with the note 2) are cycle optimised and execute in a single cycle compared to two cycles in standard 8051 controllers. hex code mnemonic operands b/c 1) hex code mnemonic operands b/c 1) 00 nop 1/1 30 jnb bit addr, code addr 3/2 01 ajmp code addr 2/2 31 acall code addr 2/2 02 ljmp code addr 3/2 32 reti 1/2 03 rr a 1/1 33 rlc a 1/1 04 inc a 1/1 34 addc a, #data 2/1 05 inc dir 2/1 35 addc a, dir 2/1 06 inc @r0 1/1 36 addc a, @r0 1/1 07 inc @r1 1/1 37 addc a, @r1 1/1 08 inc r0 1/1 38 addc a, r0 1/1 09 inc r1 1/1 39 addc a, r1 1/1 0a inc r2 1/1 3a addc a, r2 1/1 0b inc r3 1/1 3b addc a, r3 1/1 0c inc r4 1/1 3c addc a, r4 1/1 0d inc r5 1/1 3d addc a, r5 1/1 0e inc r6 1/1 3e addc a, r6 1/1 0f inc r7 1/1 3f addc a, r7 1/1 10 jbc bit addr, code 3/2 40 jc code addr 2/2 11 acall code addr 2/2 41 ajmp code addr 2/2 12 lcall code addr 3/2 42 orl dir, a 2/1 13 rrc a 1/1 43 orl dir, #data 3/2 14 dec a 1/1 44 orl a, #data 2/1 15 dec dir 2/1 45 orl a, dir 2/1 16 dec @r0 1/1 46 orl a, @r0 1/1 17 dec @r1 1/1 47 orl a, @r1 1/1 18 dec r0 1/1 48 orl a, r0 1/1 19 dec r1 1/1 49 orl a, r1 1/1 1a dec r2 1/1 4a orl a, r2 1/1 1b dec r3 1/1 4b orl a, r3 1/1 1c dec r4 1/1 4c orl a, r4 1/1 1d dec r5 1/1 4d orl a, r5 1/1 1e dec r6 1/1 4e orl a, r6 1/1 1f dec r7 1/1 4f orl a, r7 1/1 20 jb bit addr, code 3/2 50 jnc code addr 2/2 21 ajmp code addr 2/2 51 acall code addr 2/2 22 ret 1/2 52 anl dir, a 2/1 23 rl a 1/1 53 anl dir, #data 3/2 24 add a, #data 1/1 54 anl a, #data 2/1 25 add a, dir 2/1 55 anl a, dir 2/1 26 add a, @r0 2/1 56 anl a, @r0 1/1 27 add a, @r1 1/1 57 anl a, @r1 1/1 28 add a, r0 1/1 58 anl a, r0 1/1 29 add a, r1 1/1 59 anl a, r1 1/1 2a add a, r2 1/1 5a anl a, r2 1/1 2b add a, r3 1/1 5b anl a, r3 1/1 2c add a, r4 1/1 5c anl a, r4 1/1 2d add a, r5 1/1 5d anl a, r5 1/1 2e add a, r6 1/1 5e anl a, r6 1/1 2f add a, r7 1/1 5f anl a, r7 1/1
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 80 of 123 hex code mnemonic operands b/c 1) hex code mnemonic operands b/c 1) 60 jz code addr 2/2 90 mov dptr, #data 3/2 61 ajmp code addr 2/2 91 acall code addr 2/2 62 xrl dir, a 2/1 92 mov bit addr, c 2/1 2) 63 xrl dir, #data 3/2 93 movc a, @a+dptr 2/2 64 xrl a, #data 2/1 94 subb a, #data 2/1 65 xrl a, dir 2/1 95 subb a, dir 2/1 66 xrl a, @r0 1/1 96 subb a, @r0 1/1 67 xrl a, @r1 1/1 97 subb a, @r1 1/1 68 xrl a, r0 1/1 98 subb a, r0 1/1 69 xrl a, r1 1/1 99 subb a, r1 1/1 6a xrl a, r2 1/1 9a subb a, r2 1/1 6b xrl a, r3 1/1 9b subb a, r3 1/1 6c xrl a, r4 1/1 9c subb a, r4 1/1 6d xrl a, r5 1/1 9d subb a, r5 1/1 6e xrl a, r6 1/1 9e subb a, r6 1/1 6f xrl a, r7 1/1 9f subb a, r7 1/1 70 jnz code addr 2/2 a0 orl c, /bit addr 2/1 2) 71 acall code addr 2/2 a1 ajmp code addr 2/2 72 orl c, bit addr 2/1 2) a2 mov c, bit addr 2/1 73 jmp @a+dptr 1/2 a3 inc dptr 1/1 2) 74 mov a, #data 2/1 a4 mul ab 1/4 75 mov dir, #data 2/1 a5 n/a (reserved) 1/1 76 mov @r0, #data 1/1 a6 mov @r0, dir 2/1 2) 77 mov @r1, #data 1/1 a7 mov @r1, dir 2/1 2) 78 mov r0, #data 1/1 a8 mov r0, dir 2/1 2) 79 mov r1, #data 1/1 a9 mov r1, dir 2/1 2) 7a mov r2, #data 1/1 aa mov r2, dir 2/1 2) 7b mov r3, #data 1/1 ab mov r3, dir 2/1 2) 7c mov r4, #data 1/1 ac mov r4, dir 2/1 2) 7d mov r5, #data 1/1 ad mov r5, dir 2/1 2) 7e mov r6, #data 1/1 ae mov r6, dir 2/1 2) 7f mov r7, #data 1/1 af mov r7, dir 2/1 2) 80 sjmp code addr 2/2 b0 anl c, /bit addr 2/1 2) 81 ajmp code addr 2/2 b1 acall code addr 2/2 82 anl c, bit addr 2/1 2) b2 cpl bit addr 2/1 83 movc a, @a+pc 2/2 b3 cpl c 1/1 84 div ab 1/4 b4 cjne a, #data, code 3/2 85 mov dir, dir 3/2 b5 cjne a, dir, code 3/2 86 mov dir, @r0 2/1 2) b6 cjne @r0, #data, code 3/2 87 mov dir, @r1 2/1 2) b7 cjne @r1, #data, code 3/2 88 mov dir, r0 2/1 2) b8 cjne r0, #data, code 3/2 89 mov dir, r1 2/1 2) b9 cjne r1, #data, code 3/2 8a mov dir, r2 2/1 2) ba cjne r2, #data, code 3/2 8b mov dir, r3 2/1 2) bb cjne r3, #data, code 3/2 8c mov dir, r4 2/1 2) bc cjne r4, #data, code 3/2 8d mov dir, r5 2/1 2) bd cjne r5, #data, code 3/2 8e mov dir, r6 2/1 2) be cjne r6, #data, code 3/2 8f mov dir, r7 2/1 2) bf cjne r7, #data, code 3/2
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 81 of 123 hex code mnemonic operands b/c 1) hex code mnemonic operands b/c 1) c0 push dir 2/1 2) e0 movx a, @dptr 2/2 c1 ajmp code addr 2/2 e1 ajmp code addr 2/2 c2 clr bit addr 2/1 e2 movx a, @r0 2/2 c3 clr c 1/1 e3 movx a, @r1 2/2 c4 swap a 1/1 e4 clr a 1/1 c5 xch a, dir 2/1 e5 mov a, dir 2/1 c6 xch a, @r0 1/1 e6 mov a, @r0 1/1 c7 xch a, @r1 1/1 e7 mov a, @r1 1/1 c8 xch a, r0 1/1 e8 mov a, r0 1/1 c9 xch a, r1 1/1 e9 mov a, r1 1/1 ca xch a, r2 1/1 ea mov a, r2 1/1 cb xch a, r3 1/1 eb mov a, r3 1/1 cc xch a, r4 1/1 ec mov a, r4 1/1 cd xch a, r5 1/1 ed mov a, r5 1/1 ce xch a, r6 1/1 ee mov a, r6 1/1 cf xch a, r7 1/1 ef mov a, r7 1/1 d0 pop dir 2/1 2) f0 movx @dptr, a 1/2 d1 acall code addr 2/2 f1 acall code addr 2/2 d2 setb bit addr 2/1 f2 movx @r0, a 1/2 d3 setb c 1/1 f3 movx @r1, a 1/2 d4 da a 1/1 f4 cpl a 1/1 d5 djnz dir, code addr 3/2 f5 mov dir, a 2/1 d6 xchd a, @r0 1/1 f6 mov @r0, a 1/1 d7 xchd a, @r1 1/1 f7 mov @r1, a 1/1 d8 djnz r0, code addr 2/2 f8 mov r0, a 1/1 d9 djnz r1, code addr 2/2 f9 mov r1, a 1/1 da djnz r2, code addr 2/2 fa mov r2, a 1/1 db djnz r3, code addr 2/2 fb mov r3, a 1/1 dc djnz r4, code addr 2/2 fc mov r4, a 1/1 dd djnz r5, code addr 2/2 fd mov r5, a 1/1 de djnz r6, code addr 2/2 fe mov r6, a 1/1 df djnz r7, code addr 2/2 ff mov r7, a 1/1 dir .............. variable in i_ram code addr ... address in code memory data ........... immediate data bit addr....... address of a bit in bit-addressable i_ram notes: 1) ?b? = number of bytes ?c? = number of cycles 2) optimised execution in a single cycle; normally 2 cycles addressing modes the mcu comprises all standard 8051 addressing modes. for completeness they are listed here. there are five types. in two byte instructions the de stination is specified first, then the source. mode examples notes register addressing mov a, r0 register r0 in i_ram one out of 4 banks selected direct addressing mov r0, a moves contents of a to r0
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 82 of 123 mode examples notes register indirect addressing mov @r0, a movx @dptr, a moves contents of a to location addressed by r0, or by dptr immediate addressing mov r0, #data moves immediate #data to r0 index addressing movc a, @a+dptr movc a, @a+pc moves contents of location addressed by a+dptr, or a+pc to a. for reading lookup tables, applies to program memory only interrupt controller the 8051 core provides 7 interrupt sources: 2 of them are the same as in the standard 8051, the others are tied to specific internal sources. each interrupt causes the program to jump to the corresponding interrupt vector if the interrupt is enabled in the interrupt enable register (ie). the interrupt priority can be controlled via the interrupt priority register (ip) in order to override the predefined priority, starting with ip.0 as highest. for further information on the interrupt sources refer to the appropriate chapters. interrupt enable register (ie) each of the interrupt sources can be individually enabled or disabled by setting the corresponding bit in the ie register. this register contains a global enable bit ea . by clearing this bit all interrupts can be disabled at once. ie msb lsb ea ertc es2 es espi eiox et0 edsp enable bit = 0 disables the interrupt enable bit = 1 enables the interrupt interrupt priority register (ip) ip msb lsb - prtc ps2 ps pspi piox pt0 pdsp priority bit = 1 assigns high priority priority bit = 0 assigns low priority interrupt source rtc uart2 uart1 spi mpio timer 0 dsp interrupt vector 0033h 002bh 0023h 001bh 0013h 000bh 0003h
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 83 of 123 symbol position function priority ea ie.7 1 disables all interrupt when 0. if ea = 1 each interrupt is individually enabled due to its enable bit. ertc ie.6 rtc real time clock, interrupt enable bit lowest es2 ie.5 uart2, serial port, interrupt enable bit es ie.4 1 uart1, serial port, interrupt enable bit espi ie.3 spi serial port, interrupt enable bit eiox ie.2 mpio external pin, interrupt enable bit et0 ie.1 1 timer 0, interrupt enable bit edsp ie.0 dsp data available highest note: 1) standard 8051 bits
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 84 of 123 interrupt priorities each interrupt source can be individually assigned one of two priority levels. a low pr iority interrupt can always be interrupted by a higher-priority interrupt, but not by another low priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. if the corresponding ip bit is set then this interrupt is serviced first if another interrupt request occurs at the same time where the ip bit is zero. interrupt on the same priority level are serviced due to the internal polling sequence starting with dsp highest down to rtc lowest. symbol position function source flags ip.7 - prtc ip.6 real time clock, priority bit tsa, stf, a1f, a2f ps2 ip.5 uart2 serial port, priority bit ri, ti ps ip.4 1 uart1 serial port, priority bit ri, ti pspi ip.3 spi serial port, priority bit itra piox ip.2 mpio external pin, priority bit in status 0 / status 1 pt0 ip.1 1 timer 0, priority bit tf0 pdsp ip.0 dsp priority bit dai, alarm note: 1) standard 8051 bits pspi ip = 1 ip = 0 high priority interrupt low priority interrupt ie register ip register priority level high priority level low polling sequence global enable individual enables source ps piox pto pdsp ps2 prtc figure 22: interrupt control system
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 85 of 123 memory maps the mcu51 is configured as von neumann architecture merging program and data range into one 64kb address space. this space is completely accessible via movx and partly accessible via movc (0000h ? 5fffh). besides, there is the typical 8051 structure wi th 128 bytes of internal memory (i_ram) and the special function registers (sfrs) also in a 128 byte address space. sfrs direct addressing ffh 80h 128 bytes i_ram 7fh 00h internal memory unused ffffh c000h idata /ps memory special function registers unused a000h unused 1kb x_ram 24kb p_ram 5fffh 0000h 9000h 8000h 6000h unused 9fffh mpio lcdd dsp spi rtc sct 9500h 9400h 9300h 9200h 9100h 9000h direct addressing register indirect addressing register addressing movx a, @dptr (4 banks) movx @dptr, a bit addressing movc a, @a+pc movc a, @a+dptr } only for 0000h ? 5fffh movx @ri, a movxa, @ri with ri {r0, r1}, p2 represents upper address bits program memory (p_ram) the p_ram shares address and output data lines with the x_ram. 24kb out of 64kb addressable memory are used: 0000h ? 5fffh for program storage.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 86 of 123 data memory (x_ram) and block interfaces the following table shows the start (and stop) addresses for the x_ram and the block interfaces. these locations can be accessed with the movx instruction. start address stop address contents 8000h 83ffh x_ram 9000h 9002h sct registers 9100h 9133h rtc registers 9180h 9181h wdt registers 9200h 9220h lcdd registers 9300h 9338h dsp registers 9400h 9403h spi registers 9500h 951fh mpio registers detailed memory map: address contents address contents address contents address contents 8000h ? 83ffh x_ram 9000h - 9001h enable signals 9002h mcuclkdiv[2:0] 9003h - sct 9100h seconds/vl 9101h minutes 9102h hours 9103h days 9104h weekdays 9105h months/cent. 9106h years 9107h - 9108h - 9109h - 910ah - 910bh - 910ch - 910dh - 910eh - 910fh - 9110h cont./status1 9111h cont./status2 9112h sec.tim.b 0 9113h sec.tim.b 1 9114h min.alarm 1 9115h hour alarm 1 9116h day alarm 1 9117h mon. alarm 1 9118h yearsalarm 1 9119h min.alarm 2 911ah hour alarm 2 911bh day alarm 2 911ch mon. alarm 2 911dh yearsalarm 2 911eh - 911fh - 9130h divreg b 0 9131h divreg b 1 9132h divreg b 2 9133h freq. trim rtc 9180h wdte 9181h wdtclk[1:0] wdt 9200h reg1[7:0] 9201h reg1[15:8] 9202h reg1[23:16] 9203h reg1[31:24] 9204h reg1[39:32] 9205h reg1[47:40] 9206h reg1[55:48] 9207h reg1[63:56] 9208h reg1[71:64] 9209h reg1[79:72] 920ah reg1[87:80] 920bh reg1[95:88] 920ch - 920dh - 920eh - 920fh - 9210h reg2[7:0] 9211h reg2[15:8] 9212h reg2[23:16] 9213h reg2[31:24] 9214h reg2[39:32] 9215h reg2[47:40] 9216h reg2[55:48] 9217h reg2[63:56] 9218h reg2[71:64] 9219h reg2[79:72] 921ah reg2[87:80] 921bh reg2[95:88] 921ch - 921dh - 921eh use_reg 921fh selvlcd[2:0] 9220h lcdd_pd lcdd
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 87 of 123 address contents address contents address contents address contents 9300h samptoend [7:0] 9301h samptoend [15:8] 9302h np[7:0] 9303h np[15:8] 9304h np[23:16] 9305h np[31:24] 9306h sos_v[7:0] 9307h sos_v[15:8] 9308h sos_v[23:16] 9309h sos_v[31:24] 930ah sos_v[35:32] 930bh sos_i1[7:0] 930ch sos_i1[15:8] 930dh sos_i1[23:16] 930eh sos_i1[31:24] 930fh sos_i1[39:32] 9310h sos_i1[47:40] 9311h sos_i1[53:48] 9312h sos_i2[7:0] 9313h sos_i2[15:8] 9314h sos_i2[23:16] 9315h sos_i2[31:24] 9316h sos_i2[39:32] 9317h sos_i2[47:40] 9318h sos_i2[53:48] 9319h - 931ah - 931bh - 931ch - 931dh - 931eh - 931fh - 9320h pcorr_i1[7:0] 9321h pcorr_i1[8] 9322h pcorr_i2[7:0] 9323h pcorr_i2[8] 9324h cal_v[7:0] 9325h cal_v[15:8] 9326h cal_i1[7:0] 9327h cal_i1[15:8] 9328h cal_i2[7:0] 9329h cal_i2[15:8] 932ah pulselev_i1 0 932bh pulselev_i1 1 932ch pulselev_i1 2 932dh pulselev_i2 0 932eh pulselev_i2 1 932fh pulselev_i2 2 9330h mconst[3:0] 9331h - 9332h nsamp[7:0] 9333h nsamp[15:8] 9334h vconst[7:0] 9335h vconst[13:8] 9336h select 9337h gains 9338h status 9339h - 933ah - 933bh - dsp 9400h sspcon 9401h sspclkdiv 9402h sspstat 9403h sspbuf spi 9500h make_irq0 9501h make_irq1 9502h out_mux0 9503h out_mux1 9504h out_mux2 9505h set_en0 9506h set_en1 9507h sel_drv0 9508h sel_drv1 9509h sel_pupd0 950ah sel_pupd1 950bh sel_in 950ch sel_refp 950dh in0 950eh in1 950fh out0 9510h out1 9511h out2 9512h out3 9513h out4 9514h out5 9515h out6 9516h out7 9517h out8 9518h out9 9519h out10 951ah out11 951bh pcnt0 951ch pcnt1 951dh pcnt2 951eh status0 951fh status1 mpio note: shaded addresses available with the as8228 only.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 88 of 123 internal memory (i_ram) 128 bytes of i_ram are provided, which can be accessed via 3 address modes. - all memory 00h to 7fh is directly addressable. - 00h to 1fh are register addressable in four banks. bank switching is done in psw (program status word). - 20h to 2fh are bit addressable, which means that each bit of these registers can be set/cleared separately. i_ram locations 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh 70h 71h 72h 73h 74h 75h 76h 77h 68h 69h 6ah 6bh 6ch 6dh 6eh 6fh 60h 61h 62h 63h 64h 65h 66h 67h 58h 59h 5ah 5bh 5ch 5dh 5eh 5fh 50h 51h 52h 53h 54h 55h 56h 57h 48h 49h 4ah 4bh 4ch 4dh 4eh 4fh 40h 41h 42h 43h 44h 45h 46h 47h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh 30h 31h 32h 33h 34h 35h 36h 37h 28h bit 40-47 29h bit 48-4f 2ah bit 50-57 2bh bit 58-5f 2ch bit 60-67 2dh bit 68-6f 2eh bit 70-77 2fh bit 78-7f 20h bit 00-07 21h bit 08-0f 22h bit 10-17 23h bit 18-1f 24h bit 20-27 25h bit 28-2f 26h bit 30-37 27h bit 38-3f 18h r0 19h r1 1ah r2 1bh r3 1ch r4 1dh r5 1eh r6 1fh r7 10h r0 11h r1 12h r2 13h r3 14h r4 15h r5 16h r6 17h r7 08h r0 09h r1 0ah r2 0bh r3 0ch r4 0dh r5 0eh r6 0fh r7 00h r0 01h r1 02h r2 03h r3 04h r4 05h r5 06h r6 07h r7 the first 4 x 8 bytes of the internal memory can be ad dressed via instructions using the register addressing mode (register bank 0, 1, 2, 3). the following 16 bytes (16 x 8 = 128 bits, address 20h to 2fh) can be addressed via instructions using the direct-bit addressing mode. the address space from 30h to 7fh is accessible via the direct addressing mode only. gray-shaded r0 and r1 registers can be used for register indirect addressing. special function registers (sfr) the following table shows the locations of the special function registers. sfrs in bold style are original 8051 registers. sfrs in italic style are additional registers specific to the AS8218 / as8228 ics.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 89 of 123 sfr locations f8h f9h fah fbh fch fdh feh ffh f0h b f1h f2h f3h f4h f5h f6h f7h e8h sqrtin0 e9h sqrtin1 eah sqrtin2 ebh sqrtin3 ech sqrtin4 edh sqrtout0 eeh sqrtout1 efh sqrtout2 e0h acc e1h e2h e3h e4h e5h e6h e7h d8h d9h dah dbh dch ddh deh dfh d0h psw d1h d2h d3h d4h d5h d6h d7h c8h c9h cah cbh cch cdh ceh cfh c0h scon2 c1h sbuf2 c2h sbaudl2 c3h sbaudh2 c4h c5h c6h c7h b8h ip b9h bah bbh bch bdh beh bfh b0h sovr2 b1h b2h b3h b4h b5h b6h b7h a8h ie a9h aah abh ach adh aeh afh a0h p2 a1h a2h a3h a4h a5h a6h a7h 98h scon 99h sbuf 9ah sbaudl 9bh sbaudh 9ch 9dh 9eh 9fh 90h sovr 91h 92h 93h 94h 95h 96h 97h 88h tcon 89h tmod 8ah tl0 8bh 8ch th0 8dh 8eh t0pre 8fh 80h p0 81h sp 82h dpl 83h dph 84h 85h 86h 87h 128 bytes of sfr address space is available using the direct addressing mode. the following table describes the use of the register bytes: symbol register name address notes standard registers acc accumulator e0h b b register f0h psw program status word d0h sp stack pointer 81h dptr data pointer 2 bytes dpl low byte 82h dph high byte 83h p0 port 0 80h p2 port 2 a0h ip interrupt priority control b8h ie interrupt enable control a8h tmod timer mode control 89h tcon timer control 88h th0 timer 0 high byte 8ch tl0 timer 0 low byte 8ah scon serial control (uart1) 98h sbuf serial data buffer (uart1) 99h custom registers t0pre timer 0 prescaler 8eh sovr serial overflow (uart1) 90h sbaudl serial baudrate low (uart1) 9ah sbaudh serial baudrate high (uart1) 9bh scon2 uart2 control c0h sbuf2 uart2 serial data buffer c1h
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 90 of 123 symbol register name address notes sbaudl2 uart2 baudrate low c2h sbaudh2 uart2 baudrate high c3h sovr2 uart2 overflow b0h sqrtin0 square root input [7:0] e8h wr iting to this location triggers the squareroot calculation sqrtin1 square root input [15:8] e9h sqrtin2 square root input [23:16] eah sqrtin3 square root input [31:24] ebh sqrtin4 square root input [39:32] ech sqrtout0 square root output [7:0] edh sqrtout1 square root output [15:8] eeh sqrtout2 square root output [23:16] efh notes: 1) ports p1 and p3 do not exist. 2) timer 1 is not implemented (and the related sfrs). 3) ports p0 and p2 are not connected to pins. p0 and p2 can be used as a register in general. however, p2 can be used for x_ram access, when ?@ri? is used in the register indirect addressing mode (with ri being either r0 or r1). in that case p2 will form the higher byte of the x_ram address. 4) ie/ip: the sources for the interrupts ar e defined in interrupt controller section. 5) tcon, tmod, th0, tlo described in section timer 0. 6) scon, sbuf, sbaudl, sbaudh, sovr are related to uart1 described in the uart section. 7) scon2, sbuf2, sbaudl2, sbaudh2, sovr2 are related to uart2 described in the uart2 section.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 91 of 123 squareroot block (sqrt) this sqrt block calculates the square root of a 40 bit input value (mapped to 5 eight bit input registers). the output is a 20 bit number which is mapped to 3 eight bit output registers. the calculation starts immediately after the least significant byte has been written (= address e8h). for the square root calculation the gypsi- or radicand algorithm is used, which produces one bit per clock cycle. thus after 20 cycles the result is available in the sqrtout[2:0] registers. note: the interrupt signal is not connected to the interrupt controller of the mcu, because the result is available after a defined period of 4 machine cycles. the programmer has to take care for the correct timing. for instance, 4 nop instructions must be inserted before reading out the result. when writing sqrtin[39:36] are don?t care. when reading sqrtout[23:20] those bits equal zero. data registers sfr-address name description e8h sqrtin0 input value[7:0] e9h sqrtin1 input value[15:8] eah sqrtin2 input value[23:16] ebh sqrtin3 input value[31:24] ech sqrtin4 input value[39:32] edh sqrtout0 output value[7:0] eeh sqrtout1 output value[15:8] efh sqrtout2 output value[19:16] mov sqrt4, #... 4 3 2 mov sqrt0, #... mov a, sqrt2, ... 0 4 cyc square root calculation start calculation result available figure 23: timing diagram during the time of calculation data must not be overri dden. as soon as the register sqrt0 is written, the calculation sequence is retriggered and the result is calcul ated from the latest contents of the 5 input registers.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 92 of 123 boot loader (bootload) after power-up the boot loader loads the program data from the eeprom down to the on-chip p_ram (note: parameters or settings stored in the eeprom will not be loaded by bootload, this will be handled by the mcu program.). only when this is finished the chip can start with its normal operation. (it is also possible to trigger a bootload during normal operation, when for example a new program has been written to the eeprom (debugging!)) the bootload block can be seen as a direct interface between spi and p_ram. bootload mcu spi b o o t m u x p_ram b o o t n o r m a l boot_sel eeprom AS8218/as8228 figure 24: bootload block diagram eeprom data organisation 1. program data are stored beginning at address 0000h. 2. program data size must not be bigger than 24,576 bytes (0000h ? 6000h-1), due to p_ram size. 3. the length of the program must be stored at the two topmost bytes. the program length is given as number of bytes, expressed as hexadecimal. the lower byte goes to the lower address, the higher byte to the higher address. for a 32kb eeprom this means: 7ffeh: length, lower byte, 7fffh: length, higher byte. 4. if the length value is bigger than 6000h, the bootloader will just stop after 6000h program data bytes. 5. if the length value is 0000h or ffffh, no program load will be done. 6. it is also possible to use smaller sized eeproms, the length value still has to be stored in the two topmost bytes. the bootloader will always read from the two topmost 32kb addresses, which then are assumed to ?rolled down? to the existing two topmost addresses. this adds flexibility to the system configuration. 7. meter data and system parameters (selects etc.) are stored in the remaining memory space. the allocation of memory space is totally up to the mcu program. 8. please note that the program data is not protected against overwrites from the mcu program. 9. case of no program: in case there is no program stored in the eeprom (b oot loader detects all 0s or all 1s at the program length address) the boot loader writes ?sjmp $? (h ex code: 80feh) to address 0 of the p_ram. this guarantees the well defined behavior after first power on.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 93 of 123 watchdog timer (wdt) a watchdog timer is provided on-chip to automatically initiate a system reset if a ?hold-off? signal is not detected within a predefined timeout period, by the watchdog. the watchdog timer consists of a programmable timer driven either by the mclk (main oscillator output frequency), or the mcu clock (microcontroller unit cloc k). the watchdog timer timeout period is dependent upon the programming of the wdtclk register. when the watchdog times out, a reset signal is generated which is or-ed with the main system reset. thus a watchdog timer reset is identical to a power on reset. if the watchdog timer function is required, the watchdog is enabled by setting the wdte register lsb (bit 0). as soon as this bit is enabled, the program must periodically access the wdtclk register (either read or write) to prevent the watchdog timer from timeout and thus resetting the device. register name address reset value description wdte 9180h xxxx.xxx0b enables or disables the watchdog timer function 0: watchdog disabled 1: watchdog enabled wdtclk[1:0] 9181h xxxx.xxx00b a read or write access clears the watchdog timer. writing bits [1:0] selects the clock source. x ........don?t care watchdog timer enable register (wdte) msb lsb - - - - - - - wdte0 bit symbol function 7 - not used 6 - not used 5 - not used 4 - not used 3 - not used 2 - not used 1 - not used 0 wdte0 disables and enables the watchdog timer function 0: watchdog disabled 1: watchdog enabled the watchdog timer has a selectable counter length of 18 bit, 20 bit or 22 bit for the mclk and 18 bits for the mcu_clk. it should be noted that while the mclk has a fixed frequency, depending on the crystal frequency, the mcu clock is programmable, being divisible by 1 to 128, in binary steps (see mcuclkdiv register (?mcu_clk?)). the timeout periods below assume t he mclk = 3.579545mhz (fixed crystal frequency).
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 94 of 123 watchdog timer clock register (wdtclk) msb lsb - - - - - - wdtclk1 wdtclk0 bit symbol function 7 - not used 6 - not used 5 - not used 4 - not used 3 - not used 2 - not used clock source timeout period (ms) bit1 bit0 mclk ? default after reset 73.2 0 0 1 wdtclk1 mclk 292.8 0 1 mclk 1171.2 1 0 mcu_clk (div=1) 73.2 0 wdtclk0 watchdog timeout period (mclk = 3.579545mhz) mcuclk (div=128) 9300 1 1 2 nd uart (uart2) an additional serial interface, uart2 is provided for debugging purposes. uart2 is accessible via two of the multi-purpose i/os (mpio). the uart2 is functionally identical to uart1. the sfr addresses are defined as follows: register name address description scon2 c0h serial port control register ? see serial interface ? uart1 for details. sbuf2 c1h serial port buffer register ? see serial interface ? uart1 for details. sbaudl2 c2h baudrate reload register ? low address sbaudh2 c3h baudrate reload register ? high address sovr2 b0h ?serial overflow? register, which indicates when data in sbuf has been overwritten before being read. the flag is the lsb with the other 7 bits all being 0. below is an example how to configure the ports io7 and io6 as uart2s txd2 (io7) and rxd2 (io6) pins. ;------------------------------------------------------------------------------- ; configure uart2 to the pins io6 and io7 with the baudrate of 19200 baud: ;------------------------------------------------------------------------------- ; map txd2 = io7 ; map rxd2 = io6 ;------------------------------------------------------------------------------- xdata mem: outmux1 (9503h) <- 80h ; maps txd2 to io7 xdata mem: set_eno (9505h) <- 80h ; enable output io7 xdata mem: sel_pupdo (9509h) <- 40h ; enable pullup for io6 xdata mem: sel_in (950bh) <- 05h ; map rxd2 to io6 idata mem: sbaudl2 (0c2) <- 11h ; set baudrate register low idata mem: sbaudh2 (0c3) <- 00h ; set baudrate register high idata mem: scon2 (0c0) <- 50h ; setup uart2 serial port for rx and tx. ;-------------------------------------------------------------------------------
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 95 of 123 ;------------------------------------------------------------------------------- ; program fragment for enabling uart2 for serial communication. ; ; sfr locations -- ; scon2 equ 0c0h ; serial 2 control register sbuf2 equ 0c1h ; serial 2 port register sbaudl2 equ 0c2h ; serial 2 baudload lowbyte sbaudh2 equ 0c3h ; serial 2 baudload highbyte ; ; variables -- ; baudratelo equ 11 ; baudrate value for 19200 baud, baudratehi equ 0 ; mcu_clk = 3.58mhz ; ; memory map for the uart2 configurations -- ; outmux1 equ 09503h ; need to be set as 0x80 set_eno equ 09505h ; need to be set as 0x80 sel_pupdo equ 09509h ; need to be set as 0x40 sel_in equ 0950bh ; need to be set as 0x05 ; ; instruction code fragment ; ... mov ie,#0a0h ; enable serial interrupt uart2 0xa0 mov dptr,#outmux1 ; 09503h <- 80h ; maps txd2 to io7 mov a,#080h movx @dptr,a mov dptr,#set_eno ; 09505h <- 80h ; enable output io7 mov a,#080h movx @dptr,a mov dptr,#sel_pupdo ; 09509h <- 40h ; enable pullup for io6 mov a,#040h movx @dptr,a mov dptr,#sel_in ; 0950bh <- 05h ; map rxd2 to io6 mov a,#005h movx @dptr,a mov sbaudl2,#baudratelo ; set baudrate (16 bits) mov sbaudh2,#baudratehi mov scon2,#050h ; set up uart2 serial port for rx and tx. ; ... ;------------------------------------------------------------------------------- timer 0 there is only timer 0 present, timer 1 is not implemented except for some flags in the tcon register, which are also used for timer 0. furthermore, there is no counter mode available as the inputs t1 and into of the standard 8051 are not mapped to external pins. the c onnection of timer 0 in each of its four operating modes is shown below.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 96 of 123 there are five special function registers (sfr) related to the timer 0: register name address description tmod 89h timer mode register tcon 88h timer control register t0pre 8eh timer 0 8 bit prescaler register th0 8ch timer 0 higher byte tl0 8ah timer 0 lower byte tmod msb lsb 0 0 0 0 gate c/t_n m1 m0 bit symbol function 7 - not used 6 - not used 5 - not used 4 - not used 3 gate has no effect on timer 0 operation can be used as register bit 2 c/t_n acts like an enable signal mode description bit1 bit0 0 13 bit timer (mcs-48 compatible) 0 0 1 m1 1 same as mode 0 but 16 bit timer 0 1 2 configures timer 0 as 8 bit autoreload timer. overflow from tl0 sets tf0 and reloads tl0 with the value of th0. 1 0 0 m0 mode select 3 two 8 bit timers, tl0 controlled by timer 0 standard bits, th0 controlled by timer 1 control bits but no interrupt 1 1 tcon msb lsb tf1 tr1 tf0 tr0 - - - - bit symbol function 7 tf1 timer 0 (mode 3) th0 overrun flag, generates no interrupt, flag can be polled by software. 6 tr1 timer 0 (mode 3) th0 enable flag, th0 runs if ?1? in all other modes the flag has no effect. 5 tf0 timer 0 overrun flag, generates an interrupt. flag is cleared by hardware when the processor jumps to the interrupt routine 4 tr0 timer 0 run control bit. timer runs if ?1?. cleared/set by software. 3 - not used 2 - not used 1 - not used 0 - not used
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 97 of 123 t0pre ct_n = 0 ct_n = 1 tr0 tl0 (5 bits) th0 (8 bits) tf0 control timer 0 interrupt mcu_clk (8bits) *) 1 6 1 n mcu_clk x x 6 : n : figure 25: timer 0 mode 0 and mode 1 *) : 13 bit counter t0pre ct_n = 0 ct_n = 1 tr0 tl0 (8 bits) tf0 control timer 0 interrupt mcu_clk clk _ mcu 6 1 th0 (8 bits) reload 1 6 1 n mcu_clk xx 6 : n : figure 26: timer 0 mode 2: 8 bit counter t0pre ct_n = 0 ct_n = 1 tr0 tl0 (8 bits) tf0 control timer 0 interrupt mcu_clk clk _ mcu 6 1 tr1 control th0 (8 bits) tf1 1 6 1 n mcu_clk x x 6 : n : figure 27: timer 0 mode 3: two 8 bit counters t0pre unlike the standard 8051 there is a 8-bit prescaler register available for timer 0. values of 0x00 (default after reset) and 0x01 do not have any effect. for all other values the timer input frequency is divided according to the value (ranging from 2 up to 255).
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 98 of 123 8.7 system control (sct) the system control is responsible for handling differen t modes of operation such as normal mode (metering functions) and test mode. the clock generation and reset control are also available in system control (sct). modes of operation power off in this mode everything is off including the ?system timing and rtc? block, provided that no battery is connected to vdd_bat or the battery is discharged. nothing happens. rtc on, rest of the chip off in this mode the ?system timing and rtc? block is supplied by a battery, the rtc is working, but no interrupts are generated. at the moment the battery is inserted, a power-on reset just for the rtc will be generated. the reset will be set to 0 after the first clock edges arrive. power-up phase when the power is switched on (for the ?rest? of the chip), there is a power-on reset first and the reset is held until the bootload block has finished operation. the bootload block will load the p_ram from the external eeprom. after bootload the mcu will start to work. the loaded program will be executed. it is assumed that at the beginning of the program various system parameters are set (sel_i, sel_v, sel_p, creep etc.) no eeprom programmed, must be loaded from outside if the eeprom does not contain a program the mcu will run idle mode. it is necessary to write a program to the eeprom next. write to eeprom the eeprom can directly be written (from outside) using the uart1 interface. the following diagram shows the main blocks involved: uart1 sct spi eeprom rxd s_n so sc si
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 99 of 123 note: it would also be possible to write to the eeprom via the uart2 and the mcu, but then a dedicated mcu program is required to handle the data flow. transmission protocol: in order to make the data transfer easier for the system control a defined protocol is used for talking to the uart1, where the length of the data to be written to the eeprom is specified at the beginning of the transmission. the protocol is as follows: write command (8 bits) 7 0 1 2 3 4 5 6 15 8 9 10 11 12 13 14 7 0 1 2 3 4 5 6 start address (16 bits) 15 8 9 10 11 12 13 14 7 0 1 2 3 4 5 6 block length (16 bits) data 7 0 1 2 3 4 5 6 ... acknowledge 7 0 1 2 3 4 5 6 (txd) notes: 1) when ?enable_crc? is set to 0 the uart1 only sends back the acknowledge word (fah). 2) when ?enable_crc? is set to 1 a 16-bit checksum has to be transferred to the uart1 at the end of the data stream. the sct will calculate the checksum and depending on the result it will send back the acknowledge word (fah) or the not-acknowledge word (fbh). read from eeprom if it is required to read out the eeprom data this can also be done using the uart1 interface. the following diagram shows the main blocks involved: uart1 sct spi eeprom rxd s_n so sc si txd again it would also be possible to do this using uart2 and mcu. transmission protocol: in order to make the data transfer easier for the system control a defined protocol is used for talking to the uart1, where the length of the data to be read from the eeprom is specified at the beginning of the transmission. the protocol is as follows: data 7 0 1 2 3 4 5 6 ... read command (8 bits) 7 0 1 2 3 4 5 6 15 8 9 10 11 12 13 14 7 0 1 2 3 4 5 6 start address (16 bits) 15 8 9 10 11 12 13 14 7 0 1 2 3 4 5 6 block length (16 bits) (txd)
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 100 of 123 note: when ?enable_crc? is set to 1 a 16-bit checksum word will be sent after the data stream. it can be used to validate the received data. reset chip: externally triggered bootload when a (new) program has been written to the eeprom it will be necessary to force the chip to load it into the p_ram. this can be done by generating a chip reset, which triggers a bootload sequence. after the related command has been detected by the sct on the uart1 interface the reset/boot sequence will start. next the mcu will run the program from the beginning. this command can also be used for a simple reset. the bootload is just the extra you get with it. normal operation the mcu is working through its program, access to certain blocks/functions may be done via the uart interfaces. for example, it may be required to read data from the eeprom or from the rtc block. during these operations the mcu is not reset! program debugging program debugging can be done using a so-called monitor program, which may communicate with a pc using the uart2 interface or the uart1 interface in direct access mode. note: direct access mode (?dam? register bit) turns o ff the command interpreter. so if an mcu program does that there is no way out, because after a system reset there is a bootload sequence, which loads the same program again. solution: if pin si is held at 1 during the startup phase, the ?dam? bit will be reset. read from xdata address mainly for evaluation purposes it will be required to read registers, which are located in the xdata address space (x_ram and block interfaces). a dedicated command is reserved for this. the following diagram shows the main blocks involved here: uart1 sct rxd txd sct registers dsp registers rtc registers mpio registers spi registers x_ram
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 101 of 123 transmission protocol: in order to make the data transfer easier for the system control a defined protocol is used for talking to the uart1, where also the length of the data to be read from the xdata address space is specified at the beginning of the transmission. it looks like this: data 7 0 1 2 3 4 5 6 ... read command (8 bits) 7 0 1 2 3 4 5 6 15 8 9 10 11 12 13 14 7 0 1 2 3 4 5 6 start address (16 bits) 15 8 9 10 11 12 13 14 7 0 1 2 3 4 5 6 block length (16 bits) (txd) note: when ?enable_crc? is set to 1 a 16-bit checksum word will be sent after the data stream. it can be used to validate the received data. write to xdata address for evaluation, but also for setting the rtc it will be re quired to write to a register located in the xdata address space (x_ram and block interfaces). also for this an sct command is prepared. the following diagram shows the main blocks involved and the data and signal flow: uart1 sct rxd sct registers dsp registers rtc registers mpio registers spi registers x_ram lcdd registers notes: 1) it is guaranteed that the mcu finishes its last (current) command before the xdata access takes place. 2) in principle it is possible that a value, which has been modified using this write-command, immediately gets overwritten by the mcu. therefore this command has to be used in an intelligent way. transmission protocol: in order to make the data transfer easier for the system control a defined protocol is used for talking to the uart1, where also the length of the data to be written to the xdata address space is specified at the beginning of the transmission. it looks like this:
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 102 of 123 write command (8 bits) 7 0 1 2 3 4 5 6 15 8 9 10 11 12 13 14 7 0 1 2 3 4 5 6 start address (16 bits) 15 8 9 10 11 12 13 14 7 0 1 2 3 4 5 6 block length (16 bits) data 7 0 1 2 3 4 5 6 ... acknowledge 7 0 1 2 3 4 5 6 (txd) notes: 1) when ?enable_crc? is set to 0 the uart1 only sends back the acknowledge word (fah). 2) when ?enable_crc? is set to 1 a 16-bit checksum has to be transferred to the uart1 at the end of the data stream. the sct will calculate the checksum and depending on the result it will send back the acknowledge word (fah) or the not-acknowledge word (fbh). flow diagram of operational modes vdd[d|a] off vdd_bat off vdd[d|a] off vdd_bat on insert battery vdd[d|a] on vdd_bat off: - no clock - chip stays reset power-up (vmain on) vdd[d|a] on vdd_bat on power-up (vmains on) bootload power-on reset mcu in idle mode, "loop program" running mcu: program execution, command mode active finished. program available finished. no program receiving sct command evaluating sct command write to eeprom read from eeprom reset chip receiving sct command boot load 16 bit address 8 bit data in (...) 16 bit address back to mcu back to mcu back to mcu f4h f3h f0h program execution command mode disable command mode enable uart handling interrupt from uart read from xdata address write to xdata address f6h f5h 16 bit address 8 bit data in (...) 16 bit address back to mcu back to mcu 16 bit blocklength 16 bit blocklength 8 bit data out (...) 8 bit data out (...) read prompt set baudrate 8 bit out: "a" 8 bit out: "l" 8 bit out: "i" 8 bit out: "v" 8 bit out: "e" back to mcu sbaudh sbaudl back to mcu f2h f1h 16 bit blocklength 16 bit blocklength ack / nack ack / nack
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 103 of 123 note: during ?write/read eeprom? or ?write/read xdat a? the mcu keeps running. the sct guarantees that there is no collision between mcu and sct memory accesses. command interpreter the command interpreter continuously looks at the uart1 input to detect if a command has been sent, i.e. a specific byte that is defined to initiate a dedicated mode of operation (see flow diagram above). the commands have been specified to lie outside the ?normal? ascii range. all codes not specified within the following table can directly be transferred to the mcu without any interference by the sct. command name code description soft_reset f0h resets the chip and initiates a bootload sequence, then the mcu program is started. rd_prompt f1h the chip sends a specific signature, ?a live? which is ascii coded. this can be used to test the uart1/sct interface. sbaud f2h makes it possible to set the uart1 baudrat e from outside the chip by directly accessing the sfrs ?sbaudl? and ?sbaudh?. default setting: 11 (3.5795mhz crystal and 19200 baud) read_p f3h enables reading of data from eeprom. write_p f4h data can be written to the eeprom. read_x f5h data from the xdata address space can be read. write_x f6h data can be written to any location in the xdata address space. sct registers the system control (sct) registers provide for the setti ng of various enables signals and selection of the mcu clock (mcu_clk) frequency. register name address reset value description - 9000h - not used enable signals 9001h 000b see table below mcuclkdiv[2:0] 9002h 000b see table below enable signals register the enable signals register includes power-down signals and other control signals. msb lsb - - enable_crc u2clkoff u1clkoff dam sdmi2_pd afe_pd bit symbol function 7 - not used 6 - not used
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 104 of 123 bit symbol function 5 enable_crc enables checksum functionality during read/wr ite accesses to xdata address space or eeprom. if enabled, a 16-bit checksum word (see note below) is sent after the data, which is checked by the sct (in case of ?write?) or can be checked by an external component (in case of ?read?). 0: checksum disabled 1: checksum enabled 4 u2clkoff switches off the uart2 clock (which is also running at the highest system frequency ?mclk?): 0: clock active 1: clock switched off 3 u1clkoff switches off the uart1 clock (which is runn ing at the highest system frequency ?mclk?): 0: clock active 1: clock switched off 2 dam select direct access mode for uart1; in case of ?dam? input data will no longer be interpreted as commands. 0: direct access mode off 1: dam on 1 sdmi2_pd set power-down for current channel 2 (active high) 0: no power-down 1: i2 powered down 0 afe_pd set power-down for the entire analog front end (afe) 0: afe powered up 1: afe powered down note: the checksum is calculated using the following formula: g(x) = x 16 + x 12 + x 5 + 1 mcuclkdiv register (?mcu_clk?) the mcu clock divider (mcuclkdiv) divides down the main clock (mclk) which is the output from the low power oscillator. division of the mcu_clk frequency is provided to enable low power operating modes, for example when the AS8218 / as8228 ics are in a battery operating mode, when vddd is connected to a battery. msb lsb - - - - - mcuclkdiv.2 mcuclkdiv.1 mcuclkdiv.0 bit symbol function 7 - not used 6 - not used 5 - not used 4 - not used 3 - not used bit2 bit1 bit0 division 0 0 0 mclk : 1 2 mcuclkdiv.2 0 0 1 mclk : 2 0 1 0 mclk : 4 0 1 1 mclk : 8 1 mcuclkdiv.1 1 0 0 mclk : 16 1 0 1 mclk : 32 1 1 0 mclk : 64 0 mcuclkdiv.0 these bits set the mcu_clk frequency by dividing down the main clock (mclk). 1 1 1 mclk : 128
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 105 of 123 8.8 serial interface ? uart1 - extended version of the standard 8051 uart1 - sbuf and scon are compatible with standard 8051 - built-in 16 bit baudrate generator (sbaudh, sbaudl) - additional sovr receiver overflow indicator register uart1 is used to communicate externally. uart1 requires only two pins to receive and transmit information. uart1 is compatible to the serial interface of the 8 051 microcontroller family, with the exception of the baudrate generation. uart1 is functionally identical to uart2. thus the instructions below are also valid for uart2. uart1 is segmented into three main functional blocks, namely baudrate , transmission and reception , as shown in the block diagram below: detected bit receive shift enable start reception endofreception, rb8 data(0...7) scon sbuf txd interrupt rxd 16 bit baudrate generator transmit baudrate timer receive baudrate timer scon register transmit unit ri or ti endoftransmission transmission reception baudrate tb8 receive shifter receive sbuf receive control receive bit detector sbaudh, sbaudl sovr figure 28: uart1 block diagram there is no direct dependency on osc clock (mode 0, 3). instead there is a built-in 16 bit wide baudrate generator for higher flexibility.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 106 of 123 uart is dedicated to the sct block for writing to and reading from other functional blocks such as rtc, lcdd; besides, it is used for selection of different modes of operation. sfrs of uart1 there are five special function registers dedicated to the uart1. register name address description read/write from mcu scon 98h serial port control register read & write sbuf 99h serial port buffer regi ster read & write (separate) sbaudl 9ah baudrate reload register ? low address write only sbaudh 9bh baudrate reload register ? high address write only sovr 90h serial receive buffer overflow register read & write, only one bit (=bit0) available sovr register serial receive buffer overflow register. if data is received before it has been read out of sbuf then the bit sov is set. it can the cleared by software. all other bits of sovr are 0. sovr msb lsb 0 0 0 0 0 0 0 sov note: overflow flag. if ?1? then a receiver buffer overflow occurred. the old buffer value has been overwritten by new incoming data. set by overflow, cleared by mcu. scon register the sfr serial port control register (scon) is used to configure the uart1 and to check the status of the transmission. scon msb lsb sm0 sm1 sm2 ren tb8 rb8 ti ri
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 107 of 123 bit symbol function mode bit7 bit6 mode 0: same as mode 1, (mode 0 is not implemented due to standard 8051) 0 0 7 sm0 mode 1: 8-bit uart1, variable ba udrate. - the serial transmission is set to 8 data bits. however up to 10 bits can be sent at port txd and received at port rxd : start bit (always ?0?), eight data bits (lsb first), and a stop bit (always ?1?). the value of a received stop bit is transferred to scon.rb8 and can be evaluated by the software. 0 1 mode 2: 9-bit uart1, variable ba udrate. - the serial transmission is set to 9 data bits. however up to 11 bits can be sent at port txd and received at port rxd : start bit (always ?0?), nine data bits (lsb first), and a stop bit (always ?1?). the value of scon.tb8 is used for transmitting the ninth data bit (usually as parity bit). the value of the received ninth data bit is transferred to scon.rb8 and can be evaluated by the software. 1 0 6 sm1 mode select flags mode 3: 9-bit uart1, variable baudrate. ? same as mode 2. 1 1 5 sm2 mode select flag 2: enables the multiproce ssor communications feature in mode 2. mode 0: sm2 is not used. mode 1: when sm2=?1?, ri is not set and sbuf is not loaded if the received stop bit is ?0?. mode 2: when sm2=?1?, ri is not set and sbuf is not loaded if the received ninth data bit is ?0?. please refer also to section multiprocessor communications. 4 ren receiver enable flag. with ren=?0? the receiver is disabled, otherwise enabled. ren is to be set and cleared by the software. 3 tb8 value of the ninth data bit to be sent when in mode 2. 2 rb8 value of the ninth data bit received when in mode 2 or value of the stop bit received when in mode 1. not used in mode 0. 1 ti transmit interrupt flag. this flag is set by the uart1 at the end of transmitting. in mode 0 flag ti is set at the end of the eighth data bit, in all others modes at the beginning of the stop bit. flag ti must be cleared by the software. 0 ri receive interrupt flag. this flag is set by the hardware at the end of receiving. in mode 0 flag ri is set at the end of the eighth data bit, in mode 1 at the mi ddle of the stop bit, and in mode 2 at the middle of the ninth data bit. flag ri must be cleared by the software. note: 1) mode select flags 0/1: these bits are used to select one of four transmission modes. in all four modes the baudrate is determined by the baudrate generator. sbuf registers the 8-bit register sbuf is the data buffer register which actually consists of two registers for both transmitting and receiving data. both are accessed by the same address sbuf. a write access to sbuf is redirected into the internal register transmitsbuf, a read access to sbuf is redirected to the internal register receivesbuf. remark: the (optional) ninth data bit is defined in scon.tb8/rb8. sbuf msb lsb data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 108 of 123 note: the sbuf register is split up within the uart1 into the internal registers transmitsbuf (when writing to the sfr) and receivesbuf (when reading from the sfr) a write access to sbuf starts a transmission, according to the selected mode. a write access during an ongoing transmission results in discarding the byte without disturbing the process of transmission. if there is a series of bytes to be transmitted, the software has to wait until the previous byte has been sent (scon.ti = ?1?), before writing to sbuf. the shift sequence (serialization) is handled by means of the internal register transmitsbuf that holds up to 12 bits (depending on the mode used): hardcoded ?1?-bit + start bit + 8 data bits + optional ninth data bit + stop bit. during transmitti ng the content of transmitsbuf is shift right, thus transmission is done with lsb first. a read access to sbuf delivers the latest byte received by the uart1. bit scon.ri has to be cleared (to ?0?) by the software after fetching a byte from sbuf, thus enabling the uart1 to receive further bytes. if scon.ri is not ?0? when a new byte is received, the new byte will be discarded (and thus is lost) and sbuf will keep its old value. sbaudh, sbaudl baudrate reload registers msb lsb sbaudl br7 bf6 br5 br4 br3 br2 br1 br0 sbaudh br15 br14 br13 br12 br11 br10 br9 br8 note: the sbaudl and sbaudh are merged into a 16 bit reload value: sbaudl = baudrate value (7:0) sbaudh = baudrate value (15:8) baudrate generator unlike the original 8051 architecture, the uart1 inco rporates a built-in baudrate generator. the baudrate is generated by a counter, which is decremented every clock cycle. when reaching the value 0, the counter is automatically reloaded. the reload value is a programmable value stored in the 16 bit register formed by sbaudh and sbaudl. a serial bit (during transmit and receive) is further divided into 16 time slices for accurate sampling. due to the full-duplex operation there is a separate transmit baudrate timer und receive baudrate timer implemented for this task. baudrate reload register the following table shows some selected values to be loaded to the brreloadregister (sbaudh + sbaudl) at a given clock frequency that may be used with the AS8218 / as8228 ics. the smaller the value, the more difficult it is to meet a demanded baudrate within a give n tolerance. if the error is greater than 5% the baudrate is not appropriate for error-free communication. baudrate [baud] 3.00mhz error [%] 3.58mhz (3579545hz) error [%] 4.00mhz error [%] 110 1704 0.0267 2033 0.0082 2272 0.0120 150 1249 0 1491 -0.0320 1666 0.0200
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 109 of 123 baudrate [baud] 3.00mhz error [%] 3.58mhz (3579545hz) error [%] 4.00mhz error [%] 300 624 0 745 0.0351 832 -0.0400 600 312 0.1597 372 0.0350 416 0.0799 1200 155 -0.1603 185 -0.2337 207 -0.1603 2400 77 -0.1603 92 -0.2337 103 -0.1603 4800 38 -0.1603 46 0.8326 51 -0.1603 9600 19 2.3438 22 -1.3232 25 -0.1603 19200 9 2.3438 11 2.8986 12 -0.1603 38400 4 2.3438 5 2.8986 (6) ? 6.9940 57600 (2) ? -8.5069 3 2.8986 (3) ? -8.5069 76800 (1) ? -22.0703 2 2.8986 (2) ? -8.5069 115200 (1) ? 18.6198 1 2.8986 (1) ? -8.5069 below there are the formulas for calculating baudrate and baudratereloadregister, but also the error. you have to divide through 16 because the serial bit is further divided into 16 time slices. () er loadregist baudratere 1 16 ency clockfrequ baudrate + = 1 baudrate 16 ency clockfrequ er loadregist baudratere ? = baudrate _ desired ) gister re load re baudrate 1 ( 16 ency clockfrequ baudrate _ desired error + ? = transmission a write access to register sbuf invokes the transmission of a byte. if there is already an ongoing transmission then the written byte is discarded. at the end of transmis sion flag scon.ti is set, indicating the software that the next byte can be written to sbuf. reception the process of receiving is initiated by setting scon .ren to ?1? and scon.ri to ?0? by software. after reception the uart1 sets scon.ri to ?1? and the data bi ts can be fetched from sbuf. each data bit of the serial data stream is probed three times (in the midd le of the bit time) to achieve noise immunity. interrupt per default the uart1 is operated in the ?command mode? (as described in section sct) and an interrupt is asserted to the mcu except when a command is detected. the uart1 can also be used in the direct access mode (bit dam = ?1? in sct register 9001h). this setting allows the mcu to operate the uart1 as defined in the standard 8051 configuration.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 110 of 123 the uart1 asserts an interrupt whenever flag scon.ri is ?1? or scon.ti is ?1?. these flags are set if a successful receive or transmit operation has taken place. the flags to scon.ri and scon.ti must be cleared by software. the mcu program branches to the interrupt routine if the serial interrupt is enabled in the ie register, with ie.4 (= es) = ?1?. since scon.ri and scon.ti are linked together (logic-or), there is a common interrupt service routine for both transmitting and receiving. the interrupt service routine has to decide which event triggered the interrupt request (by querying the flags ri and ti). it is important to clear the flags before leaving the interrupt service routine. multiprocessor communications mode 2 has a special provision for multiprocessor communications. in this mode, a 9 th data bit is received and goes into rb8. then a stop bit follows. the port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. a way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the ninth bit is 1 in an address byte and 0 in a data byte. with sm2 = 1, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bi t and prepare to receive the data bytes that will be coming. the slaves that were not being addressed leave their sm2s set and go on about their business, ignoring the coming data bytes. modes the uart1 can be used in two different modes: mode 0 (= mode 1) and mode 2 (= mode 3). the mode selection is due the bits sm0, sm1 in the scon register. mode 0 and 1 8 bit uart1 with variable baudrate c ontrolled by the baudrate generator. wrstrobesfr ti transmitenable transmitsbuf transmitting endoftransmission txd start bit 1 0 0 1 0 0 0 0 stop bit 001000010010 000100001001 000010000100 000001000010 000000100001 000000010000 000000001000 000000000100 000000000010 figure 29: transmitting in mode 1: here ?09h? is sent. the resulting bit stream on the txd line is: start bit (=?0?) + ?10010000?, for lsb is sent first. the process of transmitting is initiated by writing to sbuf. the byte written to sbuf is held in register transmitsbuf . the transmission starts with the next 1-pulse on the internal signal transmitenable . output txd is driven with a start bit (?0?), eight data bits with the lsb first shifted out from transmitsbuf , and a stop bit (?1?). at
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 111 of 123 begin of the stop bit the internal signal endoftransmission is activated, causing flag scon.ti going to high and thus indicating the end of the transmission. receiveshiftenable rxd rb8 ri startreception receiving endofreception receiveshiftregister receivesbuf start bit 0 0 1 1 0 1 1 1 1 stop bit 011111111 001111111 100111111 110011111 011001111 101100111 110110011 111011001 111101100 f6 00 figure 30: receiving in mode 1 and mode 2: here the bit stream ?0?+?01101111? is received (see signal receiveddatabit ), that is: start bit + f6 h . the start bit is the first 0-pulse of signal rxd , that is when signal receivingstartbit is active. receiving is only possible when scon.ren = ?1?. the process of receiving is started with a falling edge on rxd (internal signal startreceiption is activated) and controlled by a 4-bit counter, that means a bit time is divided into 16 time slices. the counter is reset when identifying a falling edge on rxd and is consequently synchronized. the value of rxd is probed three times at the counter stage 6, 7, and 8 (counter range is from 0 to 15). the final value ( receiveddata-bit ) is determined by majority. the multiple probing ensures a more robust serial connection. at counter = 9 the received bit is transferred into the shift register ( receiveshiftregister ). if the first received bit (stop bit) is not ?0?, then the process is aborted and the uart1 waits for the next falling edge on rxd . due to this procedure all data packets with an invalid start bit are automatically discarded. when receiving the stop bit ( endofreceiption = ?1?) the following condition is checked: scon.ri=?0? and (scon.sm2=?0? or received_stop_bit=?1?) if this condition is true, then all eight data bits are transferred to receivesbuf , the stop bit is written to scon.rb8, and scon.ri is set to ?1?. otherwise all the received data is discarded and the receiver waits for the next falling edge on rxd . mode 2 and 3 9 bit uart1 with variable baudrate c ontrolled by the baudrate generator. mode 2 is very similar to mode 1 except that nine data bits are processed. the subsequent text deals only the differences to mode 1. mode 3 is the same as mode 2. the ninth data bit during transmission is taken from sc on.tb8 and is sent after the eight bits from sbuf. when receiving the ninth data bit ( endofreceiption = ?1?) the following condition is checked: scon.ri=?0? and (scon.sm2=?0? or ninth_data_bit=?1?)
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 112 of 123 if this condition is true, then all eight data bits are transferred to receivesbuf , the ninth data bit is transferred to scon.rb8, and scon.ri is set to ?1?. otherwise all the received data is discarded and the receiver waits for the next falling edge on rxd . assembler code the following code fragments demonstrate the programming of the uart1. adjusting the baudrate (for all modes) sbl equ 9ah ; serial baudratereload lowbyte sbh equ 9bh ; serial baudratereload highbyte mov sbl,#38 ; 9600 baud, 6mhz mov sbh,#0 using mode 0 mov scon,#00h ; mode 0, ren=0, ri=0, ti=0 mov a,#53h clr ti ; clear transmit flag mov sbuf,a ; transmit 53h in mode 0 wait: jnb ti,wait ; wait until data is sent mov scon,#10h ; mode 0, ren=1 - start reception clr ren ; ren=0 wait: jnb ri,wait ; wait until data is received mov a,sbuf ; move received byte into the accu transmitting in mode 0 mov scon,#50h ; mode 1, ren=1, ri=0, ti=0 mov a,#53h clr ti ; clear transmit flag mov sbuf,a ; transmit 53h in mode 1 wait: jnb ti,wait ; wait until data is sent receiving in mode 1 (only bytes with valid stop bit) mov scon,#70h ; mode 1, sm2=1, ren=1, ri=0, ti=0 wait: jnb ri,wait ; wait until data is received clr ri ; enable another reception mov a,sbuf ; move received byte to accu transmitting in mode 2 (ninth data bit as parity bit) mov a,#0a4h ; move data to accu mov c,p ; parity information to carry flag mov tb8,c ; parity information to ninth data bit mov sbuf,a ; transmit a4h in mode 2 wait: jnb ti,wait ; wait until data is sent interrupt based receiving org 0h ; reset vector
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 113 of 123 ljmp program_start org 023h ; serial interrupt vector ljmp serialinterrupt org 100 ; begin of main program serialinterrupt: clr ri ; clear the ri bit (since we know that was ; the bit that caused the interrupt) mov p1, sbuf ; move the received data out to port one reti program_start: setb ea ; enable interrupts generally setb es ; enable serial interrupts mov scon,#50h ; mode 1, ren = 1 mov sbuf,#2fh clr ri ; ensure that ri is cleared loop: jmp loop ; endless loop interrupt based transmitting org 0h ; reset vector ljmp program_start org 023h ; serial interrupt vector ljmp serialinterrupt org 100 ; begin of main program serialinterrupt: ... ... clr ti reti program_start: setb ea ; enable interrupts generally setb es ; enable serial interrupts mov scon,#40h ; mode 1, ren = 0 mov sbuf,#2fh
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 114 of 123 9. circuit diagram ic1 AS8218 / as8228 lcd kwh vrms irms 12 xtal 3.3v d1 d3 d4 bat vdd d i1n i2p i2n vdda vssa io0 io1 io2 io3 io4 4 5 6 7 8 9 10 11 1 2 13 14 15 16 io6 io7 io8 vddd vssd si s_n so sc txd rxd vdd_bat 27 20 21 22 23 24 25 26 61 60 59 58 57 56 55 54 53 52 51 50 49 lsd8 lsd9 lsd10 lsd11 lsd12 lsd13 lsd14 lsd15 lsd16 lsd17 lsd18 lsd19 45 44 43 42 41 40 39 38 37 36 35 34 33 xout lbp0 lbp1 lbp2 lbp3 lsd0 lsd1 lsd2 lsd3 lsd4 lsd5 lsd6 c12 c13 3.3v r10 c8 ct1 c3 rsh c1 r4 r2 r1 c21 r13 c23 c22 l1 zd1 3.3v vi vo gnd ic3 nl load vp vn i1p 1 2 3 17 18 19 28 29 30 31 32 48 47 46 lsd7 64 63 62 lsd21 lsd22 lsd23 vssd io5 io9 io11 io10 xin res_n n.c. n.c. lsd20 c14 3.3v r5 c4 r12 r11 d5 + c7 + d2 ic2 3.3v vcc 3.3v 3.3v hold i/os examples only as8228 only as8228 only r3 c2 c5 r6 r7 c6 c18 c19 + r9 r8 c10 c9 3.3v c11 3.3v c15 c16 c17 + vdda vddd c20 +
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 115 of 123 10. parts list designation value unit description ic1 AS8218 or as8228 mete ring integrated circuits ic2 up to 32kb spi bus eeprom (selectable in binary steps) ic3 3.3 v voltage regulator le33cz rsh 300 ohm shunt resistor (see ?analog front end?) ct1 current transformer r1 resistor (see ?analog front end?) r2 470 ohm resistor (see ?analog front end?) r3 470 ohm resistor r4 680 ohm resistor r5 680 ohm resistor r6 680 ohm resistor r7 680 ohm resistor r8 680 ohm resistor r9 680 ohm resistor r10 4.7 ohm resistor (see ?analog front end?) r11 680 ohm resistor r12 680 ohm resistor r13 470 ohm resistor c1 100 nf capacitor c2 100 nf capacitor c3 33 nf capacitor c4 33 nf capacitor c5 33 nf capacitor c6 33 nf capacitor c7 33 nf capacitor c8 33 nf capacitor c9 33 nf capacitor c10 33 nf capacitor c11 100 nf capacitor c12 220 f capacitor c13 100 nf capacitor c14 10 nf capacitor c15 10 nf capacitor c16 1.0 f capacitor c17 100 nf capacitor
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 116 of 123 designation value unit description c18 1.0 f capacitor c19 100 nf capacitor c20 1.0 f capacitor c21 10 nf capacitor c22 0.47 f capacitor c23 470 f capacitor d1 diode 1n4148 d2 diode 1n4148 d3 diode 1n4148 d4 diode 1n4148 d5 diode 1n4004 zd1 15 v zener diode bzv85?c15 l1 varistor bat 3.0 v lithium battery lcd liquid crystal display xtal 3.579545 mhz crystal note: the external components for the programmable multi-purpose i/os (mpio) are not included in the above parts list, as they depend on the specific meter functional requirements.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 117 of 123 11. packaging lqfp64 12. product ordering guide device number mpio lcdd temperature package packing AS8218 blqs 9 20 x 4 -40c to 85c lqfp64 tray in drypack AS8218 blqw 9 20 x 4 -40c to 85c lqfp64 t & r in drypack as8228 blqs 12 24 x 4 -40c to 85c lqfp64 tray in drypack as8228 blqw 12 24 x 4 -40c to 85c lqfp64 t & r in drypack
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 118 of 123 13. collection of formulae shunt resistor for mains current sensing: p p shunt i v r = where v p is the peak input voltage to the ic at rated conditions and i p the peak imax value of the meter. ct voltage setting termination resistor for mains current sensing: 2 i v r l ) p ( in vs = where v in(p) is the peak input voltage to the ic at rated conditions (v mains ; i max ). i.e.: if gain = 4 then v in(p) must be set at 150mvpeak and i l is the ct rms secondary current at rated conditions (v mains ; i max ) voltage divider for the v mains input for the energy calculation: v mains r1a+r1b r2 v in ) p ( in ) p ( in mains v ) v v ( 2 r b 1 r a 1 r ? = + where v mains is the peak mains voltage and v in(p) is the is the peak input voltage to the ic at rated conditions. phase shift value of 1 unit of phase correction relative to the mains frequency: 8 / f f 360 f f 360 t t 360 unit 1 osc mains ovs mains mains ovs = = = 8 / f f 360 unit # phase osc mains =
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 119 of 123 where f mains is the mains frequency and f osc is the oscillator frequency. phase correction factor with a power factor (pf) of less than 1: the meter has been calibrated at pf = 1 and the error is approximately 0 for i cal (calibration current). if the pf is reduced, the effect of phase differences results in an increased error (?phase_error?): first, the related phase shift in degrees can be calculated using the following formula: [ ] ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = 60 60 cos 100 % error _ phase 1 cos arc shift _ phase where the phase_error is the measured error in percentage and cos is the phase angle. for phase_error = 9.2[%] the phase_shift is 3.0. for f osc = 3.579545mhz and f mains = 50hz one phase correction unit represents 2.41?, which is 0.04023. thus the phase correction factor must be set to units 57 . 74 04023 . 0 0 . 3 = = 75 units. the pcorr register has to be set to 4bh. rms values from the voltage (sos_v) and current (sos_i1 and sos_i2): = = nsamp 1 i 2 i rms v nsamp 1 v , where = nsamp 1 i 2 i v is the sos_v value = = nsamp 1 i 2 i rms i nsamp 1 i , where = nsamp 1 i 2 i i is the sos_i value where nsamp, the number of samples before an update rate of the mdr (meter data register), is selected to achieve coherent sampling. 16-bit calibration values for the voltage (v) and current (i) channels: the ideal values after rms calculations of voltage (v in of 100mvp at rated conditions) and current and (i in of 30mvp at rated conditions when gain = 20) are: rms_v(ideal) = 479 (rms) rms_i (ideal) = 292,100 (rms)
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 120 of 123 due to non-ideal components a different rms value is calculated: rms_i(actual). from this, the required calibration factor is calculated using the following formula: ) actual ( i _ rms ) ideal ( i _ rms i _ cal = the following formula calculates the actual value to be programmed into the calibration registers (cal_v; cal_i1; cal_i2): )) 768 , 32 i _ cal ( round ( hex ) reg ( i _ cal = fast internal pulse rate (pr int ): the fast pulse gen output always has the same relationship with the led pulse rate, which is defined by mconst. only if led is calibrated to a meter constant di fferent from those provided in the mconst table, will the fast internal pulse rate be different. [] kwh / i mconst rate pulse et arg t 800 , 204 pr int = where mconst is the meter constant. [] ws pr 600 , 3 000 , 1 i 1 int = active power calibration (pulse_lev): the pulse_lev is specified such that a typical pulse rate of 204,800i/kwh can be achieved. during energy pulse calibration the correct pulse_lev is determined in order to get the desired pulse rate. the ic default value for pulse_lev is defined for i max =40a and v mains =230v. default pulse_lev: 570,950 the formula for calculating the ideal pulse_lev is as follows: ) default ( lev _ pulse i a 40 v v 230 ) ideal ( lev _ pulse max mains = the standard or reference meter pulses are counted between two pulses from the meter under test. from the deviation the corrected pulse_lev may be calculated. na ni ) ideal ( lev _ pulse ) corrected ( lev _ pulse = , where ni is the ideal number of pulses and na is the actual number of pulses (pcnt register in mpio). the ideal number of pulses ni is the ratio between the pulse rates, which is always >1. the formula for ni is as follows:
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 121 of 123 ) mconst ( rate pulse led ) ref ( pr ni = where pr(ref) is the reference meter constant. led meter constant (non-standard): the led pulses are derived directly from the fast internal pulses (204,800i/kwh) and is specified using the parameter ?mconst? of sreg. if the target meter constant is different from one of the selectable (mconst) meter constants, the following formula applies: ) na ni lev _ pulse ideal ( where ni is calculated using the target pulse rate: rate pulse et arg t t tan cons meter ference re ni = nb: for mconst, select a pulse rate close to target pulse rate, so that the pulse_lev stays within reasonable limits. 14. terminology afe - analog front end ct - current transformer dsp - digital signal processor eeprom - electrically erasable programmable read only memory i_ram - 8051 internal memory kb - kilobyte lbpx - lcd back-plane driver pin lcd - liquid crystal display lcdd - liquid crystal display driver led - light-emitting diode lp_div - low power divider lp_osc - low power oscillator lsb - least significant bit lsdx - lcd segment driver pin mcu - microcontroller unit mdr - meter data register (in dsp block) mpio - programmable multi-purpose input/output msb - most significant bit p_accu - power accumulator for real power pf - power factor plp - power low pass filter p_ram - program memory psm - power-supply monitor
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 122 of 123 psw - program status word ram - random access memory res_n - system reset pin rms - root mean square rtc - real time clock sct - system control sdm - sigma-delta modulator sfr - special function register sqrt - square root block sreg - settings register (in dsp block) spi - serial peripheral interface uart - universal asynchronous receiver/transmitter vref - voltage reference wdt - watchdog timer x_ram - 8051 external data memory 15. revision revision date owner description 2.1 06-oct-05 dsi 3.0 31-may-06 dsi 16. copyright copyright ? 1997-2006, austriamicrosystems ag, schloss prem staetten, 8141 unterpremstaetten, austria - europe. trademarks registered ? . all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. 17. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its terms of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-s upport or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profit s, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no oblig ation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services.
data sheet AS8218 / as8228 revision 3.0, 31-may-06 page 123 of 123 18. contact austriamicrosystems ag a 8141 schloss premstaetten, austria t. +43 3136 500 0 f. +43 3136 525 01 info@austriamicrosystems.com

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