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oki semiconductor fedl9228-01 issue date: oct. 20, 2004 ml9228 82-bit duplex/triplex vfd controller/driver with digital dimming, keyscan 1/25 general description the ml9228 is a full cmos controller/driver for duplex or triplex vacuum fluorescent display tube. it conststs of 82-segment driver outputs and 3-grid pre-driver outputs, so that it can drive directly up to 246-segment vfd. ml9228 features a digita l dimming function, a 5 6 keyscan circuit. features ? driver supply voltage (v disp ) : 8.0v to 18.5v ? logic supply voltage (v dd ) : 3.3v10%, 5.0v10% ? duplex/triplex selectable ? applicable vfd tube : 2 grids 82 anodes vfd tube : 3 grids 82 anodes vfd tube ? 82-segment driver outputs : i oh = ?6 ma at v oh = v disp ?0.8 v (seg1 to 82) ? 3-grid pre-driver outputs : i ol = 10 ma at v ol = 2 v ? built-in digital dimming circuit (10-bit resolution) ? built-in 5 6 keyscan circuit ? built-in oscillation circuit (external r and c) ? built-in power-on-reset circuit ? package: 128-pin plastic qfp (qfp128-p-1420-0.50-k) (ml9228 ga)
fedl9228-01 oki semiconductor ml9228 2/25 block diagram timing generator dup/ tr i osc control out1-82 82 bit shift register in1-10 dimming latch out1-10 10 bit digital dimming por cs clock data i/o out1-3 3 bit shift register por por por 4h out1-82 segment latch 3 in1-82 0h 3h por out1-82 segment latch 2 in1-82 0h 2h por out1-82 segment latch 1 in1-82 0h 1h por mode select in1-3 por 0h 7h power on reset v dd l-gnd por out1-82 246 to 82 segment control in1-82 in1-82 in1-82 82 segment driver d-gnd v disp 3 grid pre driver g ri d 2 gri d 3 g ri d 1 seg82 seg1 5 6 key scan interface int osco c ol 1 c ol 6 row1 row5 5h 6h 7h b lank r ese t
fedl9228-01 oki semiconductor ml9228 3/25 pin configuration (top view) nc: no connection 64-pin plastic qfp nc : no connection 108 107 106 105 104 103 seg55 seg54 seg53 seg52 nc nc 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 nc nc seg73 seg72 seg71 seg70 seg69 seg68 seg67 seg66 seg65 seg64 seg62 seg61 seg60 seg59 seg58 seg57 seg56 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 nc seg12 59 60 61 62 seg16 63 64 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 nc nc seg74 seg75 seg76 seg78 seg79 seg80 seg81 seg82 v disp d-gnd vdd int row1 row2 row3 row4 row5 col 1 c ol 2 c ol 3 c ol 4 c ol 5 c ol 6 dup/ t r i seg77 31 32 33 34 35 36 37 38 b lan k r ese t l-gnd nc osc0 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 seg50 nc nc seg51 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg19 72 71 70 69 68 67 66 65 seg23 seg22 seg21 seg20 seg18 nc nc seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg13 seg14 seg15 g rid 3 seg63 cs cloc k data i/o v disp g rid 1 nc d-gnd seg17 nc g rid 2 nc nc nc
fedl9228-01 oki semiconductor ml9228 4/25 pin descriptions pin symbol type description 12,42 v disp ? high level power supply pins pin12 and pin42 should be connected externally. 14 v dd ? low level power supply pin 13,41 d-gnd ? 37 l-gnd ? d-gnd is ground pins for the vfd driver circuit. l-gnd is ground pin for the logic circuit. pin13,pin37 and pin41 should be connected externally. 3 to 11, 46 to 62, 67 to 100, 105 to 126 seg1 to 82 o segment (anode) signal output pins for a vfd tube these pins can be directly connected to the vfd tube. external circuit is not required. l oh ?6 ma, l ol 500 ? 43,44,45 grid 1 to 3 o inverted grid signal output pins for pre-driver, the external circuit is required. l oh ?6 ma, l ol 10 ma 30 cs l chip select input pin data input/output operation is valid when this pin is set at a high level. 31 clock l serial clock input pin data is input and/or output through the data l/o pin at the rising edge of the serial clock. 32 data l/o l/o serial data input/output pin data is input to/comes out from the shift register at the rising edge of the serial clock. 15 int o interrupt signal output to microcontroller. when any key of key matrix is pressed or released, key scanning is started. after the completion of the one cycle, this pin goes to high level and keeps the high level until keyscan stop mode is selected. 27 dup/ trl l duplex/triplex operation select input pin. dup/ trl = l(l-gnd) : triplex dup/ trl = h(vdd) : duplex 21 to 26 col 1 to 6 l return inputs from the key matrix these pins are active low. when key matrix are in the inactive sate, these pins are at high level through the internal pull-up resistors. all the inputs do not have the chattering absorption function for the keyscans. 16 to 20 row1 to 5 o key switch scanning outputs normally low level is output through these pin. when any switch of key matrix is depressed or released, key scanning is started and is continued until keyscan stop mode is selected. when keyscan stop mode is selected, all outputs of row1 to 5 go back to low level. 28 blank i display off control input. blank = l(l-gnd) : display off(seg1-82 = l) blank = h(vdd) : display on
fedl9228-01 oki semiconductor ml9228 5/25 pin symbol type description 29 reset i the contents of the shift registers and latches are set to ?0?. the digital dimming duty cycle is set to ?0?. all segment outputs are set to low level. grid1 output is set to low level. grid2,3 outputs are set to high level. all the row outputs are set to low level. int output is set to low level. 33 osc0 l/o rc oscillator c onnecting pins oscillation frequency changes with display pipes to be used. please refer to the right figure. 1,2,35,36, 37,38, 40,63,64, 66,65, 101,102, 127,128 nc ? open pin v dd osc0 r 2 c 2
fedl9228-01 oki semiconductor ml9228 6/25 absolute maximum ratings parameter symbol condition rating unit v disp ? ?0.3 to +20 supply voltage v dd ? ?0.3 to +6.5 input voltage v in ? ?0.3 to +6.0 v power dissipation p d ta = 85 c 590 mw storage temperature t stg ? ?55 to +150 c l o1 seg1 to 82 ?10.0 to +2.0 l o3 grid 1 to 3 ?7.0 to +20.0 output current l o4 row1 to 5, data i/o ?2.0 to +2.0 ma recommended operating conditions parameter symbol condition min. typ. max. unit driver supply voltage v disp ? 8.0 13.0 18.5 unit supply voltage 5.0 v (typ) 4.5 5.0 5.5 logic supply voltage v dd unit supply voltage 3.3 v (typ) 3.0 3.3 3.6 v vdd = 5.0 v (typ) r 2 = 10 k ? 5%, c 2 = 27 pf 5% 2.6 3.3 4.0 mhz vdd = 3.3 v (typ) oscillation frequency f osc r 2 = 8.2 k ? 5%, c 2 = 27 pf 5% 2.6 3.3 4.0 mhz 1/3 duty 211 269 325 vdd=5.0 v (typ) r 2 = 10 k ? 5% c 2 = 27 pf 5% 1/2 duty 317 403 488 hz 1/3 duty 211 269 325 frame frequency f fr vdd=3.3 v (typ) r 2 = 8.2 k ? 5% c 2 = 27 pf 5% 1/2 duty 317 403 488 hz operating temperature t op ? -40 ? +85 c
fedl9228-01 oki semiconductor ml9228 7/25 electrical ch aracteristics dc characteristics (ta = ?40 to +85c, v dd = 5.0 v10%, v disp = 8.0 to 18.5 v) parameter symbol applied pin condition min. max. unit high level input voltage v ih *1) ? 0.7 v dd ? v low level input voltage v il *1) ? ? 0.3 v dd v l ih1 *2) v ih = v dd ?5.0 +5.0 high level input current l ih2 *3) v ih = v dd ?50 ?5.0 a l il1 *2) v il = 0.0 v ?5.0 +5.0 low level input current l il2 *3) v il = 0.0 v ?120 ?10 a v oh1 seg1 to 82 l oh1 = ?6 ma v disp ?0.8 ? v oh2 grid 1 to 3 l oh3 = ?6 ma v disp ?0.8 ? l oh4 = ?120 av dd ?0.8 ? high level output voltage v oh3 *4) v disp = 9.5v output open v dd ?0.2 ? v v ol1 seg1 to 82 l ol1 = 500 a ? 2.0 v ol2 grid 1 to 3 l ol3 = 10 ma ? 2.0 low level output voltage v ol3 *5) v disp = 9.5v l ol4 = 120 a ? 0.8 v i disp v disp r 2 = 10 k ? 5%, c 2 = 27 pf 5%, no load ? 500 a i dd v dd r 2 = 10 k ? 5%, c 2 = 27 pf 5% ? 5.0 ma i slp1 v disp sleep mode ? 5.0 a supply current i slp2 v dd sleep mode ? 5.0 a *1) cs, clock, data i/o, dup/ tri , blank , reset , col 1 to 6 *2) cs, clock, data i/o, dup/ tri , blank , reset *3) col 1 to 6 *4) data i/o, int *5) data i/o, int, row1 to 5
fedl9228-01 oki semiconductor ml9228 8/25 dc characteristics (ta = ?40 to +85c, v dd = 3.3 v10%, v disp = 8.0 to 18.5 v) parameter symbol applied pin condition min. max. unit high level input voltage v ih *1) ? 0.8 v dd ? v low level input voltage v il *1) ? ? 0.2 v dd v l ih1 *2) v ih = v dd ?5.0 +5.0 high level input current l ih2 *3) v ih = v dd -40 -5.0 a l il1 *2) v il = 0.0 v ?5.0 +5.0 low level input current l il2 *3) v il = 0.0 v -100 -5.0 a v oh1 seg1 to 82 l oh1 = ?6 ma v disp ?0.8 ? v oh3 grid 1 to 3 l oh3 = ?6 ma v disp ?0.8 ? l oh4 = ?100 av dd ?0.4 ? high level output voltage v oh3 *4) v disp = 9.5v output open v dd ?0.2 ? v v ol1 seg1 to 82 l ol1 = 500 a ? 2.0 v ol2 grid 1 to 3 l ol3 = 10 ma ? 2.0 low level output voltage v ol3 *5) v disp = 9.5v l ol4 = 100 a ? 0.4 v i disp v disp r 2 = 8.2 k ? 5%, c 2 = 27 pf 5%, no load ? 500 a i dd v dd r 2 = 8.2 k ? 5%, c 2 = 27 pf 5% ? 4.0 ma i slp1 v disp sleep mode ? 5.0 a supply current i slp2 v dd sleep mode ? 5.0 a *1) cs, clock, data i/o, dup/ tri , blank , reset , col 1 to 6 *2) cs, clock, data i/o, dup/ tri , blank , reset *3) col 1 to 6 *4) data i/o, int *5) data i/o, int, row1 to 5
fedl9228-01 oki semiconductor ml9228 9/25 ac characteristics (ta = ?40 to +85c, v dd = 5.0 v10%, v disp = 8.0 to 18.5 v) parameter symbol condition min. max. unit clock frequency f c ? ? 2.0 mhz clock pulse width t cw ? 200 ? ns data setup time t ds ? 200 ? ns data hold time t dh ? 200 ? ns cs off time t csl r 2 = 10 k ? 5%, c 2 = 27 pf 5% 20 ? s cs setup time (cs-clock) t css ? 200 ? ns cs hold time (clock-cs) t csh ? 200 ? ns data output delay time (clock-data l/o) t pd ? ? 1.0 s t r t r = 20 to 80% ? 2.0 s output slew rate time t f c l =100 pf t f = 80 to 20% ? 2.0 s v dd rise time t prz mounted in a unit ? 100 s v dd off time t pof mounted in a unit, v dd = 0.0 v 5.0 ? ms cs wait time t rsoff ? 400 ? s (ta = ?40 to +85c, v dd = 3.3 v10%, v disp = 8.0 to 18.5 v) parameter symbol condition min. max. unit clock frequency f c ? ? 1.0 mhz clock pulse width t cw ? 400 ? ns data setup time t ds ? 400 ? ns data hold time t dh ? 400 ? ns cs off time t csl r 2 = 8.2 k ? 5%, c 2 = 27 pf 5% 20 ? s cs setup time (cs-clock) t css ? 400 ? ns cs hold time (clock-cs) t csh ? 400 ? ns data output delay time (clock-data l/o) t pd ? ? 1.0 s t r t r = 20 to 80% ? 2.0 s output slew rate time t f c l =100 pf t f = 80 to 20% ? 2.0 s v dd rise time t prz mounted in a unit ? 100 s v dd off time t pof mounted in a unit, v dd = 0.0 v 5.0 ? ms cs wait time t rsoff ? 400 ? s
fedl9228-01 oki semiconductor ml9228 10/25 timing diagrams v dd = 3.3 v 10% v dd = 5.0 v 10% v ih 0.8 v dd 0.7 v dd v il 0.2 v dd 0.3 v dd data input timing data output timing power-on reset timing driver output timing t pof t prz v dd cs t rsoff ?0.8 v dd ?0.0 v ? v ih ? v il ? v ih ? v il ? v ih ? v il ? v ih ? v il cs clock data i/o (input) t ds t dh t css 1/f c t cw t cw t csh t csl valid valid valid valid ? v ih ? v il ? v ih ? v il ? v ih ? v il cs clock data i/o (output) t pd t css t csh ?0.8 v disp ?0.2 v disp seg1-82 t r t f ?v ih ?v il b lank t r t f g rid 1-3 ?0.8 v disp ?0.2 v disp
fedl9228-01 oki semiconductor ml9228 11/25 keyscan characteristics (ta = ?40 to +85c, v dd = 5.0 v10%, v disp = 8.0 to 18.5 v) parameter condition min. typ. max. unit keyscan cycle time r 2 = 10 k ? 5%, c 2 = 27 pf 5% 160 194 246 s keyscan pulse width r 2 = 10 k ? 5%, c 2 = 27 pf 5% 32 39 49 s (ta = ?40 to +85c, v dd = 3.3 v10%, v disp = 8.0 to 18.5 v) parameter condition min. typ. max. unit keyscan cycle time r 2 = 8.2 k ? 5%, c 2 = 27 pf 5% 160 194 246 s keyscan pulse width r 2 = 8.2 k ? 5%, c 2 = 27 pf 5% 32 39 49 s keyscan timing row1 row5 row2 row3 row4 keyscan cycle time keyscan pulse width
fedl9228-01 oki semiconductor ml9228 12/25 output timing (duplex operation) *1 bit time = 4/f osc solid line: when dimming data is made into 1016/1024 dotted line: when dimming da ta is made into 64/1024 output timing (triplex operation) *1 bit time = 4/f osc solid line: when dimming data is made into 1016/1024 dotted line: when dimming da ta is made into 64/1024 g ri d 1 v disp d-gnd g ri d 2 v disp d-gnd g ri d 3 seg1-82 v disp d-gnd v disp d-gnd 1016 bit times 1016 bit times 1016 bit times 2048 bit times1 (display cycle) 8 bit times 8 bit times 8 bit times 64 bit times 64 bit times 64 bit times g ri d 1 v disp d-gnd g ri d 2 v disp d-gnd g ri d 3 seg1-82 v disp d-gnd v disp d-gnd 1016 bit times 1016 bit times 1016 bit times 3072 bit times (1 display cycle) 8 bit times 8 bit times 8 bit times 64 bit times 64 bit times 64 bit times
fedl9228-01 oki semiconductor ml9228 13/25 functional description power-on reset when power is turned on, ml 9228 is in itialized by the internal power-on reset circuit. the status of the internal circuit after initialization is as follows: ? the contents of the shift registers and latches are set to ?0?. ? the digital dimming duty cycle is set to ?0?. ? all segment outputs are set to low level. ? grid1 output is set to low level. grid2,3 outputs are set to high level. ? all the row outputs are set to low level. ? int output is set to low level. reset when power is turned on, ml 9228 is in itialized by the internal power-on reset circuit. the status of the internal circuit after initialization is as follows: ? the contents of the shift registers and latches are set to ?0?. ? the digital dimming duty cycle is set to ?0?. ? all segment outputs are set to low level. ? grid1 output is set to low level. grid2,3 outputs are set to high level. ? all the row outputs are set to low level. ? int output is set to low level. ? a command is received by the signal of low(l-gnd) level. blank all segment outputs are set as a low level. ? a command is received by the signal of low(l-gnd) level. data input and output data input and output through the data-i/o pin is valid only when the cs pin is set at a high level. the input data to data i/o pin is shifted into the shift register at the rising edge of the serial clock. the data is automatically loaded to the latches when the cs pin is set at a low level. 10-bit dimming data (d1 to d10) and 82-bit segment data (s1 to s82) are used for inputting of dimming data and display data. to transfer these two data, the mode data (m0 to m2) must be sent after each of these data succeddingly. the output data from the data i/o pin is output from the shift register at the rising edge of the serial clock. ml9228 outputs 30-bit key data (s11 to s56). to r eceive these data, the mode data (m0 to m2) must be sent first and then cs must be set once to low level and set again to high level. then inputting serial clocks, these data are output from the data i/o pin. when the cs pin is set at a low level, the data i/o pin returns to an input pin. to stop the keyscan, the only mode data (m0 to m2) must be sent. after the mode data transfer, the key scanning is stopped immediately. cs clock keyscan stop command data i/o m0 m1 m2 m0 m1 m2 s44 s45 s51 s52 s53 s54 s55 s56 s11 s12 s13 s14 s15 s21 s22 switch data output command switch data
fedl9228-01 oki semiconductor ml9228 14/25 mode data ml9228 has the seven function modes. the function mode is selected by the mode data (m0 to m2). the relation between function mode and mode data (m0 to m2) is as follows: function data function mode operating mode m0 m1 m2 0 segment data for grid 1-3 input 0 0 0 1 segment data for grid 1 input 1 0 0 2 segment data for grid 2 input 0 1 0 3 segment data for grid 3 input 1 1 0 4 digital dimming data input 0 0 1 5 keyscan stop 1 0 1 6 switch data output 0 1 1 7 sleep 1 1 1
fedl9228-01 oki semiconductor ml9228 15/25 segment data input [function mode: 0 to 3] ? ml9228 r eceives the segment data when function mode 0 to 3 are selected. ? the same segment data is transferred to the 3 segment data latch correspond to grid 1 to 3 at the same time when the function mode 0 is selected. ? the segment data is transferred to only one segment data latch that is selected by mode data, when the function mode is 1, 2 or 3 is selected. ? segment output (seg1 to 82) becomes high level when the segment data (s1 to s82) is high level. [data format] input data : 85 bits segment data : 82 bits mode data : 3 bits bit 1 2 3 4 ----------- 79 80 81 82 83 84 85 input data s1 s2 s3 s4 ----------- s79 s80 s81 s82 m0 m1 m2 segment data (82 bits) mode data (3 bits) [bit correspondence between segment output and segment data] seg n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 segment data s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 seg n 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 segment data s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 s32 seg n 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 segment data s33 s34 s35 s36 s37 s38 s39 s40 s41 s42 s43 s44 s45 s46 s47 s48 seg n 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 segment data s49 s50 s51 s52 s53 s54 s55 s56 s57 s58 s59 s60 s61 s62 s63 s64 seg n 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 segment data s65 s66 s67 s68 s69 s70 s71 s72 s73 s74 s75 s76 s77 s78 s79 s80 seg n 81 82 segment data s81 s82
fedl9228-01 oki semiconductor ml9228 16/25 digital dimming data input [function mode: 4] ? ml9228 r eceives the digital d imming data when function mode 4 is selected. ? the output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. ? the 10-bit digital dimming data is input from lsb. [data format] input data : 13 bits digital dimming data : 10 bits mode data : 3 bits bit 1 2 3 4 5 6 7 8 9 10 11 12 13 input data d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 m0 m1 m2 lsb msb digital dimming data (10 bits) mode data (3 bits) (lsb) dimming data (msb) d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 duty cycle 0 0 0 0 0 0 0 0 0 0 0/1024 1 0 0 0 0 0 0 0 0 0 1/1024 1 1 1 0 1 1 1 1 1 1 1015/1024 0 0 0 1 1 1 1 1 1 1 1016/1024 1 0 0 1 1 1 1 1 1 1 1016/1024 1 1 1 1 1 1 1 1 1 1 1016/1024 keyscan stop [function mode: 5] ? ml9228 stops a key scanning when function mode 5 are selected. ? to select this mode, the only mode data (m0 to m2) is needed. ? the actual time lag range between receipt of the keyscan stop command and the ceasing of scanning is 2.4 s to 3.6 s [input data format] input data : 3 bits mode data : 3 bits bit 83 84 85 input data m0 m1 m2 mode data (3 bits)
fedl9228-01 oki semiconductor ml9228 17/25 switch data output [function mode: 6] ? ml9228 output the switch data when function mode 6 is selected. ? to select this mode, the only mode data (m0 to m2) is needed. ? when ml9228 recieves this mode, the data i/o pin is changed to an output pin. ? 30-bit switch data come out from the data i/o pin synchronizing with the rise edge of the clock. ? when the cs pin is set at the low level, the data i/o pin returns to an input pin. ? contact count bits are q1 (lsb) to q3 (msb) [input data format] input data : 3 bits mode data : 3 bits bit 83 84 85 input data m0 m1 m2 mode data (3 bits) [output data format] output data : 30 bits 5 6 push switch data : 30 bits bit 1 2 3 4 5 6 7 8 9 10 11 12 output data s11 s12 s13 s14 s15 s16 s21 s22 s23 s24 s25 s26 bit 13 14 15 16 17 18 19 20 21 22 23 24 output data s31 s32 s33 s34 s35 s36 s41 s42 s43 s44 s45 s46 bit 25 26 27 28 29 30 output data s51 s52 s53 s54 s55 s56 sij: i = row1 to 5, j = col 1 to 6 sij = 1: switch on sij = 0: switch off [5 6push switch] = c ol 1 c ol 2 c ol 3 c ol 4 row1 row2 row3 row4 row5 c ol 5 c ol 6
fedl9228-01 oki semiconductor ml9228 18/25 p-in/s-out shift resistor when the switch data output mode is selected and cs goes l, all the key data send to the shift resistor, and the up/down counter is reset and the int signal goes ?l?. cs data i/o clock when cs goes l, the up/down counter is reset and the int goes ?l?. int c1 c2 c3 c4 c5 c6 row1 row4 row5 c1 c2 c3 c4 c5 c6 c1 c2 c3 c4 c5 c6
fedl9228-01 oki semiconductor ml9228 19/25 keyscan keyscanning is started only when depression or release of any key is detected in order to minimize noise caused by scanning signal. then, keyscanning is continued until the keyscan stop mode is sent from a microcomputer. the int pin goes to the high level at the completion of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the int pin can be used as an interrupt signal. [keyscan timing] note: keyscanning cannot be stopped by selecting the keyscan stop mode only once if: - keyscanning is started after depression or release of any key is detected, and then - a key is depressed or released again before the keyscan stop mode is selected. to stop keyscanning, it is required to select the keyscan stop mode once again. 1 cycle int row 5 row 4 row 3 row 2 row 1 depress/release keyscan stop mode is selected. depress depress release keyscan keyscan int cs mode5 mode5 mode5 mode5 : keyscan stop keyscan
fedl9228-01 oki semiconductor ml9228 20/25 sleep [function mode: 7] ? ml9228 oscilla tion stops and segment display turns off when function mode 7 is selected. ? key matrix is pushed, this mode will be canceled and it will usually become display mode. [input data format] input data : 3 bits mode data : 3 bits bit 83 84 85 input data m0 m1 m2 mode data (3 bits) wake up ? wake up by key press from col 6. then, key scan is performed. ? wake up by cs assert(rising edge). then, key scan does not carry out. ? oscillation restarts to a ccept normal operation. ? previous output for display data till updated by each mode. if either of these keys is pushed, an oscillation will be started and it will usually return to operation. c ol 1 c ol 2 c ol 3 c ol 4 row1 row2 row3 row4 row5 c ol 5 c ol 6 =
fedl9228-01 oki semiconductor ml9228 21/25 application circuits circuit for the triplex vfd tube with 246 segments (3 grid 82 anode) ml9228 v disp v dd l-gnd clock data i/o cs grid 2 grid 1 grid 3 seg1 seg82 triplex vfd tube s80 s81 s82 s1 s2 s3 g1 g2 v disp ef gnd gnd osc0 v dd row1 to 5 c ol 1 to 6 5 6 key matrix b lank g3 dup/ tri microcontroller r eset v dd d-gnd
fedl9228-01 oki semiconductor ml9228 22/25 power sequence ? if the power sequence (please see below) recommended by oki is not followed,it is possible to damage internal logic transistors. ? currently there is no definition for the time period between the point that v dd = 3.3v v disp = 3.3v. ? oki recommends the following sequence. 18.0v 3.3 v 2.0 0
fedl9228-01 oki semiconductor ml9228 23/25 package dimensions qfp128-p-1420-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 1.19 typ. 5 rev. no./last revised 4/nov. 28, 1996 notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ( unit: mm )
fedl9228-01 oki semiconductor ml9228 24/25 revision history page document no. date previous edition current edition description fedl9228-01 oct. 20, 2004 ? ? final edition 1
fedl9228-01 oki semiconductor ml9228 25/25 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and n ecessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2004 oki electric industry co., ltd.

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