View AT29010A_708405.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

at29c010a 1 megabit (128k x 8) 5-volt only cmos flash memory features fast read access time - 70 ns 5-volt-only reprogramming sector program operation single cycle reprogram (erase and program) 1024 sectors (128 bytes/sector) internal address and data latches for 128-bytes two 8 kb boot blocks with lockout internal program control and timer hardware and software data protection fast sector program cycle time - 10 ms data polling for end of program detection low power dissipation 50 ma active current 100 m a cmos standby current typical endurance > 10,000 cycles single 5v 10% supply cmos and ttl compatible inputs and outputs commercial and industrial temperature ranges description the at29c010a is a 5-volt-only in-system flash programmable and erasable read only memory (perom). its 1 megabit of memory is organized as 131,072 words by 8 bits. manufactured with atmels advanced nonvolatile cmos technology, the device offers access times to 70 ns with power dissipation of just 275 mw over the commer- cial temperature range. when the device is deselected, the cmos standby current is less than 100 m a. the device endurance is such that any sector can typically be writ- ten to in excess of 10,000 times. to allow for simple in-system reprogrammability, the at29c010a does not require high input voltages for programming. five-volt-only commands determine the opera- (continued) dip top view tsop top view type 1 pin configurations pin name function a0 - a16 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect plcc top view 0394b at29c010a 4-129
(continued) tion of the device. reading data out of the device is similar to reading from an eprom. reprogramming the at29c010a is performed on a sector basis; 128-bytes of data are loaded into the device and then simultaneously programmed. during a reprogram cycle, the address locations and 128- bytes of data are internally latched, freeing the address and data bus for other operations. following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. the end of a program cycle can be detected by data polling of i/o7. once the end of a program cycle has been detected, a new access for a read or program can begin. description (continued) device operation read: the at29c010a is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual- line control gives designers flexibility in preventing bus contention. byte load: byte loads are used to enter the 128- bytes of a sector to be programmed or the software codes for data protection. a byte load is performed by applying a low pulse on the we or ce input with ce or we low (re- spectively) and oe high. the address is latched on the falling edge of ce or we, whichever occurs last. the data is latched by the first rising edge of ce or we. program: the device is reprogrammed on a sector basis. if a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. the data in any byte that is not loaded during the program- ming of its sector will be indeterminate. once the bytes of a sector are loaded into the device, they are simultane- ously programmed during the internal programming pe- riod. after the first data byte has been loaded into the de- vice, successive bytes are entered in the same manner. each new byte to be programmed must have its high to low transition on we (or ce) within 150 m s of the low to high transition of we (or ce) of the preceding byte. if a high to low transition is not detected within 150 m s of the last low to high transition, the load period will end and the internal programming period will start. a7 to a16 specify the sector address. the sector address must be valid dur- ing each high to low transition of we (or ce). a0 to a6 specify the byte address within the sector. the bytes may block diagram be loaded in any order; sequential loading is not required. once a programming operation has been initiated, and for the duration of t wc , a read operation will effectively be a polling operation. software data protection: a software control- led data protection feature is available on the at29c010a. once the software protection is enabled a software algo- rithm must be issued to the device before a program may be performed. the software protection feature may be en- abled or disabled by the user; when shipped from atmel, the software data protection feature is disabled. to enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. after the software data protection is en- abled the same three program commands must begin each program cycle in order for the programs to occur. all software program commands must obey the sector pro- gram timing specifications. once set, the software data protection feature remains active unless its disable com- mand is issued. power transitions will not reset the soft- ware data protection feature, however the software fea- ture will guard against inadvertent program cycles during power transitions. once set, software data protection will remain active un- less the disable command sequence is issued. after setting sdp, any attempt to write to the device with- out the 3-byte command sequence will start the internal write timers. no data will be written to the device; however, for the duration of t wc , a read operation will effectively be a polling operation. 4-130 at29c010a
(continued) temperature under bias................. -55 c to +125 c storage temperature...................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ................... -0.6v to +6.25v all output voltages with respect to ground .............-0.6v to v cc + 0.6v voltage on oe with respect to ground ................... -0.6v to +13.5v *notice: stresses beyond those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings* after the software data protections 3-byte command code is given, a byte load is performed by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we, whichever occurs last. the data is latched by the first rising edge of ce or we. the 128-bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation. hardware data protection: hardware features protect against inadvertent programs to the at29c010a in the following ways: (a) v cc sense if v cc is below 3.8v (typical), the program function is inhibited. (b) v cc power on delay once v cc has reached the v cc sense level, the device will automatically time out 5 ms (typical) before programming. (c) program inhibit holding any one of oe low, ce high or we high inhibits program cycles. (d) noise filter pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. product identification: the product identifica- tion mode identifies the device and manufacturer as at- mel. it may be accessed by hardware or software opera- tion. the hardware operation mode can be used by an ex- ternal programmer to identify the correct programming al- gorithm for the atmel product. in addition, users may wish to use the software product identification mode to identify the part (i.e. using the device code), and have the system software use the appropriate sector size for program op- erations. in this manner, the user can have a common board design for 256k to 4-megabit densities and, with each densitys sector size in a memory map, have the sys- tem software apply the appropriate sector size. for details, see operating modes (for hardware operation) or software product identification. the manufacturer and device code is the same for both modes. data polling: the at29c010a features data poll- ing to indicate the end of a program cycle. during a pro- gram cycle an attempted read of the last byte loaded will device operation (continued) result in the complement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the program cycle. toggle bit: in addition to data p o l l i n g t h e at29c010a provides another method for determining the end of a program or erase cycle. during a program or erase operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a program cycle. optional chip erase mode: the entire device can be erased by using a 6-byte software code. please see software chip erase application note for details. boot block programming lockout: the at29c010a has two designated memory blocks that have a programming lockout feature. this feature prevents pro- gramming of data in the designated block once the feature has been enabled. each of these blocks consists of 8k bytes; the programming lockout feature can be set inde- pendently for either block. while the lockout feature does not have to be activated, it can be activated for either or both blocks. these two 8k memory sections are referred to as boot blocks . secure code which will bring up a system can be contained in a boot block. the at29c010a blocks are lo- cated in the first 8k bytes of memory and the last 8k bytes of memory. the boot block programming lockout feature can therefore support systems that boot from the lower addresses of memory or the higher addresses. once the programming lockout feature has been activated, the data in that block can no longer be erased or programmed; data in other memory locations can still be changed through the regular programming methods. to activate the lockout feature, a series of seven program commands to specific addresses with specific data must be performed. please see boot block lockout feature enable algorithm. if the boot block lockout feature has been activated on either block, the chip erase function will be disabled. at29c010a 4-131
device operation (continued) operating modes mode ce oe we ai i/o read v il v il v ih ai d out program (2) v il v ih v il ai d in 5v chip erase v il v ih v il ai standby/write inhibit v ih x (1) x x high z program inhibit x x v ih program inhibit x v il x output disable x v ih x high z product identification hardware v il v il v ih a1 - a16 = v il , a9 = v h , (3) a0 = v il manufacturer code (4) a1 - a16 = v il , a9 = v h , (3) a0 = v ih device code (4) software (5) a0 = v il manufacturer code (4) a0 = v ih device code (4) 4. manufacturer code: 1f, device code: d5 5. see details under software product identification entry/exit. notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 10 m a i lo output leakage current v i/o = 0v to v cc 10 m a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc com. 100 m a ind. 300 m a i sb2 v cc standby current ttl ce = 2.0v to v cc 3ma i cc v cc active current f = 5 mhz; i out = 0 ma 50 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma .45 v v oh1 output high voltage i oh = -400 m a 2.4 v v oh2 output high voltage cmos i oh = -100 m a; v cc = 4.5v 4.2 v dc and ac operating range at29c010a-70 at29c010a-90 at29c010a-12 at29c010a-15 operating temperature (case) com. 0 c - 70 c0 c - 70 c0 c - 70 c0 c - 70 c ind. -40 c - 85 c-40 c - 85 c-40 c - 85 c v cc power supply 5v 5% 5v 10% 5v 10% 5v 10% boot block lockout detection: a software method is available to determine whether programming of either boot block section is locked out. see software prod- uct identification entry and exit sections. when the device is in the software product identification mode, a read from location 00002 will show if programming the lower address boot block is locked out while reading location ffff2 will do so for the upper boot block. if the data is fe, the corre- sponding block can be programmed; if the data is ff, the program lockout feature has been activated and the corre- sponding block cannot be programmed. the software product identification exit mode should be used to return to standard operation. 4-132 at29c010a
ac read characteristics at29c010a-70 at29c010a-90 at29c010a-12 at29c010a-15 symbol parameter min max min max min max min max units t acc address to output delay 70 90 120 150 ns t ce (1) ce to output delay 70 90 120 150 ns t oe (2) oe to output delay 0 35 0 40 0 50 0 70 ns t df (3, 4) ce or oe to output float 0 25 0 25 0 30 0 40 ns t oh output hold from oe, ce or address, whichever occurred first 0000ns notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read waveforms (1, 2, 3, 4) t r , t f < 5 ns input test waveforms and measurement level output test load 70 ns 90/120/150 ns pin capacitance (f = 1 mhz, t = 25c) (1) typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v note: 1. this parameter is characterized and is not 100% tested. at29c010a 4-133
ac byte load characteristics symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width ( we or ce) 90 ns t ds data set-up time 35 ns t dh , t oeh data, oe hold time 0 ns t wph write pulse width high 100 ns ac byte load waveforms we controlled ce controlled 4-134 at29c010a
program cycle characteristics symbol parameter min max units t wc write cycle time 10 ms t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 35 ns t dh data hold time 0 ns t wp write pulse width 90 ns t blc byte load cycle time 150 m s t wph write pulse width high 100 ns program cycle waveforms (1, 2, 3) notes: 1. a7 through a16 must specify the sector address during each high to low transition of we (or ce). 2. oe must be high when we and ce are both low. 3. all bytes that are not loaded within the sector being programmed will be indeterminate. at29c010a 4-135
software protected program cycle waveform (1, 2, 3) notes: 1. a7 through a16 must specify the sector address during each high to low transition of we (or ce) after the software code has been entered. 2. oe must be high when we and ce are both low. 3. all bytes that are not loaded within the sector being programmed will be indeterminate. load data to sector (128 bytes) (4) load data a0 to address 5555 load data 55 to address 2aaa load data aa to address 5555 notes for software program code: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. data protect state will be activated at end of program cycle. 3. data protect state will be deactivated at end of program period. 4. 128-bytes of data must be loaded. enter data protect state (2) writes enabled software data protection enable algorithm (1) load data to sector (128 bytes) (4) load data 55 to address 2aaa load data aa to address 5555 load data 80 to address 5555 load data 55 to address 2aaa load data aa to address 5555 load data 20 to address 5555 exit data protect state (3) software data protection disable algorithm (1) 4-136 at29c010a
toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. toggle bit waveforms (1, 2, 3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling waveforms at29c010a 4-137
pause 10 ms load data 90 to address 5555 load data 55 to address 2aaa load data aa to address 5555 notes for software product identification: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. a1 - a16 = v il . manufacture code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code: 1f device code: d5 enter product identification mode (2, 3, 5) software product identification entry (1) pause 10 ms load data f0 to address 5555 load data 55 to address 2aaa load data aa to address 5555 exit product identification mode (4) software product identification exit (1) load data 80 to address 5555 load data 55 to address 2aaa boot block lockout feature enable algorithm (1) notes for boot block lockout feature enable: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. lockout feature set on lower address boot block. 3. lockout feature set on higher address boot block. load data aa to address 5555 load data 55 to address 2aaa load data aa to address 5555 pause 10 ms load data ff to address fffff (3) pause 10 ms load data 00 to address 00000 (2) load data 40 to address 5555 4-138 at29c010a
at29c010a 4-139
t acc (ns) i cc (ma) ordering code package operation range active standby 70 50 0.1 at29c010a-70jc 32j commercial at29c010a-70pc 32p6 (0 to 70 c) at29c010a-70tc 32t 90 50 0.1 at29c010a-90jc 32j commercial at29c010a-90pc 32p6 (0 to 70 c) at29c010a-90tc 32t 50 0.3 at29c010a-90ji 32j industrial at29c010a-90pi 32p6 (-40 to 85 c) at29c010a-90ti 32t 120 50 0.1 at29c010a-12jc 32j commercial at29c010a-12pc 32p6 (0 to 70 c) at29c010a-12tc 32t 50 0.3 at29c010a-12ji 32j industrial at29c010a-12pi 32p6 (-40 to 85 c) at29c010a-12ti 32t 150 50 0.1 at29c010a-15jc 32j commercial at29c010a-15pc 32p6 (0 to 70 c) at29c010a-15tc 32t 50 0.3 at29c010a-15ji 32j industrial at29c010a-15pi 32p6 (-40 to 85 c) at29c010a-15ti 32t package type 32j 32 lead, plastic j-leaded chip carrier (plcc) 32p6 32 lead, 0.600" wide, plastic dual inline package (pdip) 32t 32 lead, thin small outline package (tsop) 4-140 at29c010a

▲Up To Search▲

Price & Availability of AT29010A

	To Download AT29010A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .