the information provided herein is believed to be reliable at press time. sirenza microdevices assumes no responsibility for in accuracies or ommisions. sirenza microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at t he user?s own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. sirenza microdevices does not authorize or warrant any sirenza microdevices product for use in life-support devices and/or systems. copyright 2005 sirenza microdevices, inc. all worldwide rights reserved. 303 s. technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com 1 eds-103754 rev d preliminary the SLD2083CZ is a 10 watt high performance ldmos transistor designed for operation to 2700mhz. it is an excelle nt solution for applica- tions requiring high linearity and efficiency at a low cost. the SLD2083CZ is typically used in the design of driver stages for power amplifiers, repeaters, and rfid applications. the power transistor is fabricated using sirenza?s high per- formance xemos ii tm process. rf specifications parameter description: test conditions in sirenza evaluation board v ds = 28.0v, i dq = 125ma, t flange = 25oc unit min typ max frequency frequency of operation mhz - - 2700 gain 10 watt cw, 902mhz-928mhz db 17 18 - efficiency drain efficiency at 10 watt cw, 915mhz % 40 47 - irl input return loss, 10 watt output power, 915mhz db - -15 -10 linearity 3 rd order imd at 10 watt pep (two tone), 915mhz dbc - -28 -26 1db compression (p 1db ), 915mhz watt 10 11 - acpr=-55db, is-95 watt 1.8 1.6 - acpr=-45db, is-95 watt 3.2 3.6 - functional schematic diagram SLD2083CZ 10 watt discrete ldmos device ceramic package product features applications ? 10 watt output p 1db ? single polarity supply voltage ? high gain: 18 db typical ? high efficiency ? advanced, xemos ii ldmos ? integrated esd protection, class 1a ? base station pa driver ? repeater ? rfid product description case flange = ground esd protection pb rohs compliant & packag e green
303 s. technology court, broomfield, co 8002 1 phone: (800) smi-mmic http://www.sirenza.com 2 eds-103754 rev d preliminary SLD2083CZ 10 watt ldmos fet pin description pin # function description 1gate transistor rf input and gate bias voltage. the gate bias voltage must be temperature compensated to main- tain constant bias current over the operating temperature range. care must be taken to protect against video transients that exceed the recommended maximum input power or voltage. . 2 drain transistor rf output and drain bias voltage. typical voltage is 28v. flange source, gnd exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for optimum thermal and rf performance. see mounting instructions for recommendation. absolute maximum ratings parameters value unit drain voltage (v ds )35v gate voltage (v gs )20v rf input power +33 dbm load impedance for continuous operation without damage 10:1 vswr output device channel temperature +200 oc lead temperature during solder reflow +270 oc operating temperature range -20 to +90 oc storage temperature range -40 to +100 oc operation of this device beyond any one of these limits may cause permanent damage. for reliable continuous operation see typical setup values specified in the table on page one. caution: esd sensitive appropriate precaution in handling, packaging and testing devices must be observed. dc specifications parameter unit min typical max g m forward transconductance @ 125ma i dq ma / v 590 v gs threshold i ds =3ma volt 3.8 v ds breakdown 1ma i ds current volt 65 c iss input capacitance (gate to source) v gs =0v, v ds =28v pf 27.5 c rss reverse capacitance (gate to drain) v gs =0v, v ds =28v pf 0.81 c oss output capacitance (drain to source) v gs =0v, v ds =28v pf 14.65 r dson drain to source resistance, v gs =10v, v ds =250mv 0.6 case flange = ground esd protection pin diagram pin 1 pin 2 quality specifications parameter unit min typical max esd rating human body model volts 500 mttf 85 o c leadframe, 200 o c channel hours 1.2 x 10 6 r th thermal resistance (junction to case) oc/w 4
303 s. technology court, broomfield, co 8002 1 phone: (800) smi-mmic http://www.sirenza.com 3 eds-103754 rev d preliminary SLD2083CZ 10 watt ldmos fet typical evb test data gain, efficiency vs. output power freq=915mhz, tem p=25 o c, v ds =28v, i dq =125ma 19.4 19.5 19.6 19.7 19.8 19.9 20 02468101214 output power (w) gain (db ) 0 10 20 30 40 50 60 efficiency (% ) gain efficiency gain vs. frequency and temperature pout=10w, v ds =28v, i dq =125ma 17.5 18 18.5 19 19.5 20 900 905 910 915 920 925 930 frequency (mhz) gain (db ) 90 deg c 25 deg c -20 deg c two tone im3 vs. output power freq=915/916mhz, temp=25 o c, v ds =28v, i dq =125ma -55.0 -50.0 -45.0 -40.0 -35.0 -30.0 -25.0 -20.0 0.0 2.0 4.0 6.0 average output power (w) imd3(dbc) 902mhz 915mhz 928mhz
303 s. technology court, broomfield, co 8002 1 phone: (800) smi-mmic http://www.sirenza.com 4 eds-103754 rev d preliminary SLD2083CZ 10 watt ldmos fet to download gerber files, dxf drawings, a detailed bom, and assembly recommendations for the test board with fixture contact sirenza applications. SLD2083CZ evb layout and bom de s cr i p t i o n par t res, 10, 1/10w, 1%, 0805 r10 g po l a r i z e d j1 inductor coilcraf t 1.6nh 0603 l1 res, 0.0, 1/16w, 5%, 0603 r2, r4, r6, r7, r9, r11 cap, 1000 pf, 100v, 10%, 0603 c7, c8 cap, 0.01 uf, 100v, 5%, 0805 c10, c15 cap, 0.5 pf, 250v, +/-.1pf, 0603 c11 cap, 3.6 pf, 250v, +/-.1pf, 0603 c14 cap, 12 pf, 250v, 1%, 0603 c2 cap, 15 pf, 250v, 2%, 0603 c1 cap, 68 pf, 250v, 5%, 0603 c3, c4, c5, c6 res, 10 ohm, 0402 r5, r15 cap 0.22uf 50v ceramic x7r 1206 c13, c16 SLD2083CZ q1 evaluation board bill of materials impedance information (typical) frequency (mhz) input r (ohms) input x (ohms) output r (ohms) output x (ohms) 870 0.5 2.0 4.3 1.9 880 0.5 1.9 4.3 2.0 900 0.8 1.8 4.4 2.0 930 0.7 1.7 4.5 2.0 960 0.8 1.4 4.7 2.0 impedances are circuit impedances as seen from device at device lead.
303 s. technology court, broomfield, co 8002 1 phone: (800) smi-mmic http://www.sirenza.com 5 eds-103754 rev d preliminary SLD2083CZ 10 watt ldmos fet package outline drawings recommended landing pads for the rf083 package all dimensions are in inches part number ordering information part number devices per reel reel size SLD2083CZ 500 7?? top view side view end view 0.290 0.160 0.160 0.090 0.160 0.140 0.008 detail a 0.200 0.100 0.050 detail a 0.0000.002 r0.015 lead coplanarity lead foot to backside 0.000 0.002 chamferred lead is fet drain
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