utron UT61L5128 rev. 1.2 512k x 8 bit high speed cmos sram utron technology inc. p80061 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 1 ? revision history revision description draft date preliminary rev. 0.1 original. jun 5, 2001 preliminary rev.1.0 1.add test condition for i sb. 2.add note to vcc for access time=10ns. jun 23,2001 preliminary rev.1.1 1.revised access time : 10/12/15 ns 8ns (max.) for vcc=3.15v~3.6v 10ns (max.) for vcc=3.0v~3.6v 2.add cmos low power operating : operating current : 260/220ma (icc max.) standby current : 10/2ma(max.) 3.add data retention characteristics 4.revised terminal voltage with respect to vss(v term ) : -0.5 to v cc +0.5 -0.5 to 4.6 5.revised input high voltage (v ih ): 2.2(min)/vcc+0.5(max) 2.0(min)/vcc+0.3(max) sep 06,2002 rev.1.2 1. revised standby current : 10/2ma(max) 0.5ma(typ.) 2. delete i cc1 , i cc2 3. revised i sb : 30ma 3ma, i sb1 :10ma 2ma, 4. add i sb & i sb1 (typ.) : 1ma & 2ma 5. add overshoot : v ih +6.0v for t trc /2. undershoot : v il -2.0v for t trc /2. 6. revised data retention i dr (max) : 3ma 1ma 7. add order information for lead free product may 20,2003
utron UT61L5128 rev. 1.2 512k x 8 bit high speed cmos sram utron technology inc. p80061 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 2 ? features fast access time : 8ns (max.) for vcc=3.15v~3.6v 10/12ns (max.) for vcc=3.0v~3.6v cmos low operating power operating current : 260/240/220 ma (icc max.) standby current : 0.5 ma (typ.) single 3.0v~3.6v power supply operating temperature : commercial : 0 j ~70 j all ttl compatible inputs and outputs fully static operation three state outputs data retention voltage : 2v (min.) data byte control : lb (i/o1~i/o8) ub (i/o9~i/o16) package : 44-pin 400mil tsop-ii functional block diagram decoder i/o data circuit control circuit 512k x 8 memory array column i/o a0-a18 vcc vss i/o1-i/o8 ce oe we pin description symbol description a0 - a18 address inputs i/o1 - i/o8 data inputs/outputs ce chip enable inputs 5?5u write enable input 55u output enable input v cc power supply v ss ground nc no connection general description the UT61L5128 is a 4,194,304-bit high-speed cmos static random access memory organized as 524,288 words by 8 bits. it is fabricated using high performance, high reliability cmos technology. the UT61L5128 is designed for high-speed system applications. it is particularly suited for use in high-density high-speed system applications. the UT61L5128 operates from a single 3.0v~3.6v power supply and all inputs and outputs are fully ttl compatible. pin configuration a1 a2 a3 a4 i/o1 i/o2 i/o3 i/o4 vcc vss a17 a16 vss vcc tsop-ii 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 a15 a0 a5 a6 a7 a8 a9 a14 a13 a12 a10 nc 34 29 30 31 32 33 44 39 40 41 42 43 35 36 37 38 a11 i/o5 i/o6 i/o8 i/o7 nc nc nc nc nc a18 nc nc nc nc ce oe we UT61L5128
utron UT61L5128 rev. 1.2 512k x 8 bit high speed cmos sram utron technology inc. p80061 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 3 ? absolute maximum ratings * parameter symbol rating unit terminal voltage with respect to vss v term -0.5 to 4.6 v operating temperature t a 0 to 70 j storage temperature t stg -65 to 150 j power dissipation p d 1 w dc output current i out 50 ma soldering temperature (under 10 sec) tsolder 260 j *stress greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device or an y other conditions above those i ndicated in the operational sections of this specification is not im plied. exposure to the absolute maximum ra ting conditions for extended period may affec t device reliability. truth table mode ce 55u 5?5u i/o operation supply current standby h x x high - z i sb ,i sb1 output disable l h h high - z i cc read l l h d out i cc write l x l d in i cc note: h = v ih , l=v il , x = don't care. dc electrical characteristics (t a = 0 j to 70 j ) parameter symbol test condition min. typ. max. unit power voltage vcc 3.0 3.3 3.6 v input high voltage v ih *1 2.0 - v cc +0.3 v input low voltage v il *2 -0.3 - 0.8 v input leakage current i li v ss ?? v in ?? v cc - 1 - 1 a output leakage current i lo v ss ?? v i/o ?? v cc; output disabled - 1 - 1 a output high voltage v oh i oh = -4ma 2.4 - - v output low voltage v ol i ol = 8ma - - 0.4 v -8 - 260 ma -10 - 240 ma operating power supply current i cc cycle time=min, 100%duty, i/o=0ma, ce =v il -12 - 220 ma standby current (ttl) i sb ce =v ih, other pins =v il or v ih - 1 3 ma standby current (cmos) i sb1 ce =v cc -0.2v, other pins at 0.2v or vcc-0.2v - 0.5 2 ma notes: 1. overshoot : vcc+3.0v for pulse width less than 6ns. 2. undershoot : vss-3.0v for pulse width less than 6ns. 3. overshoot and undershoot ar e sampled, not 100% tested.
utron UT61L5128 rev. 1.2 512k x 8 bit high speed cmos sram utron technology inc. p80061 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 4 ? capacitance (t a =25 j , f=1.0mhz) parameter symbol min. max. unit input capacitance c in - 8 pf input/output capacitance c i/o - 10 pf note : these parameters are guaranteed by device characterization, but not production tested. ac test conditions input pulse levels 0v to 3.0v input rise and fall times 3ns input and output timing reference levels 1.5v output load c l =30pf, i oh /i ol =-4ma/8ma ac electrical characteristics (t a = 0 j to 70 j ) (1) read cycle UT61L5128-8 3.15v~3.6v UT61L5128-10 3.0v~3.6v UT61L5128-12 3.0v~3.6v parameter symbol min. max. min. max. min. max. unit read cycle time t rc 8 - 10 - 12 - ns address access time t aa - 8 - 10 - 12 ns chip enable access time t ace - 8 - 8 - 8 ns output enable access time t oe - 4 - 5 - 6 ns chip enable to output in low z t clz* 3 - 3 - 3 - ns output enable to output in low z t olz* 0 - 0 - 0 - ns chip disable to output in high z t chz* - 4 - 5 - 6 ns output disable to output in high z t ohz* - 4 - 5 - 6 ns output hold from address change t oh 3 - 3 - 3 - ns (2) write cycle UT61L5128-8 3.15v~3.6v UT61L5128-10 3.0v~3.6v UT61L5128-12 3.0v~3.6v parameter symbol min. max. min. max. min. max. unit write cycle time t wc 8 - 10 - 12 - ns address valid to end of write t aw 7 - 8 - 9 - ns chip enable to end of write t cw 7 - 8 - 9 - ns address set-up time t as 0 - 0 - 0 - ns write pulse width t wp 7 - 8 - 9 - ns write recovery time t wr 0 - 0 - 0 - ns data to write time overlap t dw 5.5 - 6 - 7 - ns data hold from end of write time t dh 0 - 0 - 0 - ns output active from end of write t ow* 3 - 3 - 0 - ns write to output in high z t whz* - 4 - 5 - 6 ns *these parameters are guaranteed by device char acterization, but not production tested.
utron UT61L5128 rev. 1.2 512k x 8 bit high speed cmos sram utron technology inc. p80061 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 5 ? timing waveforms read cycle 1 (address controlled) (1,2,4) t o h t rc t aa t o h data valid address dout read cycle 2 ( ce , and oe controlled) (1,3,5,6) notes : 1. 5?5u is high for a read cycle. 2. device is continuously selected ce =v il . 3. address must be valid prior to or coincident with ce transition; otherwise t aa is the limiting parameter. 4. 55u is low. 5. t clz, t olz , t chz and t ohz are specified with c l =5pf. transition is measured ? 500mv from steady state. 6. at any given temperature and voltage condition, t chz is less than t clz , t ohz is less than t olz. t rc t aa t ace t oe t chz t ohz t clz t oh t olz high-z data valid high-z address ce oe dout
utron UT61L5128 rev. 1.2 512k x 8 bit high speed cmos sram utron technology inc. p80061 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 6 ? write cycle 1 ( 5?5u controlled) (1,2,3,5,6) t wc t aw t cw t as t wp t whz t ow t wr high-z (4) (4) address ce we dout din data valid t dw t dh write cycle 2 ( ce controlled) (1,2,5) t wc t aw t cw t as t wr t wp t whz t dw t dh data valid address dout din high-z ce we notes : 1. 5?5u or ce must be high during all address transitions. 2. a write occurs during the overlap of a low ce , and a low 5?5u . 3. during a 5?5u controlled with write cycle with 55u low, t wp must be greater than t whz +t dw to allow the i/o drivers to turn off and data to be placed on the bus. 4. during this period, i/o pins are in the out put state, and input signals must not be applied. 5. if the ce low transition occurs simultaneously with or after 5?5u low transition, the outputs remain in a high impedance state. 6. t ow and t whz are specified with c l =5pf. transition is measured ? 500mv from steady state.
utron UT61L5128 rev. 1.2 512k x 8 bit high speed cmos sram utron technology inc. p80061 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 7 ? data retention characteristics (t a = 0 j to +70 j ) parameter symbol test condition min. max. unit vcc for data retention v dr ce ? v cc -0.2v , 2.0 3.6 v data retention curren t i dr vcc=2v ce ? v cc -0.2v , - 1 ma chip disable to data retention time t cdr see data retention waveforms (below) 0 - ms recovery time t r 5 - ms data retention waveform low vcc data retention waveform (1) ( ce controlled) vdr ? 2v ce ? v cc -0.2v v cc(min.) v cc(min.) v ih v ih v cc t r t cdr ce
utron UT61L5128 rev. 1.2 512k x 8 bit high speed cmos sram utron technology inc. p80061 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 8 ? package outline dimension 44-pin 400mil tsop- o package outline dimension c dimensions in millmeters dimensions in inchs symbols min. nom. max. min. nom. max. a 1.00 - 1.20 0.039 - 0.047 a1 0.05 - 0.15 0.002 - 0.006 a2 0.95 1.00 1.05 0.037 0.039 0.041 b 0.30 0.35 0.45 0.012 0.014 0.018 c 0.12 - 0.21 0.0047 - 0.083 d 18.313 18.415 18.517 0.721 0.725 0.728 e 11.854 11.836 11.838 0.460 0.466 0.470 e1 10.058 10.180 10.282 0.398 0.400 0.404 e - 0.800 - - 0.0315 - l 0.40 0.50 0.60 0.0157 0.020 0.0236 2d - 0.805 - - 0.0317 - y 0.00 - 0.076 0.000 - 0.003 k 0 o - 5 o 0 o - 5 o
utron UT61L5128 rev. 1.2 512k x 8 bit high speed cmos sram utron technology inc. p80061 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 9 ? ordering information part no. access time (ns) package UT61L5128mc-8 8 44 pin tsop-ii UT61L5128mc-10 10 44 pin tsop-ii UT61L5128mc-12 12 44 pin tsop-ii ordering information (for lead free product) part no. access time (ns) package UT61L5128mcl-8 8 44 pin tsop-ii UT61L5128mcl-10 10 44 pin tsop-ii UT61L5128mcl-12 12 44 pin tsop-ii
utron UT61L5128 rev. 1.2 512k x 8 bit high speed cmos sram utron technology inc. p80061 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 10 ? this page is left blank intentionally.
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