utron UT61L512 rev 1.2 64k x 8 bit high speed cmos sram utron technology inc. p80024 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 1 ? features ? fast access time : 10/12/15 ns (max.) ? low operating power consumption : 60 ma (typical) ? single 3.3v power supply ? all inputs and outputs ttl compatible ? fully static operation ? three state outputs ? package : 32-pin 300 mil soj 32-pin 8mmx20mm tsop-i functional block diagram memory array 512 rows x 1024 columns column i/o column decoder i/o control logic control i/o1 v ss v cc we oe ce1 i/o8 . . . . . . . . . a 11 a 9 a 3 a 2 a 0 . . . . . . 2 ce a10 a 1 row decoder a 15 a 13 a 14 a 12 a 7 a 6 a 5 a 4 a 8 pin description symbol description a0 - a15 address inputs i/o1 - i/o8 data inputs/outputs ce1 ,ce2 chip enable 1, 2 inputs we write enable input oe output enable input v cc power supply v ss ground nc no connection general description the UT61L512 is a 524,288-bit high-speed cmos static random access memory organized as 524,288 words by 8 bits. it is fabricated using high performance, high reliability cmos technology. the UT61L512 is designed for high-speed system applications. it is particularly suited for use in high-density high-speed system applications. the UT61L512 operates from a single 3.3v power supply and all inputs and outputs are fully ttl compatible. pin configuration a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 ce2 a8 a9 a11 a10 i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 vss UT61L512 soj 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 1 ce we oe a13 a14 nc nc vcc a15 29 30 31 32 a11 a9 a8 a13 i/o3 a10 a14 a12 a7 a6 a5 vcc i/o8 i/o7 i/o6 i/o5 vss i/o2 i/o1 a0 a1 a2 a4 a3 UT61L512 tsop-1 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 we oe 1 ce ce2 nc a15 32 31 30 29 nc i/o4
utron UT61L512 rev 1.2 32k x 8 bit high speed cmos sram utron technology inc. p80024 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 2 ? absolute maximum ratings * parameter symbol rating unit terminal voltage with respect to vss v term -0.5 to +7.0 v operating temperature t a 0 to +70 j storage temperature t stg -65 to +150 j power dissipation p d 1 w dc output current i out 50 ma soldering temperature (under 10 sec) tsolder 260 j *stress greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only and functional operation of the devic e or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to the absolute maximum rating condi tions for extended period may affect device reliability. truth table mode 1 5s5u ce2 55u 5?5u i/o operation supply current standby h x x x high - z i sb , i sb1 standby x l x x high -z i sb , i sb1 output disable l h h h high - z i cc read l h l h d out i cc write l h x l d in i cc note: h = v ih , l=v il , x = don't care. dc electrical characteristics (v cc =3.1v~3.6v, t a = 0 j to 70 j ) parameter symbol test condition min. max. unit input high voltage v ih 2.2 v cc +0.5 v input low voltage v il - 0.5 0.8 v input leakage current i li v ss ?? v in ?? v cc - 1 1 a output leakage current i lo v ss ?? v i/o ?? v cc ce1 = v ih or ce2 = v il or oe = v ih or we = v il - 1 1 a output high voltage v oh i oh = - 4ma 2.4 - v output low voltage v ol i ol = 8ma - 0.4 v operating power i cc ce1 = v il , ce2 = v ih - 10 - 180 ma supply current i i/o = 0ma , cycle=min. - 12 - 160 ma - 15 - 140 ma standby power i sb ce1 = v ih or ce2 = v il - 30 ma supply current i sb1 ce1 ? v cc -0.2v or ce2 ?? 0.2v - 5 ma notes: 1. overshoot : vcc+3.0v fo r pulse width less than 8ns. 2. undershoot : vss-3.0v fo r pulse width less than 8ns. 3. overshoot and undershoot ar e sampled, not 100% tested.
utron UT61L512 rev 1.2 32k x 8 bit high speed cmos sram utron technology inc. p80024 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 3 ? capacitance (t a =25 j , f=1.0mhz) parameter symbol min. max. unit input capacitance c in - 8 pf input/output capacitance c i/o - 10 pf note : these parameters are guaranteed by device characterization, but not production tested. ac test conditions input pulse levels 0v to 3.0v input rise and fall times 5ns input and output timi ng reference levels 1.3.3v output load c l =30pf, i oh /i ol =-4ma/8ma ac electrical characteristics (v cc = 3.1v~3.6v , t a = 0 j to 70 j ) (1) read cycle parameter symbol UT61L512-10 UT61L512-12 UT61L512-15 unit min. max. min. max. min. max. read cycle time t rc 10 - 12 - 15 - ns address access time t aa - 10 - 12 - 15 ns chip enable access time t ace1, t ace1 - 10 - 12 - 15 ns output enable access time t oe - 5 - 6 - 7 ns chip enable to output in low z t clz1*, t clz2* 2 - 3 - 4 - ns output enable to output in low z t olz* 0 - 0 - 0 - ns chip disable to output in high z t chz1*, t chz2* - 5 - 6 - 7 ns output disable to output in high z t ohz* - 5 - 6 - 7 ns output hold from address chang e t oh 3 - 3 - 3 - ns (2) write cycle parameter symbol UT61L512-10 UT61L512-12 UT61L512-15 unit min. max. min. max. min. max. write cycle time t wc 10 - 12 - 15 - ns address valid to end of write t aw 8 - 10 - 12 - ns chip enable to end of write t cw1, t cw2 8 - 10 - 12 - ns address set-up time t as 0 - 0 - 0 - ns write pulse width t wp 8 - 9 - 10 - ns write recovery time t wr 0 - 0 - 0 - ns data to write time overlap t dw 6 - 7 - 8 - ns data hold from end of write time t dh 0 - 0 - 0 - ns output active from end of write t ow* 2 - 3 - 4 - ns write to output in high z t whz* - 6 - 7 - 8 ns *these parameters are guaranteed by device char acterization, but not production tested.
utron UT61L512 rev 1.2 32k x 8 bit high speed cmos sram utron technology inc. p80024 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 4 ? timing waveforms read cycle 1 (address controlled) (1,2,4) t rc address dout data valid t aa t oh t oh read cycle 2 ( ce1 , ce2 and oe controlled) (1,3,5,6) notes : 1. we is high for read cycle. 2. device is continuously selected ce1 =v il and ce2=v ih. 3. address must be valid prior to or coincident with ce1 and ce2 transition; otherwise t aa is the limiting parameter. 4. oe is low. 5. t clz1 , t clz2 , t olz , t chz1 , t chz2 and t ohz are specified with c l =5pf. transition is measured ? 500mv from steady state. 6. at any given temperature and voltage condition, t chz1 is less than t clz1 , t chz2 is less than t clz2 , t ohz is less than t olz. t rc t aa t ace1 t ace2 t oe t olz t clz1 t clz2 high-z t chz1 t chz2 t ohz t oh data valid high-z a ddress 1 ce ce2 oe d out
utron UT61L512 rev 1.2 32k x 8 bit high speed cmos sram utron technology inc. p80024 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 5 ? write cycle 1 ( we controlled) (1,2,3,5) address d out high-z 1 ce we data valid d in ce2 t cw2 t cw1 t aw t wc t whz t wp t as t ow t dw t dh t wr (4) (4) write cycle 2 ( ce1 and ce2 controlled) (1,2,5) address d out high-z 1 ce we (4) data valid d in ce2 t wc t as t cw1 t aw t cw2 t wr t wp t whz t dw t dh notes : 1. we or ce1 must be high during all address transitions. 2. a write occurs during the overlap of a low ce1 and a low we . 3. during a we controlled with write cycle with oe low, t wp must be greater than t whz +t dw to allow the drivers to turn off and data to be placed on the bus. 4. during this period, i/o pins are in the output state, and input singals must not be applied. 5. if the ce1 low transition occurs simultaneously with or after we low transition, the outputs remain in a high impedance state. 6. t ow and t whz are specified with c l = 5pf. transition is measured ? 500mv from steady state.
utron UT61L512 rev 1.2 32k x 8 bit high speed cmos sram utron technology inc. p80024 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 6 ? package outline dimension 32pin soj package outline dimension unit symbol inch(base) mm(ref) a 0.148 (max) 3.759 (max) a1 0.026 (min) 0.660 (min) a2 0.100 ? 0.005 2.540 ? 0.127 b 0.018 (typ) 0.457(typ) b1 0.028 (typ) 0.711 (typ) c 0.010 (typ) 0.254 (typ) d 0.830 (max) 21.082 (max) e 0.335 (typ) 8.509 (typ) e1 0.300 ? 0.005 7.620 ? 0.127 e 0.050 (typ) 1.270 (typ) l 0.086 ? 0.010 2.184 ? 0.254 y 0.003 (max) 0.076 (max)
utron UT61L512 rev 1.2 32k x 8 bit high speed cmos sram utron technology inc. p80024 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 7 ? 32pin tsop-i package outline dimension unit symbol inch(base) mm(ref) a 0.047 (max) 1.20 (max) a1 0.004 ? 0.002 0.10 ? 0.05 a2 0.039 ? 0.002 1.00 ? 0.05 b 0.008 + 0.002 - 0.001 0.20 + 0.05 -0.03 c 0.005 (typ) 0.127 (typ) d 0.724 ? 0.004 18.40 ? 0.10 e 0.315 ? 0.004 8.00 ? 0.10 e 0.020 (typ) 0.50 (typ) hd 0.787 ? 0.008 20.00 ? 0.20 l 0.0197 ? 0.004 0.50 ? 0.10 l1 0.0315 ? 0.004 0.08 ? 0.10 y 0.003 (max) 0.076 (max) k 0 o ?? 5 o 0 o ?? 5 o h c c e b
utron UT61L512 rev 1.2 32k x 8 bit high speed cmos sram utron technology inc. p80024 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 8 ? ordering information part no. access time (ns) package UT61L512jc-10 10 32pin soj UT61L512jc-12 12 32pin soj UT61L512jc-15 15 32pin soj UT61L512lc-10 10 32pin tsop-i UT61L512lc-12 12 32pin tsop-i UT61L512lc-15 15 32pin tsop-i
utron UT61L512 rev 1.2 32k x 8 bit high speed cmos sram utron technology inc. p80024 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 9 ? revision history revision description date rev. 1.0 original. aug. 24,1999 rev 1.1 revise ?write cycle? oct. 18,1999 rev. 1.2 t he symbols ce1#,oe# and we# are revised as 1 ce , oe and we . may. 25,2001
utron UT61L512 rev 1.2 32k x 8 bit high speed cmos sram utron technology inc. p80024 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 10 ? this page is left blank intentionally.
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