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technical manual S1D15715 series
notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. all other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ?seiko epson corporation 2004, all rights reserved.
configuration of product number devices s1 d 15710 d 00b0 00 packing specifications specifications shape (d: chip, t:tcp, f : qfp) model number model name (d : lcd driver) product classification (s1:semiconductors)
general rule when using these development specifications, note the following points: 1. the contents of the development specifications are subject to change without notice for improvement. 2. the development specifications do not guarantee or grant license of any industrial property or other rights to any person. examples of application shown in the development specifications are intended for your better understanding of the product. we are not responsible for any problems about circuit arising out of their use. ?large? or ?small? in the characteristics refers to the relationship on a numbered line. 3. no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. when using the semiconductor chip, note the following points: ic handling notes on light: as a semiconductor chip is principally identical to a solar cell, its performance may change if exposed to bright light. therefore, the ic may malfunction if exposed to light. since the measures against light is incomplete, perform the following to boards and products that the ic is implemented. (1) design and mount the ic so that it is not exposed to light during actual operation. (2) during the inspection process, the environment design must made be made so that the ic is not exposed to light. (3) make sure that the front, back and the sides of the ic chip are not exposed to light.
rev.1.0 epson i contents 1. description ................................................................................................................. ...................1 2. features .................................................................................................................... .....................1 3. block diagram (S1D15715 1/17 duty)........................................................................................2 4. pin assignment .............................................................................................................. ...............3 4.1 chip specification......................................................................................................... ..............3 4.2 alignment marks............................................................................................................ .............3 5. pin description............................................................................................................. ..............10 5.1 power supply pins .......................................................................................................... ..........10 5.2 lcd power supply circuit pins .............................................................................................. ....10 5.3 system bus connection pins................................................................................................. .... 11 5.4 lcd driver pins............................................................................................................ .............12 5.5 test pins.................................................................................................................. ..................12 6. functional description ...................................................................................................... ...13 6.1 mpu interface.............................................................................................................. .............13 6.1.1 interface type selection...............................................................................................13 6.1.2 parallel interface....................................................................................................... ..13 6.1.3 serial interface......................................................................................................... ...14 6.1.4 chip select .............................................................................................................. ....14 6.1.5 access to ddram and internal registers...................................................................15 6.2 ddram...................................................................................................................... ...............16 6.2.1 ddram.................................................................................................................... ...16 6.2.2 page address circuit ...................................................................................................16 6.2.3 column address circuit ...............................................................................................16 6.2.4 line address circuit..................................................................................................... 18 6.2.5 display data latch circuit.............................................................................................18 6.3 oscillation circuit........................................................................................................ ...............18 6.4 display timing generator circuit ........................................................................................... ..19 6.5 lcd driver circuits........................................................................................................ ...........20 6.6 power supply circuit....................................................................................................... ...........22 6.6.1 booster circuit .......................................................................................................... ...22 6.6.2 voltage regulator circuit ..............................................................................................23 6.6.3 liquid crystal voltage generator circuit.......................................................................27 6.6.4 on-chip power supply turn off command sequence ...............................................27 6.6.5 sample circuits .......................................................................................................... .28 6.7 reset circuit .............................................................................................................. ................30 7. command description ......................................................................................................... ....31 7.1 display on/off ............................................................................................................. ..........31 7.2 display normal/reverse..................................................................................................... ........31 7.3 display all points on/off.................................................................................................. ......31 7.4 page address set........................................................................................................... ...........32 7.5 column address set......................................................................................................... .........32 7.6 display start line address set ............................................................................................. ......33 7.7 adc select (segment driver direction select) ..........................................................................33 7.8 common output status select................................................................................................ ...33 7.9 display data read.......................................................................................................... ............33
ii epson rev.1.0 7.10 display data write ........................................................................................................ .............34 7.11 read modify write......................................................................................................... ............34 7.12 end ....................................................................................................................... ....................35 7.13 power control set......................................................................................................... .............35 7.14 v 0 voltage regulator internal resistance ratio set .....................................................................35 7.15 electronic volume set ..................................................................................................... ..........36 7.16 lcd bias set .............................................................................................................. ...............36 7.17 n-line inversion drive register set....................................................................................... .......36 7.18 canceling n-line inversion drive .......................................................................................... .....36 7.19 power save (composite command)..........................................................................................37 7.20 reset ..................................................................................................................... ...................38 7.21 nop ....................................................................................................................... ...................38 7.22 test ...................................................................................................................... .....................38 8. absolute maximum rating ..................................................................................................... 45 9. dc characteristics.......................................................................................................... ........46 10. ac characteristics......................................................................................................... .........52 11. mpu interface (reference examples) ..............................................................................59
S1D15715 series technical manual rev.1.0 epson 1 1. description S1D15715 series is a single-chip liquid crystal display (=lcd) driver for dot matrix lcds that can be connected directly to a microprocessor (=mpu) bus. it accepts 8-bit parallel or serial display data from a mpu, stores it in an on-chip display data ram (=ddram), and generates a lcd drive signal independent of the mpu clock. the use of the on-chip ddram of 33 102 bits and a one-to-one correspondence between lcd panel pixel dots and on-chip ddram bits offer high flexibility in graphic display. the S1D15715 is equipped with 17 circuits of common output and 102 circuits of segment output, and displays in 17 102 dots. the s1d15716 is equipped with 9 circuits of common output and 102 circuits of segment output, and displays in 9 102 dots. the s1d15717 is equipped with 33 circuits of common output and 102 circuits of segment output, and displays in33 102 dots. S1D15715 series can perform reading and writing of the display data ram with minimum power consumption since it does not require external operation clock. moreover, since the series is equipped with low-power-consumption and highly efficient lcd driver power supply and display clock cr oscillation circuit, it is suited for display system of the high-performance handy device and in-vehicle device. 2. features ? direct display of ram data through the display data ram. ram bit data: 1? non-illuminated 0? illuminated (during normal display) ? ram capacity 33 102=3366 bits ? display driver circuits common output of 17, segment output of 102: S1D15715 common output of 9, segment output of 102: s1d15716 common output of 33, segment output of 102: s1d15717 ? high-speed 8-bit mpu interface (the chip can be connected directly to the 80-series mpus and the 68-series mpus) ? high-speed serial interface are supported. ? abundant command functions display data read/write, display on/off, normal/reverse display mode, page address set, display start line set, column address set, display all points on/off, electronic volume, read modify write, segment driver direction select, power saver, common output direction select, v 0 voltage regulator internal resistor ratio set, n-line inversion drive ? liquid crystal display power supply circuit equipped internally. booster circuit (with boost ratios of double/triple, where the step-up voltage reference power supply can be input externally) high-accuracy voltage regulator circuit (thermal gradient -0.05%/oc) v 0 voltage regulator resistors equipped internally, v 1 to v 4 voltage divider resistors equipped internally, electronic volume function equipped internally, voltage follower. ? cr oscillator circuit equipped internally (external clock can also be input) ? low power consumption ? power supply logic power supply voltage : v dd -v ss =1.8v to 5.5v liquid crystal drive power supply : v 0 -v ss =4.5v to 9.0v ? wide range of operating temperatures : -40 to +85 c ? cmos process ? shipping forms : bare chip ? the chip is not designed for resistance to light or resistance to radiation. series specifications product name duty com dr seg dr bias v reg temperature shipping forms S1D15715d00b000 1/17 17 s1d15716d00b000 1/9 9 s1d15717d00b000 1/33 33 102 1/6, 1/5 -0.05%/ c bare chip
S1D15715 series technical manual 2 epson rev.1.0 3. block diagram (S1D15715 1/17 duty) * the com pins for s1d15716 and s1d15717 differ. S1D15715 com0 to com15, coms s1d15716 com0 to com7, coms s1d15717 com0 to com32, coms v dd v 0 v 3 v 2 v 1 cap1- v r v out cap1+ v ss v 4 coms com15 com0 seg101 ___ cs coms shift register circuit com drivers oscillator circuit display timing generator circuit line address circuit page address circuit i/o buffer power supply circuit display data latch circuit mpu interface command decoder bus holder command decoder display data ram 33 102 seg drivers cap2- cap2+ c l ?????????????????? ??????? seg0 c86 p/s a 0 ___ wr ( r/ __ w ) ___ rd ( e ) d5 d4 d3 d2 d1 d0 d7 ( si ) d6 ( scl ) ____ r e s
S1D15715 series technical manual rev.1.0 epson 3 4. pin assignment 4.1 chip specification size x y unit chip size 8.13 1.99 mm chip thickness 0.625 mm bump pitch 50 (min.) m bump size pad no.1 to 76 71 86 m pad no.77 to 78 86 117 m pad no.79 to 226 33 117 m pad no.227 to 228 86 117 m bump height 17 (typ.) m 4.2 alignment marks alignment coordinates: 1 ( 3924.1, 842.7 ) m 2 ( -3918.6, -842.7) m mark size: a =69.5 m b =29.6 m c =80.8 m S1D15715 series 1 77 76 (0, 0) 228 d157fd0b die no. alignment mark c alignment mark d 1 2 a b c
S1D15715 series technical manual 4 epson rev.1.0 ? S1D15715 series pad center coordinates unit: m pad no. pin name x y pad no. pin name x y pad no. pin name x y 1 (nc) 3809 843 51 v out -1401 843 101 (nc) -2600 -828 2 ____ res 3713 52 v out -1497 102 seg0 -2550 3 ___ cs 3618 53 v ss -1593 103 seg1 -2499 4 v ss 3522 54 v r -1689 104 seg2 -2449 5 v ss 3426 55 v 0 -1785 105 seg3 -2398 6 v ss 3330 56 v 0 -1881 106 seg4 -2348 7 ___ wr(r/ __ w) 3234 57 v 1 -1977 107 seg5 -2297 8 ___ rd (e) 3138 58 v 1 -2072 108 seg6 -2247 9 test0 3042 59 v 2 -2168 109 seg7 -2196 10 test1 2946 60 v 2 -2264 110 seg8 -2146 11 v ss 2850 61 v 3 -2360 111 seg9 -2095 12 test2 2755 62 v 3 -2456 112 seg10 -2045 13 test3 2659 63 v 4 -2552 113 seg11 -1994 14 ____ res 2563 64 v 4 -2648 114 seg12 -1944 15 ___ cs 2467 65 v out -2744 115 seg13 -1893 16 v ss 2371 66 cap2+ -2839 116 seg14 -1843 17 v ss 2275 67 cap2+ -2935 117 seg15 -1792 18 v ss 2179 68 cap2+ -3031 118 seg16 -1742 19 v dd 2083 69 cap2- -3127 119 seg17 -1691 20 cl 1988 70 cap2- -3223 120 seg18 -1641 21 a0 1892 71 cap2- -3319 121 seg19 -1590 22 d7(si) 1796 72 cap1+ -3415 122 seg20 -1540 23 d7(si) 1700 73 cap1+ -3511 123 seg21 -1489 24 d6(scl) 1604 74 cap1- -3606 124 seg22 -1439 25 d6(scl) 1508 75 cap1- -3702 125 seg23 -1388 26 d5 1412 76 (nc) -3798 126 seg24 -1338 27 d4 1316 77 (nc) -3909 -828 127 seg25 -1287 28 d3 1221 78 (nc) -3797 128 seg26 -1237 29 d2 1125 79 coms -3711 129 seg27 -1187 30 d1 1029 80 com0 -3661 130 seg28 -1136 31 d0 933 81 com1 -3610 131 seg29 -1086 32 v dd 837 82 com2 -3560 132 seg30 -1035 33 v dd 741 83 com3 -3509 133 seg31 -985 34 v dd 645 84 com4 -3459 134 seg32 -934 35 p/s 549 85 com5 -3408 135 seg33 -884 36 c86 453 86 com6 -3358 136 seg34 -833 37 v ss 358 87 com7 -3307 137 seg35 -783 38 test4 262 88 com8 -3257 138 seg36 -732 39 test5 106 89 com9 -3206 139 seg37 -682 40 test6 -49 90 com10 -3156 140 seg38 -631 41 test7 -204 91 com11 -3105 141 seg39 -581 42 test8 -360 92 com12 -3055 142 seg40 -530 43 test9 -515 93 com13 -3004 143 seg41 -480 44 test10 -671 94 com14 -2954 144 seg42 -429 45 v ss -826 95 com15 -2903 145 seg43 -379 46 v ss -922 96 coms -2853 146 seg44 -328 47 v ss -1018 97 (nc) -2802 147 seg45 -278 48 v ss -1114 98 (nc) -2752 148 seg46 -227 49 v ss -1209 99 (nc) -2701 149 seg47 -177 50 v ss -1305 100 (nc) -2651 150 seg48 -126
S1D15715 series technical manual rev.1.0 epson 5 unit: m pad no. pin name x y pad no. pin name x y 151 seg49 -76 -828 201 seg99 2449 -828 152 seg50 -25 202 seg100 2499 153 seg51 25 203 seg101 2550 154 seg52 76 204 (nc) 2600 155 seg53 126 205 (nc) 2651 156 seg54 177 206 (nc) 2701 157 seg55 227 207 (nc) 2752 158 seg56 278 208 (nc) 2802 159 seg57 328 209 coms 2853 160 seg58 379 210 com15 2903 161 seg59 429 211 com14 2954 162 seg60 480 212 com13 3004 163 seg61 530 213 com12 3055 164 seg62 581 214 com11 3105 165 seg63 631 215 com10 3156 166 seg64 682 216 com9 3206 167 seg65 732 217 com8 3257 168 seg66 783 218 com7 3307 169 seg67 833 219 com6 3358 170 seg68 884 220 com5 3408 171 seg69 934 221 com4 3459 172 seg70 985 222 com3 3509 173 seg71 1035 223 com2 3560 174 seg72 1086 224 com1 3610 175 seg73 1136 225 com0 3661 176 seg74 1187 226 coms 3711 177 seg75 1237 227 (nc) 3797 178 seg76 1287 228 (nc) 3909 179 seg77 1338 180 seg78 1388 181 seg79 1439 182 seg80 1489 183 seg81 1540 184 seg82 1590 185 seg83 1641 186 seg84 1691 187 seg85 1742 188 seg86 1792 189 seg87 1843 190 seg88 1893 191 seg89 1944 192 seg90 1994 193 seg91 2045 194 seg92 2095 195 seg93 2146 196 seg94 2196 197 seg95 2247 198 seg96 2297 199 seg97 2348 200 seg98 2398
S1D15715 series technical manual 6 epson rev.1.0 ? s1d15716 series pad center coordinates unit: m pad no. pin name x y pad no. pin name x y pad no. pin name x y 1 (nc) 3809 843 51 v out -1401 843 101 (nc) -2600 -828 2 ____ res 3713 52 v out -1497 102 seg0 -2550 3 ___ cs 3618 53 v ss -1593 103 seg1 -2499 4 v ss 3522 54 v r -1689 104 seg2 -2449 5 v ss 3426 55 v 0 -1785 105 seg3 -2398 6 v ss 3330 56 v 0 -1881 106 seg4 -2348 7 ___ wr(r/ __ w) 3234 57 v 1 -1977 107 seg5 -2297 8 ___ rd (e) 3138 58 v 1 -2072 108 seg6 -2247 9 test0 3042 59 v 2 -2168 109 seg7 -2196 10 test1 2946 60 v 2 -2264 110 seg8 -2146 11 v ss 2850 61 v 3 -2360 111 seg9 -2095 12 test2 2755 62 v 3 -2456 112 seg10 -2045 13 test3 2659 63 v 4 -2552 113 seg11 -1994 14 ____ res 2563 64 v 4 -2648 114 seg12 -1944 15 ___ cs 2467 65 v out -2744 115 seg13 -1893 16 v ss 2371 66 cap2+ -2839 116 seg14 -1843 17 v ss 2275 67 cap2+ -2935 117 seg15 -1792 18 v ss 2179 68 cap2+ -3031 118 seg16 -1742 19 v dd 2083 69 cap2- -3127 119 seg17 -1691 20 cl 1988 70 cap2- -3223 120 seg18 -1641 21 a0 1892 71 cap2- -3319 121 seg19 -1590 22 d7(si) 1796 72 cap1+ -3415 122 seg20 -1540 23 d7(si) 1700 73 cap1+ -3511 123 seg21 -1489 24 d6(scl) 1604 74 cap1- -3606 124 seg22 -1439 25 d6(scl) 1508 75 cap1- -3702 125 seg23 -1388 26 d5 1412 76 (nc) -3798 126 seg24 -1338 27 d4 1316 77 (nc) -3909 -828 127 seg25 -1287 28 d3 1221 78 (nc) -3797 128 seg26 -1237 29 d2 1125 79 coms -3711 129 seg27 -1187 30 d1 1029 80 com0 -3661 130 seg28 -1136 31 d0 933 81 com0 -3610 131 seg29 -1086 32 v dd 837 82 com1 -3560 132 seg30 -1035 33 v dd 741 83 com1 -3509 133 seg31 -985 34 v dd 645 84 com2 -3459 134 seg32 -934 35 p/s 549 85 com2 -3408 135 seg33 -884 36 c86 453 86 com3 -3358 136 seg34 -833 37 v ss 358 87 com3 -3307 137 seg35 -783 38 test4 262 88 com4 -3257 138 seg36 -732 39 test5 106 89 com4 -3206 139 seg37 -682 40 test6 -49 90 com5 -3156 140 seg38 -631 41 test7 -204 91 com5 -3105 141 seg39 -581 42 test8 -360 92 com6 -3055 142 seg40 -530 43 test9 -515 93 com6 -3004 143 seg41 -480 44 test10 -671 94 com7 -2954 144 seg42 -429 45 v ss -826 95 com7 -2903 145 seg43 -379 46 v ss -922 96 coms -2853 146 seg44 -328 47 v ss -1018 97 (nc) -2802 147 seg45 -278 48 v ss -1114 98 (nc) -2752 148 seg46 -227 49 v ss -1209 99 (nc) -2701 149 seg47 -177 50 v ss -1305 100 (nc) -2651 150 seg48 -126
S1D15715 series technical manual rev.1.0 epson 7 unit: m pad no. pin name x y pad no. pin name x y 151 seg49 -76 -828 201 seg99 2449 -828 152 seg50 -25 202 seg100 2499 153 seg51 25 203 seg101 2550 154 seg52 76 204 (nc) 2600 155 seg53 126 205 (nc) 2651 156 seg54 177 206 (nc) 2701 157 seg55 227 207 (nc) 2752 158 seg56 278 208 (nc) 2802 159 seg57 328 209 coms 2853 160 seg58 379 210 com7 2903 161 seg59 429 211 com7 2954 162 seg60 480 212 com6 3004 163 seg61 530 213 com6 3055 164 seg62 581 214 com5 3105 165 seg63 631 215 com5 3156 166 seg64 682 216 com4 3206 167 seg65 732 217 com4 3257 168 seg66 783 218 com3 3307 169 seg67 833 219 com3 3358 170 seg68 884 220 com2 3408 171 seg69 934 221 com2 3459 172 seg70 985 222 com1 3509 173 seg71 1035 223 com1 3560 174 seg72 1086 224 com0 3610 175 seg73 1136 225 com0 3661 176 seg74 1187 226 coms 3711 177 seg75 1237 227 (nc) 3797 178 seg76 1287 228 (nc) 3909 179 seg77 1338 180 seg78 1388 181 seg79 1439 182 seg80 1489 183 seg81 1540 184 seg82 1590 185 seg83 1641 186 seg84 1691 187 seg85 1742 188 seg86 1792 189 seg87 1843 190 seg88 1893 191 seg89 1944 192 seg90 1994 193 seg91 2045 194 seg92 2095 195 seg93 2146 196 seg94 2196 197 seg95 2247 198 seg96 2297 199 seg97 2348 200 seg98 2398
S1D15715 series technical manual 8 epson rev.1.0 ? s1d15717 series pad center coordinates unit: m pad no. pin name x y pad no. pin name x y pad no. pin name x y 1 (nc) 3809 843 51 v out -1401 843 101 (nc) -2600 -828 2 ____ res 3713 52 v out -1497 102 seg0 -2550 3 ___ cs 3618 53 v ss -1593 103 seg1 -2499 4 v ss 3522 54 v r -1689 104 seg2 -2449 5 v ss 3426 55 v 0 -1785 105 seg3 -2398 6 v ss 3330 56 v 0 -1881 106 seg4 -2348 7 ___ wr(r/ __ w) 3234 57 v 1 -1977 107 seg5 -2297 8 ___ rd (e) 3138 58 v 1 -2072 108 seg6 -2247 9 test0 3042 59 v 2 -2168 109 seg7 -2196 10 test1 2946 60 v 2 -2264 110 seg8 -2146 11 v ss 2850 61 v 3 -2360 111 seg9 -2095 12 test2 2755 62 v 3 -2456 112 seg10 -2045 13 test3 2659 63 v 4 -2552 113 seg11 -1994 14 ____ res 2563 64 v 4 -2648 114 seg12 -1944 15 ___ cs 2467 65 v out -2744 115 seg13 -1893 16 v ss 2371 66 cap2+ -2839 116 seg14 -1843 17 v ss 2275 67 cap2+ -2935 117 seg15 -1792 18 v ss 2179 68 cap2+ -3031 118 seg16 -1742 19 v dd 2083 69 cap2- -3127 119 seg17 -1691 20 cl 1988 70 cap2- -3223 120 seg18 -1641 21 a0 1892 71 cap2- -3319 121 seg19 -1590 22 d7(si) 1796 72 cap1+ -3415 122 seg20 -1540 23 d7(si) 1700 73 cap1+ -3511 123 seg21 -1489 24 d6(scl) 1604 74 cap1- -3606 124 seg22 -1439 25 d6(scl) 1508 75 cap1- -3702 125 seg23 -1388 26 d5 1412 76 (nc) -3798 126 seg24 -1338 27 d4 1316 77 (nc) -3909 -828 127 seg25 -1287 28 d3 1221 78 (nc) -3797 128 seg26 -1237 29 d2 1125 79 coms -3711 129 seg27 -1187 30 d1 1029 80 com0 -3661 130 seg28 -1136 31 d0 933 81 com1 -3610 131 seg29 -1086 32 v dd 837 82 com2 -3560 132 seg30 -1035 33 v dd 741 83 com3 -3509 133 seg31 -985 34 v dd 645 84 com4 -3459 134 seg32 -934 35 p/s 549 85 com5 -3408 135 seg33 -884 36 c86 453 86 com6 -3358 136 seg34 -833 37 v ss 358 87 com7 -3307 137 seg35 -783 38 test4 262 88 com8 -3257 138 seg36 -732 39 test5 106 89 com9 -3206 139 seg37 -682 40 test6 -49 90 com10 -3156 140 seg38 -631 41 test7 -204 91 com11 -3105 141 seg39 -581 42 test8 -360 92 com12 -3055 142 seg40 -530 43 test9 -515 93 com13 -3004 143 seg41 -480 44 test10 -671 94 com14 -2954 144 seg42 -429 45 v ss -826 95 com15 -2903 145 seg43 -379 46 v ss -922 96 coms -2853 146 seg44 -328 47 v ss -1018 97 (nc) -2802 147 seg45 -278 48 v ss -1114 98 (nc) -2752 148 seg46 -227 49 v ss -1209 99 (nc) -2701 149 seg47 -177 50 v ss -1305 100 (nc) -2651 150 seg48 -126
S1D15715 series technical manual rev.1.0 epson 9 unit: m pad no. pin name x y pad no. pin name x y 151 seg49 -76 -828 201 seg99 2449 -828 152 seg50 -25 202 seg100 2499 153 seg51 25 203 seg101 2550 154 seg52 76 204 (nc) 2600 155 seg53 126 205 (nc) 2651 156 seg54 177 206 (nc) 2701 157 seg55 227 207 (nc) 2752 158 seg56 278 208 (nc) 2802 159 seg57 328 209 coms 2853 160 seg58 379 210 com31 2903 161 seg59 429 211 com30 2954 162 seg60 480 212 com29 3004 163 seg61 530 213 com28 3055 164 seg62 581 214 com27 3105 165 seg63 631 215 com26 3156 166 seg64 682 216 com25 3206 167 seg65 732 217 com24 3257 168 seg66 783 218 com23 3307 169 seg67 833 219 com22 3358 170 seg68 884 220 com21 3408 171 seg69 934 221 com20 3459 172 seg70 985 222 com19 3509 173 seg71 1035 223 com18 3560 174 seg72 1086 224 com17 3610 175 seg73 1136 225 com16 3661 176 seg74 1187 226 coms 3711 177 seg75 1237 227 (nc) 3797 178 seg76 1287 228 (nc) 3909 179 seg77 1338 180 seg78 1388 181 seg79 1439 182 seg80 1489 183 seg81 1540 184 seg82 1590 185 seg83 1641 186 seg84 1691 187 seg85 1742 188 seg86 1792 189 seg87 1843 190 seg88 1893 191 seg89 1944 192 seg90 1994 193 seg91 2045 194 seg92 2095 195 seg93 2146 196 seg94 2196 197 seg95 2247 198 seg96 2297 199 seg97 2348 200 seg98 2398
S1D15715 series technical manual 10 epson rev.1.0 5. pin description 5.1 power supply pins pin name i/o description number of pins v dd supply internal logic power supply and internal power circuit power supply. connect to mpu power pin v cc . 4 v ss supply 0v pin connected to the system ground. 15 v 0 ,v 1 ,v 2 , v 3 ,v 4 supply multi-level, lcd drive power supply pins. the voltage specified according to liquid crystal cells is impedance-converted by a split resistor or operational amplifier and applied. the voltages need to be specified based on the v ss to establish the following relationship: v 0 v 1 v 2 v 3 v 4 v ss when power circuit turns on, the following voltages are applied to v 1 to v 4 from the internal power circuit. 10 (2 each) 5.2 lcd power supply circuit pins pin name i/o description number of pins cap1+ o boosting capacitor positive connection pin. capacitor is connected across cap1-pins. 2 cap1- o boosting capacitor negative connection pin. capacitor is connected across cap1+pins. 2 cap2+ o boosting capacitor positive connection pin. capacitor is connected across cap2-pins. 3 cap2- o boosting capacitor negative connection pin. capacitor is connected across cap2+pins. 3 v out o booster output. capacitor is connected across v ss or v dd . 3 v r i voltage regulator pin. provides v 0 to v ss voltage using split resistors. operable only when the built-in resistor for v 0 adjustment is not used. [v 0 resistance ratio is (d 2 , d 1 , d 0 )=(1.1.1)] this pin is disabled when the built-in resistor for v 0 adjustment is used. the pin must be open in this case. 1 S1D15715/16/17 1/5 bias 1/6 bias v 1 4/5 v 0 5/6 v 0 v 2 3/5 v 0 4/6 v 0 v 3 2/5 v 0 2/6 v 0 v 4 1/5 v 0 1/6 v 0
S1D15715 series technical manual rev.1.0 epson 11 5.3 system bus connection pins pin name i/o description number of pins d7 to d0 (si) (scl) i/o 8-bit bi-directional data bus to be connected to the standard 8-bit or 16-bit mpu data bus. when the serial interface is selected (p/s=low); d7: serial data input (si) d6: serial clock input (scl) d0 to d5 switches to high impedance status. when chip select is in non-active status, d0 to d7 switches to high impedance status. 10 a0 i normally the lowest order bit of the mpu address bus is connected to discriminate data/commands. a0=high: the data on d7 to d0 is display data. a0=l o w : t he data on d 7 to d 0 is control data. 1 ___ cs i chip select signal. when ___ cs =low, the mpu interface of the ic becomes active and the input/output of data/command is enabled. 2 ____ res i initialized by setting ____ res to low. r eset operation is performed at the signal le v el. 2 ___ rd (e) i when connected to an 80-series mpu; this is active low. this pin connects the ___ rd signal of the 80-series mpu. while the signal is low, S1D15715 series data bus is in an output status. when connected to an 68-series mpu; this is active high. this is used as an enable clock input pin of the 68-series mpu. 1 ___ wr (r/ __ w) i when connected to an 80-series mpu; this is active low. this pin connects the ___ wr signal of 80-series mpu. the signals on the data bus are latched at the rising edge of the ___ wr signal. when connected to an 68-series mpu; this is used as the input pin of the read/write control signal. r/ __ w=high: read r/ __ w=low: write 1 c86 i mpu interface selection pin. c86=high: 68-series mpu interface c86=low: 80-series mpu interface 1 p/s i serial data input/parallel data input selection pin. p/s=high: parallel data input p/s=low: serial data input the following applies depending on the p/s status: when p/s=low, d5 to d0 switches to high impedance status. d5 to d0 can also be high, low or open. ___ rd (e) and ___ wr (r/ __ w) must always be high or low. in serial mode, no data can be read from ddram. 1 p/s data/command data read/write serial clock high a0 d0 to d7 ___ rd , ___ wr - low a0 si(d7) write only scl(d6)
S1D15715 series technical manual 12 epson rev.1.0 5.4 lcd driver pins pin name i/o description number of pins cl i this pin is used for enabling or disabling the built-in oscillation circuit for the display clock. cl=high : built-in oscillation circuit is enabled. cl=low : built-in oscillation circuit (external input) is disabled. when inputting external clock, input clock to the cl pin. when using the built-in oscillation circuit, select cl=high (v dd ). 1 seg0 to sed101 o these pins output the signal for the segment drive of lcd. one of v 0 , v 2 , v 3 and v ss levels is selected depending on a given combination of display ram data and internal fr signal. 102 com0 to com15 (com0 to com7) (com0 to com31) o these pins output the signal for the common drive of lcd. they are branched by the sel pins as follows. one of v 0 , v 1 , v 4 and v ss levels is selected depending on a given combination of scan data and fr signal. in case multiple number of the com pins for the same signal names exist, the same signal will be output from all the pins. 32 (16) coms o they are com pins exclusively used for the indicator. the same signal will be output from all the 4 pins. they must be made open when not used. 4 5.5 test pins pin name i/o description number of pins test0 to test10 i these are terminals for ic chip testing. they are set to open. 11 total: 212 pins note and caution ? in case the control signal being transmit from the mpu is at a high impedance, excess current may occur in the inside of the ic. take measures to prevent the input pin from switching to the high impedance status. output voltage ram data internal fr signal normal display reversing display high high v 0 v 2 high low v ss v 3 low high v 2 v 0 low low v 3 v ss power save - v ss model com S1D15715 com0 to com15 s1d15716 com0 to com7 s1d15717 com0 to com31 scan data fr output voltage high high v ss high low v 0 low high v 1 low low v 4 power save - v ss
S1D15715 series technical manual rev.1.0 epson 13 6. functional description 6.1 mpu interface 6.1.1 interface type selection S1D15715 series can transfer data via 8-bit bi-directional buses (d7 to d0) or via serial data input (si). through selecting the p/s pin polarity to high or low, it is possible to select either 8-bit parallel data input or serial data input as shown in table 1. table 1 p/s ___ cs a0 ___ rd ___ wr c86 d7 d6 d5 to d0 high: parallel input ___ cs a0 ___ rd ___ wr c86 d7 d6 d5 to d0 low: serial input ___ cs a0 - - - si scl hz - : must always be high or low. hz is a high impedance state 6.1.2 parallel interface when the parallel interface has been selected (p/s=high), then it is possible to connect directly to either an 80-series mpu or 68-series mpu (as shown in table 2) by selecting c86 pin to either high or low. table 2 c86 ___ cs a0 ___ rd ___ wr d7 to d0 high: 68-series mpu bus ___ cs a0 e r/ __ w d7 to d0 low: 80-series mpu bus ___ cs a0 ___ rd ___ wr d7 to d0 moreover, the S1D15715 series identifies the data bus signal according to a0, ___ rd(e), ___ wr(r/ __ w) signals, as shown in table 3. table 3 common 68-series 80-series a0 r/ __ w ___ rd ___ wr function 1 1 0 1 reads the display data 1 0 1 0 writes the display data 0 0 1 0 writes control data (command)
S1D15715 series technical manual 14 epson rev.1.0 6.1.3 serial interface when the serial interface has been selected (p/s=low), then when the chip is in active state ( ___ cs =low) the serial data input (si) and the serial clock input (scl) can be received. the serial interface consists of an 8-bit shift register and a 3-bit counter. the serial data is read from the serial data input pin in the rising edge of the serial clocks d7, d6 through d0, in this order. this data is converted to 8 bits parallel data in the rising edge of the eighth serial clock for the processing. the a0 input is used to determine whether the serial data input is display data or command data; when a0=high, the data is display data, and when a0=low, then the data is command data. the a0 input is read and used for detection every 8 n-th rising edge of the serial clock after the chip becomes active. fig.1 is a serial interface signal chart. fig.1 when the chip is inactive, the shift register and the counter is reset to the initial state. data read is not available as long as the serial interface is selected. reasonable care must be exercised so that scl signal may not be exposed undesirable effects resulting from, for instance, terminal reflection of wiring or external noises. before using the signal, it is recommended to test the signal in actual system. 6.1.4 chip select the mpu interface (either parallel or serial) is enabled only when ___ cs =low. when the chip select is inactive, d0 to d7 enter a high impedance state, and a0, ___ rd and ___ wr inputs are disabled. when the serial interface is selected, the shift register and the counter are reset. _ __ cs si d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 scl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a0
S1D15715 series technical manual rev.1.0 epson 15 6.1.5 access to ddram and internal registers in accessing the ddram and the internal registers of the S1D15715 series, the mpu is required to satisfy the only cycle time ( t cyc ), and is not needed to consider the wait time. accordingly, it is possible to transfer data at higher speed. in order to realize the higher speed accessing, the S1D15715 series can perform a type of pipeline processing between lsis using bus holder of internal data bus when data is sent from/to the mpu. for example, when the mpu writes data to the ddram, once the data is stored in the bus holder, then it is written to the ddram before the next data write cycle. and when the mpu reads the contents of the ddram, the first data cycle (dummy read cycle) stores the read data in the bus holder, and then the data is read from the bus holder to the system bus at the next data read cycle. thus, there is a certain restriction in the ddram read sequence. when an address is set, the specified address data is not output at the immediately following read instruction. the address data is output during second data read. a single dummy read must be inserted after address setup and after write cycle. fig.2 write read n+3 n+2 n+1 n n+3 n+2 n+1 n _ __ wr data latch bus holder write signal n+1 n n n increment preset n+2 n+1 n n+2 n+1 n n dummy read address set #n _ __ wr _ __ rd data address preset read signal column address bus holder data read #n+1 data read #n internal timing mpu internal timing mpu
S1D15715 series technical manual 16 epson rev.1.0 6.2 ddram 6.2.1 ddram the ddram stores pixel data for lcd. it is in a 33 (4 page8 bit+1) 102bit array. desired bits can be accessed by specifying page and column addresses. as is shown in fig.3, the d7 to d0 display data from the mpu corresponds to the lcd common direction. moreover, reading from and writing to the display ram from the mpu side is performed through the i/o buffer, which is an independent operation from signal reading for the liquid crystal driver consequently, even if the display data ram is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering). d0 0 1 1 1 0 com0 d1 1 0 0 0 0 com1 d2 0 0 0 0 0 com2 d3 0 1 1 1 0 com3 d4 1 0 0 0 0 com4 - - ddram display on lcd fig.3 6.2.2 page address circuit as shown in fig.4, the page address of the ddram is specified using the page address set command. to access the data using a new page, the page address is respecified. page address 4h (d3, d2, d1, d0=0, 1, 1, 0) is ddram area dedicate to the indicator, and display data d0 is only valid. 6.2.3 column address circuit designate the column side address of the indication data ram as shown in fig.4, using the column address setting command. since the designated column address increments (+1) each time an indication data read/write command is input, the mpu can make access to the indication data in succession. also, as shown in fig.5, after an access has been made to the final column address (65h), the column address will return to (00h) and the page address will be automatically incremented (by +1). thanks to this feature, it is possible to write continuous data being divided between adjoining pages. furthermore, after accesses have been made to the final addresses of both of the page and column (column=65h and page=3h), both of the column address and the page address returns to (00h). (the page will not increment to 4h. therefore, be careful when executing ?read modify write? processes). also, as shown in table 4, the correlation between the column address of the indication data ram and the segment output can be reversed by use of the adc select command (segment driver direction select command). thanks to this feature, ic layout limitations when constituting a lcd module can be lessened. table 4 column address 00h 01h 02h 63h 64h 65h normal direction seg0 seg1 seg2 seg99 seg100 seg101 reverse direction seg101 seg100 seg99 seg2 seg1 seg0
S1D15715 series technical manual rev.1.0 epson 17 example of S1D15715 (1/17duty) fig.4 data d0 d1 d2 d3 d4 d5 d6 0h 0 1 2 100 101 d7 1h 102 103 104 202 203 2h 204 205 206 304 305 page address 3h 306 307 308 406 407 4h 00h 01h 02h 64h 65h column address fig.5 column address 110 0 11 0 10 0 01 000 page address line address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh d 2 d 1 d 0 com15 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com0 coms com1 com14 com output normal direction reverse direction normal direction reverse direction seg output seg101 seg100 seg 99 seg 98 seg 97 seg 96 seg 95 seg6 seg5 seg4 seg3 seg2 seg1 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg95 seg96 seg97 seg98 seg99 seg100 seg101 seg0 start 00h 01h 02h 03h 04h 05h 5fh 60h 06h 61h 62h 63h 64h 65h com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 coms com15 com14 com11 com13 com12 com10 regardless of the indication starting line or the address, the S1D15715 will be accessed to the 17th line, the s1d15716 will be accessed to the 9th line and the s1d15717 will be accessed to the 33rd line. page0 page1 page2 page3 page4 data d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d1 d0 d7 d2 d3 d6 d5 d4 d7 d0 d0
S1D15715 series technical manual 18 epson rev.1.0 6.2.4 line address circuit the line address specifies the line address (as shown in fig.4) relating to the com output when the contents of the ddram are displayed. using the display start line address set command, the top line is normally selected (in case of the forward common output state, the S1D15715 will designate the com0 output, in case of the reverse common output state, the S1D15715 will designate the com15 output, the s1d15716 will designate the com7 output and the s1d15717 will designate the com31 output.) the display area of each driver is secured starting from the specified display start line address in the address incrementing direction as follows: for S1D15715 (1/17duty), 16 lines and a line of page 4 (total of 17 lines); for s1d15716 (1/9duty), 8 lines and a line of page 4 (total of 9 lines); for s1d15717 (1/33duty), 32 lines and a line of page 4 (total of 33 lines). and common driver direction select command can be used to reverse the relationship between the ddram line address and common output. for example, as is shown in table 5, the display start line address corresponds to the com0 output when the common driver direction is normal, or the com15 output when common driver direction is reversed (S1D15715). this allows flexible ic layout during lcd module assembly. if the display start line address is changed dynamically using the display start line address set command, then screen scrolling and page swapping can be performed. table 5 S1D15715 at display start line address=1ch (corresponds to fig.4) line address 1ch 1dh 1fh 00h 0ah 0bh normal direction com0 com1 com3 com4 com14 com15 reverse direction com15 com14 com12 com11 com1 com0 6.2.5 display data latch circuit the display data latch circuit is a latch which temporarily stores the display data that is output to the lcd driver circuit from the ddram. display on/off command, display normal/reverse command, and display all points on/off command control only the data within the latch, and do not change the data within the ddram. 6.3 oscillation circuit S1D15715 series generates display clocks using its built-in cr oscillation circuit. the built-in oscillation circuit is enabled when cl=high is selected and the power save mode is turned off. you can stop operation of the cr oscillation circuit by selecting cl=low. display clock can be externally entered via cl pin (when external clock is turned off, cl pin must be placed in low). table 6 cl operation high built-in cr oscillation circuit is enabled. low built-in cr oscillation circuit is turned off [display clock is turned off]. clock input external clock input mode table 7 shows relationship between frequency of external clock ( f cl ), frequency of built-in oscillation circuit ( f osc ) and f fr . since cl pin is used for resetting the built-in cr oscillation circuit, it must satisfy the f cl requirements given in the ?dc characteristics?. table 7 item f fr computation formula when built-in oscillation circuit is used f fr =f osc / (17 16) S1D15715 1/17 duty when external clock input is used f fr =f cl / (17 16) when built-in oscillation circuit is used f fr =f osc / (9 32) s1d15716 1/9 duty when external clock input is used f fr =f cl / (9 16) when built-in oscillation circuit is used f fr =f osc / (33 8) s1d15717 1/33 duty when external clock input is used f fr =f cl / (33 16)
S1D15715 series technical manual rev.1.0 epson 19 6.4 display timing generator circuit the display timing generator circuit generates the timing signal from the display clocks to the line address circuit and the display data latch circuit. since the read out of the displayed data to the lcd driver circuit is independent from access to the display data ram from mpu, accessing the display data ram asynchronously during liquid crystal display will not negatively affect the display such as flickering. the display timing generator circuit also generates common timing signal and liquid crystal alternating signal from the display clocks. normally, lcd waveform generates dual-frame driver waveform. however, by setting the data (n-1) to the n-line inversion drive register, n-line inversion driver waveform can be generated. when problem in display quality such as crosstalk exists, it can be solved by using the n-line inversion driver waveform. the number of the lines n to be alternated shall be determined by actually displaying on the lcd. dual-frame driver waveform (example of S1D15715 1/17duty) fig.6 16 17 1 2 3 4 5 6 12 13 14 15 16 17 1 2 3 4 5 6 cl frame alternating com 0 com 1 ram data seg n v 0 v 1 v 4 v ss v 0 v 1 v 4 v ss v 0 v 2 v 3 v ss
S1D15715 series technical manual 20 epson rev.1.0 n-line inversion driver waveform (example when S1D15715 1/17duty n=5 line reverse register is set to 4) fig.7 6.5 lcd driver circuits these are multiplexers outputting the lcd panel driving 4-level signal. it outputs lcd driver voltage that corresponds to the combinations of the display data, com scan signal and lcd ac signal. fig.8 shows an example of seg and com output waveforms. 16 17 1 2 3 4 5 6 12 13 14 15 16 17 1 2 3 4 5 6 cl frame alternating com 0 com 1 ram data seg n v 0 v 1 v 4 v ss v 0 v 1 v 4 v ss v 0 v 2 v 3 v ss
S1D15715 series technical manual rev.1.0 epson 21 fig.8 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 v ss v dd fr com0 v 0 v 1 v 2 v 3 v 4 v ss com1 com2 seg0 seg1 seg2 com0-seg0 com0-seg1 v 0 v 1 v 2 v 3 v 4 v ss v 0 v 1 v 2 v 3 v 4 v ss v 0 v 1 v 2 v 3 v 4 v ss v 0 v 1 v 2 v 3 v 4 v ss v 0 v 1 v 2 v 3 v 4 v ss v 0 v 1 v 2 v 3 v 4 v ss -v 4 -v 3 -v 2 -v 1 -v 0 v 0 v 1 v 2 v 3 v 4 v ss -v 4 -v 3 -v 2 -v 1 -v 0
S1D15715 series technical manual 22 epson rev.1.0 6.6 power supply circuit this power supply circuit is a low power supply consumption circuit that generates voltage required for driving liquid crystals, which consists of booster, voltage regulator and voltage follower circuits. the power supply circuit is controlled by power control set command. using this command, the booster circuit, the voltage regulator circuit, and the voltage follower circuit can be independently turned on or off. consequently, the external power supply and part of internal power supply circuit functions can be used simultaneously. table 8 lists the functions controllable from 3 bits data of the power control set command. and, table 9 shows sample combinations of the bits. table 8 state item ?1? ?0? d2 booster circuit control bit on off d1 voltage regulator circuit (v regulator circuit) control bit on off d0 voltage follower circuit (v/f circuit) control bit on off table 9 usage d2 d1 d0 booster circuit v regulator circuit v/f circuit external voltage input pins on booster circuit built-in power supply alone is used 1 1 1 on on on v dd used v regulator circuit and v/f circuits are used 0 1 1 off on on v out 1 open v/f circuits alone are used 0 0 1 off off on v 0 1 open external power supply alone is used 0 0 0 off off off v 0 to v 4 1 open pins on the booster circuits denote cap1+, cap1-, cap2+, cap2- pins. combinations other than the above cannot be used. 6.6.1 booster circuit using the booster circuit, it is possible to triple/double boosting of the v dd -v ss voltage level. triple boosting: if capacitor c 1 is inserted between cap1+ and cap1-, between cap2+ and cap2- and between v out and v dd , the potential between v dd and v ss is boosted to triple toward the positive side and it is output at v out pin. double boosting: if capacitor c 1 is inserted between cap1+ and cap1-, between v out and v dd , open cap2-, and jumper between cap2+ and v out , the potential between v dd and v ss is boosted to double toward the positive side and it is output at v out pin. if the potential between v dd -v ss is 5v 10% and is double boosting, the clamp circuit (approximately 5v) built in the v dd will prevent the v out potential from exceeding the absolute maximum rating (10v) fig.9 shows the connections and voltage relationships :
S1D15715 series technical manual rev.1.0 epson 23 fig.9 * the capacitance depends on the load of the lcd panel to be driven. set a value that lcd driver voltage may be stable (reference value = 1.0 to 4.7 f). 6.6.2 voltage regulator circuit the boosting voltage generated at the v out pin outputs liquid crystal drive voltage v 0 through the voltage regulator circuit. because the S1D15715 series has the high-accuracy constant voltage source, the 32-level electronic volume function and the internal resistor for the v 0 voltage regulator (= v 0 -resistor), it is possible to construct a high-accuracy voltage regulator circuit without external component. (a) when using the v 0 voltage regulator internal resistor the internal resistor for the v 0 voltage regulator resistor and the electronic volume function allows for the control of the liquid crystal voltage v 0 through commands only, without the need of adding an external resistor, and allows for the adjustment of the liquid crystal display contrast. the v 0 voltage can be calculated using the following expression within the range of |v 0 |<|v out |. v 0 =(1+rb/ra) ? v ev =(1+ rb/ra) ? (1- /200) ? v reg (expression a-1) [v ev =(1- /200) ? v reg ] v reg represents the constant voltage source within an ic. its value at t a =25 c is constant as shown in table 10. table 10 model v reg thermal gradient S1D15715, s1d15716, s1d15717 1.2v -0.05%/ c v dd v dd + v out + v out cap1- cap1- + cap1+ + cap1+ cap2- open cap2- + cap2+ cap2+ triple boosting double boosting S1D15715 series S1D15715 series v out = 3 v dd v out = 2 v dd = 9.0v = 10.0v v dd = 5.0v v dd = 3.0v v ss = 0v v ss = 0v potential relationship in triple boosting potential relationship in double boosting
S1D15715 series technical manual 24 epson rev.1.0 fig.10 is a value of the electronic volume, and can be set to one of 32-states by setting the 5-bit data in the electronic volume register. table 11 shows the value of . table 11 table 12 (reference values) d4 d3 d2 d1 d0 0 0 0 0 0 31 d3 d2 d1 1+rb/ra 0 0 0 0 1 30 0 0 0 5.45 0 0 0 1 0 29 0 0 1 5.71 : : 0 1 0 6.00 : : 0 1 1 6.32 1 1 1 0 0 3 1 0 0 6.67 1 1 1 0 1 2 1 0 1 7.06 1 1 1 1 0 1 1 1 0 7.50 1 1 1 1 1 0 1 1 1 external resistor can be used. rb/ra is the v 0 voltage regulator internal resistance ratio, and can be set to one of the 7 steps using the v 0 voltage regulator internal resistance ratio set command. by setting the 3-bit data in the v 0 voltage regulator internal resistance ratio register, the reference value of (1+rb/ra) ratio will be as the values shown in table 12. fig.11 shows the v 0 voltage based on the values of the v 0 voltage regulator internal resistance ratio register and the electronic volume register at t a =25 c. fig.11 v 0 voltage based on the values of v 0 voltage regulator internal resistance ratio register and the electronic volume register [t a =25c] internal rb internal ra - + v ev (constant voltage source + electronic volume) v 0 v ss 0 1 2 3 4 5 6 7 8 9 10 0 8 16 24 32 electric volume resister[decimal] v 0 [v] 0 1 2 3 4 5 6
S1D15715 series technical manual rev.1.0 epson 25 from fig.11 and expression a-1, the following setting will be employed. table 13 register content d7 d6 d5 d4 d3 d2 d1 d0 v 0 voltage regulator internal resistance ratio 0 0 1 0 0 0 1 1 electronic volume 1 0 0 1 0 0 0 0 table 14 shows v 0 voltage variable range and its pitch width available from electronic volume function when the above setting is employed. table 14 v 0 min. typ. max. unit variable range 6.41[80h] to 7.0[90h] to 7.58[9fh] [v] pitch width 38 [mv] [ ]: commands selected from the electronic volume. (b) when using the external resistor (when v 0 voltage regulator internal resistor is not used) it is also possible to select a supply voltage v 0 for lcd without using the v 0 voltage regulator internal resistor (resistance ratio select command [27h] for the internal v 0 voltage regulator resistors) by adding a resistor across v ss and v r as well as v r and v 0 . in this case too, using the electronic volume allows you to control lcd v 0 through the command and, thus, adjust the contrast of lcd display. voltage v 0 is given by the following expression when external resistance values ra' and rb' are specified in the range of |v 0 |<|v out |. v 0 = (1+rb?/ra?) ? v ev = (1+ rb?/ra?) ? (1- /200) ? v reg (expression b-1) [v ev =(1- /200) ? v reg ] v reg represents the constant voltage source on the ic. its value at t a =25c is constant as shown in table 10. fig.12 external rb' external ra' - + v ev (constant voltage source + electronic volume) v 0 v ss v r
S1D15715 series technical manual 26 epson rev.1.0 when the intermediate resistor values (d4, d3, d2, d1, d0) = (1, 0, 0, 0, 0) are selected from the electronic volume, the following is given by expression b-1 since = 15 and v reg = 1.2v (expression b-2). v 0 =(1+ rb?/ra?) ? (1- /200) ? v reg 7v=(1+ rb?/ra?) ? (1-15/200) ? 1.2 (expression b-2) if you select 5a for the current conducted to ra? and rb?, the following expression is derived: ra? rb? 1.4m ? (expression b-3) thus, the following is derived from expressions b-2 and b-3: rb?/ra? 5.31 ra? 220k ? , rb?=1180k ? table 15 shows the command selected from the electronic volume. table 16 lists v 0 voltage variable range and pitch width available from the electronic volume function. table 15 register content d7 d6 d5 d4 d3 d2 d1 d0 v 0 voltage regulator internal resistance ratio 0 0 1 0 0 1 1 1 electronic volume 1 0 0 1 0 0 0 0 table 16 v 0 min. typ. max. unit variable range 6.45[80h] to 7.0[90h] to 7.64[9fh] [v] pitch width 38.4 [mv] [ ]: commands selected from the electronic volume. (c) when using external resistors (when using variable resistors instead of the v 0 voltage regulator internal resistors) when using the above external resistor, lcd voltage v 0 can also be set by adding a variable resistor to finely tune ra? and rb?. in this case too, using the electronic volume function permits you to control an lcd voltage v 0 through the command and, thus, adjust the contrast of lcd display. the v 0 voltage can be obtained from the following expression by setting external resistors r1, r2 (variable resistors) and r3 within the range of |v 0 |<|v out | and finely tuning r2 ( ? r2): v 0 ={1+ (r3+r2- ? r2) / (r1+ ? r2)} ? v ev ={1+ (r3+r2- ? r2) / (r1+ ? r2)} ? (1- /200) ? v reg (expression c-1) [v ev =(1- /200) ? v reg ] v reg is the constant voltage source in the ic and its value remains at a constant level as shown in table 10 (t a =25c). fig.13 rb' ra' - + v ev (constant voltage source + electronic volume) v 0 v ss external resistor r1 external resistor r2 external resistor r3 ? r1 v r
S1D15715 series technical manual rev.1.0 epson 27 =15 and v reg = 1.2v when intermediate resistor values (d4, d3, d2, d1, d0) = (1, 0, 0, 0, 0) are selected from the electronic volume. thus, using expression c-1, you can select v 0 =9v when ? r2=0 ? in the following manner: 9v={1+(r3+r2)/r1} ? (1-15/200) ? 1.2 r3+r2=7.11 ? r1 (expression c-2) if you select 5a for the current to be conducted across v 0 and v ss when v 0 =7v (center value), sum of resistance of r1, r2 and r3 can be derived as shown below: r1+r2+r3 1.4m ? (expression c-3) from expressions c-2 and c-3, r1 1.4m ? /8.11 173k ? and, you can select v=5v when ? r2=r2 through the following computation: 5v={1+r3/(r1+r2)} ? (1-15/200) ? 1.2 r3/(r1+r2)=3.5 (expression c-4) r2 137k ? , r3 1.09m ? are derived from expressions c-2, c-3 and c-4. table 15 lists the command used, and table 17 lists v 0 voltage variable range and pitch width available from the electronic volume. table 17 v 0 min. typ. max. unit variable range 6.39[80h] to 7.0[90h] to 7.57[9fh] [v] pitch width 38.1 [mv] [ ]: commands selected from the electronic volume. when using the v 0 voltage regulator internal resistor or the electronic volume function, both of the voltage regulator circuit and the voltage follower circuit must be activated, as a minimum requirement, by the power control set command. when the booster circuit is turned off, necessary voltage must be supplied from v out . v r pin is enabled only when the v 0 voltage regulator internal resistors are not used. v r pin must be made open when these resistors are used. since vr pin has a higher input impedance, appropriate noise protection measures must be provided including cutting the wiring distance shorter or using shielded wire. 6.6.3 liquid crystal voltage generator circuit the v 0 voltage is divided by resistor-split within an ic and generates v 1 , v 2 , v 3 and v 4 potentials required for driving liquid crystals. then, v 1 , v 2 , v 3 and v 4 potentials are impedance-converted by the voltage follower circuit and supplied to the liquid crystal drive circuit. using the command, either 1/5 bias or 1/6 bias can be selected as bias ratio. 6.6.4 on-chip power supply turn off command sequence to turn the built-in power supply off, it is recommended that the following command sequence be observed to set the system in the power save state beforehand so that the residual power is discharged from the lcd panel, power supply pins and others. you can also turn the built-in power supply off by initializing it using ____ res pin or the reset command. when low level is input to the ____ res pin, short-circuit occurs between v out and v dd2 and between v 0 and v ss due to discharge. keep this in mind when using an external power supply. table 18 command address sequence contents (command and state) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 step1 display off 1 0 1 0 1 1 1 0 step2 display all points on 1 0 1 0 0 1 0 1 power save command (composite command) end built-in power off 0 0 1 0 1 0 0 0
S1D15715 series technical manual 28 epson rev.1.0 (1) when v 0 voltage regulator internal resistors are used (when triple boosting) (2) when v 0 voltage regulator internal resistors are not used (when triple boosting) (1) when v 0 voltage regulator internal resistors are not used (2) when v 0 voltage regulator internal resistors are used 6.6.5 sample circuits 1 when booster, voltage regulator and v/f circuits are all used 2 when voltage regulator and v/f circuits alone are used v dd c1 c1 c1 v 3 v 2 v 1 v ss v 0 v r v 4 v dd v out cap1- cap2- cap2+ cap1+ S1D15715 v ss c2 c2 c2 c2 c2 c1 c1 c1 v dd v 3 v 2 v 1 v 0 v r v 4 v dd v out cap1- cap2- cap2+ cap1+ S1D15715 v ss r1 r3 r2 v ss c2 c2 c2 c2 c2 v dd external power supply v 3 v 2 v 1 v ss v 0 v r v 4 v dd v out cap1- cap2- cap2+ cap1+ S1D15715 r1 r3 r2 v ss c2 c2 c2 c2 c2 v dd external power supply v 3 v 2 v 1 v ss v 0 v r v 4 v dd v out cap1- cap2- cap2+ cap1+ S1D15715 v ss c2 c2 c2 c2 c2
S1D15715 series technical manual rev.1.0 epson 29 (3) when v/f circuit alone is used (4) when built-in power supply is not used since v r pin has a higher impedance, wiring distance must be minimized or shielded wire must be used. sample setting when v 0 is varied between 8 and 9v item setting unit c1 1.0 to 4.7 f c2 0.01 to 1.0 f fig.14 v 3 v 2 v 1 v ss v 0 v r v 4 v dd v out cap1- cap2- cap2+ cap1+ S1D15715 v dd v ss external power supply c2 c2 c2 c2 c2 external power supply v ss v 3 v 2 v 1 v ss v 0 v r v 4 v dd v out cap1- cap2- cap2+ cap1+ S1D15715 v dd
S1D15715 series technical manual 30 epson rev.1.0 6.7 reset circuit when the ____ res pin is made to the low level or when the reset command is used, this lsi will become the initial setting state. indicated below is the initial setting state. ? serial interface internal shift register and counter clear ? power saver mode is entered. ? oscillation circuit is stopped. ? lcd power supply circuit is stopped. ? display off ? display all points on : (display all points on on/off command d0=?1?) ? segment/common driver outputs go to the v ss level. ? display normal ? page address : 0h ? column address : 0h ? display start line address : set at the first line ? segment driver direction : normal ? common driver direction : normal ? n-line inversion drive : cancel ? read modify write : off ? power control register : (d2, d1, d0) = (0, 0, 0) ? v 0 -resistor ratio register : (d2, d1, d0) = (0, 0, 0) ? electronic volume register : (d4, d3, d2, d1, d0) = (1, 0, 0, 0, 0) ? test mode is released. * voltage short circuit across v out and v dd as well as v 0 and v ss [allowed only when ____ res pin = low level]. when reset is detected, this lsi is set to above initialized states. however it has no effect on contents of ddram. because the internal state of the ic becomes inconstant during power on, initialization by ____ res pin is always required. check that each input pin is controlled after initialization through ____ res pin. if the control signal from mpu has high impedance, an overcurrent may flow through the ic. a protection is required to prevent high impedance at the input pin during power-on.
S1D15715 series technical manual rev.1.0 epson 31 7. command description S1D15715 series identifies the data bus signal by a combination of a0, ___ rd(e) and ___ wr(r/ __ w) signals. interpretation and execution of commands are performed only by the internal timing independent of external clocks. in the 80-series mpu interface, the command is activated when a low pulse is input to ___ rd pin for reading and when a low pulse in input to ___ wr pin for writing. in the 68-series mpu interface, the S1D15715 series enters a read mode when a high level is input to r/w pin and a write mode when a low level is input to r/ __ w pin, and the command is activated when a high pulse is input to e pin. therefore, in the command description and command table, the 68-series mpu interface is different from the 80-series mpu interface in that ___ rd(e) becomes ?1(h)? in status read and display data read command. taking the 80-series mpu interface as an example, commands will be explained below. when the serial interface is selected, the data is input in sequence starting with d7. 7.1 display on/off this command turns the display on and off. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 setting 0 1 0 1 0 1 0 1 1 1 0 display off 1 display on when the display off command is executed when in the display all points on mode, power saver mode is entered. see the section on the power saver for details. 7.2 display normal/reverse this command can reverse the lit and unlit display without overwriting the contents of the ddram. the contents of the ddram will be maintained. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 setting 0 1 0 1 0 1 0 0 1 1 0 normal: ddram data high 1 = lcd on potential normal: ddram data low = lcd on potential 7.3 display all points on/off this command makes it possible to force all display points on regardless of the content of the ddram. even when this is done, the ddram contents are maintained. this command takes priority over the display normal/reverse command. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 setting 0 1 0 1 0 1 0 0 1 0 0 normal display mode 1 display all points on when the display all points on command is executed when in the display off mode, power saver mode is entered. see the section on the power saver for details.
S1D15715 series technical manual 32 epson rev.1.0 7.4 page address set this command specifies the page address that corresponds to the low address when accessing the ddram from the mpu side (refer to fig.4). specifying the page address and column address enables the access to a desired bit of the ddram. even when the page address is changed, the display state will not be changed. for details, see the page address circuit of the ?functional description?. after the last column address (65h), page address is incremented by +1 (refer to fig.5). after the very last address (column=65h, page=3h), page address returns to 0h. page address 7h is the ddram area dedicate to the indicator, and only d0 is valid for data change. see the function explanation in ?ddram and page/column address circuit?, for details. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 page address 0 1 0 1 0 1 1 0 0 0 0 0h 0 0 1 1h 0 1 0 2h 0 1 1 3h 1 0 0 4h 7.5 column address set this command specifies the column address of the ddram (refer to fig.4). the column address is split into two sections (the upper 3-bits and lower 4-bits) when it is set (fundamentally, set continuously). each time the ddram is accessed, the column address automatically increments, making it possible for the mpu to continuously read and write the display data after the last column address (65h), column address returns to 00h (refer to fig.5). see the function explanation in ?ddram and page/column address circuit?, for details. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 setting 0 1 0 0 0 0 1 0 a6 a5 a4 upper bit address 0 a3 a2 a1 a0 lower bit address *disabled bit a6 a5 a4 a3 a2 a1 a0 column address 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 1 01h 0 0 0 0 0 1 0 02h : : 1 1 0 0 1 0 0 64h 1 1 0 0 1 0 1 65h
S1D15715 series technical manual rev.1.0 epson 33 7.6 display start line address set this command is used to specify the display start line address of the ddram (refer to fig.4). see the function explanation in ?line address circuit? for details. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 line address 0 1 0 0 1 0 0 0 0 0 0 00h 0 0 0 0 1 01h 0 0 0 1 0 02h : : 1 1 1 1 0 1eh 1 1 1 1 1 1fh 7.7 adc select (segment driver direction select) this command can reverse the correspondence between the ddram column address and the segment driver output (refer to fig.4). see the function explanation in ?ddram and page/column address circuit?, for details. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 setting 0 1 0 1 0 1 0 0 0 0 0 normal 1 reverse 7.8 common output status select this command can select the scanning direction of the com output pin. it can reverse the correspondence between the ddram line address and the common driver output. see the function explanation in ?line address circuit? for details. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 setting 0 1 0 1 1 0 0 0 * * * normal 1 reverse *disabled bit 7.9 display data read this commands reads 8-bit data from the specified ddram address. since the column address is automatically incremented after each read, the mpu can continuously read multiple-word data. one dummy read is required immediately after the column address has been set. see the function explanation in ?access to ddram and internal registers? and ?ddram and page/column address circuit?, for details. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 read data
S1D15715 series technical manual 34 epson rev.1.0 7.10 display data write this command writes 8-bit data to the specified ddram address. since the column address is automatically incremented after each write, the mpu can continuously write multiple-word data. see the function explanation in ?ddram and page/column address circuit?, for details. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 write data 7.11 read modify write this command is used paired with end command. once this command is issued, the column address is not incremented by display data read command but is incremented by display data write command. this mode is maintained until end command is issued. when end command is issued, the column address returns to the address it was at when read modify write command was issued. this function makes it possible to reduce the mpu load when there are data to change repeatedly in a specified display region, such as blinking cursor. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 1 1 0 0 0 0 0 * when end command is issued, only column address returns to the address. consequently, read modify write mode cannot be used over pages. since the page address is automatically incremented for this ic, when end command is executed after the data is written to the last column address (65h), it does not return to the original location in the display. when you want to maintain the current page address after a read modify write operation done on a column address between the start and the final column address (65h), you must specify the page address again. * even if in read modify write mode, other commands besides display data read/write can also be used. however, column address set command cannot be used. ? the sequence for cursor display fig.15 no yes completed? end dummy read page address set column address set read modify write data write data read data processing
S1D15715 series technical manual rev.1.0 epson 35 7.12 end this command releases the read modify write mode, and returns the column address to the address it was when read modify write command was issued. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 1 1 0 1 1 1 0 fig.16 7.13 power control set this command sets the power supply circuit function on/off. see the function explanation in ?power supply circuit? for details. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 mode 0 1 0 0 0 1 0 1 0 booster: off 1 booster: on 0 voltage regulator: off 1 voltage regulator: on 0 voltage follower: off 1 voltage follower: on 7.14 v 0 voltage regulator internal resistance ratio set this command sets the v 0 voltage regulator circuit internal resistance ratio. see the function explanation in ?power supply circuit? for details. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 rb/ra ratio v 0 voltage 0 1 0 0 0 1 0 0 0 0 0 small low 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 large high 1 1 1 external resistor mode n+1 n return end read modify write column address n+3 n+2 ??? ?????? ??? n n+m
S1D15715 series technical manual 36 epson rev.1.0 7.15 electronic volume set this command controls the liquid crystal drive voltage v 0 output from the voltage regulator circuit of the built-in liquid crystal power supply and can adjust the contrast of lcd panel display. see the function explanation in ?power supply circuit? for details. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 v 0 voltage 0 1 0 1 0 0 0 0 0 0 0 31 low 0 0 0 0 1 30 0 0 0 1 0 29 1 1 1 1 0 1 1 1 1 1 1 0 high 7.16 lcd bias set this command selects the voltage bias ratio required for the lcd. this command is enabled when the voltage follower circuit operates. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 bias s1d15a08 0 1 0 1 0 1 0 0 0 1 0 1/5 bias 1 1/6 bias 7.17 n-line inversion drive register set this command sets the number of the inversion lines of the lcd alternating driver to the register. the number of lines that can be set is between 2 to 16. for details, refer to the functional description of ?display timing generation circuit?. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 number of reverse line 0 1 0 0 0 1 1 0 0 0 0 - 0 0 0 1 2 0 0 1 0 3 1 1 1 0 15 1 1 1 1 16 7.18 canceling n-line inversion drive this command cancels n-line inversion drive and restores the normal dual-frame inversion driving. the value of n-line inversion drive register will not change. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 1 1 0 0 1 0 0
S1D15715 series technical manual rev.1.0 epson 37 7.19 power save (composite command) when the display all points on command is executed when in the display off mode, power save mode is entered, and the power consumption can be greatly reduced. fig.17 this mode stops every operation of the circuits for the driver, and can reduce current consumption nearly to a static current value if no access is made from the mpu. the internal states in the power saver mode is as follows: ? the oscillation circuit is stopped. ? the lcd power supply circuit is stopped. ? all lcd driver circuits are stopped and segment/common driver outputs output the v ss level. ? the display data and operation mode before execution of the power saver command are held, and the mpu can access to the ddram and internal registers. power save (display off & display all points on) power save mode power save off (display all points off) power save mode cancel (display off)
S1D15715 series technical manual 38 epson rev.1.0 7.20 reset when this command is issued, S1D15715 series is initialized (same operation as ____ res pin=low input this command, however, is not used for introducing short circuit across v out and v dd or v 0 and v ss .) also note that initialization of the ddram does not take place in parallel with initialization of the lsi. see the function explanation in ?reset circuit? for details. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 1 1 0 0 0 1 0 when initializing the S1D15715 series while power is turned on, reset signal to the ____ res pin is used. this signal cannot be replaced by the reset command. 7.21 nop non-operation command a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 1 1 0 0 0 1 1 7.22 test this is a command for lsi chip testing. please do not use. if the test command is issued by accident, it can be cleared by applying an low signal to the ____ res pin, or by issuing the reset command or the display on/off command. a0 e ___ rd r/ __ w ___ wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 1 * 1 * * * * *disabled bit *: S1D15715 series chip maintain their operating modes, but excessive external noise, etc., may happen to change them. measures are required to prevent noise generation or influence on installation and systems. moreover, it is recommended that the operating modes are refreshed periodically to prevent the effects of unanticipated noise.
S1D15715 series technical manual rev.1.0 epson 39 table 19 S1D15715 series command table command code command a0 ___ rd _ _ _ wr d7 d6 d5 d4 d3 d2 d1 d0 function (1) display on/off 0 1 0 1 0 1 0 1 1 1 0 1 lcd display on/off 0: off, 1: on (2) display normal/reverse 0 1 0 1 0 1 0 0 1 1 0 1 lcd display normal/reverse 0: normal, 1: reverse (3) display all points on/off 0 1 0 1 0 1 0 0 1 0 0 1 display all points 0: normal display, 1: all points on (4) page address set 0 1 0 1 0 1 1 0 page address page address sets the ddram page address (5) column address set upper 3-bit address 0 1 0 0 0 0 1 0 upper column address upper column address sets the upper 3-bit for ddram column address column address set lower 4-bit address 0 1 0 0 0 0 0 lower column address lower column address sets the lower 4-bit for ddram column address (6) display start line address set 0 1 0 0 1 0 display start address display start address sets the ddram display start line address (7) adc select 0 1 0 1 0 1 0 0 0 0 0 1 supports the seg output of the ddram 0: normal, 1: reverse (8) common output status select 0 1 0 1 1 0 0 0 1 * * * selects the scanning direction of com output 0: normal, 1: reverse (9) display data read 1 0 1 read data reads from the ddram (10) display data write 1 1 0 write data writes to the ddram (11) read modify write 0 1 0 1 1 1 0 0 0 0 0 column address increment at write: +1, at read: 0 (12) end 0 1 0 1 1 1 0 1 1 1 0 releases read modify write mode (13) power control set 0 1 0 0 0 1 0 1 operating mode sets the on-chip power supply circuit operating mode (14) v 0 voltage regulator internal resistance ratio set 0 1 0 0 0 1 0 0 resistance ratio setting selects the state of internal resistance ratio (rb/ra) (15) electronic volume register 0 1 0 1 0 0 electronic volume value sets the v 0 output voltage to the electronic volume register (16) lcd bias set - - - 1 0 1 0 0 0 1 0 1 setting the lcd driver voltage bias ratio 0: 1/5 bias, 1 1/6 bias (17) n-line inversion drive register set 0 1 0 0 0 1 1 number of inversion line line inversion drive setting the line number (18) n-line inversion drive cancel 0 1 0 1 1 1 0 0 1 0 0 canceling the line inversion drive (19) power saver - - - - - - - - - - - compound command of display off and display all points on (20) reset 0 1 0 1 1 1 0 0 0 1 0 software reset (21) nop 0 1 0 1 1 1 0 0 0 1 1 non-operation (22) test 0 1 0 1 1 * 1 * * * * ic test command. do not use. (note) * : disabled data
S1D15715 series technical manual 40 epson rev.1.0 instruction setup example (for your reference) note: if charge remains on the smoothing capacitor connected across the lcd drive voltage output pin troubles (such as momentary blackening) can occur on the display screen during its powering on process. in order to avoid such troubles, it is recommended to implement the following flow. 1 when switching to the built-in power supply takes place immediately after powering on: wait until power is settled turn v dd - v ss power on while ____ res pin=low is selected initial setup is complete [the built-in power supply is turned on, display off state.] selecting necessary functions using the commands (user setup) (14) specify the v 0 voltage regulator internal resistance ratio * 7 (15) set up the electronic volume * 8 selecting necessary function from the command (user setup) (13) set up the power control * 9 selecting necessary functions using the commands (user setup) (2) select either normal/reversing display * 2 (6) specify the start line set * 3 (7) implement adc select * 4 (8) select the common output mode * 5 (17) setting n-line inversion drive register set * 6 initial state (default) * 1 release the reset mode ( ____ res pin=high) canceling the power save mode (user setup) (3) display all points off * 10
S1D15715 series technical manual rev.1.0 epson 41 note : reference items *1: refer to 6. functional description ?6.7 reset circuit? in the initial setup mode (default), too, contents of the display data ram is still uncertain. *2: refer to the 7. command description ?(2) normal/reversing display? *3: refer to the 7. command description ?(6) display start line set? *4: refer to the 7. command description ?(7) adc select? *5: refer to the 7. command description ?(8) common output status select? *6: refer to the 7. command description ?(17) setting n-line inversion drive register set? *7: refer to thee 6. functional description ?6.6 power supply circuit? and 7. command description ?(14) v 0 voltage regulator internal resistance ratio set?. *8: refer to the 6. functional description ?6.6 power supply circuit? and 7. command description ?(15) electronic volume?. *9: refer to the 6. functional description ?6.6 power supply circuit? and 7. command description ?(13) power control set?. *10: refer to the 7. command description : ?(19) power save?
S1D15715 series technical manual 42 epson rev.1.0 2 data display note: reference items *9: refer to the 7. command description ?(6) display start line set? *10: refer to the 7. command description ?(4) page address set? *11: refer to the 7. command description ?(5) column address set? *12: refer to the 7. command description ?(10) display data write? *13: refer to the 7. command description ?(1) display on/off? the all-white display of data should be avoided as much as practicable right after the display mode is turned on (during display on). 3 powering off *14 note: reference items *14: this ic is provided on the power supply v dd -v ss logic to offer control over the v 0 -v ss drivers on the lcd power supply. thus, if the power supply v dd -v ss is turned off while voltage is still remaining on the lcd power supply v 0 -v ss , the drivers (both com and seg) can generate uncontrolled output. make sure to observe the following powering off procedure: ? turn off the built-in power supply first, then, after making sure that potential on v 0 to v 4 is lower than the lcd panel threshold voltage, turn the ic power (v dd -v ss ) off. also refer to the 6. functional description ?power supply circuit?. *15: refer to the 7. command description ?(19) power save? after entering the power save command, you must implement reset procedure from ____ res pin before turning off v dd -v ss power. selecting necessary functions using the commands (user setup) (6) select the display start line * 9 (4) select the page address * 10 (5) select the column address * 11 initialization is complete data display is ended selecting necessary functions using the commands (user setup) (1) turn on or off the display * 13 selecting necessary functions using the commands (user setup) (10) turn on the display data write operation * 12 turn v dd -v ss power off any state selecting necessary functions using the commands (user setup) (19) select the power save mode * 15 select the reset active ( ____ res pin=low) the time ( t l ) provided between turning on of the reset active and turning off of v dd -v ss power (v dd -v ss =1.8v) must be longer than the time required for v 0 -v 4 potential to go lower ( t h ) than the threshold voltage set on the lcd panel (usually 1v). for ? t h ?, see the ?reference data? in the following section. if ? t h ? is excessively long, it must be cut short by installing a resistor across v 0 and v ss .
S1D15715 series technical manual rev.1.0 epson 43 4 refresh it is recommended that the operating modes and display contents be refreshed periodically. 5 precautions on powering off turn the power (lcd power (v 0 -v ss ) system off) save mode off -> then, turn the power (v dd -v ss ) off. ? the requirement t l > t h must be strictly observed. ? if t l < t h , display failures can result. t l must be specified on software from mpu. t h depends on discharging capability of the drivers. see ?reference data? in the following section. it also depends on a given lcd panel, thus actual timing must be determined after experimenting on your lcd panel. display on/off command refresh sequence implement ddram refresh set every command to the selected setting v dd seg com v 4 v 3 v 2 v 1 v 0 approximately 1v: lower than vth on the lcd panel 1.8v t l t h power save power off for t h , see the ?reference data?. since power (v dd -v ss ) is turned off, output cannot be maintained at a fixed level. v ss v ss v ss
S1D15715 series technical manual 44 epson rev.1.0 turn off the reset mode(lcd power (v 0 -v ss ) system ). -> then turn the power (v dd -v ss ) off. ? the requirement t l > t h must be strictly observed. ? if t l < t h , display failures can result. when specifying t l , measures such as extending fall time of power supply (v dd -v ss ) should be considered. t h depends on discharging capability of the drivers. see ?reference data? in the following section. it also depends on model of a given lcd panel, thus actual timing must be determined after experimenting on your lcd panel. 6 reference data the following data is for your reference alone. t h is significantly affected by capacity of v 0 pin, thus you must verify appropriateness of a selected t h on the panel being equipped with the pin. [conditions: v dd =1.8v, voltage is tripled and capacity of the boosting capacitor=1.0f] when v 0 is under no-load, t h per voltage is 22s. it becomes 200s when v 0 =9v. capacity dependency is 1pf. ? t h per voltage is 50ns. an example: when v dd =1.8v, v 0 =8.0v and v 0 pin capacity [board capacity] (c l )=100pf. t h =22 s 8v+50ns 100pf 8v=216s v dd seg com v 4 v 3 v 2 v 1 v 0 approximately 1v : lower than v th on the lcd panel 1.8v t l t h reset power off for t h , see the ?reference data?. since power (v dd -v ss ) is turned off, output cannot be maintained at a fixed level. v ss v ss v ss
S1D15715 series technical manual rev.1.0 epson 45 8. absolute maximum rating table 20 item symbol standard value unit -0.3 to +6.0 v double boosting -0.3 to +5.0 supply voltage (1) triple boosting v dd -0.3 to +3.3 supply voltage (2) v 0 , v out -0.3 to +10.0 v supply voltage (3) v 1 , v 2 , v 3 , v 4 -0.3 to v 0 v input voltage v in -0.3 to v dd +0.3 v output voltage v o -0.3 to v dd +0.3 v operating temperature t opr -40 to +85 c storage tcp t str -55 to +100 c temperature bare chip -55 to +125 note 1: all voltages are based on the condition that the v ss is equal to 0v. note 2: voltages v 0 , v 1 , v 2 , v 3 and v 4 must always keep up the condition of v 0 v 1 v 2 v 3 v 4 v ss and v out v 0 v ss , v out v dd . note 3: if the lsi chip is used in an environment exceeding the absolute maximum ratings, it may be destroyed permanently. during normal operation, electrical characteristics conditions should be observed. otherwise, the lsi chip may malfunction or the lsi reliability may drop. v cc S1D15715 series side gnd system v 0 ,v out v 1 to v 4 v ss v dd v ss
S1D15715 series technical manual 46 epson rev.1.0 9. dc characteristics table 21 v ss = 0v, v dd = 3v10%, t a = -40 to +85c unless otherwise noted standard value item symbol condition min. typ. max. unit pin used supply voltage (1) v dd - 1.8 - 5.5 v v dd * 1 v 0 - 4.5 - 9.0 - v 0 * 2 v 1 , v 2 - 0.6 v 0 - v 0 v v 1 , v 2 supply voltage (2) v 3 , v 4 - v ss - 0.4 v 0 - v 3 , v 4 high-level input voltage v ih - 0.8 v dd - v dd v low-level input voltage v il - v ss - 0.2 v dd v * 3 high-level output voltage v oh i oh =-0.5ma 0.8 v dd - v dd v low-level output voltage v ol i ol = 0.5ma v ss - 0.2 v dd v * 4 input leak current i li -1.0 - 1.0 a * 5 output leak current i lo v in = v dd or v ss -3.0 - 3.0 a * 6 lcd driver on resistance r on v 0 =7.0v t a =25 c - 4.0 10.0 k ? segn, comn * 7 static current consumption i ddq t a =25 c - 0.01 5.0 a v dd , v dd2 output leak current i 0q v 0 =7.0v t a =25 c - 0.01 15.0 a v 0 input pin capacitance c in t a =25 c, f=1mhz - 20.0 30.0 pf S1D15715 20.67 21.76 22.85 s1d15716 21.88 23.04 24.2 built-in oscillation f osc t a =25 c s1d15717 20.06 21.12 22.18 khz * 8 S1D15715 10.88 21.76 43.52 s1d15716 5.76 11.52 23.04 oscillation frequency external input f cl t a =25 c s1d15717 21.12 42.24 84.48 khz cl * 8 table 22 standard value item symbol condition min. typ. max. unit pin used double boosting 1.8 - 5.5 input voltage v dd triple boosting 1.8 - 3.3 v dd * 1 boosted output voltage v out - - - 10.0 v out operating voltage of voltage regulator circuit v out - 5.0 - 10.0 v out operating voltage of v/f circuit v 0 - 4.5 - 9.0 v 0 * 9 built-in power supply circuit reference voltage v reg -0.05%/ c t a =25c 1.16 1.20 1.24 v note 1: all voltages are based on the condition that the v ss is equal to 0v. note 2: voltages v 0 , v 1 , v 2 , v 3 and v 4 must always keep the condition of v 0 v 1 v 2 v 3 v 4 v ss and v out v 0 v ss , v out v dd . note 3: if the lsi chip is used in an environment exceeding the absolute maximum ratings, it may be destroyed permanently. during normal operation, electrical characteristics conditions should be observed. otherwise, the lsi chip may malfunction or the lsi reliability may drop.
S1D15715 series technical manual rev.1.0 epson 47 dynamic operating current (1) - when display is turned on with the built-in power supply being disconnected [t a =25c and output under no-load]. following shows current consumed by entire ic when external power supply is used. table 23.1 display: all-white item symbol condition min. typ. max. unit remarks i ss (1) v dd =3.0v,v 0 =7.0v - 24 41 S1D15715 i ss (1) v dd =5.0v,v 0 =7.0v - 26 44 a * 10 i ss (1) v dd =3.0v,v 0 =7.0v - 24 41 s1d15716 i ss (1) v dd =5.0v,v 0 =7.0v - 25 43 a * 10 i ss (1) v dd =3.0v,v 0 =7.0v - 25 43 s1d15717 i ss (1) v dd =5.0v,v 0 =7.0v - 27 46 a * 10 table 23.2 display: checker pattern item symbol condition min. typ. max. unit remarks i ss (1) v dd =3.0v,v 0 =7.0v - 25 43 S1D15715 i ss (1) v dd =5.0v,v 0 =7.0v - 27 46 a * 10 i ss (1) v dd =3.0v,v 0 =7.0v - 24 41 s1d15716 i ss (1) v dd =5.0v,v 0 =7.0v - 26 44 a * 10 i ss (1) v dd =3.0v,v 0 =7.0v - 26 44 s1d15717 i ss (1) v dd =5.0v,v 0 =7.0v - 29 49 a * 10 dynamic operating current (2) - when display is turned on with the built-in power supply being connected [t a =25c and output under no-load]. table 24.1 display: all-white item symbol condition min. typ. max. unit remarks i ss (2) v dd =5.0v,v 0 =7.0v, double boosting - 35 60 S1D15715 i ss (2) v dd =3.0v,v 0 =7.0v, triple boosting - 42 72 a * 10 i ss (2) v dd =5.0v,v 0 =7.0v, double boosting - 32 55 s1d15716 i ss (2) v dd =3.0v,v 0 =7.0v, triple boosting - 38 65 a * 10 i ss (2) v dd =5.0v,v 0 =7.0v, double boosting - 36 62 s1d15717 i ss (2) v dd =3.0v,v 0 =7.0v, triple boosting - 43 73 a * 10 table 24.2 display: checker pattern item symbol condition min. typ. max. unit remarks i ss (2) v dd =5.0v,v 0 =7.0v, double boosting - 37 63 S1D15715 i ss (2) v dd =3.0v,v 0 =7.0v, triple boosting - 43 73 a * 10 i ss (2) v dd =5.0v,v 0 =7.0v, double boosting - 33 56 s1d15716 i ss (2) v dd =3.0v,v 0 =7.0v, triple boosting - 39 67 a * 10 i ss (2) v dd =5.0v,v 0 =7.0v, double boosting - 39 67 s1d15717 i ss (2) v dd =3.0v,v 0 =7.0v, triple boosting - 46 78 a * 10
S1D15715 series technical manual 48 epson rev.1.0 current consumption in the power save mode [t a =25c and output under no-load] table 25 item symbol condition min. typ. max. unit remarks S1D15715 i ss (3) v dd =1.8v to 5.0v - 0.01 5 - s1d15716 i ss (3) v dd =1.8v to 5.0v - 0.01 5 - s1d15717 i ss (3) v dd =1.8v to 5.0v - 0.01 5 a -
S1D15715 series technical manual rev.1.0 epson 49 [reference data 1] dynamic operating current (1) - when lcd display is turned on with external power supply being connected (all-white display) fig.16 dynamic operating current (1) - when lcd display is turned on with external power supply being connected (checker pattern display) fig.17 0 10 20 30 40 0.0 2.0 4.0 6.0 8.0 v dd [v] iss(1) [a] S1D15715 s1d15716 s1d15717 conditions: built-in power supply off external power supply on v 0 -v ss =7.0v t a =25 c display pattern : all-white remarks: see *10 conditions: built-in power supply off external power supply on v 0 -v ss 7.0v t a =25 c display pattern : checker remarks: see *10 0 10 20 30 40 0.0 2.0 4.0 6.0 8.0 v dd [v] iss(1) [a] S1D15715 s1d15716 s1d15717
S1D15715 series technical manual 50 epson rev.1.0 [reference data 2] dynamic operating current (3) - during an access is being made fig.18 [reference data 3] operating voltage range of v dd and v 0 systems. *2 fig.19 this chart shows curren t consumption when the checke r p attern write is constantl y implemented in f cyc . i ss (1) alone is consume d when an access is not taking place. conditions: s1d15717 built-in power supply off, external power supply on v 0 -v ss 7.0v t a =25 c tbd operating consumption current idd 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 f cyc [mhz] idd [ma] v dd =3.0v v dd =5.0v S1D15715 series 1 0 . 0 5.0 0 0 2 4 6 9.0 5.4 4.5 1.8 3.0 5.5 v 0 [v] v dd [v] operation ran g e
S1D15715 series technical manual rev.1.0 epson 51 [reference items] *1 although wide operating voltage range is warranted, and exemption to it is when an access made by mpu is accompanied with radical voltage fluctuations. an access made by mpu is accompanied with radical voltage fluctuations. *2 see fig.21 for the operating voltage range of v dd and v 0 systems. it is applicable when an external power supply is used. *3 a0, d0 to d5, d6(scl), d7(si), __ rd(e), __ wr(r/ _ w), __ cs, cl, c86, p/s, ____ res and sel pins. v ih =0.8v dd to v dd , v il =v ss to 0.2v dd when v dd =1.8v to 2.7v. *4 d0 to d7 pins. i oh =-0.25ma, i ol =0.25ma when v dd =1.8v to 2.7v. *5 a0, __ rd (e), __ wr(r/ _ w), __ cs, c86, p/s, cl, ____ res and sel pins. *6 it is applicable when d0 to d5, d6(scl) and d7(si) pins are placed in high impedance. *7 it represents the resistance value to be employed when 0.1v is applied across the output pin segn or comn and respective power terminals (v 1 , v 2 , v 3 and v 4 ). it must be selected within the operating voltage range (3). r on =0.1v/ ? i ( ? i represents the current conducted when 0.1v is applied when the power supply is turned on). *8 for the relationship between the oscillating frequency and frame frequency, refer to table 6. external inputs listed in the standard value space are recommended values. *9 adjustment of the v 0 voltage regulator circuit must be done within the operating voltage range of the voltage follower circuit. *10 the built-in oscillation circuit is used. it indicates current consumed by the independent ic when the display is turned on. it does not include current consumed due to the lcd panel capacity or wiring capacity (driver output is under no-load). these values are applicable when the access is not made by mpu.
S1D15715 series technical manual 52 epson rev.1.0 10. ac characteristics system bus read/write characteristics 1 (80-series mpu) fig.20 table 26 v dd = 4.5v to 5.5v, t a = -40 to +85 c standard value item signal symbol condition min. max. unit address setup time a0 t aw8 - 0 - ns address hold time t ah8 - 15 - system cycle time - t cyc8 - 400 - control low pulse width ( ___ wr) ___ wr t cclw - 80 - control low pulse width ( ___ r d ) ___ rd t cclr - 200 - control high pulse width ( ___ wr) ___ wr t cchw - 100 - control high pulse width ( ___ rd ) ___ rd t cchr - 100 - data setup time d7 to d0 t ds8 - 60 - data hold time t dh8 - 25 - rd access time t acc8 c l =100pf - 210 output disable time t oh8 - 5 100 t cclr, t cclw t cchr, t cchw t cyc8 t aw8 t ah8 t ds8 t dh8 t acc8 t oh8 a0 d 7 to d 0 (write) d 7 to d 0 (read) ___ cs ___ wr, ___ rd
S1D15715 series technical manual rev.1.0 epson 53 table 27 v dd = 2.7v to 4.5v, t a = -40 to +85 c standard value item signal symbol condition min. max. unit address setup time a0 t aw8 - 0 - ns address hold time t ah8 - 15 - system cycle time - t cyc8 - 500 - control low pulse width ( ___ wr) ___ wr t cclw - 100 - control low pulse width ( ___ rd ) ___ rd t cc l r - 250 - control high pulse width ( ___ wr) ___ wr t cchw - 100 - control high pulse width ( ___ rd ) ___ rd t cchr - 100 - data setup time d7 to d0 t ds8 - 120 - data hold time t dh8 - 20 - rd access time t acc8 c l =100pf - 230 output disable time t oh8 - 5 100 table 28 v dd = 1.8v to 2.7v, t a = -40 to +85 c standard value item signal symbol condition min. max. unit address setup time a0 t aw8 - 0 - ns address hold time t ah8 - 10 - s y stem c y cle time - t c y c8 - 1000 - control low pulse width ( ___ w r ) ___ wr t cc l w - 150 - control low pulse width ( ___ rd ) ___ rd t cclr - 350 - control high pulse width ( ___ wr) ___ wr t cchw - 150 - control high pulse width ( ___ rd ) ___ rd t cchr - 150 - data setup time d7 to d0 t ds8 - 120 - data hold time t dh8 - 20 - rd access time t acc8 c l =100pf - 310 output disable time t oh8 - 10 200 ? the rise and fall times (tr and tf) of the input signal are specified for less than 15ns. ? when using the system cycle time at high speed, they are specified for ( t r + t f ) ( t cyc8 - t cclw - t cchw ) or ( t r + t f ) ( t cyc8 - t cclr - t cchr ). ? all timings are specified based on the 20 and 80% of v dd . ? t cclw and t cclr are specified for the overlap period when ___ cs is at low level and ___ wr, ___ rd are at the low level. ? the timing for a 0 is specified for the overlap period when ___ cs is at low level and ___ wr, ___ rd are at the low level.
S1D15715 series technical manual 54 epson rev.1.0 system bus read/write characteristics 2 (68-series mpu) fig.21 table 29 v dd = 4.5v to 5.5v, t a = -40 to +85 c standard value item signal symbol condition min. max. unit address setup time a0, t aw6 - 0 - ns address hold time ___ wr t ah6 - 5 - system cycle time - t cyc6 - 400 - enable high pulse width read e t ewhr - 200 - write t ewhw - 80 - enable low pulse width read - t ewlr - 100 - write t ewlw - 100 - data setup time d7 to d0 t ds6 - 60 - data hold time t dh6 - 25 - rd access time t acc6 c l =100pf - 210 output disable time t oh6 - 5 100 t ewhr , t ewhw t ewlr , t ewlw t cyc6 t aw6 t ah6 t ds6 t dh6 t acc6 t oh6 e d 7 to d 0 (write) d 7 to d 0 (read) ___ cs a 0 , r/ __ w
S1D15715 series technical manual rev.1.0 epson 55 table 30 v dd = 2.7v to 4.5v, t a = -40 to +85 c standard value item signal symbol condition min. max. unit address setup time a0, t aw6 - 0 - ns address hold time ___ wr t ah6 - 5 - system cycle time - t cyc6 - 500 - enable high pulse width read e t ewhr - 250 - write t ewhw - 100 - enable low pulse width read - t ewlr - 100 - write t ewlw - 100 - data setup time d7 to d0 t ds6 - 70 - data hold time t dh6 - 20 - rd access time t acc6 c l =100pf - 230 output disable time t oh6 - 5 100 table 31 v dd = 1.8v to 2.7v, t a = -40 to +85 c standard value item signal symbol condition min. max. unit address setup time a0, t a w 6 - 0 - ns address hold time ___ wr t ah6 - 5 - system cycle time - t cyc6 - 1000 - enable high pulse width read e t ewhr - 350 - write t ewhw - 150 - enable low pulse width read - t ewlr - 150 - write t ewlw - 150 - data setup time d7 to d0 t ds6 - 120 - data hold time t dh6 - 20 - rd access time t acc6 c l =100pf - 310 output disable time t oh6 - 10 200 ? the rise and fall times ( t r and t f ) of the input signal are specified for less than 15ns. when using the system cycle time at high speed, they are specified for ( t r + t f ) ( t cyc6 - t ewlw - t ewhw ) or ( t r + t f ) ( t cyc6 - t ewlr - t ewhr ). ? all timings are specified based on the 20 and 80% of v dd . ? t ewlw and t ewlr are specified for the overlap period when ___ cs is at low level and e is at the high level. ? the timing of a0 is specified for the overlap period when ___ cs is at low level and e is at the high level.
S1D15715 series technical manual 56 epson rev.1.0 serial interface characteristics fig.22 table 32 v dd = 4.5v to 5.5v, t a = -40 to +85 c standard value item signal symbol condition min. max. unit serial clock cycle scl t scyc - 125 - ns scl high pulse width t shw - 50 - scl low pulse width t slw - 50 - address setup time a0 t sas - 75 - address hold time t sah - 75 - data setup time si t sds - 50 - data hold time t sdh - 50 - ___ cs -scl time ___ cs t css - 75 - t csh - 75 - t scyc t css t csh t sas t r t slw t sds si scl a0 ___ cs t sah t shw t sdh t f
S1D15715 series technical manual rev.1.0 epson 57 table 33 v dd = 2.7v to 4.5v, t a = -40 to +85 c standard value item signal symbol condition min. max. unit serial clock cycle scl t scyc - 125 - ns scl high pulse width t shw - 50 - scl low pulse width t slw - 50 - address setup time a0 t sas - 75 - address hold time t sah - 75 - data setup time si t sds - 50 - data hold time t sdh - 50 - ___ cs -scl time ___ cs t css - 75 - t csh - 75 - table 34 v dd = 1.8v to 2.7v, t a = -40 to +85 c standard value item signal symbol condition min. max. unit serial clock cycle scl t scyc - 200 - ns scl high pulse width t shw - 75 - scl low pulse width t slw - 75 - address setup time a0 t sas - 75 - address hold time t sah - 75 - data setup time si t sds - 50 - d a ta hold time t sdh - 50 - ___ cs -scl time ___ cs t css - 100 - t csh - 100 - ? the rise and fall times ( t r and t f ) of the input signal are specified for less than 15ns. ? every timing is specified on the basis of 20% and 80% of v dd .
S1D15715 series technical manual 58 epson rev.1.0 reset input timing fig.23 table 35 v dd = 4.5v to 5.5v, t a = -40 to +85 c standard value item signal symbol condition min. max. unit reset time - t r - - 1000 ns reset low pulse width ____ res t rw - 1000 - table 36 v dd = 2.7v to 4.5v, ta = -40 to +85 c standard value item signal symbol condition min. max. unit reset time - t r - - 1000 ns reset low pulse width ____ res t rw - 1000 - table 37 v dd = 1.8v to 2.7v, ta = -40 to +85 c standard value item signal symbol condition min. max. unit reset time - t r - - 1500 ns reset low pulse width ____ res t rw - 1500 - ? the rise and fall times ( t r and t f ) of the input signal are specified for less than 15ns. ? every timing is specified on the basis of 20% and 80% of v dd . reset done reset internal state t rw t r ____ res
S1D15715 series technical manual rev.1.0 epson 59 11. mpu interface (reference examples) the S1D15715 series can be directly connected to the 80-series mpu or to the 68-series mpu. furthermore, by employment of the serial interface, they can be operated by smaller number of signal lines. after initialization has been made by the ____ res pin, each input pin of the S1D15715 series needs to be controlled properly. (1) 80-series mpu (2) 68-series mpu (3) serial interface _ __ rd _ __ wr _ ___ res v ss v dd v cc gnd d0 to d7 a1 to a7 a0 v dd mpu d0 t o d7 p/s c86 _ __ cs a 0 decoder S1D15715 _ iorq ______ reset _ __ rd _ __ wr _ ___ res fig.24 v ss v ss v dd v cc gnd d0 to d7 a1 to a15 a0 v dd mpu d0 to d7 p/s c86 a 0 decoder vma e r/ _ _ w ___ _ res ______ reset r/ __ w fig.25 S1D15715 _ ___ res e _ __ cs v ss v dd v dd or v ss v ss v cc gnd port 1 port 2 a1 to a7 a0 v dd mpu p/s c86 a 0 decoder _ _____ reset si scl fig.26 _ ___ res ___ _ r e s _ __ cs v ss S1D15715
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document code: 405001202 first issue march, 2004 printed in japan h a epson electronic devices website electronic devices marketing division oo http://www.epsondevice.com/ S1D15715 series technical manual

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