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1 dac7734 16-bit, quad voltage output, serial input digital-to-analog converter dac7734 description the dac7734 is a 16-bit, quad voltage output, digital- to-analog converter with guaranteed 16-bit monotonic performance over the specified temperature range. it accepts 24-bit serial input data, has double-buffered dac input logic (allowing simultaneous update of all dacs), and provides a serial data output for daisy chaining multiple dacs. programmable asynchronous reset clears all registers to a mid-scale code of 8000 h or to a zero-scale of 0000 h . the dac7734 can operate from a single +15v supply or from +15v and C15v, and +5v supplies. low power and small size per dac make the dac7734 ideal for automatic test equipment, dac-per-pin pro- grammers, data acquisition systems, and closed-loop servo-control. the dac7734 is available in a 48-lead ssop package and offers guaranteed specifications over the C40 c to +85 c temperature range. features l low power: 200mw l unipolar or bipolar operation l single supply output range: +10v l dual supply output range: 10v l settling time: 10 m s to 0.003% l 16-bit monotonicity: C40 c to +85 c l programmable reset to mid-scale or zero-scale l double-buffered data inputs l 1 lsb dnl: C40 c to +85 c applications l process control l ate pin electronics l closed-loop servo-control l motor control l data acquisition systems l dac-per-pin programmers ? 1999 burr-brown corporation pds-1570a printed in u.s.a. december, 1999 international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? i mmediate product info: (800) 548-6132 for most current data sheet and other product information, visit www.burr-brown.com dac a dac register a input register a shift register dac b dac register b input register b dac c dac register c input register c dac d dac register d input register d v ref l ab v ref h ab v ref h ab sense v ref l ab sense v out d v out c v out b v out a v out b sense v ref l cd v ref h cd sdi sdo control logic cs clock rst restsel ldac load agnd dgnd v out c sense v out d sense v out a sense v cc v ss v dd dac7734 v ref l cd sense v ref h cd sense dac7734 sbas138
2 dac7734 the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. dac7734e dac7734eb dac7734ec parameter conditions min typ max min typ max min typ max units accuracy linearity error (inl) t = 25 c 3 [ 2 lsb t min to t max 4 [ 3 lsb linearity match 4 [ 2 lsb differential linearity error (dnl) t = 25 c 3 2 1 lsb t min to t max 3 2 1 lsb monotonicity, t min to t max 14 15 16 bits bipolar zero error t = 25 c 0.01 0.025 [[ % of fsr bipolar zero error, t min to t max 0.05 [[ % of fsr full-scale error t = 25 c 0.025 [[ % of fsr full-scale error, t min to t max 0.05 [[ % of fsr bipolar zero matching channel-to-channel 0.024 [[ % of fsr matching full-scale matching channel-to-channel 0.024 [[ % of fsr matching power supply rejection ratio (psrr) at full scale 25 [[ ppm/v analog output voltage output v ref lv ref h [[[ [ v output current 5 [[ ma maximum load capacitance 500 [[ pf short-circuit current 20 [[ ma short-circuit duration to v ss , v cc or gnd indefinite [[ reference input ref high input voltage range v ref l + 1.25 +10 [[[ [ v ref low input voltage range C10 v ref h C 1.25 [[[ [ v ref high input current C0.3 2.6 [[ ma ref low input current C3.2 C0.3 [[ ma dynamic performance settling time to 0.003%, 20v 9 11 [[ [ [ m s output step channel-to-channel crosstalk see figure 5 0.5 [[ lsb digital feedthrough 2 [[ nv-s output noise voltage f = 10khz 60 [[ nv/ ? hz digital input v ih 0.7 ? v dd v dd [[ v v il 0 0.3 ? v dd [ v i ih 10 [ m a i il 10 [ m a digital output v oh i oh = C0.8ma 3.6 4.5 [[ [[ v v ol i ol = 1.6ma 0.3 0.4 [[ [ [ v power supply v dd +4.75 +5.0 +5.25 [[[[[ [ v v cc +14.25 +15.0 +15.75 [[[[[ [ v v ss C14.25 C15.0 C15.75 [[[[[ [ v i dd 50 [[ m a i cc 6 [[ ma i ss C5 [[ ma power 170 200 [[ mw temperature range specified performance C40 +85 [[[ [ c [ specifications same as grade to the left. specifications (dual supply) at t a = t min to t max , v cc = +15v, v dd = +5v, v ss = C15v, v ref h = +10v, and v ref l = C10v, unless otherwise noted.
3 dac7734 dac7734e dac7734eb dac7734ec parameter conditions min typ max min typ max min typ max units accuracy linearity error (1) (inl) t = 25 c 3 [ 2 lsb t min to t max 4 [ 3 lsb linearity match 4 [ 2 lsb differential linearity error (dnl) t = 25 c 3 2 1 lsb t min to t max 3 2 1 lsb monotonicity, t min to t max 14 15 16 bits unipolar zero t = 25 c 0.01 0.025 [[ % of fsr unipolar zero error, t min to t max 0.05 [[ % of fsr full-scale error t = 25 c 0.025 [[ % of fsr full-scale error, t min to t max 0.05 [[ % of fsr unipolar zero matching channel-to-channel 0.024 [[ % of fsr matching full-scale matching channel-to-channel 0.024 [[ % of fsr matching power supply rejection ratio (psrr) at full scale 25 [[ ppm/v analog output voltage output v ref l = 0v, v ss = 0v 0 v ref h [[[ [ v r = 10k w output current 5 [[ ma maximum load capacitance 500 [[ pf short-circuit current 20 [[ ma short-circuit duration to v cc or gnd indefinite [[ reference input ref high input voltage range v ref l + 1.25 +10 [[[ [ v ref low input voltage range 0 v ref h C 1.25 [[[ [ v ref high input current C0.3 1.0 [[ ma ref low input current C1.5 C0.3 [[ ma dynamic performance settling time to 0.003%, 10v 8 10 [[ [ [ m s output step channel-to-channel crosstalk see figure 6 0.5 [[ lsb digital feedthrough 2 [[ nv-s output noise voltage f = 10khz 60 [[ nv/ ? hz digital input v ih 0.7 ? v dd v dd [[ v v il 0 0.3 ? v dd [ v i ih 10 [ m a i il 10 [ m a digital output v oh i oh = C0.8ma 3.6 4.5 [[ [[ v v ol i ol = 1.6ma 0.3 0.4 [[ [ [ v power supply v dd +4.75 +5.0 +5.25 [[[[[ [ v v cc +14.25 +15.0 +15.75 [[[[[ [ v v ss 0 [[ v i dd 50 [[ m a i cc 3.5 [[ ma power 50 70 [[ mw temperature range specified performance C40 +85 [[[ [ c [ specifications same as grade to the left. note: (1) if v ss = 0v, the specification applies at code 0021 h and above, due to possible negative zero scale error. specifications (single supply) at t a = t min to t max , v cc = +15v, v dd = +5v, v ss = gnd, v ref h = +10v, and v ref l = +50mv, unless otherwise noted.
4 dac7734 absolute maximum ratings (1) v cc to v ss ........................................................................... C0.3v to +32v v cc to agnd ...................................................................... C0.3v to +16v v ss to agnd ...................................................................... +0.3v to C16v agnd to dgnd ................................................................. C0.3v to +0.3v v ref h to agnd ..................................................................... C9v to +11v v ref l to agnd ...................................................................... C11v to +9v v dd to gnd ........................................................................... C0.3v to +6v v ref h to v ref l ........................................................................ C1v to 22v digital input voltage to gnd ................................... C0.3v to v dd + 0.3v digital output voltage to gnd ................................. C0.3v to v dd + 0.3v maximum junction temperature ................................................... +150 c operating temperature range ........................................ C40 c to +85 c storage temperature range ......................................... C65 c to +150 c lead temperature (soldering, 10s) ............................................... +300 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package/ordering information linearity differential package specification error nonlinearity drawing temperature ordering transport product (lsb) (lsb) package number range number (1) media dac7734e 4 3 ssop-48 333 C40 c to +85 c dac7734e rails "" " "" " dac7734e/1k tape and reel dac7734eb 4 2 ssop-48 333 C40 c to +85 c dac7734eb rails "" " "" " dac7734eb/1k tape and reel dac7734ec 3 1 ssop-48 333 C40 c to +85 c dac7734ec rails "" " "" " dac7734ec/1k tape and reel note: (1) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /1k indicates 1000 dev ices per reel). ordering 1000 pieces of dac7734e/1k will get a single 1000-piece tape and reel. esd protection circuits refh v out sense v cc v ss v dd dgnd v cc agnd v ss v dd dgnd v out refh sense refl sense refl 1 of 2 1 of 4 typ of each logic input pin sdo
5 dac7734 top view ssop pin configuration nc nc sdi dgnd clk dgnd ldac dgnd load dgnd cs dgnd sdo dgnd rstsel dgnd rst dgnd nc nc dgnd dgnd v dd v dd v out a sense v out a agnd v ss v ref l ab sense v ref l ab v ref h ab v ref h ab sense v out b sense v out b v out c sense v out c v ref h cd sense v ref h cd v ref l cd v ref l cd sense v out d sense v out d v ss v ss agnd agnd v cc v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 dac7734 pin name description 1 nc no connection 2 nc no connection 3 sdi serial data input 4 dgnd digital ground 5 clk data clock input 6 dgnd digital ground 7 ldac dac register load control, rising edge triggered 8 dgnd digital ground 9 load dac input register load control, active low 10 dgnd digital ground 11 cs chip select, active low 12 dgnd digital ground 13 sdo serial data output 14 dgnd digital ground 15 rstsel reset select. determines the action of rst. if high, a rst common will set the dac registers to mid-scale (8000h). if low, a rst command will set the dac registers to zero (0000h). 16 dgnd digital ground 17 rst reset, rising edge triggered. depending on the state of rstsel, the dac registers are set to either mid-scale or zero. 18 dgnd digital ground 19 nc no connection 20 nc no connection 21 dgnd digital ground 22 dgnd digital ground 23 v dd digital +5v power supply 24 v dd digital +5v power supply 25 v cc analog +15v power supply 26 v cc analog +15v power supply 27 agnd analog ground 28 agnd analog ground 29 v ss analog C15v power supply or 0v single supply 30 v ss analog C15v power supply or 0v single supply 31 v out d dac d output voltage 32 v out d sense dac ds output amplifier inverting input. used to close feedback loop at load. 33 v ref l cd sense dac c and d reference low sense input 34 v ref l cd dac c and d reference low input 35 v ref h cd dac c and d reference high input 36 v ref h cd sense dac c and d reference high sense input 37 v out c dac c output voltage 38 v out c sense dac cs output amplifier inverting input. used to close the feedback loop at the load. 39 v out b dac b output voltage 40 v out b sense dac bs output amplifier inverting input. used to close the feedback loop at the load. 41 v ref h ab sense dac a and b reference high sense input 42 v ref h ab dac a and b reference high input 43 v out l ab dac a and b reference low input 44 v ref l ab sense dac a and b reference low sense input 45 v ss analog C15v power supply or 0v single supply 46 agnd analog ground 47 v out a dac a output voltage 48 v out a sense dac as output amplifier inverting input. used to close the feedback loop at the load. pin descriptions
6 dac7734 typical performance curves: v ss = 0v at t a = +25 c, v dd = +5v, v cc = +15v, v ss = 0, v ref h = +10v, and v ref l = 0v, representative unit, unless otherwise specified. +25 c +85 c 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, +25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, +85 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac d, +25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac b, +25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac b, +85 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac c, +25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h
7 dac7734 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, ?0 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac d, ?0 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac d, +85 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h typical performance curves: v ss = 0v (cont.) at t a = +25 c, v dd = +5v, v cc = +15v, v ss = 0, v ref h = +10v, and v ref l = 0v, representative unit, unless otherwise specified. +85 c (cont.) C40 c 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac b, ?0 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac c, +85 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac c, ?0 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h
8 dac7734 typical performance curves: v ss = 0v (cont.) at t a = +25 c, v dd = +5v, v cc = +15v, v ss = 0, v ref h = +10v, and v ref l = 0v, representative unit, unless otherwise specified. 1.0 0.8 0.6 0.4 0.2 0 ?.2 ?.4 v ref (current (ma) reference current vs code all dacs sent to indicated code (dac a and b) v refh v refl 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 0 ?.2 ?.4 ?.6 ?.8 ?.0 ?.2 ?.4 v ref (current (ma) 1.0 0.8 0.6 0.4 0.2 0 ?.2 ?.4 v ref (current (ma) reference current vs code all dacs sent to indicated code (dac c and d) v refh v refl 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 0 ?.2 ?.4 ?.6 ?.8 ?.0 ?.2 ?.4 v ref (current (ma) 2 1.5 1 0.5 0 ?.5 ? ?.5 ? temperature ( c) ?0 ?0 ?0 0 ?0 10 20 40 50 30 70 80 90 60 zero-scale error vs temperature negative full-scale error (mv) code (0040 h ) code (0000 h ) dac d dac a dac c dac b 2 1.5 1 0.5 0 ?.5 ? ?.5 ? temperature ( c) ?0 ?0 ?0 0 ?0 10 20 40 50 30 70 80 90 60 positive full-scale error vs temperature positive full-scale error (mv) dac a dac d dac b dac c code (ffff h ) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?.5 temperature ( c) ?0 ?0 ?0 0 ?0 10 20 40 50 30 70 80 90 60 power supply current vs temperature quiescent current (ma) i cc i dd data = ffff h (all dacs) no load 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?.5 digital input code 0 2000 h 4000 h 6000 h 8000 h a000 h c000 h e000 h ffff h positive supply current vs digital input code i cc (ma) no load i cc i dd
9 dac7734 typical performance curves: v ss = 0v (cont.) at t a = +25 c, v dd = +5v, v cc = +15v, v ss = 0, v ref h = +10v, and v ref l = 0v, representative unit, unless otherwise specified. +5v ldac 0 time (2 s/div) output voltage vs settling time (0v to +10v) output voltage +5v ldac 0 time (2 s/div) output voltage vs settling time (+10v to 0v) output voltage +5v ldac 0 time (1 s/div) output voltage midscale glitch performance output voltage (200mv/div) +5v ldac 0 time (1 s/div) output voltage (200mv/div) output voltage midscale glitch performance broadband noise time (100 m s/div) noise voltage (20 m v/div) bw = 10khz code = 8000 h 120 100 80 60 40 20 0 frequency (hz) 100 1k 10k 100k 1m output noise voltage vs frequency noise (nv/ ? hz) large-signal settling time: 5v/div small-signal settling time: 3lsb/div large-signal settling time: 5v/div small-signal settling time: 3lsb/div 7fff h to 8000 h 8000 h to 7fff h
10 dac7734 typical performance curves: v ss = 0v (cont.) at t a = +25 c, v dd = +5v, v cc = +15v, v ss = 0, v ref h = +10v, and v ref l = 0v, representative unit, unless otherwise specified. 16 14 12 10 8 6 4 2 0 r load (k w ) 0.01 0.1 1 10 100 output voltage vs r load v out (v) source sink 30 25 20 15 10 5 0 ? ?0 ?5 ?0 ?5 ?0 input code 0000 h 2000 h 4000 h 6000 h 8000 h a000 h c000 h e000 h ffff h single-supply current limit vs input code i out (ma) short to ground short to v cc 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 frequency (hz) 100 1k 10k 100k 1m power supply rejection ratio vs frequency psrr (db) +15v +5v +5v clk 0v time (50ns/div) clock feedthrough output voltage (5mv/div)
11 dac7734 typical performance curves: v ss = C15v at t a = +25 c, v dd = +5v, v cc = +15v, v ss = C15v, v ref h = +10v, and v ref l = C10v, representative unit, unless otherwise specified. +85 c +25 c 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, +25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, +85 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac b, +25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac b, +85 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac c, +25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) linearity error and differential linearity error vs code (dac d, +25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 dle (lsb)
12 dac7734 typical performance curves: v ss = C15v (cont.) at t a = +25 c, v dd = +5v, v cc = +15v, v ss = C15v, v ref h = +10v, and v ref l = C10v, representative unit, unless otherwise specified. +85 c (cont.) C40 c 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, ?0 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac b, ?0 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac c, ?0 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac c, +85 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) linearity error and differential linearity error vs code (dac d, +85 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 dle (lsb) 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) linearity error and differential linearity error vs code (dac d, ?0 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 dle (lsb)
13 dac7734 typical performance curves: v ss = C15v (cont.) at t a = +25 c, v dd = +5v, v cc = +15v, v ss = C15v, v ref h = +10v, and v ref l = C10v, representative unit, unless otherwise specified. 2.5 2.0 1.5 1.0 0.5 0 ?.5 v ref (current (ma) reference current vs code all dacs sent to indicated code (dac a and b) v refh v refl 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 0.0 ?.5 ?.0 ?.5 ?.0 ?.5 ?.0 v ref (current (ma) 2.5 2.0 1.5 1.0 0.5 0 ?.5 v ref (current (ma) reference current vs code all dacs sent to indicated code (dac c and d) v refh v refl 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 0.0 ?.5 ?.0 ?.5 ?.0 ?.5 ?.0 v ref (current (ma) 2 1.5 1 0.5 0 ?.5 ? ?.5 ? temperature ( c) 403020100 102030405060708090 bipolar zero scale error vs temperature (code 8000 h ) bipolar zero scale error (mv) dac a dac d dac c dac b 2 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 temperature ( c) ?0 ?0 0 ?0 ?0 90 10 20 30 40 50 60 70 80 positive full-scale error vs temperature (code ffff h ) positive full-scale error (mv) dac a dac b dac d dac c 2 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 temperature ( c) ?0 ?0 0 ?0 ?0 90 10 20 30 40 50 60 70 80 negative full-scale error vs temperature (code 0000 h ) negative full-scale error (mv) dac a dac d dac b dac c 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? temperature ( c) ?0 ?0 0 ?0 ?0 90 10 20 30 40 50 60 70 80 power supply current vs temperture quiescent current (ma) i ss i cc i dd data = ffff h (all dacs) no load
14 dac7734 time (2 s/div) output voltage vs settling time (?0v to +10v) output voltage +5v ldac 0 typical performance curves: v ss = C15v (cont.) at t a = +25 c, v dd = +5v, v cc = +15v, v ss = C15v, v ref h = +10v, and v ref l = C10v, representative unit, unless otherwise specified. 15 10 5 0 ? ?0 ?5 r load (k w ) 0.01 0.1 1 10 100 output voltage vs r load v out (v) sink source 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? supply current vs code (ma) digital input code 0000 h 2000 h 4000 h 6000 h 8000 h a000 h c000 h e000 h ffff h i cc i dd i ss time (2 s/div) output voltage vs settling time (+10v to ?0v) output voltage +5v ldac 0 20 15 10 5 0 ? ?0 ?5 ?0 digital input code 0000 h 2000 h 4000 h 6000 h 8000 h a000 h c000 h e000 h ffff h dual-supply current limit vs input code (short-to-ground) i out (ma) large-signal settling time: 5v/div small-signal settling time: 3lsb/div large-signal settling time: 5v/div small-signal settling time: 3lsb/div 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 frequency (hz) 100 1k 10k 100k 1m power supply rejection ratio vs frequency psrr (db) ?5v +15v +5v
15 dac7734 time (1 s/div) output voltage mid-scale glitch performance output voltage (200mv/div) +5v ldac 0 typical performance curves: v ss = C15v (cont.) at t a = +25 c, v dd = +5v, v cc = +15v, v ss = C15v, v ref h = +10v, and v ref l = C10v, representative unit, unless otherwise specified. time (1 s/div) output voltage mid-scale glitch performance output voltage (200mv/div) +5v ldac 0 7fff h to 8000 h 8000 h to 7fff h
16 dac7734 theory of operation the dac7734 is a quad voltage output, 16-bit digital-to- analog converter (dac). the architecture is an r-2r ladder configuration with the three msbs segmented, fol- lowed by an operational amplifier that serves as a buffer. each dac has its own r-2r ladder network, segmented msbs, and output op amp, as shown in figure 1. the minimum voltage output (zero-scale) and maximum voltage output (full-scale) are set by the external voltage references v ref l and v ref h. the digital input is a 24-bit serial word that contains a 2-bit address code for selecting one of four dacs, a quick load bit, five unused bits and the 16-bit dac code (msb first). the converters can be powered from either a single +15v supply or a dual 15v supply and a +5v logic supply. the device offers a reset function which immediately sets all dac output voltages and dac registers to mid-scale code 8000 h or to zero-scale, code 0000 h . see figures 2 and 3 for the basic operation of the dac7734. figure 1. dac7734 architecture. figure 2. basic single-supply operation of the dac7734. r 2r 2r 2r 2r 2r 2r 2r 2r 2r v ref h v out v out sense v ref h sense v ref l v ref l sense r f nc nc sdi dgnd clk dgnd ldac dgnd load dgnd cs dgnd sdo dgnd rstsel dgnd rst dgnd nc nc dgnd dgnd v dd v dd v out a sense v out a agnd v ss v ref l ab sense v ref l ab v ref h ab v ref h ab sense v out b sense v out b v out c sense v out c v ref h cd sense v ref h cd v ref l cd v ref l cd sense v out d sense v out d v ss v ss agnd agnd v cc v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 dac7734 reset dac registers chips select serial data out serial data in clock load dac registers load nc = no connection 0v to +10v 0v to +10v 0v to +10v 0v to +10v +10.000v +10.000v +15v 0.1 f 1 f + 0.1 f 1 f +5v +
17 dac7734 figure 3. basic dual-supply operation of the dac7734. analog outputs when v ss = C15v (dual supply operation), the output amplifier can swing to within 4v of the supply rails, guar- anteed over the C40 c to +85 c temperature range. when v ss = 0v (single-supply operation), and with r load also connected to ground, the output can swing to ground. care must also be taken when measuring the zero-scale error when v ss = 0v. since the output voltage cannot swing below ground, the output voltage may not change for the first few digital input codes (0000 h , 0001 h , 0002 h , etc.) if the output amplifier has a negative offset. at the negative limit of C5mv, the first specified output starts at code 0021 h . due to the high accuracy of these d/a converters, system design problems such as grounding and contact resistance become very important. a 16-bit converter with a 10v full- scale range has a 1lsb value of 152 m v. with a load current of 1ma, series wiring and connector resistance of only 150m w (r w2 ) will cause a voltage drop of 150 m v, as shown in figure 4. to understand what this means in terms of a system layout, the resistivity of a typical 1 ounce copper- clad printed circuit board is 1/2 m w per square. for a 1ma load, a 20 milli-inch wide printed circuit conductor 6 inches long will result in a voltage drop of 150 m v. the dac7734 offers a force and sense output configuration for the high open-loop gain output amplifier. this feature allows the loop around the output amplifier to be closed at the load (as shown in figure 4), thus ensuring an accurate output voltage. figure 4. analog output closed-loop configuration (1/2 dac7734). r w represents wiring resis- tances. nc nc sdi dgnd clk dgnd ldac dgnd load dgnd cs dgnd sdo dgnd rstsel dgnd rst dgnd nc nc dgnd dgnd v dd v dd v out a sense v out a agnd v ss v ref l ab sense v ref l ab v ref h ab v ref h ab sense v out b sense v out b v out c sense v out c v ref h cd sense v ref h cd v ref l cd v ref l cd sense v out d sense v out d v ss v ss agnd agnd v cc v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 dac7734 reset dac registers chips select serial data out serial data in clock load dac registers load nc = no connection ?0v to +10v ?0v to +10v ?0v to +10v ?0v to +10v +10.000v +10.000v ?0.000v ?0.000v +5v +15v 0.1 f 1 f 1 f + 0.1 f 0.1 f 1 f ?5v ?5v +5v + + v out a sense v out a agnd v ss v ref l ab sense v ref l ab v ref h ab v ref h ab sense v out b sense v out b 48 47 46 45 44 43 42 41 40 39 dac7734 r w1 r w2 +10v +v v out r w1 r w2 v out
18 dac7734 reference inputs the reference inputs, v ref l and v ref h, can be any voltage between v ss + 4v and v cc C 4v, provided that v ref h is at least 1.25v greater than v ref l. the minimum output of each dac is equal to v ref l plus a small offset voltage (essentially, the offset of the output op amp). the maximum output is equal to v ref h plus a similar offset voltage. note that v ss (the negative power supply) must either be connected to ground or must be in the range of C14.25v to C15.75v. the voltage on v ss sets several bias points within the converter. if v ss is not in one of these two configura- tions, the bias values may be in error and proper operation of the device is not guaranteed. the current into the v ref h input and out of v ref l depends on the dac output voltages, and can vary from a few microamps to approximately 2.0ma. the reference input appears as a varying load to the reference. the dac7734 features a reference drive and sense connection such that the internal errors caused by the changing reference current and the circuit impedances can be minimized. figures 5 through 9 show different reference configurations, and the effect on the linearity and differential linearity. the analog supplies have to come up first. if v cc and v ss don't come up together, then v ss should come up first. if the power supplies for the reference come up first, then the v cc and v ss supplies will be powered from the reference via the esd protection diode, see page 4. figure 5. dual supply configuration-buffered references, used for dual supply performance (1/2 dac7734). figure 6. single-supply buffered reference with a reference low of 50mv used for single-supply performance curves (1/2 dac7734). +10v +v ?0v ? v out ?5v v out v out a sense v out a agnd v ss v ref l ab sense v ref l ab v ref h ab v ref h ab sense v out b sense v out b 48 47 46 45 44 43 42 41 40 39 dac7734 2200pf 100 w 1000pf 1000pf 2200pf +v opa2234 ? 100 w v out v out a sense v out a agnd v ss v ref l ab sense v ref l ab v ref h ab v ref h ab sense v out b sense v out b 48 47 46 45 44 43 42 41 40 39 dac7734 +10v +v opa350 opa227 99.5k w +0.050v 500 w 50 w v out note: v ref l has been chosen to be 50mv to allow for current sinking voltage drops across the 100 w resistor and the output stage of the buffer op amp. 2200pf 100 w 1000pf 1000pf 2200pf +v 100 w
19 dac7734 figure 8. dual-supply buffered reference with v ref l = C5v and v ref h = +5v (1/2 dac7734). +5v +v ?v ? v out v out a sense v out a agnd v ss v ref l ab sense v ref l ab v ref h ab v ref h ab sense v out b sense v out b 48 47 46 45 44 43 42 41 40 39 dac7734 opa2234 v out 2200pf 100 w 1000pf 1000pf 2200pf +v ? 100 w figure 7. integral linearity and differential linearity error curves for figure 8. 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) linearity error and differential linearity error vs code (dac a, 25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 dle (lsb) 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) linearity error and differential linearity error vs code (dac b, 25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 dle (lsb) 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) linearity error and differential linearity error vs code (dac c, 25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 dle (lsb) 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) linearity error and differential linearity error vs code (dac d, 25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 dle (lsb)
20 dac7734 figure 9. single-supply buffered reference with a reference low of 50mv and reference high of +5v. v out a sense v out a agnd v ss v ref l ab sense v ref l ab v ref h ab v ref h ab sense v out b sense v out b 48 47 46 45 44 43 42 41 40 39 dac7734 v out v out 99k w 0.05v 1k w +5v +v 1000pf 2200pf +v opa350 opa227 100 w 1000pf 2200pf 100 w note: v ref l has been chosen to be 50mv to allow for current sinking voltage drops across the 100 w resistor and the output stage of the buffer op amp. 50 w figure 10. integral linearity and differential linearity error curves for figure 9. 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) linearity error and differential linearity error vs code (dac a, 25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 dle (lsb) 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) linearity error and differential linearity error vs code (dac b, 25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 dle (lsb) 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) linearity error and differential linearity error vs code (dac c, 25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 dle (lsb) 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 le (lsb) linearity error and differential linearity error vs code (dac d, 25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 dle (lsb)
21 dac7734 input dac a1 a0 cs rst rstsel ldac load register register mode dac l l l h x x l write hold write input a l h l h x x l write hold write input b h l l h x x l write hold write input c h h l h x x l write hold write input d xxhhx - h hold write update all x x h h x h h hold hold hold all xxx - l x x reset to zero reset to zero reset to zero all xxx - h x x reset to midscale reset to midscale reset to midscale all table i. dac7734 logic truth table. digital interface table i shows the basic control logic for the dac7734. the interface consists of a signal data clock (clk) input, serial data (sdi), dac input register load control signal (load), and dac register load control signal (ldac). in addition, a chip select (cs) input is available to enable serial communication when there are multiple serial devices. an asynchronous reset (rst) input, by the rising edge, is provided to simplify start-up conditions, periodic resets, or emergency resets to a known state, depending on the status of the reset select (rstsel) signal. the dac code, quick load control, and address are provided via a 24-bit serial interface (see table i). the first two bits shifted into the shift register, b23 and b22, are the dac register address. these bits select the input register that will be updated when load goes low. the third bit, b21, is a quick load bit such that if high, the code in the shift register is loaded into all dac input registers when the load signal goes low, independent of the state of the address bits, b23 and b22. if the quick load bit is low, the contents of the shift register is loaded only to the dac register that is addressed. bits b20 through b16 are not used and can assume any logical value. the last sixteen bits, b15 through b0, make up the dac code to be loaded into the selected input register. the internal dac register is edge triggered and not level triggered. when the ldac signal is transitioned from low to high, the digital word currently in the dac input register is latched. the first set of registers (the dac input registers) are level triggered via the load signal. this double-buffered architecture has been designed so that new data can be entered for each dac without disturbing the analog outputs. when the new data has been entered into the b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 a1 a0 x x x x x d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 quick load serial data input device, all of the dac outputs can be updated simulta- neously by the rising edge of ldac. additionally, it allows the dac input registers to be written to at any point, then the dac output voltages can be synchronously changed via a trigger signal (ldac). note that cs and clk are combined with an or gate, which controls the serial-to-parallel shift register. these two inputs are completely interchangeable. in addition, care must be taken with the state of clk when cs rises at the end of a serial transfer. if clk is low when cs rises, the or gate will provide a rising edge to the shift register, shifting the internal data one additional bit. the result will be incorrect data and possible selection of the wrong input register(s). if both cs and clk are used, cs should rise only when clk is high. if not, then either cs or clk can be used to operate the shift register. see table ii for more information. cs (1) clk (1) load rst serial shift register h (2) x (3) h h no change l (4) l h h no change l - (5) h h advanced one bit - l h h advanced one bit h (6) xl (7) h no change h (6) xh - (8) no change notes: (1) cs and clk are interchangeable. (2) h = logic high. (3) x = dont care. (4) l = logic low (5) = positive logic transition. (6) a high value is suggested in order to avoid a false clock from advancing the shift register and changing the shift register. (7) if data is clocked into the serial register while load is low, the selected dac register will change as the shift register bits flow through a1 and a0. this will corrupt the data in each dac register that has been erroneously selected. (8) rising edge of rst causes no change in the contents of the serial shift register. table ii. serial shift register truth table.
22 dac7734 (1) vvl vhvln out ref ref ref =+ () , 65 536 figure 11. daisy-chaining dac7734. serial-data output the serial-data output (sdo) is the internal shift register's output. for dac7734, the sdo is a driven output and does not require an external pull-up. any number of dac7734's can be daisy chained by connecting the sdo pin of one device to the sdi pin of the following device in the chain, as shown in figure 11. digital timing figure 12 and table iii provide detailed timing for the digital interface of the dac7734. digital input coding the dac7734 input data is in straight binary format. the output voltage is given by equation 1. where n is the digital input code. this equation does not (2) i vhvl r vlr out ref ref sense ref sense = ? ? ? ? ? ? ? ? ? ? ? ? + () , / n 65 536 digitally-programmable current source the dac7734 offers a unique set of features that allows a wide range of flexibility in designing applications circuits such as programmable current sources. the dac7734 offers both a differential reference input, as well as an open-loop configuration around the output amplifier. the open-loop configuration around the output amplifier allows a transistor to be placed within the loop to implement a digitally- programmable, unidirectional current source. the availabil- ity of a differential reference allows programmability for both the full-scale and zero-scale currents. the output cur- rent is calculated as: include the effects of offset (zero-scale) or gain (full-scale) errors. dac7734 clk sdi cs sck din cs ldac sdo dac7734 clk sdi cs sdo load dac7734 load load load clk sdi cs ldac ldac ldac sdo to other serial devices
23 dac7734 symbol description min max units t ds data valid to clk rising 10 ns t dh data held valid after clk rises 20 ns t ch clk high 25 ns t cl clk low 25 ns t css cs low to clk rising 15 ns t csh clk high to cs rising 0 ns t ld1 load high to clk rising 10 ns t ld2 clk rising to load low 30 ns t ldrw load low time 30 ns t lddwl ldac low time 40 ns t lddh ldac high time 40 ns t sdo sdo propagation delay 10 45 ns t rsss resetsel valid to reset high 0 ns t rssh reset high to resetsel not valid 100 ns t rstl reset low time 10 ns t rsth reset high time 10 ns t lddd load low to ldac rising time 40 ns t s settling time 10 (dual)/11(single) m s table iii. timing specifications (t a = C40 c to +85 c). figure 12. digital input and output timing. a1 (lsb) sdi clk cs load a0 d3 d2 d1 d0 sdi clk ldac reset v out t css t ld1 t cl t sdo t ch t ds t dh t ld2 t ldrw t s t rsth t rstl t rsss t rssh sdo t csh t s 0.003% error band 0.003% error band resetsel d15 d14 d13 xxxxx quick load (msb) t lddd ldac t lddh t lddl
24 dac7734 (3) figure 13. 4-to-20ma digitally controlled current source (1/2 dac7734). i out v programmed r sense 250 w i out v programmed r sense 250 w v out a sense v out a agnd v ss v ref l ab sense v ref l ab v ref h ab v ref h ab sense v out b sense v out b 48 47 46 45 44 43 42 41 40 39 dac7734 5v opa2350 80k w 20k w 1.0v 2200pf 100 w 1000pf 1000pf 2200pf +v +v 100 w i vv n v out = ? ? ? ? ? ? ? ? ? ? ? + ? ? ? 51 250 65 536 1 250 , ww figure 13 shows a dac7734 in a 4ma to 20ma current output configuration. the output current can be determined by equation 3: at full-scale, the output current is 16ma, plus the 4ma, for the zero current. at zero scale the output current is the offset current of 4ma (1v/250 w ).
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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