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| publication # 24267 rev: a amendment/ 0 issue date: december 2000 amd powernow!? technology platform design guide for embedded processors application note
? 2000 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. (amd) products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd's standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd's product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice. trademarks amd, the amd logo, and combinations thereof, amd-k6, 3dnow!, and amd powernow! are trademarks, and fusione86 is a service mark of advanced micro devices, inc. microsoft, windows, and windows nt are registered trademarks of microsoft corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. contents iii 24267A/0december 2000 preliminary information contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi amd powernow!? technology initiative . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 overview of this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 enhanced power management features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 enhanced power management register (epmr) . . . . . . . . . . . . . . . . 3 epm 16-byte i/o block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 dynamic core frequency and core voltage control . . . . . . . . . . . . . . . . . . . 7 effective bus divisors ebf[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 bf[2:0] strapping considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 dynamic core frequency control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 voltage identification (vid) outputs . . . . . . . . . . . . . . . . . . . . . . . . . 12 guaranteed cpu core voltage at power on . . . . . . . . . . . . . . . . . . . 14 dynamic core voltage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 amd powernow! technology initialization . . . . . . . . . . . . . . . . . . . . 16 hardware implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 safe voltage and frequency combination at reset . . . . . . . . . . . . . 20 voltage versus frequency options. . . . . . . . . . . . . . . . . . . . . . . . . . . 22 vid[4:0] modification for maximum bf[2:0] boot option . . . . . . . . 24 gating pgood during a voltage transition . . . . . . . . . . . . . . . . . . . 26 software implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 using an rtos enabled for amd powernow!? technology . . . . . 28 using an smm handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 using a microsoft ? windows ? driver supporting amd powernow! technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 using a bios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 amd powernow!? technology descriptor table. . . . . . . . . . . . . . . 30 event sequence for amd powernow!? technology state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 pinout information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 documentation and technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 appendix afrequently asked questions . . . . . . . . . . . . . . . . . . . . . . . . . . 39 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 iv list of figures 24267A/0december 2000 list of figures figure 1. enhanced power management register (epmr) . . . . . . . . . . . . 4 figure 2. epm 16-byte i/o block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. bus divisor and voltage id control (bvc) field . . . . . . . . . . . 11 figure 4. example hardware implementation . . . . . . . . . . . . . . . . . . . . . 19 figure 5. vid[4:0] modification for maximum frequency initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 6. gating the pgood signal with maximum frequency initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 list of tables v 24267A/0december 2000 preliminary information list of tables table 1. basic set of amd powernow!? technology operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 2. enhanced power management register (epmr) definition . . 4 table 3. epm 16-byte i/o block definition . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4. processor-to-bus clock ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. bus divisor and voltage id control (bvc) definition . . . . . . . 11 table 6. vid [4:0] input-to-output voltage codes (typical for dc/dc regulators). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. regulator solution using a subset of cpu vid outputs . . . . 13 table 8. alternative components for amd powernow!? technology hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. supported voltages and operating frequencies for low-power amd-k6?-2e+ processors enabled with amd powernow!? technology . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. supported voltages and operating frequencies for low-power amd-k6?-iiie+ processors enabled with amd powernow!? technology . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. amd powernow!? technology descriptor table . . . . . . . . . . 31 table 12. pins added for amd powernow!? technology . . . . . . . . . . . . 33 table 13. cpga pin designations by functional grouping . . . . . . . . . . . 34 table 14. cpga pin designations for no connect, reserved, power, and ground pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 15. obga pin designations by functional grouping . . . . . . . . . . . 36 table 16. obga pin designations for no connect, reserved, power, and ground pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 vi revision history 24267A/0december 2000 preliminary information revision history date rev description december 2000 a initial public release. amd powernow!? technology initiative 1 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information application note amd powernow!? technology platform design guide for embedded processors amd powernow!? technology initiative amds latest power-saving initiative, amd powernow!? technology, enables embedded system designers to offer superior performance. amd powernow! technology uses combinations of cpu core voltage and frequency (amd powernow! technology states) to enable maximum performance in any thermal environment, while providing the embedded system designer with the ability to finely tune performance dependent upon the specific demands of the application. table 1 on page 2 shows the basic set of amd powernow! technology operational modes or states. however, amd powernow! technology is not restricted to the operation modes listed. additionally, amd powernow! technology can be used in conjunction with existing power management schemes, such as advanced configuration and power interface (acpi). this allows amd powernow! technology to optimize the performance and power savings of a device. 2 amd powernow!? technology initiative amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information overview of this document this document identifies and describes the key components of amd powernow! technology as they apply to embedded system designers desiring to incorporate amd powernow! technology features. unless otherwise noted, the terms cpu or processor refer to the amd-k6?-2e+ and/or the amd-k6?-iiie+ processor built in 0.18-micron process technology. specifically, this document addresses the following: n identification of the enhanced power management (epm) features designed in the 0.18-micron amd-k6-2e+ and the amd-k6-iiie+ processors for supporting amd powernow! technology. n description of how the epm features can be incorporated to create embedded platforms enabled with amd powernow! technology. n description of design considerations including new processor pinouts, voltage regulator recommendations, and other implementation options specific to designing with amd powernow! technology. note: the information presented in this document is preliminary and subject to change. table 1. basic set of amd powernow!? technology operational modes operational mode description application power high-performance operation at peak frequency and voltage, maximizing performance within thermal constraints < 12 w automatic core voltage and frequency are scaled to exactly meet application demand and conserve power usage 3 C11 w power-saver operation at lowest supported frequency and voltage to maximize power efficiency < 3 w enhanced power management features 3 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information enhanced power management features amd-k6-2e+ and amd-k6-iiie+ low-power processors enabled with amd powernow! technology include two new features specifically designed to enhance power management functionality: n dynamic core frequency control n core voltage control these enhanced power management (epm) features are accessed and controlled through an aligned 16-byte block of i/o address space that is defined by a model-specific register (msr) called the enhanced power management register (epmr). enhanced power management register (epmr) the epmr register allows software to access the aligned epm 16-byte block of i/o address space, which contains bits for enabling, controlling, and monitoring the epm features. all accesses to the epm 16-byte i/o block must be aligned dword accesses. valid accesses to the epm 16-byte block do not generate i/o cycles on the host bus, keeping epmr accesses local to the cpu, while non-aligned and non-dword accesses are passed to the host bus. figure 1 on page 4 and table 2 define the epmr register. the epmr can be addressed at msr location c000_0086h. an assertion of reset clears all of the bits of the 16-byte i/o block to 0 (excluding the voltage id output bits which default to 01010b). bios or the real-time operating system (rtos) must always initialize the epmr register and epm features after the processor comes out of reset. 4 enhanced power management features amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information figure 1. enhanced power management register (epmr) table 2. enhanced power management register (epmr) definition bit description r/w function 1 notes: 1. all bits default to 0 when reset is asserted. 63C16 reserved r all reserved bits are always read as 0. 15-4 i/o base address (iobase) r/w iobase defines a base address for a 16-byte block of i/o address space accessible for enabling, controlling, and monitoring the epm features. 3-2 reserved r all reserved bits are always read as 0. 1 generate special bus cycle (gsbc) r/w this bit controls whether a special bus cycle is generated upon dword accesses within the epm 16-byte i/o block. if set to 1, an epm special bus cycle is generated, where be[7:0]# = bfh and a[4:3] = 00b. 0 enable amd powernow! technology management (en) r/w this bit controls access to the i/o-mapped address space for the amd powernow! technology epm features. clearing this bit to zero does not affect the state of bits defined in the epm 16-byte i/o block. reserved 0 16 63 15 4 31 2 e n g s b c iobase symbol description b it iobase i/o base address 5-4 gsbc generate special bus cycle 1 en enable amd powernow! technology management 0 enhanced power management features 5 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information iobase field the epm 16-byte i/o block is located at the i/o address specified by the iobase field and is initialized during power- on self test (post) by the bios or rtos. the epm 16-byte i/o block is then used to access the epm features. the epm features are hidden from all application software and need only be accessible by an rtos or an smm handler for microsoft ? operating systems. therefore, the bios does not need to report the i/o range to the operating system. gsbc bit if the gsbc bit is enabled (set to 1), a special bus cycle is generated once a dword access is made within the epm 16-byte i/o block. the epm special bus cycle is defined by the processor driving d/c# low, m/io# low, w/r# high, be[7:0]# to bfh and a[31:3] to 0000h. the system logic must return brdy# in response to all processor special cycles. en bit the enable amd powernow! technology management (en) bit should only be enabled (set to 1) by the rtos, bios, or smm handler when attempting to access the epm features. upon exiting, the en bit should be disabled to protect the epm 16-byte i/o block from spurious activity. when the en bit is disabled, accesses to the epm block 16-byte i/o block are passed to the host bus. 6 enhanced power management features amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information epm 16-byte i/o block the epm 16-byte i/o block contains a single 4-byte field for enabling, controlling, and monitoring the epm features. this bus divisor and voltage id control (bvc) field (see figure 2, dynamic core frequency control on page 10, and figure 3 on page 11) is the control center for supported state transitions. table 3 defines the functions supported by each of the byte- fields within the epm 16-byte i/o block. figure 2. epm 16-byte i/o block table 3. epm 16-byte i/o block definition byte description r/w function 1 notes: 1. all bits default to 0 when reset is asserted 15-12 reserved r all reserved bits are always read as 0. 11-8 bus divisor and voltage id control (bvc) r/w the bit fields within the bvc bytes allow software to change the processor bus divisor and core voltage. see dynamic core fre- quency control on page 10 and figure 3 on page 11 for detailed information about this field. 7-0 reserved r all reserved bits are always read as 0. reserved 0 12 15 11 87 bvc symbol description bytes bvc bus divisor and voltage id control 11-8 dynamic core frequency and core voltage control 7 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information dynamic core frequency and core voltage control amd-k6-2e+ and amd-k6-iiie+ processors enabled with amd powernow! technology support the ability to change the bus frequency divisor and core voltage seamlessly during run time. these features are implemented in conjunction with a new clock control statethe epm stop grant state. to invoke an amd powernow! technology state transition, the desired settings for core voltage and processor frequency are written to the voltage id output (vido) and internal bf divisor (ibf) fields of the bvc field. the epm stop grant state and state transition then occur automatically by writing a 1 to the generate special bus cycle (gsbc) bit in the epmr and a non-zero value to the stop grant time-out counter (sgtc) field. for microsoft operating systems, the epmr register should be accessed using an smm handler. in these environments, the smm handler can initiate a special bus cycle for core voltage and frequency transitions by writing a 1 to the gsbc field in the epmr and a non-zero value to the sgtc. n this action enables the processor to enter the epm stop grant state and transitions the cpu core voltage and frequency to the values specified in the vido and iibf fields of the bvc field. n once the sgtc period has expired, the epm stop grant state is exited and the amd powernow! technology state transition is completed. 8 dynamic core frequency and core voltage control amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information effective bus divisors ebf[2:0] the processor core frequency is controlled by the effective bus frequency divisorebf[2:0]which dictates the processor-to- bus clock ratio supplied to the processors internal pll. this processor-to-bus clock ratio is multiplied by the external bus frequency to set the frequency of operation for the processor core. n at the fall of reset, the ebf[2:0] value is determined by the state of the processor bf[2:0] input pins. n afterwards, the ebf[2:0] value can be dynamically controlled through amd powernow! technology state transitions. table 4 lists valid ebf[2:0] states and equivalent processor- to- bus clock ratios. table 4. processor-to-bus clock ratios state of ebf[2:0] processor-to-bus clock ratio 100b 2.0x 1 notes: 1. the 0.18-micron processors do not support the 2.5x ratio supported by earlier processors. instead, a ratio of 2.0x is selected when ebf[2:0] equals 100b 101b 3.0x 110b 6.0x 111b 3.5x 000b 4.5x 001b 5.0x 010b 4.0x 011b 5.5x dynamic core frequency and core voltage control 9 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information bf[2:0] strapping considerations systems that do not use the amd powernow! technology dynamic core frequency control mechanism should strap the bf[2:0] inputs of the cpu (with pull-up/pull-down resistors) to select the desired cpu operating frequency at power up. systems that use amd powernow! technology dynamic core frequency control mechanisms have two primary strapping options for the bf[2:0] inputs: n strap the bf[2:0] inputs to select the maximum cpu core frequency at power up (recommended) n strap the bf[2:0] inputs to select the minimum cpu core frequency at power up selecting maximum cpu core frequency systems can strap the bf[2:0] inputs to allow the processor to boot at its maximum rated frequency when reset is asserted. bios can then determine the maximum frequency of the processor by reading the psor model-specific register, which stores the state of the ebf[2:0] bits. for more information on the psor register, see the embedded amd-k6? processors bios design guide application note , order# 23913. see safe voltage and frequency combination at reset on page 20 for the advantages and disadvantages of booting at maximum core frequency. selecting minimum cpu core frequency systems that strap the processor bf[2:0] inputs to 100b allow the processor to boot with a core frequency of 2.0x the processor bus frequency when reset is asserted. if a different cpu core frequency is desired prior to loading the os, it is the responsibility of the bios, early in the post routine, to transition the processor core frequency and voltage to the desired performance level. see safe voltage and frequency combination at reset on page 20 for the advantages and disadvantages of booting at a minimum core frequency. 10 dynamic core frequency and core voltage control amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information dynamic core frequency control for microsoft operating systems, the bvc field of the epm 16- byte i/o block is accessed through an smm handler. n to invoke a new processor core frequency, the smm handler initiates core voltage and frequency transitions by writing a 1 to the gsbc field in the epmr and a non-zero value to the sgtc. n this action initiates a special bus cycle to place the processor into the epm stop grant state and transitions the cpu core voltage and frequency to the values specified in the vido and ibf fields of the bvc field. note: system-initiated inquire (snoop) cycles are not supported and must be prevented by the bios or operating system while in the epm stop grant state. bvc field figure 3 on page 11 shows the format and table 5 defines the function of each bit of the bvc field located within the epm 16- byte i/o block. dynamic core frequency and core voltage control 11 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information figure 3. bus divisor and voltage id control (bvc) field table 5. bus divisor and voltage id control (bvc) definition bit description r/w function 1 notes: 1. all bits default to 0 when reset is asserted, except the vido bits which default to 01010b 31-12 stop grant time-out counter (sgtc) w writing a non-zero value to this field causes the processor to enter the epm stop grant state internally. this 20-bit value is multiplied by 4096 to determine the duration of the epm stop grant state, measured in processor bus clocks. 11 bus divisor and vid change mode (bvcm) r/w this bit controls the mode in which the bus-divisor and the voltage control bits are allowed to change. if bvcm=0, the bus divisor and voltage id changes take effect only upon entering the epm stop grant state as a result of the sgtc field being programmed. bvcm=1 is reserved. 10 voltage id control (vidc) r/w this bit controls the mode of voltage id control. if vidc=0, the pro- cessor vid[4:0] pins are unchanged upon entering the epm stop grant state. if vidc=1, the processor vid[4:0] pins are pro- grammed to the vido value upon entering the epm stop grant state. bios should initialize this bit to 1 during the post routine. 9-8 bus divisor control (bdc) r/w this 2-bit field controls the mode of bus divisor control. if bdc[1:0]=00b, the bf[2:0] pins are sampled at the falling edge of reset. if bdc[1:0]=1xb, the ibf[2:0] field is sampled upon entering the epm stop grant state. bdc[1:0]=01b is reserved. bios should initialize these bits to 10b during the post routine. 7-5 internal bf divisor (ibf) r/w if bdc[1:0]=1xb, the processor ebf[2:0] field of the psor is pro- grammed to the ibf[2:0] value upon entering the epm stop grant state. 4-0 voltage id output (vido) r/w this 5-bit value is driven out on the processor vid[4:0] pins upon entering the epm stop grant state if the vidc bit=1. these bits are initialized to 01010b and driven on the processor vid[4:0] pins at reset. reserved 0 12 31 9 8 75 symbol description bits sgtc stop grant time-out counter 31-12 bvcm bus divisor and vid change mode 11 vidc voltage id control 10 bdc bus divisor control 9-8 ibf[2:0] internal bf divisor 7-5 vido voltage id output 4-0 v i d c ibf[2:0] 11 10 b v c m bdc vido 4 sgtc 12 dynamic core frequency and core voltage control amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information voltage identification (vid) outputs amd-k6-2e+ and amd-k6-iiie+ low-power processors enabled with amd powernow! technology feature voltage id (vid) outputs to support dynamic control of the core voltage. these outputs should serve as inputs to a dc/dc regulator that supplies the processor core voltage. based on its vid[4:0] inputs, the regulator outputs a corresponding voltage. (see hardware implementation on page 18 for more detailed information on using the vid outputs in embedded systems.) for regulators that do not support vid inputs, the processors vid[4:0] outputs must be used to manipulate the regulators feedback voltage to vary the regulator output voltage. it is not necessary to drive all of the processor vid[4:0] outputs to the voltage select inputs of the dc/dc regulator. any voltage select inputs of the dc/dc regulator that are not driven by the processor vid[4:0] outputs should be tied to ground. all vid[4:0] output pins used system implementations that incorporate all processor vid outputs typically support a voltage range of 0.925 v to 2.0 v. table 6 on page 13 lists vid[4:0] codes that are typical for dc/dc regulators. subset of vid[4:0] outputs used system implementations that use a subset of the processor vid outputs will require external logic to translate the processor vid pins into a full five-bit dc/dc regulator input code. one solution that is recommended for a maximum bf[2:0] boot strap option (see page 9) requires that regulator d[4] and d[0] inputs be connected to gnd while inputs d[3:1] are connected to the processor vid[4], vid[2], and vid[0] outputs, respectively, through external logic. for a 2.1-v core voltage implementation, the available core voltage is thereby limited to a range of 1.36 v to 2.1 v in approximately 100-mv increments, but the rework and external logic cost is minimal. table 7 on page 13 shows the voltage translation using the max1711 dc/dc regulator. unused vid[4:0] outputs system designs that do not use the dynamic core voltage control feature provided in amd powernow! technology should simply leave the processor vid[4:0] outputs as no-connects (nc) on the motherboard. dynamic core frequency and core voltage control 13 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information . table 6. vid [4:0] input-to-output voltage codes (typical for dc/dc regulators) vid inputs output voltage vid inputs output voltage d[4] d[3] d[2] d[1] d[0] d[4] d[3] d[2] d[1] d[0] 0 0 0 0 0 2.00 v 10000 1.275 v 0 0 0 0 1 1.95 v 10001 1.250 v 0 0 0 1 0 1.90 v 10010 1.225 v 0 0 0 1 1 1.85 v 10011 1.200 v 0 0 1 0 0 1.80 v 10100 1.175 v 0 0 1 0 1 1.75 v 10101 1.150 v 0 0 1 1 0 1.70 v 10110 1.125 v 0 0 1 1 1 1.65 v 10111 1.100 v 0 1 0 0 0 1.60 v 11000 1.075 v 0 1 0 0 1 1.55 v 11001 1.050 v 0 1 0 1 0 1.50 v 11010 1.025 v 0 1 0 1 1 1.45 v 11011 1.000 v 0 1 1 0 0 1.40 v 11100 0.975 v 0 1 1 0 1 1.35 v 11101 0.950 v 0 1 1 1 0 1.30 v 11110 0.925 v 0111 1 shutdown 1 notes: 1. if the voltage regulator is to be powered when the processor is to be powered off (for example, during suspend to ram), it is necessary to assert the regulators shutdown pin to power off the processor. 11111 shutdown 1 table 7. regulator solution using a subset of cpu vid outputs max1711 regulator d[4:0] inputs connection to cpu vid outputs cpu vid[4:0] outputs 1 notes: 1. cpu vid[3] and vid[1] are each treated as an nc (no-connect) and represented by x. regulator d[4:0] inputs 2 2. regulator d[4] and d[0] are tied to gnd. voltage selected 3 3. assumes a resistor divide circuit is used with the regulator to support a 2.1-v core voltage. d[4] gnd 0 x0 x0 0000 0 2.00 v d[3] cpu vid[4] 4 4. cpu vid[4], vid[2], and vid[0] are connected to the regulator through external logic. 0 x0 x1 0001 0 1.90 v d[2] cpu vid[2] 4 0 x1 x0 0010 0 1.80 v d[1] cpu vid[0] 4 0 x1 x1 0011 0 1.70 v d[0] gnd 1 x0 x0 0100 0 1.60 v 1 x0 x1 0101 0 1.50 v 1 x1 x0 0110 0 1.40 v 1 x1 x1 0111 0 1.30 v 14 dynamic core frequency and core voltage control amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information guaranteed cpu core voltage at power on the processor vid[4:0] outputs are initialized to a default state of 01010b, but they are only initialized after reset is asserted, the cpu input clock is running, and an i/o voltage is applied. as a result, it is necessary to drive the input select pins of the dc/dc regulator from a source other than the cpu during system power up. this can be accomplished by placing external logic between the vid[4:0] outputs of the processor and the voltage select inputs of the dc/dc regulator. the system power good (spwrgd) signal can then be used as an input to the external logic to strap the dc/dc regulators voltage select inputs to the desired state until the processors vid[4:0] outputs have been initialized. n when spwrgd is negated, the external logic drives the selected strap value to the regulators d[4:0] inputs. n when spwrgd is asserted, the external logic allows the cpu vid[4:0] outputs to drive the regulators d[4:0] inputs. note: the spwrgd signal must only assert after all power good signals (i/o, core, +5-v, etc.) are asserted. for a minimum bf[2:0] boot strap option (see page 9), a multiplexer and the spwrgd signal can be used for this purpose. for a maximum bf[2:0] boot strap option (see page 9), a multiplexer function is incorporated through the recommended and-gate solution discussed in "subset of vid[4:0] outputs used" on page 12. in both cases, the spwrgd signal, when equal to 0, forces the vid[4:0] outputs of the external logic to a value equivalent to the output state that the processor drives on its vid[4:0] pins when spwrgd transitions to a 1. once reset is negated, bios is free to transition the processor core frequency and voltage as needed. figure 5 on page 25 helps to illustrate the concept of implementing a guaranteed cpu core voltage at power on. dynamic core frequency and core voltage control 15 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information dynamic core voltage control for microsoft operating systems, the bvc field of the epm 16- byte i/o block is accessed through an smm handler. to invoke a new processor core voltage, the smm handler initiates core voltage and frequency transitions by writing a 1 to the gsbc field in the epmr and a non-zero value to the sgtc. this action automatically places the processor into the epm stop grant state and transitions the cpu core voltage to the value specified in the vido field of the bvc field. note: system-initiated inquire (snoop) cycles are not supported and must be prevented by the bios or operating system while in the epm stop grant state. this is typically accomplished through the use of the acpi-defined arb_dis control bit, which turns off the pci bus arbiter in the north bridge. the vid[4:0] outputs are determined by the value stored in the vido field within the bvc field of the 16-byte i/o block during amd powernow! technology state transitions. for more information on the format and definition of the bvc field, see bvc field on page 10. 16 dynamic core frequency and core voltage control amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information amd powernow! technology initialization initialization of the amd-k6-2e+ and amd-k6-iiie+ low-power processors is straightforward. below is a complete summary illustrating the actions required to properly initialize these processors for implementation of amd powernow! technology. software initialization detailed information for effective software control of devices enabled with amd powernow! technology is provided in the software implementation section, beginning on page 28. to initialize the software: n write the i/o base address (iobase) field (epmr[15:4]) for the 16-byte epm i/o block. this sets up the location in the i/o map where the epm i/o block will reside. be sure to locate the epm i/o block so that it does not conflict with other system i/o-mapped resources. the epmr is accessed at msr location c000_0086h. n clear the enable amd powernow! technology management (en) bit (epmr[0]) to disable address decodes of the epm i/o block fields. clearing epmr[0] ensures that errant writes to i/o space do not accidentally change the amd powernow! technology state. for windows desktop- based operating systems, the smi handler will set epmr[0]=1b only when smm is entered for the purpose of doing an amd powernow! technology state transition. real- time operating systems should set epmr[0]=1b only when attempting an amd powernow! technology state transition. this bit may be cleared in the same msr write that initializes the epm i/o block base. note: epmr[0] should be cleared upon completing any amd powernow! technology state transition to ensure errant writes to i/o space do not inadvertently alter the amd powernow! technology state of the processor. n the vidc bit (bvc[10]) should be set to 1 at power-on self test (post). all subsequent writes to this field should ensure that this bit equals 1b at all times. initializing this bit causes a read/modify-bit/write operation on the bvc field. after reading the bvc field and setting the vidc bit during initialization, be sure to clear all bits in the sgtc field before writing the bvc field back out. this is required because the data returned in the sgtc field is invalid, as it is a write-only field. dynamic core frequency and core voltage control 17 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information note: both the vidc and bdc bits may be initialized at the same time. n the bdc field (bvc [9:8]) should be set to 10b at post. all subsequent writes to this field should ensure that these bits remain 10b at all times. after reading the bvc field and setting the bdc bits during initialization, be sure to clear all bits in the sgtc field before writing the bvc field back out. this is required because the data returned in the sgtc field is invalid, as it is a write-only field. note: both the vidc and bdc bits may be initialized at the same time. n make the amd powernow!? technology descriptor table (see page 30) visible in the system memory map on a 16-byte boundary within the range of 0x0c0000C0x0fffff or within the first kbyte of the extended bios data area. hardware initialization information on implementing an efficient amd powernow! technology device is provided in the hardware implementation section, beginning on page 18. to initialize the hardware: n strap the system for one of the recommended power-up configurations: maximum cpu frequency or minimum cpu frequency setting. see safe voltage and frequency combination at reset on page 20 for details. n at reset, both the amd-k6-2e+ and amd-k6-iiie+ low- power processors drive 01010b on the vid[4:0] pins. the vid-capable voltage regulator and implementation must be equipped to handle this signaling at reset. see safe voltage and frequency combination at reset on page 20 for details. n logic and gates should be used in conjunction with the spwrgd signal to ensure voltage continuity from the voltage regulator at reset. 18 hardware implementation amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information hardware implementation embedded system designs can be modified to support amd powernow! technology with minimal design changes. new traces must be added to route the new processor output pins to the proper hardware components. based on the desired implementation of the amd powernow! technology features, additional hardware may be required; and depending on the current system design, the voltage regulator may need to be updated to properly support amd powernow! technology voltage transitions. figure 4 on page 19 illustrates an amd powernow! technology design which uses the maxim 1711 dc/dc regulator. obviously, other devices can be used in exchange for those used in this example. alternative components and matching input pins are provided in table 8 on page 19. hardware implementation 19 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information figure 4. example hardware implementation table 8. alternative components for amd powernow!? technology hardware implementation component model and input pin information dc/dc voltage regulator maxim 1711 maxim 1714b comment pin name pin no. pin name pin no. d[4:0] 16-20 n/a n/a 1714b does not use vid[4:0] inputs pgood 12 pgood 7 max1711 dc/dc regulator d[4] d[3] d[2] d[1] d[0] bf2 bf1 bf0 amd-k6?-2e+ or amd-k6?- iii e+ processor vid[4] vid[2] vid[0] spwrgd v cc2 d[3] d[2] d[1] 74lvc08 1 2 3 6 8 4 5 10 9 20 hardware implementation amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information safe voltage and frequency combination at reset a safe voltage and frequency combination at reset is a combination that provides functional processor operation conditions when reset is negated. minimum frequency initialization systems that strap the processor bf[2:0] inputs to 100b configure the processor to boot with a core frequency of 2.0x the processor bus frequency upon reset, which is the lowest supported frequency, are set for the minimum frequency initialization. n the advantage to this implementation is that any supported amd-k6-2e+ and amd-k6-iiie+ processor core voltage can be used for proper operation for the minimum frequency setting with the bf multiplier of 2.0x. n the disadvantage of this method is that the maximum rated frequency of the processor cannot be determined by the state of the bf[2:0] pins. c onnecting the processors vid[4:0] outputs to the regulators d[4:0] inputs through a multiplexer that selects the processors vid[4:0] outputs when spwrgd = 1 will result in a cpu voltage of 1.5 v. if the processors vid[4:0] outputs are mapped with a one-to-one correspondence to the regulators d[4:0] inputs, it is required that the multiplexer drive 01010b to the d[4:0] regulator inputs, respectively, when spwrgd = 0. this maintains v cc2 continuity at 1.5 v for the core voltage as spwrgd transitions from unstable to good. the combination of 1.5 v and a 2.0x bus frequency multiplier provides a voltage and frequency at power up that guarantees functional operating conditions. if the bf[2:0] inputs are strapped to select a 2.0x bus frequency multiplier, but a higher performance level is desired before loading the os, then it is the responsibility of the bios or the rtos to adjust the processors core frequency and voltage to the desired operational level early in the post routine. hardware implementation 21 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information maximum frequency initialization (recommended) systems that strap the processor bf[2:0] inputs so that the processor runs at the highest supported frequency are set for maximum frequency. n the advantage of this implementation is that it does allow the bios to directly determine the cpus maximum frequency by the state of the bf[2:0] pins. n the disadvantage of this method is that it limits the number of regulator vid[4:0] input combinations and the output core voltage range available. it is also important to note that the v cc2 voltage will be initialized to 2.0 v. if it is desired to have the processor run at its maximum frequency whenever reset is asserted, all of the processors vid[4:0] outputs cannot be tied directly to the regulators d[4:0] inputs using this method. a total one-to-one vid[4:0] correspondence results in a core voltage supply of 1.5 v, which does not guarantee functional operation conditions at the processors maximum frequency. in the case that the bf[2:0] inputs to the processor are strapped to select the maximum cpu core frequency, additional logic is required to translate the cpus default vid[4:0] output into a regulator input that is interpreted as a voltage that provides functional operation conditions at the processors maximum frequency. the recommended solution is shown in figure 4 on page 19. for a step-by-step example of how to modify an existing design for this recommended implementation, see vid[4:0] modification for maximum bf[2:0] boot option on page 24. 22 hardware implementation amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information voltage versus frequency options in addition to initializing the processor at the minimum or maximum frequencies, intermediate frequency/voltage combinations can be selected, thereby allowing for additional flexibility in performance and power consumption. table 9 on page 23 and table 10 list the minimum core voltage required to support various frequencies of a particular speed grade. for example, an amd-k6-iiie+ processor rated to run at 500 mhz at a nominal core voltage of 1.8 v is designed to run between 200 and 300 mhz with a nominal core voltage of 1.4 v. hardware implementation 23 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information table 9. supported voltages and operating frequencies for low-power amd-k6?-2e+ processors enabled with amd powernow!? technology ordering part number 1 notes: 1. an x in this column represents the package type. see the processor data sheet for a full description of ordering part number notation. core voltage range of supported operating frequencies 2 2. amd powernow! technology enables the operating frequency to step down in increments corresponding to the available bus freque ncy multipliers. note that 250-mhz operation is not supported due to exclusion of 2.5 bus frequency multiplier. active power 3 3. active application power dissipation for highest and lowest supported frequency at specified voltage. amd-k6-2e+/450apz 1.7 v 450C200 mhz 8.70C4.90 w 1.6 v 400C200 mhz 6.90C4.20 w 1.5 v 350C200 mhz 5.60C3.70 w 1.4 v 300C200 mhz 4.30C2.95 w amd-k6-2e+/400xtz 1.6 v 400C200 mhz 6.90C4.20 w 1.5 v 350C200 mhz 5.60C3.70 w 1.4 v 300C200 mhz 4.30C2.95 w amd-k6-2e+/350xuz 1.5 v 350C200 mhz 5.60C3.70 w 1.4 v 300C200 mhz 4.30C2.95 w table 10. supported voltages and operating frequencies for low-power amd-k6?- iii e+ processors enabled with amd powernow!? technology ordering part number 1 notes: 1. an x in this column represents the package type. see the processor data sheet for a full description of ordering part number notation. core voltage range of supported operating frequencies 2 2. amd powernow! technology enables the operating frequency to step down in increments corresponding to the available bus freque ncy multipliers. note that 250-mhz operation is not supported due to exclusion of 2.5 bus frequency multiplier. active power 3 3. active application power dissipation for highest and lowest supported frequency at specified voltage. amd-k6- iii e+500anz 1.8 v 500C200 mhz 11.40C5.80 w 1.7 v 450C200 mhz 8.95C4.90 w 1.6 v 400C200 mhz 7.10C4.20 w 1.5 v 350C200 mhz 5.60C3.70 w 1.4 v 300C200 mhz 4.30C2.95 w amd-k6- iii e+450apz 1.7 v 450C200 mhz 8.95C4.90 w 1.6 v 400C200 mhz 7.10C4.20 w 1.5 v 350C200 mhz 5.60C3.70 w 1.4 v 300C200 mhz 4.30C2.95 w amd-k6- iii e+400xtz 1.6 v 400C200 mhz 7.10C4.20 w 1.5 v 350C200 mhz 5.60C3.70 w 1.4 v 300C200 mhz 4.30C2.95 w 24 hardware implementation amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information vid[4:0] modification for maximum bf[2:0] boot option the following section discusses a step-by-step process for modifying a design to accommodate the recommended maximum bf[2:0] boot option using the maxim 1711 dc/dc voltage regulator. an assisting diagram is provided in figure 5 on page 25. n disconnect processor output pins: ah32, an35, r34, e25, and e17 from any current destinations n leave processor output pins an35 and e25 unconnected n connect the maxim 1711 dac inputs d4 (pin16) and d0 (pin 20) directly to gnd n add a 74lvc08 quadruple 2-input and gate, connecting v cc (pin 14) to +3.3v and gnd (pin 7) to gnd. n connect processor vid[4] (pin e17) to 74lvc08 pin 1 n connect processor vid[2] (pin r34) to 74lvc08 pin 4 n connect processor vid[0] (pin ah32) to 74lvc08 pin 10 n add 10k-ohm pull-up resistors on 74lvc08 pins 1, 4, 10 to +3.3v n connect spwrgd (system power good) to 74lvc08 pins 2, 5, and 9 n connect 74lvc08 pin 8 to maxim 1711 dac input d[1] (pin 19) n connect 74lvc08 pin 6 to maxim 1711 dac input d[2] (pin 18) n connect 74lvc08 pin 3 to maxim 1711 dac input d[3] (pin 17) n connect 74lvc08 pins 12 and 13 to gnd to prevent the unused inputs from floating hardware implementation 25 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information figure 5. vid[4:0] modification for maximum frequency initialization max1711 dc/dc regulator d[4] d[3] d[2] d[1] d[0] amd-k6?-2e+ or amd-k6?- iii e+ processor vid[4] vid[2] vid[0] spwrgd v cc2 74lvc08 d[3] d[2] d[1] 16 17 18 19 20 pgood logic to generate spwrgd 12 1 2 3 +3.3 v +3.3 v 10 k 10 k 10 k 6 8 4 5 10 9 vid[3] vid[1] vpwrgd 26 hardware implementation amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information gating pgood during a voltage transition most dc/dc regulators, such as the maxim 1711, have an output to indicate a stable core voltage (pgood) that may glitch low during amd powernow! technology voltage transitions. pgood can be used by system logic to generate the spwrgd (system power good) signal. because the south bridge asserts cpurst when spwrgd is negated, any glitches of pgood during these state transitions must be intercepted in order to prevent a cpu reset. the recommended solution for intercepting pgood and ensuring that a system reset does not occur during amd powernow! technology core voltage transitions is to logically or the pgood output with the pcirst# signal. however, since the regulator s pgood signal is gated, this solution does not allow the system to monitor the cpu core voltage for guarding against an out-of-spec condition. figure 6 on page 27 illustrates the necessary modifications for intercepting the dc/dc regulator pgood signal amd powernow! technology voltage transitions. hardware implementation 27 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information figure 6. gating the pgood signal with maximum frequency initialization max1711 dc/dc regulator d[4] d[3] d[2] d[1] d[0] amd-k6?-2e+ or amd-k6?- iii e+ processor vid[4] vid[2] vid[0] spwrgd v cc2 74lvc08 d[3] d[2] d[1] 16 17 18 19 20 pgood logic to generate spwrgd 12 1 2 3 +3.3 v +3.3 v 10 k 10 k 10 k 6 8 4 5 10 9 vid[3] vid[1] vpwrgd +5 v 10 k 1 2 3 10 k pcirst# +3.3 v 74lvc32 28 software implementation amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information software implementation cpu frequency and voltage setting combinations, called amd powernow! technology states , are dependent upon a number of factors. the hardware design directly influences what states are available and supported in the system. these may be dependent upon performance preferences, power requirements or, most often, a combination of both. apart from the hardware design is the software implementation. how and what is implemented in software directly impacts when a state transition takes place and what voltage and frequency settings are invoked by the hardware. some software components that can be utilized to implement a fully acpi-compliant power management scheme include: n real-time operating system (rtos) enabled for amd powernow! technology n smm handler n microsoft windows ? driver that supports amd powernow! technology n bios using an rtos enabled for amd powernow!? technology some real-time operating systems supporting amd powernow! technology will not require bios support or even a bios. in these instances, all the software required to invoke the epm stop grant state and change the settings for voltage and frequency, or both, resides in the rtos. software implementation 29 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information using an smm handler the amd powernow! technology bios smi api is the amd- defined method for a driver to communicate with the bios in a microsoft desktop operating system or with embedded windows nt. n if a driver is used, it will search for a bios-supplied table of information, which includes the address of the smi command port. n with the command port established, the driver then sets up parameters in general-purpose registers (the function and sub-function placed in the cx register) and generates an smi by writing to the smi command port. n as the smi command port mapping is specific to the south bridge, the bios/smm developer must assign an eight-bit code to properly execute the smm handler and enter smm. n values are then returned in general-purpose registers, and smm is entered. n the driver can use amd powernow! technology bios calls in smm to invoke amd powernow! technology state transitions, where these bios calls function in a similar manner to the bios intn functions supported by microsoft. using a microsoft ? windows ? driver supporting amd powernow! technology the amd powernow! technology-specific microsoft windows driver is the device driver that allows the communication of amd powernow! technology preferences from the system to the bios or smm code. any bios that complies with the amd powernow! technology bios smi api specification is expected to support driver requests from any operating system or utility system that is able to make the proper calls. the amd powernow! technology driver also: n updates the memory table that is used to communicate user performance preferences to bios. n communicates system preferences or changes to the bios. this involves invoking the smm handler (via the south bridges smi command port) when a state transition is desired. 30 software implementation amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information using a bios the bios should contain the following: n table of amd powernow! technology supported states used by the driver and smm handler n data reflecting the current amd powernow! technology settings n the mapping information required by the driver to access the smi command port in the systems south bridge. amd powernow!? technology descriptor table the amd powernow! technology descriptor table is a data structure typically built in the bios memory area at post. it is used to convey information to an amd powernow! technology enabled operating system kernel, device driver, or other interested application software. after searching for, locating, and reading the table during initialization after post, the amd powernow! technology controlling software will have all the platform-specific information and will know how to access it through amd powernow! technology control features. the signature for the table is located on a 16-byte boundary in the area from 0x0c0000 to 0x0fffff or within the first 1 kbyte of the extended bios data area. table 11 on page 31 provides the field definitions for the amd powernow! technology descriptor table. software implementation 31 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information table 11. amd powernow!? technology descriptor table offset length description 04 signature: gbdt 41 length, in bytes, of the entire amd powernow! technology bios descriptor table (no larger than 256 bytes.) 5 1 amd powernow! technology bios api revision in bcd. tens = major, ones = minor 6 1 checksum; entire table must sum to zero 71reserved 8 2 bus speed in binary mhz (66, 75, 83, 92, 100, 112, 133, 150, 200, etc.) 10 2 maximum cpu frequency for current processor in binary mhz 12 1 maximum amd powernow! technology state support by system (n). there are n+1 possible states and n<16. the minimum state is always zero. amd powernow! technology smi command port information 13 1 smi command port type/size: bit 0: address space, where 0 = x86 i/o address, and 1 = memory-mapped address. bits 6C4: data size, where 001 = 8 bits (byte access), 010 = 16 bits, 100 = 32 bits. bits 3C1, 7, and 8 are reserved and must be 0. 14 4 address of smi command port 18 4 amd powernow! technology_code (load esi register with this number before making smi call. currently the code is defined as 9800_0089h.) voltage/frequency to state map for current system 22 2 state 0 cpu voltage (a.bcd format) 24 2 state 0 cpu frequency (in binary mhz) 26 1 state 0 vid[4:0] 27 1 state 0 bf[2:0] 28 2 state 1 cpu voltage 30 2 state 1 cpu frequency 32 1 state 1 vid[4:0] 33 1 state 1 bf[2:0] 34 2 state 2 cpu voltage 36 2 state 2 cpu frequency 38 1 state 2 vid[4:0] 39 1 state 2 bf[2:0] xx 2 state n cpu voltage xx 2 state n cpu frequency xx 1 state n vid[4:0] xx 1 state n bf[2:0] 32 software implementation amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information event sequence for amd powernow!? technology state transitions the following is a summary sequence of events outlining what must occur for a successful amd powernow! technology state transition: n an smm handler or bios or operating system function may be called to carry out the amd powernow! technology state transition. n set the acpi-defined arb_dis bit in the north bridge to prevent pci and agp bus masters from being granted the bus and access to system memory while the amd powernow! technology state transition is taking place. this is necessary because the processor is not capable of responding to cache snoops while its core voltage and/or frequency are being transitioned. note: all bus activity to the processor must cease before initiating the amd powernow! technology state transition. this is critical as a bus transaction may be in progress when the arb_dis bit is set. additionally, there may be several memory accesses queued, which must be completed prior to entering epm stop grant state. n enable the en bit of the epmr register, making the frequency and voltage control fields accessible within the epm 16-byte i/o block. n write the desired values for the requested operating voltage and frequency settings in the bvc field. n initiate the amd powernow! technology state transition by writing a non-zero value to the sgtc field within the bvc field of the epm 16-byte i/o block. this action causes the processor to enter the epm stop grant state. n after the amd powernow! technology state transition, disable the en bit of the epmr register, which renders the frequency and voltage control fields invisible within i/o space. n clear the arb_dis bit in the north bridge to allow system memory accesses. n if an smm handler is used to invoke epm stop grant state, a rsm instruction should be executed to return the cpu to normal operation. pinout information 33 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information pinout information amd-k6-2e+ and amd-k6-iiie+ low-power processors enabled with amd powernow! technology use the amd standard, 321- pin cpga package and are also available in a 349-ball obga package. to support amd powernow! technology, five new output pins have been added that replace pins previously designated as either nc or inc pins. table 12 lists the new pins added to support amd powernow! technology. table 13 on page 34 and table 14 on page 35 list the cpga processor pins. table 15 on page 36 and table 16 on page 37 list the obga processor pins. table 12. pins added for amd powernow!? technology amd powernow!? technology function pin name cpga pin number obga pin number description voltage id control vid[4] e-17 a-11 these voltage identification outputs are used to drive the vid inputs of the dc/dc converter that generates the core voltage for the processor. the processor vid[4:0] outputs default to 01010b when reset is asserted. vid[3] e-25 c-15 vid[2] r-34 l-19 vid[1] an-35 w-16 vid[0] ah-32 w-17 34 pinout information amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information table 13. cpga pin designations by functional grouping pin name pin number pin name pin number pin name pin number pin name pin number control address data data a20m# ak-08 a3 al-35 d0 k-34 d52 e-03 ads# aj-05 a4 am-34 d1 g-35 d53 g-05 adsc# am-02 a5 ak-32 d2 j-35 d54 e-01 ahold v-04 a6 an-33 d3 g-33 d55 g-03 apchk# ae-05 a7 al-33 d4 f-36 d56 h-04 be0# al-09 a8 am-32 d5 f-34 d57 j-03 be1# ak-10 a9 ak-30 d6 e-35 d58 j-05 be2# al-11 a10 an-31 d7 e-33 d59 k-04 be3# ak-12 a11 al-31 d8 d-34 d60 l-05 be4# al-13 a12 al-29 d9 c-37 d61 l-03 be5# ak-14 a13 ak-28 d10 c-35 d62 m-04 be6# al-15 a14 al-27 d11 b-36 d63 n-03 be7# ak-16 a15 ak-26 d12 d-32 test bf0 y-33 a16 al-25 d13 b-34 tck m-34 bf1 x-34 a17 ak-24 d14 c-33 tdi n-35 bf2 w-35 a18 al-23 d15 a-35 tdo n-33 boff# z-04 a19 ak-22 d16 b-32 tms p-34 brdy# x-04 a20 al-21 d17 c-31 trst# q-33 brdyc# y-03 a21 af-34 d18 a-33 parity breq aj-01 a22 ah-36 d19 d-28 ap ak-02 cache# u-03 a23 ae-33 d20 b-30 dp0 d-36 clk ak-18 a24 ag-35 d21 c-29 dp1 d-30 d/c# ak-04 a25 aj-35 d22 a-31 dp2 c-25 eads# am-04 a26 ah-34 d23 d-26 dp3 d-18 ewbe# w-03 a27 ag-33 d24 c-27 dp4 c-07 ferr# q-05 a28 ak-36 d25 c-23 dp5 f-06 flush# an-07 a29 ak-34 d26 d-24 dp6 f-02 hit# ak-06 a30 am-36 d27 c-21 dp7 n-05 hitm# al-05 a31 aj-33 d28 d-22 voltage id hlda aj-03 d29 c-19 vid0 ah-32 hold ab-04 d30 d-20 vid1 an-35 ignne# aa-35 d31 c-17 vid2 r-34 init aa-33 d32 c-15 vid3 e-25 intr ad-34 d33 d-16 vid4 e-17 inv u-05 d34 c-13 ken# w-05 d35 d-14 lock# ah-04 d36 c-11 m/io# t-04 d37 d-12 na# y-05 d38 c-09 nmi ac-33 d39 d-10 pcd ag-05 d40 d-08 pchk# af-04 d41 a-05 pwt al-03 d42 e-09 reset ak-20 d43 b-04 scyc al-17 d44 d-06 smi# ab-34 d45 c-05 smiact# ag-03 d46 e-07 stpclk# v-34 d47 c-03 vcc2det al-01 d48 d-04 vcc2h/l# an-05 d49 e-05 w/r# am-06 d50 d-02 wb/wt# aa-05 d51 f-04 pinout information 35 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information table 14. cpga pin designations for no connect, reserved, power, and ground pins pin numbers no connect (nc) v cc2 v cc3 v ss v ss a-37 a-07 a-19 a-03 aj-27 c-01 a-09 a-21 b-06 aj-31 s-33 a-11 a-23 b-08 aj-37 s-35 a-13 a-25 b-10 al-37 w-33 a-15 a-27 b-12 am-08 aj-15 a-17 a-29 b-14 am-10 aj-23 b-02 e-21 b-16 am-12 al-19 e-15 e-27 b-18 am-14 internal no connect (inc) g-01 e-37 b-20 am-16 h-34 j-01 g-37 b-22 am-18 y-35 l-01 j-37 b-24 am-20 z-34 n-01 l-33 b-26 am-22 ac-35 q-01 l-37 b-28 am-24 al-07 s-01 n-37 e-11 am-26 an-01 u-01 q-37 e-13 am-28 an-03 w-01 s-37 e-19 am-30 reserved (rsvd) y-01 t-34 e-23 an-37 j-33 aa-01 u-33 e-29 l-35 ac-01 u-37 e-31 p-04 ae-01 w-37 h-02 q-03 ag-01 y-37 h-36 q-35 aj-11 aa-37 k-02 r-04 an-09 ac-37 k-36 s-03 an-11 ae-37 m-02 s-05 an-13 ag-37 m-36 aa-03 an-15 aj-19 p-02 ac-03 an-17 aj-29 p-36 ac-05 an-19 an-21 r-02 ad-04 an-23 r-36 ae-03 an-25 t-02 ae-35 an-27 t-36 an-29 u-35 v-02 v-36 x-02 x-36 z-02 z-36 ab-02 ab-36 ad-02 ad-36 af-02 af-36 ah-02 aj-07 aj-09 aj-13 aj-17 aj-21 aj-25 36 pinout information amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information table 15. obga pin designations by functional grouping pin name pin number pin name pin number pin name pin number pin name pin number control address data data a20m# w-4 a3 t-14 d0 h-18 d52 a-3 ads# u-1 a4 t-13 d1 g-19 d53 d-5 adsc# t-3 a5 w-15 d2 h-19 d54 c-3 ahold k-4 a6 v-14 d3 f-17 d55 e-3 apchk# r-1 a7 u-14 d4 h-17 d56 d-2 be0# u-6 a8 t-12 d5 f-18 d57 e-4 be1# w-5 a9 w-14 d6 f-19 d58 d-3 be2# v-6 a10 v-12 d7 e-16 d59 d-1 be3# w-6 a11 w-13 d8 e-17 d60 e-1 be4# u-7 a12 w-12 d9 e-19 d61 f-3 be5# t-8 a13 u-13 d10 d-19 d62 f-2 be6# u-8 a14 w-11 d11 f-16 d63 f-4 be7# v-8 a15 u-12 d12 d-18 test bf0 n-17 a16 t-11 d13 d-14 tck j-19 bf1 m-17 a17 w-10 d14 d-17 tdi k-19 bf2 n-19 a18 v-10 d15 d-15 tdo j-16 boff# l-3 a19 u-10 d16 a-17 tms k-18 brdy# k-1 a20 t-10 d17 b-18 trst# k-17 brdyc# l-1 a21 t-17 d18 c-19 parity breq p-4 a22 t-19 d19 b-16 ap r-3 cache# j-4 a23 u-19 d20 a-16 dp0 g-17 clk u-9 a24 t-18 d21 d-13 dp1 c-17 d/c# u-3 a25 v-18 d22 c-16 dp2 b-14 eads# v-4 a26 u-17 d23 a-15 dp3 c-11 ewbe# k-3 a27 t-15 d24 c-14 dp4 c-8 ferr# g-4 a28 r-16 d25 c-13 dp5 a-4 flush# t-7 a29 u-16 d26 a-14 dp6 c-1 hit# w-3 a30 v-16 d27 c-12 dp7 f-1 hitm# u-4 a31 u-15 d28 a-13 voltage id hlda t-2 d29 a-12 vid0 w-17 hold m-3 d30 b-12 vid1 w-16 ignne# p-19 d31 d-11 vid2 l-19 init p-17 d32 b-10 vid3 c-15 intr p-16 d33 a-10 vid4 a-11 inv j-1 d34 d-10 ken# k-2 d35 c-10 lock# t-1 d36 d-9 m/io# j-3 d37 a-9 na# l-4 d38 c-9 nmi r-17 d39 a-8 pcd r-4 d40 a-7 pchk# p-3 d41 b-8 pwt v-2 d42 d-7 reset w-9 d43 c-7 scyc w-8 d44 b-6 smi# p-18 d45 a-6 smiact# p-2 d46 c-6 stpclk# m-18 d47 a-5 w/r# u-5 d48 d-6 wb/wt# m-2 d49 c-5 d50 c-4 d51 b-2 pinout information 37 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information table 16. obga pin designations for no connect, reserved, power, and ground pins pin numbers no connect (nc) v cc2 v cc3 v ss v ss b-4 c-2 b-13 b-3 k-13 l-17 d-4 b-17 b-5 k-15 m-16 e-5 e-18 b-7 l-6 m-19 f-6 f-14 b-9 l-7 t-5 f-7 g-15 b-11 l-8 t-9 f-8 h-10 b-15 l-9 u-11 f-9 h-11 c-18 l-10 w-7 f-10 h-12 d-8 l-11 internal no connect (inc) f-11 h-13 d-12 l-12 n-16 g-2 h-14 d-16 l-13 reserved (rsvd) g-5 h-16 e-2 l-14 g-1 h-4 j-15 e-6 l-16 g-3 h-6 j-18 e-7 l-18 g-16 h-7 k-14 e-8 m-5 h-1 j-5 l-15 e-9 m-12 h-2 k-6 m-14 e-10 m-13 h-3 k-7 n-15 e-11 m-15 j-17 k-8 n-18 e-12 n-2 k-16 k-9 p-11 e-13 n-6 m-1 k-10 p-12 e-14 n-7 n-1 k-11 p-14 e-15 n-8 n-3 l-2 r-10 f-5 n-9 n-4 l-5 r-13 f-12 n-10 p-1 m-4 u-18 f-13 n-11 p-8 m-6 v-11 f-15 n-12 r-8 m-7 v-15 g-6 n-13 r-19 m-8 g-7 n-14 m-9 g-8 p-5 m-10 g-9 p-7 m-11 g-10 p-9 n-5 g-11 p-10 p-6 g-12 p-13 r-2 g-13 p-15 r-5 g-14 r-6 t-4 g-18 r-7 v-3 h-5 r-9 v-7 h-8 r-11 h-9 r-12 h-15 r-14 j-2 r-15 j-6 r-18 j-7 t-6 j-8 t-16 j-9 u-2 j-10 v-5 j-11 v-9 j-12 v-13 j-13 v-17 j-14 k-5 k-12 38 documentation and technical support amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information documentation and technical support the following documents provide additional information regarding the amd powernow! technology initiative and the operation of the amd-k6-2e+ and amd-k6-iiie+ processors: n embedded amd-k6? processors bios design guide application note ( order# 23913) n amd-k6?-2e+ embedded processor data sheet (order# 23542) n amd-k6?-2e+ embedded processor data sheet (order# 23543) appendix afrequently asked questions 39 24267A/0december 2000 amd powernow!? technology platform design guide for embedded processors preliminary information appendix afrequently asked questions new output pins question: what kind of output buffer do the new amd powernow!? technology output pins have? answer: the new processor output pins have standard cmos push-pull driver buffers. all outputs are always driven. question: are the new amd powernow! technology output pins 5-v-tolerant? answer: no. the new amd powernow! technology output pins adhere to the standard 3.3-v amd-k6 family i/o voltage specification. question: what should be done for any amd powernow! technology output pin that is not used? answer: unused amd powernow! technology output pins should be treated as ncs (no-connects). amd powernow!? technology state transitions question: are there any design limitations to voltage or bus frequency transitions? answer: yes. system-initiated inquire (snoop) cycles are not supported and must be prevented during amd powernow! technology transitions by setting the arb_dis bit in the north bridge. question: is there a need to stop the cpu clock during state transitions? answer: no. however, state transitions must be performed while the processor is in the epm stop grant state. the epm stop grant state is a low-power, clock-control state entered by writing a non-zero value to the sgtc field for the purpose of changing the processor core frequency and voltage. 40 appendix afrequently asked questions amd powernow!? technology platform design guide for embedded processors 24267A/0december 2000 preliminary information question: is there a need to assert reset to perform amd powernow! technology state transitions? answer: no. amd powernow! technology state transitions are designed to operate dynamically and transparent to normal system operation. question: are there any timing specifications for the length of a amd powernow! technology transition period? answer: the suggested duration of time for a complete amd powernow! technology transition is 200 m s. hardware implementation question: if a maximum bf[2:0] boot strap option is implemented using the recommended and-gate logic solution, is a multiplexer still required to guarantee a deterministic voltage at power on? answer: no. the and-gate logic solution functions as a multiplexer. when the system power good (spwrgd) signal is low, the and-gate logic drives the regulator inputs appropriately. when spwrgd is high, the and-gate logic allows the processor vid[4:0] outputs to drive the regulator inputs. question: can a signal other than the spwrgd be used for gating the cpu vid[4:0] outputs? answer: yes, the pci reset pin can also be used to gate the cpu vid[4:0] outputs to the dc/dc regulator. however, the system must ensure that pcirst# is driven low when power is applied to the processor. software implementation question: if the bios needs to access the epmr register during post before the smm handler is installed, can the epmr register be accessed outside of smm? answer: yes. however, the smm handler must be installed before smis initiated by amd powernow! technology can be serviced. 41 24267A/0december 2000 preliminary information index a agp bus control during state transitions . . . . . . . . . . . . . . . . . . . . . 32 amd powernow!? technology descriptor table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 , 30 documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 enhanced power management features . . . . . . . . . . . . . . . 3 frequently asked questions . . . . . . . . . . . . . . . . . . . . . . . . 39 hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . 18 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 initiative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 operational modes (table) . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pinout information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 software implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 28 state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 and gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 , 40 api revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 b bdc field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 , 17 bf[2:0] signals, strapping considerations. . . . . . . . . . . . . . . 9 bios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 descriptor table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 epmr access outside of smm . . . . . . . . . . . . . . . . . . . . . . 40 initializing the epm i ? block after reset . . . . . . . . . . . . . . . 5 initializing the epmr register after reset . . . . . . . . . . . . . 3 reporting i/o range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 using a different cpu core frequency . . . . . . . . . . . . . 9 , 20 boot option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 bus divisor and vid change mode (bvcm) . . . . . . . . . . . . 11 bus divisor control (bdc) . . . . . . . . . . . . . . . . . . . . . . . . 11 , 17 bus speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 bvc field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 , 16 bvcm field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 c cmos push-pull driver buffers . . . . . . . . . . . . . . . . . . . . . . 39 core frequency and voltage control . . . . . . . . . . . . . . . . . . 20 cpga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 pin designations by function (table) . . . . . . . . . . . . . . . . . 34 cpu clock, stopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 cpu core voltage, guaranteed at power on . . . . . . . . . . . . 14 cpurst signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 cx register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 d dc ? dc regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 , 30 C 31 documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 dynamic core frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 core frequency control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 core voltage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 15 e ebf[2:0] field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 effective bus divisors ebf[2:0] . . . . . . . . . . . . . . . . . . . . . . . .8 en bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 , 16 enable amd powernow! technology management (en)4 , 16 enhanced power management features . . . . . . . . . . . . . . . . .3 core voltage control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 dynamic core frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 enhanced power management register (epmr) . . . . . . . .3 enhanced power management register (epmr) . . . . . . . . .3 epm 16-byte i/o block . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 , 16 epm stop grant state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 entering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 C 11 , 32 exiting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 epmr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 , 32 accessing outside of smm. . . . . . . . . . . . . . . . . . . . . . . . . . 40 accessing using smm handler . . . . . . . . . . . . . . . . . . . . . . .7 esi register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 extended bios data area . . . . . . . . . . . . . . . . . . . . . . . 17 , 30 f frequency dynamic core frequency control. . . . . . . . . . . . . . . . . . . . . 10 maximum frequency initialization (recommended). . . . . 21 minimum frequency initialization . . . . . . . . . . . . . . . . . . . 20 selecting maximum cpu core frequency . . . . . . . . . . . . . .9 selecting minimum cpu core frequency. . . . . . . . . . . . . . .9 frequently asked questions . . . . . . . . . . . . . . . . . . . . . . . . . 39 g generate special bus cycle (gsbc) . . . . . . . . . . . . . . . . . . . .4 gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 C 13 , 24 ground pin designations (table) . . . . . . . . . . . . . . . . . . . . . . . 35 , 37 regulator inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 , 24 regulator inputs (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 gsbc bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 , 7 h hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 core frequency and voltage control . . . . . . . . . . . . . . . . . . 20 example implementation (figure) . . . . . . . . . . . . . . . . . . . 19 gating pgood during a voltage transition. . . . . . . . . . . . 26 gating pgood signal with maximum frequency initializa- tion (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 logic and gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 , 40 safe voltage and frequency combination at reset . . . . . . 20 spwrgd signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 , 20 , 26 vid[4:0] modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 vid[4:0] modification for maximum frequency initializa- tion (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 voltage versus frequency options. . . . . . . . . . . . . . . . . . . . 22 42 23542a/0september 2000 preliminary information i i/o base address (iobase) . . . . . . . . . . . . . . . . . . . . . . . 4 , 16 ibf field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 10 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 inquire cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 not supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 internal bf divisor (ibf) . . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 11 iobase field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 , 16 m maxim 1711 dc ? ?c regulator . . . . . . . . . . . . . . . . . . . . . 18 , 24 memory completing accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 disabling accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 updating table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 microsoft? windows? driver . . . . . . . . . . . . . . . . . . . . . . . . 29 multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 n nc pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 unused vid[4:0] outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 12 north bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 o obga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 pin designations by function (table) . . . . . . . . . . . . . . . . . 36 operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 output buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 p pci bus control during state transitions . . . . . . . . . . . . . . . . . . . . . 32 reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 40 pcirst# signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 40 pgood signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 gating during voltage transition . . . . . . . . . . . . . . . . . . . . 26 pins new output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 pinout information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 power-on self test (post) . . . . . . . . . . . . . . . . . . . . . .5 , 16 C 17 processor core frequency control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 dynamic core frequency control . . . . . . . . . . . . . . . . . . . . 10 maximum core frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . 9 minimum core frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 processor state observability register (psor) . . . . . . . . . . 9 processor-to-bus clock ratios (table) . . . . . . . . . . . . . . . . . . . 8 psor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 r real-time operating system . . . . . . . . . . . . . . . . . . . . . . . . . 28 registers cx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 enhanced power management (epmr) . . . . . . . . . . . . . 3 C 4 esi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 general-purpose. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 processor state observability (psor) . . . . . . . . . . . . . . . . . 9 regulator d[4:0] to vid[4:0] mapping . . . . . . . . . . . . . . . . . . . . .20 C 21 dc/dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 driving input select pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 external logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 maxim 1711 dc/dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 pgood signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 pin connections (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 using a subset of cpu vid outputs (table). . . . . . . . . . . . 13 reserved (rsvd) pins pin designations (table) . . . . . . . . . . . . . . . . . . . . . . . 35 , 37 reset hardware initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 safe voltage and frequency combination . . . . . . . . . . . . .20 reset signal bvc effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ebf value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 epm i/o block effect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 epmr effect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 C 4 selecting maximum cpu core frequency . . . . . . . . . . . . . .9 selecting maximum frequency initialization . . . . . . . . . . 21 selecting minimum cpu core frequency. . . . . . . . . . . . . . .9 selecting minimum frequency initialization . . . . . . . . . . . 20 state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 vid[4:0] effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 rtos. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 enabling amd powernow! technology features . . . . . . . . .5 initializing the epm i ? block after reset . . . . . . . . . . . . . . .5 initializing the epmr register after reset . . . . . . . . . . . . .3 using a different cpu core frequency. . . . . . . . . . . . . . . . 20 s sgtc field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 11 , 16 C 17 signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 smi command port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 C 31 smm handler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 , 29 accessing the epm i ? block . . . . . . . . . . . . . . . . . . . . . . . . . 10 accessing the epmr register . . . . . . . . . . . . . . . . . . . . . . . .7 core voltage and frequency transitions . . . . . . . . . . . . 7 , 10 dynamic core voltage control . . . . . . . . . . . . . . . . . . . . . . .15 enabling amd powernow! technology features . . . . . . . . .5 initiating a special bus cycle . . . . . . . . . . . . . . . . . . . . . . . .7 using rsm instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 snoop cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 not supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 software implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 amd powernow!? technology descriptor table . . . . . . . 30 initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 state transition event sequence . . . . . . . . . . . . . . . . . . . . . 32 using a bios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 using a microsoft? windows? driver . . . . . . . . . . . . . . . . 29 using an rtos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 using an smm handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 south bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 29 C 30 special bus cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 spwrgd signal . . . . . . . . . . . . . . . . . . . . . .14 , 17 , 24 , 26 , 40 state map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 43 24267A/0december 2000 preliminary information state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 controlling with bvc field . . . . . . . . . . . . . . . . . . . . . . . . . . 6 event sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 stop grant time-out counter (sgtc) . . . . . . . . . . . . . . . . . 11 strapping considerations. . . . . . . . . . . . . . . . . . . . . . . . . . 9 , 14 system management mode (smm) . . . . . . . . . . . . . . . . . . . . 29 system power good (spwrgd) signal . . . . . . . . . . . . . . . . 14 t technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 timing requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 v vcc2 pins core voltage of 1.5 v at power-up . . . . . . . . . . . . . . . . . . . 20 initialized to 2.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 pin designations (table) . . . . . . . . . . . . . . . . . . . . . . . . 35 , 37 vcc3 pins pin designations (table) . . . . . . . . . . . . . . . . . . . . . . . . 35 , 37 vid[4:0] signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 input-to-output voltage codes (table) . . . . . . . . . . . . . . . . 13 modification for maximum bf[2:0] boot option . . . . . . . 24 outputs not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 , 14 , 33 using all outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 voltage id control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 voltage id output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 vidc bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 , 16 vido field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 10 C 11 , 15 voltage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 dynamic core voltage control. . . . . . . . . . . . . . . . . . . . . . . 15 pgood gating during transition. . . . . . . . . . . . . . . . . . . . 26 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 C 13 , 17 safe voltage and frequency combination at reset . . . . . 20 versus frequency options . . . . . . . . . . . . . . . . . . . . . . . . . . 22 voltage id control (vidc). . . . . . . . . . . . . . . . . . . . . . . . 11 , 16 voltage id output (vido) . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 11 vss pins pin designations (table) . . . . . . . . . . . . . . . . . . . . . . . . 35 , 37 w windows? driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 44 23542a/0september 2000 preliminary information |
Price & Availability of 24267A
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