1 ltc1250 very low noise zero-drift bridge amplifier n electronic scales n strain gauge amplifiers n thermocouple amplifiers n high resolution data acquisition n low noise transducers n instrumentation amplifiers u s a o pp l ic at i n very low noise: 0.75 m v p-p typ, 0.1hz to 10hz n dc to 1hz noise lower than op-07 n full output swing into 1k load n offset voltage: 10 m v max n offset voltage drift: 50nv/ c max n common-mode rejection ratio: 110db min n power supply rejection ratio: 115db min n no external components required n pin-compatible with standard 8-pin op amps s f ea t u re d u escriptio the ltc ? 1250 is a high performance, very low noise zero- drift operational amplifier. the ltc1250s combination of low front-end noise and dc precision makes it ideal for use with low impedance bridge transducers. the ltc1250 features typical input noise of 0.75 m v p-p from 0.1hz to 10hz, and 0.2 m v p-p from 0.1hz to 1hz. the ltc1250 has dc to 1hz noise of 0.35 m v p-p , surpassing that of low noise bipolar parts including the op-07, op-77, and lt1012. the ltc1250 uses the industry-standard single op amp pinout, and requires no external components or nulling signals, allowing it to be a plug-in replacement for bipolar op amps. the ltc1250 incorporates an improved output stage capable of driving 4.3v into a 1k load with a single 5v supply; it will swing 4.9v into 5k with 5v supplies. the input common mode range includes ground with single power supply voltages above 12v. supply current is 3ma with a 5v supply, and overload recovery times from positive and negative saturation are 0.5ms and 1.5ms, respectively. the internal nulling clock is set at 5khz for optimum low frequency noise and offset drift; no external connections are necessary. the ltc1250 is available in standard 8-pin ceramic and plastic dips, as well as an 8-pin soic package. input referred noise 0.1hz to 10hz time (s) 0 m v 1 2 8 lt1250 ta02 0 ? ? 2 4 6 10 v s = ?v
a v = 10k differential bridge amplifier + 5v ?v 1000pf 18.2k 1000pf 18.2k 7 6 4 3 2 ?v 0.1 m f 5v a v = 100 1250 ta01 350 w strain
gauge 50 w
gain
trim ltc1250 u a o pp l ic at i ty p i ca l and ltc are registered trademarks and lt is a trademark of linear technology corporation.
2 ltc1250 wu u package / o rder i for atio a u g w a w u w a r b s o lu t exi t i s order part number 1
2
3
4 8
7
6
5
top view nc
in
+in
v nc
v +
out
nc n8 package
8-lead plastic dip j8 package
8-lead ceramic dip s8 package
8-lead plastic soic total supply voltage (v + to v C ) ............................. 18v input voltage ........................ (v + + 0.3v) to (v C C 0.3v) output short circuit duration ......................... indefinite operating temperature range ltc1250m..................................... C 55 c to 125 c ltc1250c .......................................... 0 c to 70 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec.) ................ 300 c ltc1250mj8 ltc1250cj8 ltc1250cn8 ltc1250cs8 t jmax = 150 c, q ja = 100 cw (j8) t jmax = 110 c, q ja = 130 cw (n8) t jmax = 110 c, q ja = 200 cw (s8) s8 part marking e lectr ic al c c hara terist ics ltc1250m ltc1250c symbol parameter conditions min typ max min typ max units v os input offset voltage t a = 25 c (note 1) 5 10 5 10 m v d v os average input offset drift (note 1) l 0.01 0.05 0.01 0.05 m v/ c long term offset drift 50 50 nv/ ? mo e n input noise voltage (note 2) t a = 25 c, 0.1hz to 10hz 0.75 1.0 0.75 1.0 m v p-p t a = 25 c, 0.1hz to 1hz 0.2 0.2 m v p-p i n input noise current f = 10hz 4.0 4.0 fa/ ? hz i b input bias current t a = 25 c (note 3) 50 150 50 200 pa l 950 450 pa i os input offset current t a = 25 c (note 3) 100 300 100 400 pa l 500 500 pa cmrr common-mode rejection ratio v cm = C 4v to 3v l 110 130 110 130 db psrr power supply rejection ratio v s = 2.375v to 8v l 115 130 115 130 db a vol large-signal voltage gain r l = 10k, v out = 4v l 125 170 125 170 db maximum output voltage swing r l = 1k l 4.0 4.3/C4.7 4.0 4.3 /C4.7 v r l = 100k 4.92 4.95 v sr slew rate r l = 10k, c l = 50pf 10 10 v/ m s gbw gain-bandwidth product 1.5 1.5 mhz i s supply current no load, t a = 25 c 3.0 4.0 3.0 4.0 ma l 7.0 5.0 ma f s internal sampling frequency t a = 25 c 4.75 4.75 khz v in = 5v, t a = operating temperature range, unless otherwise noted. ltc1250m ltc1250c symbol parameter conditions min typ max min typ max units v os input offset voltage t a = 25 c (note 1) 2 5 2 5 m v d v os average input offset drift (note 1) l 0.01 0.05 0.01 0.05 m v/ c e n input noise voltage (note 2) t a = 25 c, 0.1hz to 10hz 1.0 1.0 m v p-p t a = 25 c, 0.1hz to 1hz 0.3 0.3 m v p-p i b input bias current t a = 25 c (note 3) 20 100 20 100 pa i os input offset current t a = 25 c (note 3) 40 200 40 200 pa v in = 5v, t a = operating temperature range, unless otherwise noted. 1250
3 ltc1250 e lectr ic al c c hara terist ics ltc1250m ltc1250c symbol parameter conditions min typ max min typ max units maximum output voltage swing r l = 1k 4.0 4.3 4.0 4.3 v r l = 100k 4.95 4.95 v i s supply current t a = 25 c 1.8 2.5 1.8 2.5 ma f s sampling frequency t a = 25 c 3 3 khz the l denotes specifications which apply over the full operating temperature range. note 1: these parametes are guaranteed by design. thermocouple effects preclude measurement of these voltage levels during automated testing. note 2: 0.1hz to 10hz noise is specified dc coupled in a 10s window; 0.1hz to 1hz noise is specified in a 100s window with an rc high-pass v in = 5v, t a = operating temperature range, unless otherwise noted. filter at 0.1hz. the ltc1250 is sample tested for noise; for 100% tested parts contact ltc marketing dept. note 3: at t 0 c these parameters are guaranteed by design and not tested. cc hara terist ics uw a t y p i ca lper f o r c e sampling frequency vs supply voltage total supply voltage, v + to v (v) 4 0 input noise ( m v p-p ) 0.2 0.4 0.6 0.8 68 10 12 ltc1250 g01 1.0 1.2 1.4 1.6 14 16 t a = 25? 0.1hz to 10hz 0.1hz to 1hz total supply voltage, v + to v (v) 4 0 supply current (ma) 0.5 1.0 1.5 2.0 68 10 12 ltc1250 g02 2.5 3.0 3.5 4.0 14 16 t a = 25? supply current vs supply voltage input noise vs supply voltage temperature (?) ?0 sampling frequency (khz) 4 5 6 25 ltc1250 g06 3 2 ?5 0 50 1 0 8 7 75 100 150 v s = ?v sampling frequency vs temperature temperature (?) ?0 2.0 supply current (ma) 3.0 4.5 0 50 75 ltc1250 g05 2.5 4.0 3.5 ?5 25 100 125 v s = ?v supply current vs temperature input noise vs temperature temperature (?) ?0 input noise ( m v p-p ) 0.8 1.0 1.2 25 75 ltc1250 g04 0.6 0.4 ?5 0 50 100 125 0.2 0 v s = 5v
0.1hz to 10hz 0.1hz to 1hz total supply voltage, v + to v (v) 4 2 sampling frequency (khz) 3 4 68 10 12 ltc1250 g03 5 6 14 16 t a = 25?
4 ltc1250 cc hara terist ics uw a t y p i ca lper f o r c e voltage noise vs frequency frequency (hz) 20 voltage noise (nv/ ? hz) 30 40 50 80 1 100 1k 10k ltc1250 g11 0 10 70 60 10 v s = 5v
r s = 10 w frequency (hz) 0 gain (db) 20 40 60 100 1k 100k 1m 10m ltc1250 g10 ?0 10k 80 0 phase margin (deg) 20 40 60 100 ?0 80 gain phase:
r l = 1k phase:
r l = 100k v s = 5v or
single 5v
t a = 25?
c l = 100pf temperature (?) ?5 10 100 1000 100 75 ltc1250 g14 ?0 125 bias current ( | pa | ) 50 025 v s = ?v frequency (hz) 20 cmrr (db) 40 80 120 140 1 100 1k 100k ltc1250 g12 0 10 10k 60 100 v s = 5v
v cm = 1v rms common-mode rejection ratio vs frequency supply voltage ( v) 2 ? input common mode range (v) ? ? ? 0 34 5 6 ltc1250 g07 2 4 6 8 7 8 t a = 25? 0.2 0 0 C5 input (v) 500 m s/div a v = 100, r l = 100k, c l = 50pf, v s = 5v output (v) overload recovery 2v/div 1 m s/div a v = 1, r l = 100k, c l = 50pf, v s = 5v transient response load resistance (k w ) 0 output swing ( v) 6 8 10 8 ltc1250 g08 4 2 0 2 4 6 10 1 3 5 7 9 1357 9 r l to gnd v s = 8v v s = ?v v s = ?.5v negative swing
positive swing gain/phase vs frequency common-mode input range vs supply voltage output swing vs load resistance, dual supplies output voltage swing vs load resistance, single supply load resistance (k w ) 0 0 output swing (v) 4 6 8 18 12 2 4 59 ltc1250 g09 2 14 16 10 13 6 7 8 v s = 16v v s = 10v v s = 5v 10 v = gnd
r l to gnd bias current (magnitude) vs temperature
5 ltc1250 cc hara terist ics uw a t y p i ca lper f o r c e output swing vs output current, 5v supply short-circuit current vs temperature output swing vs output current, single 5v supply test circuits offset test circuit + 5v 100pf 100k 7 6 4 3 2 ?v output 1250 tc01 ltc1250 10 w u s a o pp l ic at i wu u i for atio input noise the ltc1250, like all cmos amplifiers, exhibits two types of low frequency noise: thermal noise and 1/f noise. the ltc1250 uses several design modifications to minimize these noise sources. thermal noise is minimized by rais- ing the g m of the front-end transistors by running them at high bias levels and using large transistor geometries. 1/f noise is combated by optimizing the zero-drift nulling loop to run at twice the 1/f corner frequency, allowing it to reduce the inherently high cmos 1/f noise to near thermal levels at low frequencies. the resultant noise spectrum is quite low at frequencies below the internal 5khz clock figure 1. voltage noise vs frequency frequency (hz) 20 voltage noise (nv/ ? hz) 30 40 50 80 0.01 1 ltc1250 f01 0 0.1 70 60 10 v s = 5v
r s = 10 w ltc1250 op-07 op-27 output current (ma) 0.01 ? output voltage (v) 0 1 2 3 0.1 1 10 ltc1250 g16 ? ? ? ? 4 5 v s = 5v output current (ma) 0.01 2 output voltage (v) 3 4 5 0.1 1 10 ltc1250 g17 1 0 6 v s = single 5v temperature (?) ?0 0 10 20 25 ltc1250 g18 ?0 ?0 ?5 0 50 ?0 ?0 40 75 100 125 short-circuit current (ma) 30 v s = ?5v v out = v v out = v + dc to 10hz noise test circuit (for dc to 1hz multiply all capacitor values by 10) 100pf 100k output 1250 tc02 + 5v 7 6 4 3 2 ?v ltc1250 10 w + 7 5 6 0.02 m f 800k + 3 2 800k 800k 0.04 m f 0.01 m f 1/2
lt1057 5v 8 1 4 ?v 1/2
lt1057
6 ltc1250 where a v = closed-loop gain. note that c f is not dependent on the value of r f . circuits with higher gain (a v > 50) or low loop impedance should not require c f for stability. frequency, approaching the best bipolar op amps at 10hz and surpassing them below 1hz (figure 1). all this is accomplished in an industry-standard pinout; the ltc1250 requires no external capacitors, no nulling or clock sig- nals, and conforms to industry-standard 8-pin dip and 8- pin soic packages. input capacitance and compensation the large input transistors create a parasitic 55pf capaci- tance from each input to v + . this input capacitance will react with the external feedback resistors to form a pole which can affect amplifier stability. in low gain, high impedance configurations, the pole can land below the unity-gain frequency of the feedback network and degrade phase margin, causing ringing, oscillation, and other unpleasantness. this is true of any op amp, however, the 55pf capacitance at the ltc1250s inputs can affect stability with a feedback network impedance as low as 1.9k. this effect can be eliminated by adding a capacitor across the feedback resistor, adding a zero which cancels the input pole (figure 2). the value of this capacitor should be: u s a o pp l ic at i wu u i for atio fully cancel the 1/f noise spectrum and the low frequency noise of the part will rise. if the loop is underdamped (large r f , no c f ) it will ring for more than 150 m s and the noise and offset will suffer. the solution is to add c f as above but beware! too large a value of c f will overdamp the loop, again preventing it from reaching a final value by the 150 m s deadline. this condition doesnt affect the ltc1250s offset or output stability, but 1/f noise begins to rise. as a rule of thumb, the r f c f feedback pole should be 3 7khz (1/150 m s, the frequency at which the loop settles) for best 1/f perfor- mance; values between 100pf and 500pf work well with feedback resistors below 100k. this ensures adequate gain at 7khz for the ltc1250 to properly null. high value feedback resistors (above 1m) may require experimenta- tion to find the correct value because parasitics, both in the ltc1250 and on the pc board, play an increasing role. low value resistors (below 5k) may not require a capaci- tor at all. input bias current the inputs of the ltc1250, like all zero-drift op amps, draw only small switching spikes of ac bias current; dc leakage current is negligible except at very high tempera- tures. the large front-end transistors cause switching spikes 3 to 4 times greater than standard zero-drift op amps: the 50pa bias current spec is still many times better than most bipolar parts. the spikes dont match from one input pin to the other, and are sometimes (but not always) of opposite polarity. as a result, matching the impedances at the inputs (figure 3) will not cancel the bias current, and may cause additional errors. dont do it. + c f r in 1250 f02 ltc1250 r f c p figure 2. c f cancels phase shift due to parasitic c p larger values of c f , commonly used in band-limited dc circuits, may actually increase low frequency noise. the nulling circuitry in the ltc1250 closes a loop that includes the external feedback network during part of its cycle. this loop must settle to its final value within 150 m s or it will not c pf a f v 3 55 + r in 1250 f03 ltc1250 r f figure 3. extra resistor will not cancel bias current errors
7 ltc1250 u s a o pp l ic at i wu u i for atio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. output drive the ltc1250 includes an enhanced output stage which provides nearly symmetrical output source/sink currents. this output is capable of swinging a minimum of 4v into a 1k load with 5v supplies, and can sink or source >20ma into low impedance loads. lightly loaded (r l 3 100k), the ltc1250 will swing to within millivolts of either rail. in single supply applications, it will typically swing 4.3v into a 1k load with a 5v supply. minimizing external errors the input noise, offset voltage, and bias current specs for the ltc1250 are all well below the levels of circuit board parasitics. thermocouples between the copper pins of the ltc1250 and the tin/lead solder used to connect them can overwhelm the offset voltage of the ltc1250, especially if a soldering iron has been around recently. note also that when the ltc1250s output is heavily loaded, the chip may dissipate substantial power, raising the temperature of the package and aggravating thermocouples at the inputs. although the ltc1250 will maintain its specified accuracy under these conditions, care must be taken in the layout to prevent or compensate circuit errors. be especially careful of air currents when measuring low frequency noise; nearby moving objects (like people) can create very large noise peaks with an unshielded circuit board. for more detailed explanations and advice on how to avoid these errors, see the ltc1051/ltc1053 data sheet. sampling behavior the ltc1250s zero-drift nulling loop samples the input at ? 5khz, allowing it to process signals below 2khz with no aliasing. signals above this frequency may show aliasing behavior, although wideband internal circuitry generally keeps errors to a minimum. the output of the ltc1250 will have small spikes at the clock frequency and its harmonics; these will vary in amplitude with different feedback configu- rations. low frequency or band-limited systems should not be affected, but systems with higher bandwidth (oversampling a/ds, for example) may need to filter out these clock artifacts. output spikes can be minimized with a large feedback capacitor, but this will adversely affect noise performance (see input capacitance and compensation on the previous page). applications which require spike-free output in addition to minimum noise will need a low-pass filter after the ltc1250; a simple rc will usually do the job (figure 4). the ltc1051/ltc1053 data sheet includes more information about zero-drift amplifier sampling behavior. single supply operation the ltc1250 will operate with single supply voltages as low as 4.5v, and the output swings to within millivolts of either supply when lightly loaded. the input stage will common mode to within 250mv of ground with a single 5v supply, and will common mode to ground with single supplies above 11v. most bridge transducers bias their inputs above ground when powered from single supplies, allowing them to interface directly to the ltc1250 in single supply applica- tions. single-ended, ground-referenced signals will need to be level shifted slightly to interface to the ltc1250s inputs. fault conditions the ltc1250 is designed to withstand most external fault conditions without latch-up or damage. however, unusually severe fault conditions can destroy the part. all pins are protected against faults of 25ma or 5v beyond either supply, whichever comes first. if the external circuitry can exceed these limits, series resistors or voltage clamp diodes should be included to prevent damage. the ltc1250 includes internal protection against esd dam- age. all data sheet parameters are maintained to 1kv esd on any pin; beyond 1kv, the input bias and offset currents will increase, but the remaining specs are unaffected and the part remains functional to 5kv at the input pins and 8kv at the output pin. extreme esd conditions should be guarded against by using standard anti-static precautions. + ltc1250 47k r f c f 0.01 1250 f04 figure 4. rc output pole limits bandwidth to 330hz
8 ltc1250 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7487 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 ? linear technology corporation 1994 u s a o pp l ic at i ty p i ca l reference buffer differential thermocouple ampliifer 0.016 ?0.050
0.406 ?1.270 0.010 ?0.020
(0.254 ?0.508) 45 0 8?typ 0.008 ?0.010
(0.203 ?0.254) so8 0294 0.053 ?0.069
(1.346 ?1.752) 0.014 ?0.019
(0.355 ?0.483) 0.004 ?0.010
(0.101 ?0.254) 0.050
(1.270)
bsc 1 2 3 4 0.150 ?0.157*
(3.810 ?3.988) 8 7 6 5 0.189 ?0.197*
(4.801 ?5.004) 0.228 ?0.244
(5.791 ?6.197) *these dimensions do not include mold flash or protrusions.
mold flash or protrusions shall not exceed 0.006 inch (0.15mm). s8 package 8-lead plastic soic n8 0694 0.045 ?0.015
(1.143 ?0.381) 0.100 ?0.010
(2.540 ?0.254) 0.065
(1.651)
typ 0.045 ?0.065
(1.143 ?1.651) 0.130 ?0.005
(3.302 ?0.127) 0.015
(0.380)
min 0.018 ?0.003
(0.457 ?0.076) 0.125
(3.175)
min
12 3 4 87 6 5 0.255 ?0.015*
(6.477 ?0.381)
0.400*
(10.160)
max 0.009 ?0.015
(0.229 ?0.381) 0.300 ?0.325
(7.620 ?8.255) 0.325 +0.025
0.015 +0.635
0.381 8.255 () *these dimensions do not include mold flash or protrusions.
mold flash or protursions shall not exceed 0.010 inch (0.254mm). j8 0694 0.014 ?0.026
(0.360 ?0.660) 0.200
(5.080)
max 0.015 ?0.060
(0.381 ?1.524) 0.125
3.175
min 0.100 ?0.010
(2.540 ?0.254) 0.300 bsc
(0.762 bsc) 0.008 ?0.018
(0.203 ?0.457) 0??15 0.385 ?0.025
(9.779 ?0.635) 0.005
(0.127)
min 0.405
(10.287)
max 0.220 ?0.310
(5.588 ?7.874) 12 3 4 87 65 0.025
(0.635)
rad typ 0.045 ?0.068
(1.143 ?1.727)
full lead
option 0.023 ?0.045
(0.584 ?1.143)
half lead
option corner leads option
(4 plcs) 0.045 ?0.068
(1.143 ?1.727)
note: lead dimensions apply to solder dip/plate or tin plate leads. j8 package 8-lead ceramic dip n8 package 8-lead plastic dip package descriptio u dimensions in inches (millimeters) unless otherwise noted. + 5v type k ? r4
1m
0.1% c1
100pf 7 6 4 3 2 ?v v out
100mv/? 1250 ta04 ltc1250 r5
3k r6
7.5k
1% r7
500 w
full-scale trim r9
33k ?v c2
100pf + r3
1m
0.1% r8
5k
1% 5v gnd v in v out lt1025 10mv/? r1
10k
0.1% r2
10k
0.1% v cm ? for best accuracy, thermocouple
resistance should be less than 100 w + 15v 7 6 4 3 2 ?0ppm error at ?5ma
1 m v p-p output noise
2.5 m v/? drift (due to lm399) 1250 ta03 ltc1250 7.5k lm399 31 2 4 lt/gp 0894 2k rev a ? printed in usa
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