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| asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 1 - general description the AK4534 targeted at pda and other low - power, small size applications. it features a 16 - bit stereo codec with a built - in microphone - amplifier, headphone - amplifier and speaker - amplifier. input circuits includ e a microphone - amplifier and an alc (auto level control) circuit. the AK4534 is available in a 52 - qfn, utilizing less board space than competitive offerings. features 1. resolution : 16bits 2. recording function 1ch mon o input 1 st mic amplifier : +20db or 0db 2 nd amplifier with alc : +27.5db ~ - 8db, 0.5db step adc performance : s/(n+d) : 79db, dr, s/n : 83db 3. playback function digital de - emphasis filter (tc=50/15 m s, fs=32khz, 44.1khz, 48khz) digital volume (0db ~ - 127db, 0.5db step, mute) headphone - amp - s/(n+d) : 70db, s/n : 90db - output power : 15mw@16 w (hvdd=3.3v) mono speaker - amp with alc - s/(n+d) : 64db@250mw, 20db@300mw, s/n : 90db - btl output - output power : 300mw@8 w (thd=10%, hvdd=3.3v) mo no and stereo beep inputs mono line output 4. power management 5. master clock (1) pll mode frequencies : 11.2896mhz, 12mhz and 12.288mhz input level : cmos (2) external clock mode frequencies : 2.048mhz ~ 12.288mhz 6. output master clock frequencies : 32fs/64fs/12 8fs/256fs 7. sampling rate (1) pll mode 8khz, 11.025khz, 16khz, 22.05khz, 24khz, 32khz, 44.1khz, 48khz (2) external clock mode 8khz ~ 48khz 8. control mode: 4 - wire serial / i 2 c bus 9. master/slave mode 10. audio interface format : msb first, 2?s compliment adc : i 2 s, 16bit msb justified dac : i 2 s, 16bit msb justified, 16bit lsb justified 11. ta = - 10 ~ 70 c 16bit d s codec with mic/hp/spk - amp AK4534
asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 2 - 12. power supply: 2.4v ~ 3.6v (typ. 3.3v) 13. power supply current avdd+dvdd : 16ma pvdd : 1.2ma hvdd (hp - amp=on, spk - amp=off) : 6.5ma hvdd (hp - amp=off, spk - amp=on) : 9ma 14. package : 52pin qfn n block diagram alc1 (ipga) pmmic avdd avss micout ain lrck bick sdto sdti pdn dsp and up dvdd dvss hvdd hvss vcom mutet alc2 mout- hpl pmhpl hp-amp hpr pmhpr hp-amp control register interface audio pmspk spk- amp spp spn i2c csn/cad1 cclk/scl cdti/sda cdto pmmo cad0 mout+ xti/mcki xto mcko vcoc pvdd pvss mix mix mix mpe mic power supply ext int mic-amp 0db or 20db mpi mic power supply m/s hpf adc pmadc pmdac datt smute dac min mout2 mix pll pmpll pmxtl mix beepl beepr pmbps beepm pmbpm block diagram asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 3 - n ordering guide AK4534vn - 10 ~ +70 c 52pin qfn (0.4mm pitch) akd4534 evaluation board for AK4534 n pin layout micout nc 52 51 1 50 49 48 47 46 45 44 43 42 39 38 37 36 35 34 33 32 31 30 29 24 23 22 21 20 19 18 17 16 15 14 2 3 4 5 6 7 8 9 10 11 AK4534vn top view tst1 ext mpe mpi int vcom avss avdd pvdd pvss cclk/scl dvdd dvss xto xti/mcki m/s spp spn hvdd hvss hpr hpl beepl beepr beepm tst5 tst4 mout+ mout- tst3 mout2 12 vcoc 25 28 nc 41 min csn/cad1 pdn cdti/sda cdto i2c sdti sdto lrck bick mcko nc 13 26 27 40 nc tst2 ain cad0 mutet asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 4 - pin/function no. pin name i/o function 1 micout o microphone analog output pin 2 tst1 - test pin. this pin should be open. 3 ext i external microphone input pin ( mon o input) 4 mpe o mic power supply pin for external microphone 5 mpi o mic power supply pin for internal microphone 6 int i internal microphone input pin ( mon o input) 7 vcom o common voltage output pin, 0.45 x avdd bias voltage of adc inputs and dac outputs. 8 avss - analog ground pin 9 avdd - analog power sup ply pin 10 pvdd - pll power supply pin 11 pvss - pll ground pin 12 vcoc o output pin for loop filter of pll circuit this pin should be connected to pvss with one resistor and capacitor in series. 13 nc - no connect. no internal bonding. 14 cad0 i chip address 0 select pin 15 pdn i power - down mode pin ? h ? : power up, ? l ? : power down reset and initializes the control register. csn i chip select pin (i2c = ? l ? ) 16 cad1 i chip address 1 select pin (i2c = ? h ? ) cclk i control data clock pin ( i2c = ? l ? ) 17 scl i control data clock pin (i2c = ? h ? ) cdti i control data input pin (i2c = ? l ? ) 18 sda i/o control data input pin (i2c = ? h ? ) 19 cdto o control data output pin (i2c = ? l ? ) 20 i2c i control mode select pin ? h ? : i 2 c bus, ? l ? : 4 - wire serial 21 sdti i audio serial data input pin 22 sdto o audio serial data output pin 23 lrck i /o input / output channel clock pin 24 bick i/o audio serial data clock pin 25 mcko o master clock output pin 26 nc - no connect. no internal bonding. asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 5 - 27 nc - no connect. no internal bonding. 28 dvdd - digital power supply pin 29 dvss - digital ground pin 30 xto o x ? tal output pin xti i x ? tal input pin 31 mcki i external master clock input pin 32 m/s i master / slave mode pin ? h ? : master mod e, ? l ? : slave mode 33 spp o speaker amp positive output pin 34 spn o speaker amp negative output pin 35 hvdd - headphone amp power supply pin 36 hvss - headphone amp ground pin 37 hpr o rch headphone amp output pin 38 hpl o lch headphone amp output pin 39 mutet o mute time constant control pin connected to hvss pin with a capacitor for mute time constant. 40 min i alc input pin 41 mout2 o analog mixing output pin 42 tst2 - test pin. this pin should be open. 43 tst3 - test pin. this pin shoul d be open. 44 mout - o mono line negative output pin 45 mout+ o mono line positive output pin 46 tst4 - test pin. this pin should be open. 47 tst5 - test pin. this pin should be open. 48 beepm i mono beep signal input pin 49 beepr i rch stereo beep si gnal input pin 50 beepl i lch stereo beep signal input pin 51 ain i analog input pin 52 nc - no connect. no internal bonding. note: all input pins except analog input pins (int, ext, ain, min, beepm, beepl, and beepr ) should not be left floating. asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 6 - a bsolute maximum ratings (avss , dvss, pvss, hvss= 0v ; note 1) parameter symbol min max units power supplies: analog digital pll headphone - amp / speaker - amp |avss ? pvss| (note 2) |avss ? dvss| (note 2) |avss ? hvss| (note 2) avdd dv dd pvdd hvdd d gnd1 d gnd2 d gnd3 - 0.3 - 0.3 - 0.3 - 0.3 - - - 4.6 4.6 4.6 4.6 0.3 0.3 0.3 v v v v v v v input current, any pin except supplies iin - 10 ma analog input voltage vina - 0.3 avdd+0.3 v digital input voltage vind - 0.3 dvdd+0.3 v ambient temperat ure (powered applied) ta - 10 70 c storage temperature tstg - 65 150 c note 1 . all voltages with respect to ground . note 2. avss, dvss, pvss and hvss must be connected to the same analog ground plane . warning : operation at or beyond these limits may r esult in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions ( avss, dvss, pvss , hvss =0v ; note 1) parameter symbol min typ max units power supplies (note 3) analog digital pll hp / spk - amp avdd dvdd pvdd hvdd 2.4 2.4 2.4 2.4 3.3 3.3 3.3 3.3 3.6 avdd avdd avdd v v v v note 1. all voltages with respect to ground. note 3. the power up sequence between avdd, dvdd, hvdd and pvdd is not critical. it is recommen ded that dvdd and pvdd are the same voltage as avdd in order to reduce the current at power down mode. * akm assumes no responsibility for the usage beyond the conditions in this datasheet. asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 7 - analog characteristics ( ta=25 c ; avdd=dvdd=pvdd=hvdd = 3.3v ; a vss=dvss=pvss=hvss=0v; fs=4 4.1k hz , bick=64fs; signal frequency =1khz ; 16bit data; measurement frequency=20hz ~ 20khz; unless otherwise specified) parameter min typ max units mic amplifier input resistance 20 30 40 k w gain (m gain bit = ? 0 ? ) (mgain bit = ? 1 ? ) - - 0 20 - - db db mic power supply output voltage (note 4) 2.22 2.47 2.72 v output current - - 1.25 ma input pga characteristics: input resistance (note 5) 5 10 15 k w step size 0.1 0.5 0.9 db gain control range - 8 +27.5 db adc analog input characteristics: mic gain=20db, ipga=0db, alc1=off, mic ? ipga ? adc resolution 16 bits input voltage (mic gain=20db, note 6) 0.168 0.198 0.228 vpp s/(n+d) ( - 1dbfs) 71 79 db d - range ( - 60dbfs, a - weighted) 75 83 db s/n (a - weighted) 75 83 db dac characteristics: resolution 16 bits mono line output characteristics: r l =20k w , dac ? mout+/mout - output voltage (note 7) 3. 56 3.96 4.36 vpp s/(n+d) ( - 3dbfs) 79 89 dbfs s/n (a - weighted) 85 95 db load resistance 20 k w load capacitance 30 pf headphone - amp characteristics: r l =22.8 w , dac ? hpl/hpr, datt=0db output voltage (note 8) 1 .54 1.92 2.30 vpp s/(n+d) ( - 3dbfs) 60 70 db s/n (a - weighted) 80 90 db interchannel isolation 70 85 db interchannel gain mismatch 0.1 0.5 db load resistance 20 w load capacitance (c1 of figure 1) (c2 of figure 1) 30 300 pf pf speaker - amp characteristics: r l =8 w , btl, dac ? mout2 ? min ? spp/spn, alc2=off output voltage (note 9) 2.37 2.96 3.55 vpp s/(n+d) 50 64 db s/n (a - wei ghted) 82 90 db load resistance 8 w load capacitance 30 pf beep input: beepl, beepr, beepm pin maximum input voltage (note 10) 1.98 vpp feedback resistance 14 20 26 k w mon o input: min pin maximum input voltage (note 11) 1.98 vpp input resistance (note 12) 12 24 36 k w asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 8 - parameter min typ max units mon o output: r l =10k w , dac ? mix ? mout2 output voltage (note 13) 1.94 vpp load resistance 10 k w load capacitance (note 14) 30 pf power supplie s power up (pdn = ? h ? ) avdd+dvdd (note 15) 16 26 ma pvdd 1.2 2 ma hvdd: hp - amp normal operation no output (note 16) 6.5 10 ma hvdd: spk - amp normal operation no output (note 17) 9 18 ma power down (pdn = ? l ? ) (note 18) avdd+dvdd 10 100 m a pvdd 10 100 m a hvdd 10 100 m a note 4. output voltage is proportional to avdd voltage. vout = 0.75 x avdd. note 5. when ipga gain is changed, this typical value changes between 8k w and 11k w . note 6. input voltage is proportional to avdd voltage. vin = 0.06 x avdd. note 7. output voltage is proportional to avdd voltage. vout = 1.2 x avdd at full - differential output. vout = 0.6 x avdd at single - end output note 8. output voltage is pr oportional to avdd voltage. vout = 0.582 x avdd. note 9. output voltage is proportional to a vdd voltage. vout = 0.897 x avdd at full - differential output. note 10. beep - amp can ? t output more than this maximum voltage. note 11. maximum input voltage is propo rtional to avdd voltage. vin = 0.6 x avdd. note 12. when alc2 gain is changed, this typical value changes between 22k w and 26k w . note 13. output voltage is proportional to avdd voltage. vout = 0.588 x avdd. note 14. when the output pin drives a capacitive load, a resistor should be added in series between the output pin and capacitive load. note 15. pmmic=pmadc=pmdac=pmmo=pmspk=pmhpl=pmhpr=pmvcm=pmpll=pmxtl=pmbpm =pmbps= ? 1 ? ,mcko= ? 1 ? and master mode. avdd : 10ma (typ.), dvdd : 6ma (typ.) avdd : 10ma (typ.), dvdd : 4ma (typ.) at mcko= ? 0 ? in slave mode note 16. pmmic=pmadc=pmdac=pmmo=pmhpl=pmhpr=pmvcm=pmpll=pmxtl=pmbpm =pmbps= ? 1 ? , pmspk= ? 0 ? . note 17. pmmic=pmadc=pmdac=pmmo=pmspk=pmvcm=pmpll=pmxtl=pmbpm=pmbps= ? 1 ? pmhpl=pmhpr= ? 0 ? . note 18. all digital input pins are fixed to dvdd or dvss. hpl/hpr pin hp-amp 47 m f c1 16 w c2 > 6.8 w figure 1. headphone - amp output circuit asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 9 - filter characteristics ( ta= - 10 ~ 70 c ; a vdd , d vdd, pvdd, hvdd = 2.4 ~ 3.6v; fs=4 4.1k hz ; dem=off) parameter symbol m in typ max units adc digital filter (decimation lpf): passband ( note 19) 0.1db - 1.0db - 3.0db pb 0 - - 20.0 21.1 17.4 - - khz khz khz stopband sb 27.0 khz passband ripple pr 0.1 db stopband attenuation sa 65 db group del ay ( note 20 ) gd 17.0 1/fs group delay distortion d gd 0 m s adc digital filter (hpf) : frequency response ( note 19 ) - 3.0db - 0.5db - 0.1db fr 3.4 10 22 hz hz hz dac digital filter : passband ( note 19) 0.1db - 6.0db pb 0 - 22.05 20.0 - khz khz stopband sb 24.1 khz passband ripple pr 0.06 db stopband attenuation sa 43 db group delay ( note 20 ) gd 16.8 1/fs dac digital filter + scf: frequency response: 0 ~ 20.0khz fr 0.5 db boost filter: (note 21) min 20hz 100hz 1khz fr - - - 5.74 2.92 0.0 - - - db db db mid 20hz 100hz 1khz fr - - - 5.94 4.71 0.14 - - - db db db frequency response max 20hz 100hz 1khz fr - - - 16.04 10.55 0. 3 - - - db db db note 19. the passband and stopband frequencies scale with fs ( system sampling rate ) . for example, adc is pb=0.454*fs ( @-1.0db ) , dac is pb=0.454*fs ( @-0. 0 1db ) . note 20. the calculat ed delay time caused by digital filtering. this time is from the input of analog signal to setting of the 16 - bit data of both channels from the input register to the output register of the adc. this time includes the group delay of the hpf . for the dac, this time is from setting the 16 - bit data of both channel s from the input register to the output of analog signal. note 21. these frequency response s scale with fs . if a high - level and low frequency signal is input, the analog output clips to the full - scale. asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 10 - dc characteristics ( ta= - 10 ~ 70 c ; avdd , dv d d, pvd d, hvdd=2.4 ~ 3.6 v ) parameter symbol min typ max units high - level input voltage low - level input voltage input voltage at ac coupling (note 22) vih vil vac 70%dvdd - 50%dvdd - - - - 30%dvdd - v v v high - level output voltage ( iout= - 200 m a) low - level output voltage (except sda pin: iout=200 m a) ( sda pin: iout= 3ma) voh vol vol dvdd - 0.2 - - - - - - 0.2 0.4 v v v input leakage current iin - - 10 m a note 22. when ac coupled capacitor is connected to mcki pin. switching characteristics ( ta= - 10 ~ 70 c ; avdd, dvdd, pvdd, hvdd = 2.4 ~ 3.6 v ; c l =2 0pf ) parameter symbol min t yp max units master clock timing crystal resonator frequency 11.2896 - 12.288 mhz external clock frequency pul se width low pulse width high ac pulse width (note23) fclk tclkl tclkh tacw 2.048 0.4/fclk 0.4/fclk 0.4/fclk - 12.288 mhz ns ns ns mcko output frequency duty cycle : except fs=32khz fs=32khz at 256fs (note 24) fmck dmck dmck 0.256 40 50 33 12.288 60 mhz % % lrck frequency frequency fs 8 48 khz duty cycle slave mode master mode duty duty 45 50 55 % % audio interface timing slave mode bick period bick pulse width low pulse width high lrck edge to bick ? - ? (note 25) bick ? - ? to lrck edge (note 25) lrck to sdto ( msb ) ( except i 2 s mode ) bick ? ? to sdto sdti hold time sdti setup time tbck tbckl tbckh tlrb tblr tlrs tbsd tsdh tsds 312.5 130 130 50 50 50 50 80 80 ns ns ns ns ns ns ns ns ns master mode bick frequency bick duty bick ? ? to lrck bick ? ? to sdto sdti hold time sdti setup time fbck dbck tmblr tbsd tsdh tsds - 80 - 80 50 50 64fs 50 80 80 hz % ns ns ns ns note 23. pulse width to ground level when mcki is connected to a capacitor in series and a resistor is connected to ground. (refer to figure 2) note 24. pmpll bit = ? 1 ? . note 25. bick rising edge must not occur at the same time as lrck edge. asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 11 - parameter symbol min t yp max units control interface timing (4 - wire serial mode): cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ? h ? time csn ? ? to cclk ? - ? cclk ? - ? to csn ? - ? cdto delay csn ? - ? to cdto hi - z tcck tc ckl tcckh tcds tcdh tcsw tcss tcsh tdcd tccz 200 80 80 40 40 150 50 50 50 70 ns ns ns ns ns ns ns ns ns ns control interface timing (i 2 c bus mode): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling (note 26) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp - 4.7 4.0 4.7 4.0 4.7 0 0.25 - - 4.0 0 100 - - - - - - - 1.0 0.3 - 50 khz m s m s m s m s m s m s m s m s m s m s ns reset timing pdn pulse width (note 27) pmadc ? - ? to sdto valid (note 28) tpd tpdv 150 2081 ns 1/fs note 26. data must be held long enou gh to bridge the 300ns - transition time of scl. note 27. the AK4534 can be reset by the p dn pin = ? l ? . note 28. this is the count of lrck ? - ? from the pmadc bit = ? 1 ? . purchase of asahi kasei microsystems co., ltd i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system, provided the system conform to the i 2 c specifications defined by philips. asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 12 - n timing diagram 1/fclk mclk tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil mcko dmck dmck 50%dvdd fmck clock timing mcki input measurement point agnd tacw t acw agnd 1/fclk 1000pf 100k w vac figure 2. mcki ac coupl ing timing asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 13 - lrck vih vil tblr bick vih vil tlrs sdto 50%dvdd tlrb tbsd tsds sdti vil tsdh vih audio interface timing (slave mode) lrck vih vil bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih tmblr dbck audio interface timing (master mode) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 14 - csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w cdto hi-z write/read command input timing csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 cdto hi-z d2 write data input timing asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 15 - csn vih vil cclk vih vil cdti vih vil a0 cdto a1 50%dvdd tdcd d7 d6 hi-z read data output timing 1 csn vih vil tcsh cclk vih vil cdti vih tcsw vil cdto 50%dvdd d2 d1 d0 tccz hi-z read data output timing 2 asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 16 - stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih vil thd:sta tsu:sta vih vil tsu:sto tsp i 2 c bus mode timing csn vih vil tpdv sdto tpd 50%dvdd pdn vil power down & reset timing asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 17 - operation overview n master clock source the AK4534 requires a master clock (mclk). this master clock is input to the AK4534 by connecting a x ? tal oscillator to xti and xto pins or by inputting an external cmos - level clock to the xti pin or by inputting an extern al clock that is greater than 50% of the dvdd level to the xti pin through a capacitor. when using a x ? tal oscillator , there should be capacitors between xti/xto pins and dvss. when using an external clock, there are two choices: direct, where an external clock is input directly to the xti pin and indirect, where the external clock is input through a capacitor. master clock status pmxtl bit mckpd bit x ? tal oscillator (figure 3) oscillator on 1 0 oscillator off 0 1 external cloc k direct input (figure 4) clock is input to mcki pin. 0 0 mcki pin is fixed to ? l ? . 0 0/1 mcki pin is fixed to ? h ? . 0 0 mcki pin is hi - z 0 1 ac coupling input (figure 5) clock is input to mcki pin. 1 0 clock isn?t input to mcki pin. 0 1 table 1. master clock status by pmxtl bit and mckpd bit (1) x ? tal oscillator xti xto AK4534 25k w mckpd = "0" pmxtl = "1" c c figure 3. x ? tal mode - note: the capacitor values depend on the x ? tal oscillator used. (c : typ. 10 ~ 30pf) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 18 - (2) external clock direct input xti xto AK4534 25k w mckpd = "0" pmxtl = "0" external clock figure 4. external clock mode (input : cmos level) - note: this clock level must not exceed dvdd level. (3) ac coupling input xti xto AK4534 25k w mckpd = "0" pmxtl = "1" external clock c figure 5. external clock mode (input : 3 50%dvdd) - note: this clock leve l must n o t exceed dvdd level. (c : 0.1 m f) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 19 - n system clock (1) pll mode (pmpll bit = ? 1 ? ) a fully integrated analog phase locked loop (pll) generates a clock that is selected by the pll1 - 0 and fs2 - 0 bits (see table.2 and table.3). the frequency of the mcko output is selectable via the ps1 - 0 bits registers as defined in table.4 and the mcko output enable is controlled by the mcko bit . if ps1 - 0 bits are changed before lrck is input, mcko is not output. ps1 - 0 bits should be changed after lrck is input in slave mode. the pll should be powered - up after the x ? tal oscillator becomes stable or external master clock is inputted. if x'tal and pll are powered - up at the same time or pll is powered - up before external master clock is inputted, the pll does not start. it takes x ? tal oscillator 20ms(typ) to be stable after pmxtl bit= ? 1 ? . the pll needs 40ms lock time, whenever the sampling frequency changes or the pll is powered - up (pmpll bit= ? 0 ? ? ? 1 ? ). if the sampling frequency is changed and the pll goes to unlock state when the dac is operated(pmdac bit= ? 1 ? ), the dac data should be soft - muted or ? 0 ? . in case of the adc(pmadc bit = ? 1 ? ), the adc data acquired during the frequency change may be erroneous and therefore should n o t be used. lrck and bick are output from the AK4534 in master mode. when the clock input to mcki pin stops during normal operation (pmpll bit = ? 1 ? ), the internal pll continues to oscillate (a few mhz), and lrck and bick outputs go to ? l ? (see table 5). in slave mode, the lrck input should be synchr onized with mcko. the master clock (mcki) should be synchronized with sampling clock (lrck). the phase between these clocks does not matter. lrck and bick must be present whenever the AK4534 is operating (pmadc bit = ? 1 ? or pmdac bit = ? 1 ? ). if these clock s are not provided, the AK4534 may draw excess current due to its use of internal dynamically refreshed logic. if the external clocks are not present, place the AK4534 in power - down mode (pmadc bit = pmdac bit = ? 0 ? ). mode pll1 pll0 mcki 0 0 0 12.288mhz default 1 0 1 11.2896mhz 2 1 0 12mhz 3 1 1 n/a table 2. mcki input frequency (pll mode) fs2 fs1 fs0 sampling frequency 0 0 0 44.1khz default 0 0 1 22.05khz 0 1 0 11.025khz 0 1 1 48khz 1 0 0 32khz 1 0 1 24khz 1 1 0 16khz 1 1 1 8khz table 3. sampling frequency (pll mode) mode ps1 ps0 mcko 0 0 0 256fs default 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 4. mcko frequency (pll mode, mcko bit = ? 1 ? ) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 20 - master mode (m/s pin = ? h ? ) power up power down pll unlock mcki pin frequen cy set by pll1 - 0 bits (refer to table 2) r efer to table 1 frequency set by pll1 - 0 bits (refer to table 2) mcko pin mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : output ? l ? mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : unsettling bick pin bf bit = ? 0 ? : 64fs output bf bi t = ? 1 ? : 32fs output ? l ? ? l ? lrck pin output ? l ? ? l ? table 5. clock operation at master mode (pll mode) slave mode (m/s pin = ? l ? ) power up power down pll unlock mcki pin frequency set by pll1 - 0 bits (refer to table 2) r efer to table 1 frequency se t by pll1 - 0 bits (refer to table 2) mcko pin mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : output ? l ? mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : unsettling bick pin input fixed to ? l ? or ? h ? externally input lrck pin input fixed to ? l ? or ? h ? externally input table 6. clock operation at slave mode (pll mode) (2) external mode (pmpll bit = ? 0 ? ) when the pmpll bit = ? 0 ? , the AK4534 works in external clock mode. the mcko pin outputs a buffered clock of mcki input. for example, when mcki = 256fs, the sampling frequency i s changeable from 8khz to 48khz (table 7). the mcko bit controls mcko output enable . the frequency of mcko is selectable via register the ps1 - 0 bits as defined in table.8. if ps1 - 0 bits are changed before lrck is input, mcko is not output. ps1 - 0 bits shoul d be changed after lrck is input in slave mode. the master clock frequency should be changed only when both the pmadc and pmdac bits = ? 0 ? . lrck and bick are output from the AK4534 in master mode. the clock to the mcki pin must n o t stop during normal oper ation (pmpll bit = ? 1 ? ). if this clock is not provided, the AK4534 may draw excess current due to its use of internal dynamically refreshed logic. if the external clocks are not present, place the AK4534 in power - down mode (pmadc bit = pmdac bit = ? 0 ? ). m cki, bick and lrck clocks are required in slave mode. the master clock (mcki) should be synchronized with sampling clock (lrck). the phase between these clocks does not matter. lrck and bick should always be present whenever the AK4534 is in normal operati on (pmadc bit = ? 1 ? or pmdac bit = ? 1 ? ). if these clocks are not provided, the AK4534 may draw excess current due to its use of internal dynamically refreshed logic. if the external clocks are not present, place the AK4534 in power - down mode (pmadc bit = p mdac bit = ? 0 ? ). mode fs1 fs0 sampling frequency (fs) mcki 0 0 0 8khz ~ 48khz 256fs default 1 0 1 8khz ~ 24khz 512fs 2 1 0 8khz ~ 12khz 1024fs 3 1 1 8khz ~ 48khz 256fs table 7. sampling frequency select (ext mode) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 21 - mode ps1 ps0 mcko 0 0 0 256fs default 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 8. mcko frequency (ext mode, mcko bit = ? 1 ? ) master mode (m/s pin = ? h ? ) power up power down mcko pin mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : output ? l ? bick pin bf bit = ? 0 ? : 64fs output bf bit = ? 1 ? : 32fs output ? l ? lrck pin output ? l ? table 9. clock operation at master mode (ext mode) slave mode (m/s pin = ? l ? ) power up power down mcko pin mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : output ? l ? bick pin input fixed to ? l ? or ? h ? external ly lrck pin input fixed to ? l ? or ? h ? externally table 10. clock operation at slave mode (ext mode) the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to o ut - of - band noise. when the out - of - band noise can be imp roved by using higher frequency of the master clock. the s/n of the dac output through headphone amp at fs=8khz is shown in table 11. mclk s/n (fs=8khz, a - weighted) 256fs 84db 512fs 88db 1024fs 88db table 11. relationship between mclk and s/n of hp - am p n master mode/slave mode the m/s pin selects either master or slave modes. m/s pin = ? h ? selects master mode and ? l ? selects slave mode. the AK4534 outputs mcko, bick and lrck in master mode. the AK4534 outputs only mcko in slave mode, while bick and lrck must be input separately. mcko bick / lrck slave mode mcko = output bick = input lrck = input master mode mcko = output bick = output lrck = output table 12. master mode/slave mode asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 22 - n system reset upon power - up, reset the ak45 34 by bringing t he pdn pin = ?l?. this ensures that all internal registers reset to their initial value s . the adc enters an initializ ation cycle that starts when the pmadc bit is changed from ? 0 ? to ? 1 ? . the initializ ation cycle time is 2081/fs, or 47.2ms@fs=44.1khz . dur ing the initializ ation cycle, the adc digital data outputs of both channels are forced to a 2's compliment, ?0?. the adc output reflects the analog input signal after the initializ ation cycle is complete . the dac does n o t require an initializ ation cycl e. n audio interface format three types of data formats are available and are selected by setting the dif1 - 0 bits. in all modes, the serial data is msb first, 2 ? s complement format. the sdto is clocked out on the falling edge of bick and th e sdti is latched on the rising edge. all data formats can be used in both master and slave modes. lrck and bick are output from AK4534 in master mode, but must be input to AK4534 in slave mode. if 16 - bit data that adc outputs is converted to 8 - bit data by removing lsb 8 - bit, - 1 at 16bit data is converted to - 1 at 8 - bit data. and when the dac playbacks this 8 - bit data, - 1 at 8 - bit data will be converted to - 256 at 16 - bit data and this is a large offset. this offset can be removed by adding the offset of 128 to 16 - bit data before converting to 8 - bit data. mode dif1 dif0 sdto (adc) sdti (dac) bick figure 0 0 0 msb justified lsb justified 3 32fs figure 6 1 0 1 msb justified msb justified 3 32fs figure 7 2 1 0 i 2 s i 2 s 3 32fs figure 8 default 3 1 1 n/a n/ a n/a - table 13. audio interface format lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 1 10 13 13 2 3 7 7 6 5 4 3 2 1 0 6 5 4 3 1 0 2 9 11 12 13 14 15 0 1 2 3 15 14 13 1 0 15 15 7 6 5 4 3 2 1 0 10 9 11 12 13 14 15 bick(64fs) 0 1 16 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 13 don't care 1 0 1 15 15 2 1 0 15 0 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data figure 6. mode 0 timing asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 23 - lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 1 10 13 13 2 3 7 7 6 5 4 3 2 1 0 6 5 4 3 1 0 2 9 11 12 13 14 15 0 1 2 3 15 14 13 1 0 15 15 7 6 5 4 3 2 1 0 10 9 11 12 13 14 15 bick(64fs) 0 1 16 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 13 don't care 1 15 15 15 0 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data 13 1 0 13 1 0 15 figure 7. mode 1 timing lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 1 10 2 3 7 7 6 5 4 3 2 1 0 6 5 4 3 1 0 2 9 11 12 13 14 15 0 1 2 3 15 14 1 0 7 6 5 4 3 2 1 0 10 9 11 12 13 14 15 bick(64fs) 0 1 16 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 don't care 2 15 1 15 15 15 don't care 15:msb, 0:lsb lch data rch data 14 2 1 14 2 1 8 8 8 0 0 0 0 figure 8. mode 2 timing n digital high pass filter the adc has a d igital high pass filter for dc offset cancellation. the cut - off frequency of the hpf is 3.4hz (@fs=44.1khz) and scales with sampling rate (fs). asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 24 - n mic gain amplifier AK4534 has a gain amplifier for microphone input. this gain is 0db or 20db, selected by the mgain bit. the typical input impedance is 30k w . mgain bit input gain 0 0db 1 +20db default table 14. input gain n mic power the mpi and mpe pins supply power for the microphone. these output voltages are 0.75 x avdd (typ) and the maximum o utput current is 1.25ma. asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 25 - n manual mode the AK4534 becomes a manual mode at alc1 bit = ? 0 ? . this mode is used in the case shown below. 1. after exiting reset state, set up the registers for the alc1 operation (ztm1 - 0, lmth and etc) 2. when the register s for the alc1 operation (limiter period, recovery period and etc) are changed. for example ; when the change of the sampling frequency . 3. when ipga is used as a manual volume. when writing to the ipga6 - 0 bits continually , the control register should be written by an interval more than zero crossing timeout. n mic - alc operation the alc (automatic level control) of mic input is done by alc1 block when alc1 bit is ? 1 ? . [1] alc1 limiter operation when the alc1 limiter is enabled, and ipga output exceeds the alc1 limiter detection level (lmth), the ipga value is attenuated by the amount defined in the alc1 limiter att step (lmat1 - 0 bits) automatically. when the zelm bit = ? 1 ? , the timeout period is set by the ltm1 - 0 bits. the operation for attenuation is don e continuously until the input signal level becomes lmth or less. if the alc1 bit does not change into ? 0 ? after completing the attenuation, the attenuation operation repeats while the input signal level equals or exceeds lmth. when the zelm bit = ? 0 ? , th e timeout period is set by the ztm1 - 0 bits. this enables the zero - crossing attenuation function so that the ipga value is attenuated at the zero - detect points of the waveform. [2] alc1 recovery operation the alc1 recovery refers to the amount of time that th e AK4534 will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. the alc1 recovery operation uses the wtm1 - 0 bits to define the wait period used after completing an alc1 limiter operation. if the input signal d oes not exceed the ? alc1 recovery waiting counter reset level ? , the alc1 recovery operation starts. the ipga value increases automatically during this operation up to the reference level (ref6 - 0 bits). the alc1 recovery operation is done at a period set by the wtm1 - 0 bits. zero crossing is detected during wtm1 - 0 period, the alc1 recovery operation waits wtm1 - 0 period and the next recovery operation starts. during the alc1 recovery operation, when input signal level exceeds the alc1 limiter detection level (lmth), the alc1 recovery operation changes immediately into an alc1 limiter operation. in the case of ? (recovery waiting counter reset level) ipga output level < limiter detection level ? during the alc1 recovery operation, the wait timer for the alc1 re covery operation is reset. therefore, in the case of ?( recovery waiting counter reset level ) > i pga out put level ? , the wait timer for the alc1 recovery operation starts. the alc1 operation corresponds to the impulse noise. when the impulse noise is input, the alc1 recovery operation becomes faster than a normal recovery operation. asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 26 - [3] example of alc1 operation table 15 shows the examples of the alc1 setting. in case of this examples, alc1 operation starts from 0db. fs=8khz fs=16khz f s=44.1khz register name comment data operation data operation data operation lmth limiter detection level 1 - 4dbfs 1 - 4dbfs 1 - 4dbfs ltm1 - 0 limiter operation period at zelm = 1 00 don ? t use 00 don ? t use 00 don ? t use zelm limiter zero crossing detection 0 enable 0 enable 0 enable ztm1 - 0 zero crossing timeout period 00 16ms 01 16ms 10 11.6ms wtm1 - 0 recovery waiting period *wtm1 - 0 bits should be the same data as ztm1 - 0 bits 00 16ms 01 16ms 10 11.6ms ref6 - 0 maximum gain at recovery operation 47h +27.5db 47h +27.5db 47h +27. 5db ipga6 - 0 gain of ipga at alc1 operation start 10h 0db 10h 0db 10h 0db lmat1 - 0 limiter att step 00 1 step 00 1 step 00 1 step ratt recovery gain step 0 1 step 0 1 step 0 1 step alc1 alc1 enable bit 1 enable 1 enable 1 enable table 15. example of the alc1 setting the following registers should not be changed during the alc1 operation. these bits should be changed, after the alc1 operation is finished by alc1 bit = ? 0 ? or pmmic bit = ? 0 ? . ltm1 - 0, lmth, lmat1 - 0, wtm1 - 0, ztm1 - 0, ratt, ref6 - 0, zelm bi ts ipga gain at alc1 operation start can be changed from the default value of ipga6 - 0 bits while pmmic bit is ? 1 ? and alc1 bit is ? 0 ? . when alc1 bit is changed from ? 1 ? to ? 0 ? , ipga holds the last gain value set by alc1 operation. manual mode * the value of ipga should be t he same or smaller than ref ? s wr (ztm1 - 0, wtm1 - 0, ltm1 - 0) wr (ref6 - 0) wr (ipga6 - 0) alc1 operation wr (alc1= ? 1 ? , lmat1 - 0, ratt, lmth, zelm) example: limiter = zero crossing enable recovery cycle = 16ms @ fs= 8khz limiter and recovery step = 1 maximum gain = +27.5db limiter detection level = - 4dbfs alc2 bit = ? 1 ? ( default ) (1) addr=08h, data=00h (2) addr=0ah, data=47h (4) addr=09h, data=61h (3) addr=0bh, data=10h note : wr : write figure 9. registers set - up sequence at alc1 operation asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 27 - n de - emphasis filter the AK4534 includes the digital de - emphasis filter (tc = 50/15 m s) by iir filter. s etting the dem1 - 0 bits enables the de - emphasis filter. dem1 dem0 mode 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 16. de - emphasis control n bass boost function the bst1 - 0 bits control the amount of low frequency boost applied to the dac output signal. if the bst1 - 0 bits are set to ? 10 ? (mid level), use a 47 m f capacitor for ac - coupling. if the boosted signal exceeds full scale, the analog output clips to the full scale. figure 10 shows the boost frequency response at ? 20db signal input. figure 10. boost frequency (fs=44.1khz) bst1 bst0 mode 0 0 off de fault 0 1 min 1 0 mid 1 1 max table 17. low frequency boost control boost frequency (fs=44.1khz) -25 -20 -15 -10 -5 0 0.01 0.1 1 10 frequency [khz] output level [db] min mid max asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 28 - n digital attenuator the AK4534 has a channel - independent digital attenuator (256 levels, 0.5db step, mute). the attenuation level of each channel can be set by the attl/r7 - 0 bits (table 18). when the dattc bit = ? 1 ? , the attl7 - 0 bits control both lch and rch attenuation levels. when the dattc bit = ? 0 ? , the attl7 - 0 bits control lch level and attr7 - 0 bits control rch level. this attenuator has a soft transition function. it tak es 1061/fs from 00h to ffh. attl/r7 - 0 attenuation 00h 0db default 01h - 0.5db 02h - 1.0db 03h - 1.5db : : : : fdh - 126.5db feh - 127.0db ffh mute ( - ) table 18. datt code table n soft mute soft mute operation is performed in the digital domain. when the smute bit goes to a ? 1 ? , the output signal is attenuated by - ( ? 0 ? ) during the cycle set by the tm1 - 0 bits. when the smute bit is returned to ? 0 ? , the mute is cancelled and the output attenuation gradually changes to 0db during the cycle set of the tm1 - 0 bits. if the soft mute is cancelled within the cycle set by the tm1 - 0 bits after starting the operation, the attenuation is discontinued and returned to 0db. the soft mute is effective for changing the signal source without stopping the si gnal transmission. the soft mute function is independent of output volume and cascade connected between both functions. smute bit attenuation tm1 - 0 bit 0db - tm1 - 0 bit gd gd (1) (2) (3) analog output figure 11. soft mute function note: (1) the output signal is attenuated until - ( ? 0 ? ) by the cycle se t by the tm1 - 0 bits. (2) analog output corresponding to digital input has the group delay (gd). (3) if the soft mute is cancelled within the cycle of setting the tm1 - 0 bits, the attenuation is discounted and returned to 0db(the set value). asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 29 - n beep input when the pmbps bit is set to ? 1 ? , the stereo beep input is powered up. and when the bpshp bit is set to ? 1 ? , the input signals from the beepl and beepr pins are mixed to headphone outputs. when the bpssp bit is set to ? 1 ? , the signal of (beepl + beepr)/2 is input to speaker - amp. when the pmbpm bit is set to ? 1 ? , mono beep input is powered up. and when the bpmhp bit is set to ? 1 ? , the input signal from the beepm pin to headphone - amp. when the bpmsp bit is set to ? 1 ? , the signal from the beepm pin is input t o speaker output. the external resisters ri adjust the signal level of each beep input that are mixed to headphone and speaker outputs. the signal from the beepm pin is mixed to the headphone - amp through a ? 20db gain stage. the signal from the beepm pin i s mixed to the speaker - amp without gain. the internal feedback resistance is 20k 30% w . beepl ri rf = 20k w beepr ri rf = 20k w AK4534 beepm ri rf = 20k w bpmhp spk mix hpl mix hpr mix bpshp bpshp -20db bpmsp bpssp figure 12. block diagram of beep pins asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 30 - n headphone output power supply voltage for the headphone - amp is supplied from the hvdd pin an d centered on the hvdd/2 voltage. the headphone output load resistance is min.20 w . when the hpl and hpr bits are ? 1 ? , output signals are muted and the hpl and hpr pins output hvdd/2 voltage. when the hpl and hpr bits are ? 0 ? , the headphone - amps are in norm al operation. when the pmhpl and pmhpr bits are ? 0 ? , the headphone - amp is powered down and the outputs (hpl and hpr pins) go to ? l ? (hvss). a capacitor between the mutet pin and ground reduces pop noise at power - up . [example] : a capacitor between the mut et pin and ground = 1.0 m f, a capacitor between the hpl (hpr) pin and headphone = 47 m f time constant of rise time: t r = 100ms, time constant of fall time: t f = 188ms pmhpl/r bits hpl/r pins (1) (2) t r t f figure 13. power - up/power - down timing f or headphone - amp note: the hpl and hpr bits should be kept to ? 0 ? during power - up. (1) pmhpl and pmhpr bits = ? 1 ? headphone - amp is powered up. common voltage of headphone - amp is rising . this rise time depends on the capacitor value connected with the mut et pin. the time constant is t r = 100k x c when the capacitor value on mutet pin is ? c ? . (2) pmhpl and pmhpr bits = ? 0 ? headphone - amp is powered down. common voltage is falling. this fall time depends on the internal resistor and the capacitor value of hpl /r pins. the time constant is t f = 2k x (2 x c) when the capacitor value on hpl(hpr) pin is ? c ? . if the power supply is powered off or headphone - amp is powered - up again before the common voltage goes to gnd, some pop noise occurs. it takes 5times of t f tha t the common voltage goes to gnd. the cut - off frequency of headphone - amp output depends on the external resistor and capacitor used . table 19 shows the cut off frequency and the output power for various resistor/capacitor combinations. the headphone imped ance r l is 16 w . output powers are shown at hvdd = 2.7, 3.0 and 3.3v. the output voltage of headphone is 0.6 x avdd (vpp). when an external resistor r is smaller than 12 w , put an oscillation prevention circuit (0.22 m f+10 w ) because it has the possibility tha t headphone - amp oscillates . AK4534 hp-amp 16 w headphone 10 w 0.22 m r c figure 14. external circuit example of headphone output power [mw] r [ w ] c [ m f] fc [hz] boost=off fc [hz] boost=mid 2.7v 3.0v 3.3v 6.8 47 148.5 60 10.1 12.5 15.0 16 47 105.8 43 5.1 6.3 7.7 6.8 100 69.8 26 10.1 12.5 15.0 16 100 49.7 20 5.1 6.3 7.7 table 19. external circuit example asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 31 - n speaker output mono signal [(l+r)/2] converted from stereo dac output and beep input signal can be output via speaker - amp which is controlled by btl. alc2 cir cuit is available for dac output signal. this speaker - amp can deliver a maximum power of 300mw(typ)@thd=10%, 250mw(typ)@thd=0.1% into 8 ohm load at hvdd=3.3v. maximum output power is 137mw(typ) when dac output signal is output via alc2 circuit as system de sign example (figure 31). when beep input is used for dac output, maximum power becomes 300mw. figure 16 and figure 17 indicates connection examples for 300mw output. speaker blocks (mout2, alc2 and speaker - amp) can be powered up/down by controlling the p mspk bit. when the pmspk bit is ? 0 ? , the mout2, spp and spn pins are placed in a hi - z state. when the spps bit is ? 0 ? , the speaker - amp enters power - save - mode. in this mode, the spp pin is placed in a hi - z state and the spn pin goes to hvdd/2 voltage . and then the speaker output gradually changes to the hvdd/2 voltage and this mode can reduce pop noise at power - up. when the AK4534 is powered down, pop noise can be also reduced by first entering power - save - mode. pmspk bit spps bit spp pin spn pin hvdd/2 hvdd/2 hi-z hi-z hi-z hi-z figure 15. power - up/power - down timing for speaker - amp [connection example for 300mw output] 1) using beepm pin 13k mout2 0.047u beepm 20k 30% 45%avdd bpmsp spp spn spk - amp AK4534 figure 16. connection example for 300mw output using beepm pin asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 32 - 2) using beepl and beepr pins 15k mout2 0.1u beepl 20k 30% 45%avdd 15k beepr 20k 30% 45%avdd bpssp spp spn spk - amp bpssp AK4534 figure 17. con nection example for 300mw output using beepl and beepr pins note) 1. mout2 output is recommended to be ac coupled to avoid amplified dc offset of common voltage of mout2 and beep - amp is output via btl speaker - amp (that means stand - by current is increased). c apacitor size affects the cut - off frequency of 1 st order lpf made by this ac coupling capacitor and series resister in front of beep input. 2. internal feedback resister of beep - amp which determines beep - amp gain has 30% sample variation. n mono output (mou t2 pin) the mixed lch/rch signal of dac is output from the mout2 pin. when the mout2 bit is ? 0 ? , this output is off and the mout2 pin is forced to vcom voltage. the load impedance is 10k w (min.). when the pmspk bit is ? 0 ? , the speaker - amp enters power - dow n - mode and the output is placed in a hi - z state. n mono line output (mout+ and mout - pins) the mixed lch/rch signal of dac is output from the mout+ and mout - pins, creating a differential output. either the mout+ or mout - pins can be also used as single - ended output. asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 33 - n al c2 operation input resistance of the alc2 is 24k w (typ) and centered around vcom voltage, and the input signal level is ? 3.1dbv. (see figure 18. 0dbv=1vrms=2.828vpp) the limiter detection level is proportional to hvdd. the output l evel is limited by the alc2 circuit when the input signal exceeds ? 5.2dbv (=fs - 1.9db@hvdd=3.3v). when a continuous signal of ? 5.2dbv or greater is input to the alc2 circuit, the change period of the alc2 limiter operation is set by the rotm bit and the att enuation level is 0.5db/step. the alc2 recovery operation uses zero crossings and gains of 1db/step. the alc2 recovery operation is done until the input level of the speaker - amp goes to ? 7.2dbv (=fs-3.9db@hvdd=3.3v) . the rotm bit sets the alc2 recovery ope ration period . when the input signal is between ? 5.2dbv and ? 7.2dbv, the alc2 limiter or recovery operations are not done. when the pmspk bit changes from ? 0 ? to ? 1 ? , the initilization cycle (2048/fs = 46.4ms @fs=44.1khz at rotm bit = ? 0 ? , 512/fs = 11.4m s @fs=44.1khz at the rotm bit = ? 1 ?) starts. the alc2 is disabled during the initilization cycle and the alc2 starts after completing the initilization cycle. parameter alc 2 limiter operation alc2 recovery operation operation start level - 5.2 dbv - 7.2dbv rotm bit = ? 0 ? 2/fs = 45 m s (at 44.1khz ) 2048/fs =46.4ms (at 44.1khz ) period rotm bit = ? 1 ? 2/fs = 18 0 m s (at 11.025khz) 512 /fs =46.4ms (at 11.025khz ) zero - crossing detection no yes ( timeout = period time) att/gain 0.5db step 1db step table 20. limiter / recovery of alc2 at hvdd=3.3v 0dbv - 10dbv - 20dbv - 30dbv alc2 att+dac spk - amp fs fs - 12db - 23.3dbv - 11.3dbv fs - 1.9db = - 5.2dbv 0.4dbv - 5.6dbv +5.6db - 0.4db - 3.3dbv - 1.9db - 15.3dbv +4.1 db +8.1db +16.1db - 8db - 8db full - differential single - ended fs - 3.9db = - 7.2dbv - 3.3dbv - 15.3dbv - 1.6dbv figure 18. speaker - amp output level diagram (hvdd=3.3v, datt= - 8.0db) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 34 - n serial control interface (1) 4 - wire serial control mode (i2c pin = ? l ? ) internal registers may be written by using the 4 - wi re p interface pins ( csn , cclk, cdti and cdto). the data on this interface consists of a 2 - bit chip address, read/write, register address (msb first, 5bits) and control data (msb first, 8bits). the chip address high bit is fixed to ? 1 ? and the lower bit i s set by the cad0 pin. address and data is clocked in on the rising edge of cclk and data is clocked out on the falling edge. after a low - to - high transition of csn , data is latched for write operations and cdto bit outputs hi - z. the clock speed of cclk is 5mhz (max). the value of internal registers is initialized at pdn pin = ? l ? . csn cclk cdti 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 c1 c0 r/w a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 cdto hi-z write cdti c1 c0 r/w a4 a3 a2 a1 a0 cdto hi-z read d7 d6 d5 d4 d3 d2 d1 d0 hi-z c1 - c0 : chip address (c1="1", c0=cad0) r/w : read / write ("1" : write, "0" : read) a4 - a0 : register address d7 - d0 : control data figure 19. serial control i/f timing asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 35 - (2) i 2 c - bus control mode (i2c pin = ? h ? ) the AK4534 supports the standard - mode i 2 c - bus (max: 100khz). the ak 4534 does n o t support a fast - mode i 2 c - bus system (max: 400khz). (2) - 1. write operations figure 20 shows the data transfer sequence for the i 2 c - bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicat es a start condition (figure 26) . after the start condition, a slave address is sent. this address is 7 bits long followed by an eighth bit that is a data direction bit (r/w). the most significant five bits of the slave address are fixed as ? 00 10 0 ?. the next two bits are cad1 and cad0 (device address bits ) . these two bits identify the specific device on the bus. the hard - wired input pins (cad1 and cad0 pin s ) set the se device address bits (figure 21) . if the slave address matches that of the ak45 34, the AK4534 generates an acknowledge and the operation is executed. the master must generate the acknowledge - related clock pulse and release the sda line (high) during the acknowledge clock pulse (figure 27). a r/w bit value of ? 1 ? indicates that the re ad operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the AK4534. the format is msb first, and those most significant 3 - bits are fixed to zeros (figure 22). the data after the second byte contains control data. the format is msb first, 8bits (figure 23). the AK4534 generates an acknowledge after each byte has been received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition (figure 26) . the AK4534 can perform more than one byte write operation per sequence . after receipt of the third byte the AK4534 generates an acknowledge and awaits the next dat a. t he master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after receiving each data packet the internal 5 - bit address counter is incremented by one , and the next data is automatically tak en into the next address. if the address exceeds 0fh prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. in order to ensure proper operation, write ? 00h ? to registers 0eh and 0fh te st registers. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low (figure 28) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 20. data transfer sequence at the i 2 c - bus mode 0 0 1 0 0 cad1 cad0 r/w ( those cad1/0 should match with cad1/0 pins) figure 21. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 22. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figur e 23. byte structure after the second byte asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 36 - (2) - 2. read operations set the r /w bit = ? 1 ? for the read operation of the AK4534 . after transmission of data, t he master can read the next address ? s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. after receiving each data packet the internal 5 - bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 0fh prior to generating a stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the AK4534 supports two basic read operations: current address read and random address read . (2) - 2 - 1. current address read t he AK4534 contains an in ternal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) were to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ? 1 ?, the AK4534 generates an acknowledge , transmits 1 - byte of data to the address set by the internal address counter and increments the internal address counter by 1 . if t he master does not generate an acknowledge to the data but instead generate s a stop condition, the AK4534 ceases transmission . sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) a c k p s t o p data(n) figure 24. current address read (2) - 2 - 2. random address read the random read operation allow s the master to access any memory location at ran dom. prior to issuing the slave address with the r/w bit set to ? 1 ?, the master must first perform a ?dummy? write operation. the master issues a start request , a slave address ( r/w bit = ? 0 ? ) and then the register address to read. after the register addre ss i s acknowledge d , the master immediately reissues the start request and the slave address with the r/w bit set to ? 1 ?. the AK4534 then generates an acknowledge , 1 byte of data and increments the internal address counter by 1. if t he master does not gener ate an acknowledge to the data but instead generate s a stop condition, the AK4534 ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k a c k figure 25. random address read asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 37 - scl sda stop condition start condition s p figure 26. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 27. acknowle dge on the i 2 c - bus scl sda data line stable; data valid change of data allowed figure 28. bit transfer on the i 2 c - bus asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 38 - n register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 pmvcm pmbps pmbpm 0 pmmo 0 pmmic pmadc 01h power management 2 mckpd pmxtl pmpll 0 pmspk pmhpl pmhpr pmdac 02h signal select 1 0 psmo damo 0 bpssp bpmsp alcs mout2 03h signal select 2 dahs 0 0 0 bpshp bpmhp hpl hpr 04h mode control 1 pll1 pll0 ps1 ps0 mcko bf dif1 dif0 05h mode control 2 fs2 fs1 fs0 hprm hplm 0 loop spps 06h dac control tm1 tm0 smute dattc bst1 bst0 dem1 dem0 07h mic control 0 0 0 mpwre mpwri micad msel mgain 08h timer select 0 rotm ztm1 ztm0 wtm1 wtm0 ltm1 ltm0 09h alc mode control 1 0 alc2 alc1 zelm lmat1 lmat0 ratt lmth 0ah alc mode control 2 0 ref6 ref5 re f4 ref3 ref2 ref1 ref0 0bh input pga control 0 ipga6 ipga5 ipga4 ipga3 ipga2 ipga1 ipga0 0ch lch digital att control attl7 attl6 attl5 attl4 attl3 attl2 attl1 attl0 0dh rch digital att control attr7 attr6 attr5 attr4 attr3 attr2 attr1 attr0 the pdn pi n = ? l ? resets the registers to their default values. note: unused bits must contain a ? 0 ? value. note: only write to address 00h to 0dh. asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 39 - n register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 pmvcm pmbps pmbpm 0 pm mo 0 pmmic pmadc r/w r/w r/w r/w rd r/w rd r/w r/w default 0 0 0 0 0 0 0 0 pmadc: adc block power control 0: power down (default) 1: power up when the pm adc bit changes from ?0? to ?1?, the initializ ation cycle (2081/fs=47.2ms@44.1khz) starts. after in itializing , digital data of the adc is output. pmmic: mic in block power control 0: power down (default) 1: power up pmmo: mono line out power control 0: power down (default) 1: power up pmbpm: mono beep in power control 0: power down (default) 1: power up even if pmbpm= ? 0 ? , the path is still connected between beepm and hp/spk - amp. bpmhp and bpmsp bits should be set to ? 0 ? to disconnect these paths, respectively. pmbps: stereo beep in power control 0: power down (default) 1: power up even if pmbps= ? 0 ? , the path is still connected between beepl/r and hp/spk - amp. bpshp and bpssp bits should be set to ? 0 ? to disconnect these paths, respectively. pmvcm: vcom block power control 0: power down (default) 1: power up each block can be powered down respective ly by writing ? 0 ? in each bit. when the pdn pin is ? l ? , all blocks are powered down. when all bits except mckpd bit are ? 0 ? in the 00h and 01h addresses, all blocks are powered down. the register values remain unchanged. ipga gain is reset when pmmic bit is ? 0 ? (refer to the ipga6 - 0 bits description). when any of the blocks are powered up, the pmvcm bit must be set to ? 1 ? . mclk, bick and lrck must always be present unless pmmic=pmadc=pmdac=pmspk= ? 0 ? or pdn pin = ? l ? . the paths from beep to hp - amp and spk - amp can operate without these clocks. asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 40 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power management 2 mckpd pmxtl pmpll 0 pmspk pmhpl pmhpr pmdac r/w r/w r/w r/w rd r/w r/w r/w r/w default 1 0 0 0 0 0 0 0 pmdac: dac block power control 0: powe r down (default) 1: power up pmhpr: rch of headphone - amp power control 0: power down (default) 1: power up pmhpl: lch of headphone - amp power control 0: power down (default) 1: power up pmspk: speaker block power control 0: power down (default) 1: power up pmpll: pll block power control select 0: pll is power down and external is selected. (default) 1: pll is power up and pll mode is selected. pmxtl: x ? tal oscillation block power control 0: power down (default) 1: power up mckpd: mcki pin pull down con trol 0: master clock input enable 1: pulled down by 25k w (default) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 41 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h signal select 1 0 psmo damo 0 bpssp bpmsp alcs mout2 r/w rd r/w r/w rd r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 mout2: mout2 output e nable ( mixing = ( l+r ) /2 ) 0: off (default) 1: on when the mout2 bit = ? 0 ? , the mout2 pin outputs vcom voltage. the mout2 pin outputs signal at the mout2 bit = ? 1 ? . this bit is valid at the pmspk bit = ? 1 ? . hi - z is output at the pmspk bit = ? 0 ? . alcs: alc2 to speaker - amp enable 0: off (default) 1: on alc 2 output signal is mixed to speaker - amp at the alcs bit = ? 1 ? . bpmsp: beep m to speaker - amp enable 0: off (default) 1: on mono beep signal (beepm pin) is mixed to speaker - amp at the bpmsp bit = ? 1 ?. bpssp: b eep l/beepr to speaker - amp enable 0: off (default) 1: on stereo beep signal s (beepl/beepr pins) are mixed to speaker - amp at the bpssp bit = ? 1 ?. damo: dac to mout+/mout - enable 0: off (default) 1: on dac output signal is output through mono line output (mo ut+/mout - pins) at the damo bit = ? 1 ?. psmo: mout+/mout - output enable ( mixing = ( l+r ) /2 ) 0: power save mode ( default ) 1: on when the psmo bit = ? 0 ? , mono line output is in power save mode and the mout+ and mout - pins output 0.45 x avdd voltage. dac dahs beepm beepl bpmsp beepr bpssp mix mout2 alc2 alcs spk figure 29. speaker - amp switch control asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 42 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h signal select 2 dahs 0 0 0 bpshp bpmhp hpl hpr r/w r/w rd rd rd r/w r/w r/w r/w default 0 0 0 0 0 0 1 1 hpr: rch headphone - amp disable 0: normal operation 1: off(default) the hpr bit should be always ? 0 ? during operation. hpl: lch headphone - amp disable 0: normal operation 1: off(default) the hpl bit should be always ? 0 ? during operation. bpmhp: beep m to headphone - amp enable 0: off (default) 1: o n mono beep signal (beepm) is mixed to headphone - amp at the bpmhp bit = ? 1 ?. bpshp: beepl/beepr to headphone - amp enable 0: off (default) 1: on stereo beep signal s (beepl/beepr) is mixed to headphone - amp at the bpshp bit = ? 1 ?. dahs: dac to headphone - amp and mout2 enable 0: off (default) 1: on dac signal is mixed to headphone - amp and mout2 at the dahs bit = ? 1 ? . dac dahs beepm beepl bpmhp beepr hpl hpr mute mute bpshp hpr hpl figure 30. headphone - amp switch control asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 43 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h mode control 1 pll1 pll 0 ps1 ps0 mcko bf dif1 dif0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 dif1 - 0: audio interface format select (see table 13) default: ? 10 ? (adc: i 2 s, dac: i 2 s) bf: bick frequency select at master mode 0: 64fs (default) 1: 32fs this bit is invalid in slave mode. mcko: master clock output enable 0: disable (default) 1: enable ps1 - 0: output master clock select (see table 4, 8) default: ? 00 ? (256fs) pll1 - 0: input master clock select at pll mode (see table 2) default: ? 00 ? (12.288mhz) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 44 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h mode control 2 fs2 fs1 fs0 hprm hplm 0 loop spps r/w r/w r/w r/w r/w r/w rd r/w r/w default 0 0 0 0 0 0 0 0 spps: speaker - amp power - save - mode 0: power save mode (default) 1: normal operation when the sp ps bit = ? 1 ? , the speaker - amp is in power - save - mode and the sp p pin becomes hi - z and sp n pin is se t to hvdd/2 voltage. when the pmspk bit = ? 1 ? , this bit is valid. after the pdn pin changes from ? l ? to ? h ? , the pmspk bit is ? 0 ? , which powers down speaker - a mp loop: loopback on/off 0: off (default) 1: on when this bit is ? 1 ? , the adc output is passed to the dac input internally. the external input data to dac is ignored. hplm: lch of hp - amp output control 0: enable output from rch of headphone - amp (default) 1: lch mono output of headphone - amp. the pmhpr bit can be powered down at this time. hprm: rch of hp - amp output control 0: enable output from lch of headphone - amp (default) 1: rch mono output of headphone - amp. the pmhpl bit can be powered down at this ti me. register bit output channel register : 00h register : 05h lch rch pmhpl pmhpr hplm hprm on on 1 1 0 0 on off 1 0 1 0 off on 0 1 0 1 off off 0 0 don ? t care don ? t care table 21. output control for headphone - amp fs2 - 0: sampling frequency modes ( see table 3, 7) default: ? 000 ? (fs=44.1khz) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 45 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h dac control tm1 tm0 smute dattc bst1 bst0 dem1 dem0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 0 0 1 dem1 - 0: de - emphases response (see table 16) default is ? 01 ? (off). bst1 - 0: select low frequency boost function (see table 17) default is ? 00 ? (off). dattc: dac digital attenuator control mode select 0: attl7 - 0 and attr7 - 0 bits control the attenuator level of lch and rch respectively . 1: attl7 - 0 bi ts control both lch and rch at same time. (default) attr7 - 0 bits are n o t changed when the attl7 - 0 bits are written. smute: soft mute control 0: normal operation (default) 1: dac outputs soft - muted soft mute operation is independent of digital attenuator a nd is performed in the digital domain. tm1 - 0: soft mute time select (see table 22) default: ? 00 ? (1024/fs) tm1 tm0 cycle 0 0 1024/fs default 0 1 512/fs 1 0 256/fs 1 1 128/fs table 22. soft mute time setting asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 46 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h mic/hp control 0 0 0 mpwre mpwri micad msel mgain r/w rd rd rd r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 mgain: 1 st mic - amp gain control 0: 0db 1: 20db (default) msel: microphone select 0: internal mic (default) 1: external mic micad : switch control from mic in to adc. 0: off (default) 1: on mpwri: power supply control for internal microphone 0: off (default) 1: on mpwre: power supply for external microphone 0: off (default) 1: on asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 47 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08 h timer select 0 rotm ztm1 ztm0 wtm1 wtm0 ltm1 ltm0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 ltm1 - 0: alc1 limiter operation period at zero crossing disable (zelm bit = ? 1 ? ) (see table 23) the ipga value is changed immediately. when th e ipga value is changed continuously, the change is done by the period specified by the ltm1 - 0 bits. default is ? 00 ? (0.5/fs). alc1 limiter operation period ltm1 ltm0 8khz 16khz 44.1khz 0 0 0.5/fs 63 m s 31 m s 11 m s default 0 1 1/fs 125 m s 63 m s 23 m s 1 0 2/fs 250 m s 125 m s 45 m s 1 1 4/fs 500 m s 250 m s 91 m s table 23. alc1 limiter operation period at zero crossing disable (zelm bit = ? 1 ? ) wtm1 - 0: alc1 recovery waiting period (see table 24) a period of recovery operation when any limiter operation does n ot occur during the alc1 operation. default is ? 00 ? (128/fs). alc1 recovery operation waiting period ztm1 ztm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms default 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 2 3.2ms table 24. alc1 recovery operation waiting period ztm1 - 0: zero crossing timeout for the write operation by the m p, alc1 recovery, and zero crossing enable (zelm bit = ? 0 ? ) of the alc1 operation. (see table 25) when the ipga of each l/r channels per form zero crossing or timeout independently, the ipga value is changed by the m p write operation, alc1 recovery operation or alc1 limiter operation (zelm bit = ? 0 ? ). default is ? 00 ? (128/fs). zero crossing timeout period ztm1 ztm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms default 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 25. zero crossing timeout period rotm: period time for alc2 recovery operation 0: 2048/fs (default) 1: 512 /fs asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 48 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h alc mode control 1 0 alc2 alc1 zelm lmat1 lmat0 ratt lmth r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 1 0 0 0 0 0 0 lmth: alc1 limiter detection level / recovery waiting counter reset level (see table 26) the alc1 limiter detection level and the alc1 recovery counter reset level may be offset by about 2db . default is ? 0 ? . lmth alc1 limiter detection level alc1 recovery waiting counter reset level 0 adc input 3 - 6.0dbfs - 6.0dbfs > adc input 3 - 8.0dbfs defau lt 1 adc input 3 - 4.0dbfs - 4.0dbfs > adc input 3 - 6.0dbfs table 26. alc1 limiter detection level / recovery waiting counter reset level ratt: alc1 recovery gain step (see table 27) during the alc1 recovery operation, the number of steps changed from th e current ipga value is set. for example, when the current ipga value is 30h and ratt bit = ? 1 ? is set, the ipga changes to 32h by the alc1 recovery operation and the output signal level is gained up by 1db (=0.5db x 2). when the ipga value exceeds the ref erence level (ref6 - 0 bits), the ipga value does not increase. ratt gain step 0 1 default 1 2 table 27. alc1 recovery gain step setting lmat1 - 0: alc1 limiter att step (see table 28) during the alc1 limiter operation, when either lch or rch exceeds th e alc1 limiter detection level set by lmth, the number of steps attenuated from the current ipga value is set. for example, when the current ipga value is 47h and the lmat1 - 0 bits = ? 11 ? , the ipga transition to 43h when the alc1 limiter operation starts, r esulting in the input signal level being attenuated by 2db (=0.5db x 4). when the attenuation value exceeds ipga = ? 00 ? ( - 8db), it clips to ? 00 ? . lmat1 lmat0 att step 0 0 1 default 0 1 2 1 0 3 1 1 4 table 28. alc1 limiter att step setting zelm: enable zero crossing detection at alc1 limiter operation 0: enable (default) 1: disable when the zelm bit = ? 0 ? , the ipga of each l/r channel perform a zero crossing or timeout independently and the ipga value is changed by the alc1 operation. the zero cro ssing timeout is the same as the alc1 recovery operation. when the zelm bit = ? 1 ? , the ipga value is changed immediately . alc1: alc1 enable flag 0: alc1 disable (default) 1: alc1 enable alc2: alc2 enable flag 0: alc2 disable 1: alc2 enable (default) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 49 - a ddr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah alc mode control 2 0 ref6 ref5 ref4 ref3 ref2 ref1 ref0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 1 1 0 1 1 0 ref6 - 0: reference value at a lc1 recovery operation (see table 29) during the alc1 recovery operation , if the ipga value exceeds the setting reference value by gain operation, then the ipga does not become larger than the reference value. for example, when ref7 - 0 = ? 30h ? , ratt = 2step, ipga = 2fh, even if the input signal does not exceed the ? al c1 recovery waiting counter reset level ? , the ipga does n o t change to 2fh + 2step = 31h, and keeps 30h. default is ? 36h ? . data (hex) gain (db) step 47 +27.5 46 +27.0 45 +26.5 : : 36 +19.0 default : : 10 +0.0 : : 06 - 5.0 05 - 5.5 04 - 6.0 03 - 6.5 02 - 7.0 01 - 7.5 00 - 8.0 0.5db table 29. setting reference value at alc1 recovery operation asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 50 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh input pga control 0 ipga6 ipga5 ipga4 ipga3 ipga2 ipga1 ipga0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 0 0 0 ipga6 - 0: input analog pg a (see table 30) default: ? 10h ? (0db) when ipga gain is changed, ipga6 - 0 bits should be written while pmmic bit is ? 1 ? and alc1 bit is ? 0 ? . ipga gain is reset when pmmic bit is ? 0 ? , an d then ipga operation starts from the default value when pmmic is changed to ? 1 ? . when alc1 bit is changed from ? 1 ? to ? 0 ? , ipga holds the last gain value set by alc1 operation. when ipga6 - 0 bits are read, the register values written by the last write oper ation are read out regardless the actual gain. data (hex) gain (db) step 47 +27.5 46 +27.0 45 +26.5 : : 36 +19.0 : : 10 +0.0 default : : 06 - 5.0 05 - 5.5 04 - 6.0 03 - 6.5 02 - 7.0 01 - 7.5 00 - 8.0 0.5db table 30. i nput gain setting addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch lch digital att control attl7 attl6 attl5 attl4 attl3 attl2 attl1 attl0 0dh rch digital att control attr7 attr6 attr5 attr4 attr3 attr2 attr1 attr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 attl/r7 - 0: digital att output control (see table 18) default: ? 00h ? (0db) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 51 - system design figure 31 shows the system connection diagram. an evaluation board [akd4534] is available which demonstrates the optimum layout, power supp ly arrangements and measurement results. 0.1 m 10 m 0.1 m 10 m analog supply 2.4 ~ 3.6v 0.1 m 10 m 2.2 m 0.1 m 0.1 m 10 m analog supply 2.4 ~ 3.6v micout 1 2 3 4 5 6 7 8 9 10 11 12 13 tst1 ext mpe mpi int vcom avss avdd pvdd pvss vcoc nc nc 52 51 50 49 ain beepl beepr 48 47 45 44 46 42 41 43 40 beepm tst5 tst4 mout+ mout- tst3 tst2 mout2 min 39 38 37 36 35 34 33 32 31 30 29 28 27 mutet hpl hpr hvss hvdd spn spp m/s xti/mcki xto dvss dvdd cad0 14 pdn 15 16 csn/cad1 17 cclk/scl 18 cdti/sda 19 cdto 20 i2c 21 sdti 22 sdto 23 lrck 24 bick 25 mcko 26 reset dsp and up top view r r r 1 m 8 w 10k w 4.7n 10 1 m 2.2k 1 m 2.2k 1 m 1 m 1 m 1 m 1 m nc nc 16 w 16 w c c c c 6.8 w 6.8 w 47 m 10 w 0.22 m 10 w 0.22 m notes: - avss, dvss, pvss and hvss of the AK4534 should be distributed separately from the ground of external controllers. - values of r and c in figure 31 should depend on system. - all input pins should not be left floating. figure 31. typical connection diagram asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 52 - 1. grounding and power supply decoupling the AK4534 requires careful attention to power supply and grounding arrangements. avdd, dvdd, pvdd and hvdd are usually sup plied from the system ? s analog supply. if avdd, dvdd, pvdd and hvdd are supplied separately, the correct power up sequence should be observed . avss, dvss, pvss and hvss of the AK4534 should be connected to the analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the AK4534 as possible, with the small value ceramic capacitor being the nearest. 2. voltage refe rence vcom is a signal ground of this chip. a 2.2 m f electrolytic capacitor in parallel with a 0.1 m f ceramic capacitor attached to the vcom pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, esp ecially clocks, should be kept away from the vref and vcom pins in order to avoid unwanted coupling into the AK4534. 3. analog inputs the mic and beep inputs are single - ended. the input signal range scales with nominally at 0.06 x avdd vpp for the mic in put and 0.6 x avdd vpp for the beep input, centered around the internal common voltage ( 0.45 x avdd ). usually the input signal is ac coupled using a capacitor. the cut - off frequency is fc = (1/2 p rc). the AK4534 can accept input voltages from avss to avdd. 4. analog outputs the input data format for the dac is 2 ? s complement. the output voltage is a positive full scale for 7fffh(@16bit) and a negative full scale for 8000h(@16bit). mono output from the mout2 pin and mono line output from the mout+ and mout - pins are centered at 0.45 x avdd . the headphone - amp and speaker - amp outputs are centered at hvdd/2. asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 53 - contorol sequence n power up upon power - up, bring the pdn pin = ?l?. initialize the internal registers to default value s after the pdn pin = ?h?. se t the following registers to establish the initial condition. power supply pdn pin pmvcm bit (addr:00h, d7) dif1-0 bits (addr:04h, d1-0) bf bit (addr:04h, d2) pll1-0 bits (addr:04h, d7-6) mout2 bit (addr:02h, d0) alcs bit (addr:02h, d1) hpl/r bits (addr:03h, d1-0) dahs bit (addr:03h, d7) (2) 10 xx x xx 00 0 (3) (4) (5) (6) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz (1) power supply (2) pdn pin = ? l ? ? ? h ? (3) addr:00h, data 80h (4) addr:02h, data 03h (5) addr:03h, data 80h (6) addr:04h, data 42h figure 32. power up sequence asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 54 - n clock set up when adc, dac, alc1 and alc2 are used, the clocks (mclk, bick and lrck) must be supplied. 1. when x'tal is used in pll mode. (slave mode) mckpd bit (addr:01h, d7) bick, lrck (slave mode) ps1-0 bits (addr:04h, d5-4) pmxtl bit (addr:01h, d6) pmpll bit (addr:01h, d5) mcko bit (addr:04h, d3) mcko pin xx 00 40ms(max) output input (1) 20ms(typ) (2) (3) (4) (5) (6) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:01h, data:40h (2) addr:01h, data:60h (3) addr:04h, data 4ah (4) mcko output starts (5) bick and lrck input start (6) addr:04h, data 6ah figure 33. clock set up sequence (1) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 55 - 2. when x'tal is used in pll mode. (master mode) mckpd bit (addr:01h, d7) bick, lrck (master mode) ps1-0 bits (addr:04h, d5-4) pmxtl bit (addr:01h, d6) pmpll bit (addr:01h, d5) mcko bit (addr:04h, d3) mcko pin xx 00 40msec(max) output output (1) 20ms(typ) (2) (3) (4) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:01h, data:40h (2) addr:01h, data:60h (3) addr:04h, data 6ah (4) mcko, bick and lrck output starts figure 34. clock set up sequence (2) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 56 - 3. when an external clock is used in pll mode. (slave mode) mckpd bit (addr:01h, d7) ps1-0 bits (addr:04h, d5-4) pmpll bit (addr:01h, d5) mcko bit (addr:04h, d3) mcko pin xx 00 (1) output bick, lrck (slave mode) input external mclk input (2) (3) 40ms(max) (4) (5) (6) (7) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:01h, data:00h (2) input external mclk (3) addr:01h, data 2 0h (5) mcko output starts (6) bick and lrck input start (7) addr:04h, data 6ah (4) addr:04h, data 4ah figure 35. clock set up sequence (3) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 57 - 4. when an external clock is used in pll mode. (master mode) mckpd bit (addr:01h, d7) ps1-0 bits (addr:04h, d5-4) pmpll bit (addr:01h, d5) mcko bit (addr:04h, d3) mcko pin xx 00 40ms(max) output bick, lrck (master mode) output external mclk input (1) (2) (3) (4) (5) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:01h, data:00h (2) input external mclk (3) addr:01h, data 20h (5) mcko, bick and lrck output starts (4) addr:04h, data 6ah figure 36. clock set up sequence (4) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 58 - n mic input recording fs2-0 bits (addr:05h, d7-5) mic control (addr:07h, d2-0) pmadc bit (addr:00h, d0) pmmic bit (addr:00h, d1) adc internal state xxx 000 00001 xx1xx power down initialize normal state power down 2081 / fs (1) (2) (6) (7) alc1 state alc1 enable alc1 disable alc1 disable (5) alc1 control 1 (addr:08h) xxh 00h (3) alc1 control 2 (addr:0ah) xxh 47h (4) alc1 control 3 (addr:09h) xxh 61h or 21h example : x ? tal and pll are used. sampling frequency : 8khz mic select : internal mic pre mic amp : +20db mic power on alc1 setting : refer to figure 9 alc2 bit = ? 1 ? (default) (1 ) addr:05h, data:e0h (3) addr:08h, data:00h (4) addr:0ah, data:47h (5) addr:09h, data:61h (2) addr:07h, data:0dh ( 6) addr:00h, data 83h recording (7) addr:00h, data 80h figure 38. mic input recording sequence asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 59 - n headphone - amp output fs2-0 bits (addr:05h, d7-5) attl7-0 bits (addr:0ch 0dh, d7-0) pmdac bit (addr:01h, d0) pmhpl/r bits (addr:01h, d2-1) hpl/r pins xxx 000 0000000 xxxxxxx normal output external mute (1) bst1-0 bits (addr:06h, d3-2) 00 xx 00 (2) (3) (4) (5) (6) (7) (8) example : x ? tal and pll are used. sampling frequency : 44.1khz dattc bit = ? 1 ? (default) digital attenuator level : - 8db bass boost level : middle de - emphases response : off soft mute time : 1024/fs (1) addr:05h, data:00h (3 ) addr:0ch, data 10h (4) addr:01h, data 67h (5) release external mute playback (2) addr:06h, data 19h (6) enable external mute (7) addr:01h, data 60h (8) addr:06h, data 11h figure 39. headphone - amp output sequence asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 60 - n speaker - amp output fs2-0 bits (addr:05h, d7-5) attl7-0 bits (addr:0ch 0dh, d7-0) pmdac bit (addr:01h, d0) pmspk bit (addr:01h, d3) xxx 000 0000000 xxxxxxx spp pin normal output spps bit (addr:05h, d0) hi-z hi-z spn pin normal output hi-z hi-z hvdd/2 hvdd/2 (1) (3) x 0 (2) alc2 bit (addr:09h, d6 (4) (5) (7) (6) example : x ? tal and pll are used. sampling frequency : 48khz dattc bit = ? 1 ? (default) digital attenuator level : 0db alc1 : disable alc2 : disable (1) addr:05h, data60h (3) addr:0ch, data 00h (4) addr:01h, data 69h (5) addr:05h, data 61h playback (2) addr:09h, data 00h (6) addr:05h, data 60h (7) add r:01h, data 60h figure 40. speaker - amp output sequence asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 61 - n stop of clock mclk can be stopped when pmmic=pmadc=pmdac=pmspk= ? 0 ? . 1. when x ? tal is used in pll mode mckpd bit (addr:01h, d7) pmxtl bit (addr:01h, d6) pmpll bit (addr:01h, d5) mcko bit (addr:03h, d4) (1) (2) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:04h, data:62h (2) addr:01h, data:80h figure 41. stop of clock sequence (1) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 62 - 3. external clock mode mckpd bit (addr:01h, d7) external mclk input example : (1) addr:01h, data:80h (2) stop external clock figure 43. stop of clock sequence (3) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 63 - package 52pin qfn (unit: mm) 7.2 0.20 14 26 7.2 0.20 0.30 0.10 7.0 0.10 7.0 0.10 0.21 0.05 0.60 + 0.10 - 0.30 0.05 0.02 + 0.03 - 0.02 0.78 + 0.17 - 0.28 0.80 + 0.20 - 0.00 13 1 52 40 27 39 27 39 40 52 13 1 14 26 0.20 + 0.10 - 0.20 45 45 0.05 m 4 - c0.6 0.18 0.05 0.40 note) the part of black at four corners on reverse side must not be soldered and must be open. n material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate (pb free) asahi kasei [ AK4534] ms0133 - e - 03 2003/5 - 64 - marking n 52pin qfn 1 AK4534vn xxxxxxx akm xxxxxxx : date code identifier (7 digits) i m portant notice these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or de vices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither inten ded nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of a km. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonabl y be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safe ty or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising fro m the use of said product in the absence of such notification. |
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