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x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 1 of 12 x-mgc part number: FCU-022M101 features compliant with ieee802.3ak (10gbase-cx4) x2 msa rev 1.0b compatible module industry standard electric al connector, microgigacn tm (i/o interface) xaui four channel electrical interface (host side card edge) xaui standard 70 pin connector for host connection front panel hot swap ability. x2 msa rev 1.0b compliant mdio link alarm status interrupt (lasi) support total power consum ption under 3.0 watt 20 meters over standard infiniband copper cable (24awg) with media detect converter (o-mgc), up to 30 0 meters over standard multi mode fiber. no external clocks requirement ? oscillator on board description the x-mgc is a 10gigabit ethernet cx4 module that designed to ease x2 msa rev 1.0b and it is an electrical module that incorporates the complete physical layer functionality from xaui compliant 4 lanes x 3.125 gb/s four differential electrical interface to the microgigacn? cx4 complia nt electrical interface. the x-mgc is plugged into a x2 hosting system and connects to a 4x infiniband cable. the control interface (mdio)is also integrated. the x-mgc module include s 10gb/s ethernet transmitter and receiver ports. the host may control the x-mgc registers using xaui inte rface as defined in the x2 msa. the mux/demux, xaui interface and mdio management functions are all integrated into the module, as is a precision oscillator that removes any need for an external reference clock.
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 2 of 12 x-mgc block diagram 7 figure 1: functional brock diagram of x-mgc module (*1) in case of infiniband cable is connected, the power does not supply to cable, and if o-mgc is connected, a ground contact is changed vcc for power supply to o-mgc by media detect function. general electrical specification interface: xaui side; 70 pin smt connect or (see x2 msa rev1.0b, chapter 6.7) cx4 side; infiniband 4x connector (microgigacn? , fujitsu component ltd. patent) differential signal rate: tx and rx each 3.125 gb/s x 4 pair impedance: 100 ohms differential, ac-coupled i/o adaptable cable and link length: ; infiniband 4x cable 20m over supply voltage: 3.3v and 1.5v supports standard lvcm os 1.2v host interface. environmental specification operating case temperature: 0 - 70 degree (in an uniform air flow of 0.5 m/s.) power consumption: 2.1 watt max transceiver management media detect re-timer xaui in xaui out xgxs rx tx xaui in xaui out infiniband cable (< 20m) o-mgc + optical fiber (< 300m (*1) ) cx4 interface (midro gigacn ? connector) power ( *1 ) reference clock vcc hot swap control normalization mdio, mdc, other signal xaui interface (70pin connector)
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 3 of 12 figure 2: top level brock diagram of x-mgc driver
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 4 of 12 technical specification table 1: transmitter characteristics parameter typical units notes signal data rate 3.125 gb/s +/-100ppm unit interval (ui) nominal 320 ps differential peak to peak output voltage maximum minimum 1200 800 mvp-p mvp-p differential peak to peak output voltage difference 150 mvp-p maximum differential output return lo ss see figure 3 db minimum differential output template see figure 4 v transition time (20-80%) maximum minimum 130 60 ps ps output jitter random jitter deterministic jitter total jitter 0.27 0.17 0.35 uipp uipp uipp figure 3: transmit differential output return loss 15 10 1,000 0 5 10,000 100 frequency (mhz) loss (db)
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 5 of 12 figure 4: normalized transmit template table 2: receiver characteristics parameter typical units notes bit error ratio 10 -12 signal data rate 3.125 gb/s +/-100ppm unit interval (ui) nominal 320 ps differential input amplitude 1200 mvp-p maximum return loss differential (minim um) see figure 3 db 100ohm 0.000 5.000 10.000 0.000 time (ui) normalized amplitude (v) -1.000 -1.500 1.000 0.500 -1.500 1.500
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 6 of 12 xaui interface table 3: driver characteristics parameter typical units notes transmit data rate 3.125 gb/s +/-100ppm unit interval nominal 320 ps differential amplitude 1600 mvp-p maximum absolute output voltage limits maximum minimum 2.3 -0.4 v v differential skew 15 ps maximum differential output retu rn loss 10 db minimum common mode output return loss 6 db minimum eye mask see figure 5 symbol near-end value far-end value units x1 0.175 0.275 ui x2 0.390 0.4 ui a1 400 100 mv a2 800 800 mv a2 a1 0 -a1 -a2 1-x1 1-x2 x1 x2 differential amplitude mv) time (ui) figure 5: driver template table 4: driver template
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 7 of 12 table 5: receive input parameters parameter typical units notes transmit data rate 3.125 gb/s +/-100ppm unit interval nominal 320 ps differential input amplitude maximum minimum 1600 200 mvp-p mvp-p return loss differential common 10 6 db db input differential skew 75 ps maximum jitter amplitude tolerance peak-to-peak total jitter peak-to-peak deterministic jitter 0.65 0.47 uipp uipp
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 8 of 12 x-mgc xaui pin out 70 gnd 69 gnd 68 reserved 67 reserved 66 gnd 65 tx lane3- 64 tx lane3+ 63 gnd 62 tx lane2- 61 tx lane2+ 60 gnd 59 tx lane1- 58 tx lane1+ 57 gnd 56 tx lane0- 55 tx lane0+ 54 gnd 53 gnd 52 gnd 51 rx lane3- 50 rx lane3+ 49 gnd 48 rx lane2- 47 rx lane2+ 46 gnd 45 rx lane1- 44 rx lane1+ 43 gnd 42 rx lane0- 41 rx lane0+ 40 gnd 39 reserved 38 reserved 37 gnd 36 gnd top of transceiver pcb 1 gnd 2 gnd 3 gnd 4 5.0v 5 3.3v 6 3.3v 7 aps (1.5v) 8 aps (1.5v) 9 lasi 10 reset 11 vend specific 12 tx on/off 13 reserved 14 mod detect 15 vend specific 16 vend specific 17 mdio 18 mdc 19 prtad4 20 prtad3 22 prtad2 21 prtad1 23 prtad0 24 vend specific 25 aps set 26 reserved 27 aps sense 28 aps (1.5v) 29 aps (1.5v) 30 3.3v 31 3.3v 32 5.0v 33 gnd 34 gnd 35 gnd bottom of transceiver pcb (as viewed through top) toward bezel figure 6: x-mgc transceiver electrical pad layout
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 9 of 12 1 gnd 2 gnd 3 gnd 4 5.0v 5 3.3v 6 3.3v 7 aps (1.5v) 8 aps (1.5v) 9 lasi 10 reset 11 vend specific 12 tx on/off 13 reserved 14 mod detect 15 vend specific 16 vend specific 17 mdio 18 mdc 19 prtad4 20 prtad3 22 prtad2 21 prtad1 23 prtad0 24 vend specific 25 aps set 26 reserved 27 aps sense 28 aps (1.5v) 29 aps (1.5v) 30 3.3v 31 3.3v 32 5.0v 33 gnd 34 gnd 35 gnd lower row 70 gnd 69 gnd 68 reserved 67 reserved 66 gnd 65 tx lane3- 64 tx lane3+ 63 gnd 62 tx lane2- 61 tx lane2+ 60 gnd 59 tx lane1- 58 tx lane1+ 57 gnd 56 tx lane0- 55 tx lane0+ 54 gnd 53 gnd 52 gnd 51 rx lane3- 50 rx lane3+ 49 gnd 48 rx lane2- 47 rx lane2+ 46 gnd 45 rx lane1- 44 rx lane1+ 43 gnd 42 rx lane0- 41 rx lane0+ 40 gnd 39 reserved 38 reserved 37 gnd 36 gnd upper row toward bezel figure 7: 10gb host board pad layout
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 10 of 12 pin function definitions pin no name dir function notes 1 gnd electrical ground 1 2 gnd electrical ground 1 3 gnd electrical ground 1 4 5.0v power 2 5 3.3v power 2 6 3.3v power 2 7 aps (1.5v) adaptive power supply 2 8 aps (1.5v) adaptive power supply 2 9 lasi lvcmos 1.2v open drain 3 10 reset i lvcmos 1.2v open drain 3 11 vend specific-signal detect passive 12 tx on/off 13 reserved reserved 4 14 mod detect o passive 15 vend specific-spare passive 16 vend specific-spare passive 17 mdio i/o management data io lvcmos 1.2v open drain 3,4 18 mdc i management data clock 3,4 19 prtad4 i port address bit 4 (low = 0) 3 20 prtad3 i port address bit 3 (low = 0) 3 21 prtad2 i port address bit 2 (low = 0) 3 22 prtad1 i port address bit 1 (low = 0) 3 23 prtad0 i port address bit 0 (low = 0) 3 24 vend specific-not connected passive 25 aps set (1.5v) passive 26 reserved reserved 4 27 aps sense passive connector to a 348 ohm resistor 28 aps (1.5v) adaptive power supply 2 29 aps (1.5v) adaptive power supply 2 30 3.3v power 2 31 3.3v power 2 32 5.0v power 2 33 gnd electrical ground 1 34 gnd electrical ground 1 35 gnd electrical ground 1 table 6: xaui pin function 1
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 11 of 12 pin no name dir function notes 36 gnd electrical ground 1 37 gnd electrical ground 1 38 reserved reserved 39 reserved reserved 40 gnd electrical ground 1 41 rx lane0+ module xaui output lane 0+ 5 42 rx lane0- module xaui output lane 0- 5 43 gnd electrical ground 1 44 rx lane1+ module xaui output lane 1+ 5 45 rx lane1- module xaui output lane 1- 5 46 gnd electrical ground 1 47 rx lane2+ module xaui output lane 2+ 5 48 rx lane2- module xaui output lane 2- 5 49 gnd electrical ground 1 50 rx lane3+ module xaui output lane 3+ 5 51 rx lane3- module xaui output lane 3- 5 52 gnd electrical ground 1 53 gnd electrical ground 1 54 gnd electrical ground 1 55 tx lane0+ module xaui input lane 0+ 5 56 tx lane0- module xaui input lane 0- 5 57 gnd electrical ground 1 58 tx lane1+ module xaui input lane 1+ 5 59 tx lane1- module xaui input lane 1- 5 60 gnd electrical ground 1 61 tx lane2+ module xaui input lane 2+ 5 62 tx lane2- module xaui input lane 2- 5 63 gnd electrical ground 1 64 tx lane3+ module xaui input lane 3+ 5 65 tx lane3- module xaui input lane 3- 5 66 gnd electrical ground 1 67 reserved reserved 68 reserved reserved 69 gnd electrical ground 1 70 gnd electrical ground 1 table 7: xaui pin function 2 notes: 1) ground connections are common for tx and rx. 2) all contacts of xaui 70 pin connector are rated at 0.5a nominal. 3) 1.2v cmos compatible. 4) mdio and mdc timing must comply with ieee802.3ae, clause 45.3 5) xaui output characteristics should comply with ieee802.3ae clause 47.
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 12 of 12 package design mechanical design of x-mgc is shown as in following figure8. it is preliminary design and subject to change without notice, please check with us for the latest design. (part number: FCU-022M101-0 ) figure 8: x-mgc schematic drawing datum b is physical hard stop for transceiver. datum c is inside edge of slot on transceiver. datum d is vertical center of transceiver pcb. datum e is to p surface of slot on transceive r . n ote3) lot code, the product part number, serial number and fujitsu component limited logo are indicated. n ote2) unless otherwise specified, tolerance shall be +/-0.5mm. n ote1 ) this module is x2-cx4 transceive r . ( mid/panel-mount t yp e )

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