data sheet 26185.110e A6832 dabic-5 32-bit serial input latched sink drivers intended originally to drive thermal printheads, the A6832 has been optimized for low output-saturation voltage, high-speed operation, and pin con gurations that are the most convenient for the tight space requirements of high-resolution printheads. these integrated circuits can also be used to drive multiplexed led displays or incandescent lamps at up to 125 ma peak current. the combination of bipolar and mos technologies gives the A6832 arrays an interface exibility beyond the reach of standard buffers and power driver circuits. the devices each have 32 bipolar npn open-collector saturated driv- ers, a cmos data latch for each of the drivers, two 16-bit cmos shift registers, and cmos control circuitry. the high-speed cmos shift reg- isters and latches allow operation with most microprocessor-based sys- tems. use of these drivers with ttl may require input pull-up resistors to ensure an input logic high. mos serial data outputs permit cascading for interface applications requiring additional drive lines. the A6832 is supplied in a 44-lead plastic leaded chip carrier (package suf x ep ), for surface-mount applications requiring minimum area. these devices are lead (pb) free, with 100% matte tin plated leadframes. ? 3.3 v to 5 v l ogic supply range ? to 10 mhz data input rate ? schmitt trigger inputs for improved noise immunity ? low-power cmos logic and latches ? 40 v current sink outputs ? low saturation voltage ? ?40c operation available use the following complete part numbers when ordering: ab so lute max i mum rat ings part number pins package operating temperature A6832sep-t 44 plcc ?20oc to +85oc A6832eep-t 44 plcc ?40oc to +85oc output voltage, v out ......................................... 40 v logic supply voltage, v dd ................................... 7 v input voltage range, v in .............. ?0.3 v to v dd +0.3 v continuous output current, i out ................. 125 ma package power dissipation, p d , see chart, page 5 operating temperature range ambient temperature, t a ............ ?20c to +85c storage temperature, t s .......... ?55c to +150c caution: cmos devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges. features ? thermal printheads ? multiplexed led displays ? incandescent lamps applications A6832sep/A6832eep 44-pin plcc 12 13 14 15 16 17 10 11 9 8 7 27 26 25 24 23 22 21 28 20 19 18 35 34 33 32 31 36 37 38 39 29 2 1 44 43 42 3 4 5 6 40 41 30
2 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com A6832 dabic-5 32-bit serial-input latched sink drivers data sheet 26185.110e functional block diagram 32-bit s hift r e gis te r latches clock serial data in strobe output enable v dd serial data out mos bipolar out out out out out out 1 2 3 30 31 32 ground tpiinptcirit tpiotptdrier in v dd out v dd
3 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com A6832 dabic-5 32-bit serial-input latched sink drivers data sheet 26185.110e electrical characteristics 1 unless otherwise noted: t a = 25c, logic supply operating voltage v dd = 3.0 v to 5.5 v characteristic symbol test conditions v dd = 3.3 v v dd = 5 v units min. typ. max. min. typ. max. output leakage current i cex v out = 40 v ? ? 10 ? ? 10 a collector?emitter saturation voltage v ce(sat) i out = 50 ma ? ? 275 ? ? 275 mv i out = 100 ma ? ? 550 ? ? 550 mv input voltage v in(1) 2.2 ? ? 3.3 ? ? v v in(0) ? ? 1.1 ? ? 1.7 v input current i in(1) v in = v dd ? < 0.01 1.0 ? < 0.01 1.0 a i in(0) v in = 0 v ? < ?0.01 ?1.0 ? < ?0.01 ?1.0 a serial data output voltage v out(1) i out = ?200 a 2.8 3.05 ? 4.5 4.75 ? v v out(0) i out = 200 a ? 0.15 0.3 ? 0.15 0.3 v maximum clock fre- quency 2 f c 10 ? ? 10 ? ? mhz logic supply current i dd(1) one output on, i out = 100 ma ? ? 6.0 ? ? 6.0 ma i dd(0) all outputs off ? ? 100 ? ? 100 a output enable-to-output delay t dis(bq) v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s t en(bq) v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s strobe-to-output delay t p(sth-ql) v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s t p(sth-qh) v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s output fall time t f v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s output rise time t r v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s clock-to-serial data out delay t p(ch-sqx) i out = 200 a ? 50 ? ? 50 ? ns 1 positive (negative) current is de ned as conventional current going into (coming out of) the speci ed device pin. 2 operation at a clock frequency greater than the speci ed minimum value is possible but not warran teed. l = low logic level h = high logic level x = irrelevant p = present state r = previous state serial shift register contents serial latch contents output output contents data clock data strobe enable input input i 1 i 2 i 3 ... i n-1 i n output input i 1 i 2 i 3 ... i n-1 i n input i 1 i 2 i 3 ... i n-1 i n hhr 1 r 2 ... r n-2 r n-1 r n-1 llr 1 r 2 ... r n-2 r n-1 r n-1 xr 1 r 2 r 3 ... r n-1 r n r n xxx...x x x l r 1 r 2 r 3 ... r n-1 r n p 1 p 2 p 3 ... p n-1 p n p n hp 1 p 2 p 3 ... p n-1 p n hp 1 p 2 p 3 ... p n-1 p n x x x ... x x l h h h ... h h truth table
4 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com A6832 dabic-5 32-bit serial-input latched sink drivers data sheet 26185.110e timing requirements and speci cations (logic levels are v dd and ground) clock serial data in strobe output enable out n 50% serial data out data data 10% 90% 50% 50% 50% c a b d e high = all outputs e nable d p(s t h-q l) t p(c h-s q x ) t data p(s t h-q h) t output enable out n data 10% 50% dis (b q) t en(bq) t low = all outputs blanked (disabled) r t f t 50% 90% note: timing is representative of a 10 mhz clock. higher speeds may be attainable; operation at high temperatures will reduce the speci ed maximum clock frequency. s erial data present at the input is transferred to the shift register on the logical 0 to logical 1 transition of the clock input pulse. on succeeding clock pulses, the registers shift data information towards the serial data output. the serial data must appear at the input prior to the rising edge of the clock input waveform. information present at any register is transferred to the respective latch when the strobe is high (serial-to-parallel conversion). the latches will continue to accept new data as long as the strobe is held high. applications where the latches are bypassed (strobe tied high) will require that the output enable input be low during serial data entry. when the output enable input is low, the output sink drivers are disabled (off). the information stored in the latches is not affected by the output enable input. with the output enable input high, the outputs are controlled by the state of their respective latches. key description symbol time (ns) a data active time before clock pulse (data set-up time) t su(d) 25 b data active time after clock pulse (data hold time) t h(d) 25 c clock pulse width t w(ch) 50 d time between clock activation and strobe t su(c) 100 e strobe pulse width t w(sth) 50
5 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com A6832 dabic-5 32-bit serial-input latched sink drivers data sheet 26185.110e 1 4 5 6 18 19 20 21 22 23 24 25 26 27 28 40 41 42 43 44 2 3 7 8 9 10 11 12 13 14 15 16 17 out nc strobe 1 ground serial data in logic supply clock serial data out output enable nc out 32 38 39 37 36 35 34 33 32 31 30 29 out 31 out 21 nc out 13 out 16 ic out 17 o ut 20 nc v dd 32 shift register latches shift register latches out 12 out 2 A6832sep/A6832eep 50 75 100 125 15 0 package power dissipation (w) ambient temperature (o c) 25 4.0 3.0 3.5 0.5 0 2.5 2.0 1.5 1.0 4.5 A6832ep, r = 54 c/w ja A6832ep, r = 30 c/w ja allowable power dissipation, p d * *additional thermal information is available on the allegro web site.
6 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com A6832 dabic-5 32-bit serial-input latched sink drivers data sheet 26185.110e dimensions in inches (controlling dimensions) dimensions in millimeters (for reference only) 18 28 dwg. ma-005-44a in 0.020 min 0.050 bsc 1 44 0.021 0.013 index area 2 6 7 17 29 39 40 0.695 0.685 0.032 0.026 0.319 0.291 0.319 0.291 0.180 0.165 0.695 0.685 0.656 0.650 0.656 0.650 dwg. ma-005-44a mm 17.65 17.40 0.51 min 4.57 4.20 17.65 17.40 16.662 16.510 1.27 bsc 0.812 0.661 1 44 0.533 0.331 index area 2 28 29 39 40 6 7 17 18 16.662 16.510 8.10 7.39 8.10 7.39 n otes: 1. exact body and lead configuration at vendor? option within limits shown. 2. lead spacing tolerance is non-cumulative. A6832sep and A6832eep
7 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com A6832 dabic-5 32-bit serial-input latched sink drivers data sheet 26185.110e the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical compo- nents in life-support devices or sys tems without express written approval. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon - si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. copyright?2003, 2004, 2005 allegromicrosystems, inc.
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