following are the details: < s >: start signal scl sda high high high low the start signal is high to low transition on the sda line when scl is high. < write sa >: write slave address: 98h, 9ah, 9ch, or 9eh < read sa >: read slave address: 99h, 9bh, 9dh, or 9fh < register index >: value of the AL875 register index. < a >: acknowledge stage the acknowledge - related clock pulse is generated by the host (master). the ho st releases the sda line (high) for the AL875 (slave) to pull down the sda line during the acknowledge clock pulse. < na >: not acknowledge stage scl sda sda scl sda scl scl sda scl data bit [1] or na data bit [0] or a start bit [s] stop bit [p] not significant al250-15 i2c drawing
AL875 preliminary version subject to change without notice january 25, 2001 20 the acknowledge - related clock pulse is generated by the host (master). the host releases the sda line (high) during the acknowledge clock pulse, but the AL875 does not pull it down during this stage. < data >: data byte write to or read from the register index. in read operation, the host must release the sda line (high) before the first clock pulse is transmitte d to the AL875. < p >: stop signal scl sda high low high high the stop signal is low to high transition on the sda line when scl is high. suppose data f0h is to be written to register 0fh using write slave address 98h, the timing is as follows: suppo se data is to be read from register 55h using read slave address 99h, the timing is as follows: start slave addr = 98h ack ack ack stop index = 0fh data = f0h sda scl AL875-04 i2c write timing start slave addr = 98h ack ack ack index = 55h read slave addr = 99h sda scl AL875-05 i2c read timing nack stop data read cycle stop start
AL875 preliminary version subject to change without notice january 25, 2001 21 more information on the AL875 functionality can be found in the register definition section.
AL875 preliminary version subject to change without notice january 25, 2001 22 7.0 electrical characteristics 7.1 recommended operating cond itions parameter min max unit vdd supply voltage +3.0 +3.6 v tamb ambient operating temperature 0 +70 c 7.2 dc characteristics parameter test conditions min typ. max unit i dd supply current 90mhz 115 ma p power consumption 380 mw v ih hi - leve l input voltage vdd+0.5 - vdd+0.5 v v il lo - level input voltage +0.8 - +0.8 v v oh hi - level output voltage vdd - vdd v v ol lo - level output voltage 0.5 - 0.5 v i o output current, stand data - 0.5v AL875 preliminary version subject to change without notice january 25, 2001 23 c l digital output load cap. 15 - 50 pf t oh o utput hold time c l = 15pf 3 - - ns t pd propagation delay c l = 40pf - - 5 ns snr signal - to - noise ratio - - 48 db f c conversion speed - - 110 mhz
AL875 preliminary version subject to change without notice january 25, 2001 24 8.0 AL875 register definition the AL875 is powered up to a default state depending on the hardware mod e - setting pins. hardware configuration is disabled by setting softconfig (bit 4 of register 0x03) as 1, then software configuration is determined by the values of register 0x02, which is programmable by software. i2c sub - address: addr2, addr1 pins i 2 c writ e address i 2 c read address low, low 98h 99h low, high 9ah 9bh high, low 9ch 9dh high, high 9eh 9fh 8.1 index of control registers the following is the summary of AL875 control registers register addr r/w description default note companyid 00h r onl y company id 0100 0110 46h revision 01h r only revision number 0000 0000 00h hwconfig 02h r/w hardware configuration general 03h r/w general register family 04h r only chip family 1000 0111 87h status 05h r status register jitter test registers phitest 06h r/w clock phase test uuu0 0000 00h delta 07h r/w main and delay clock select 0000 0000 diffh 08h r only difference count in a horizontal line (high) diffl 09h r only difference count in a horizontal line (low) pll - related registers dividerh 0ah r/w pll divider high - byte 0101 0011 53h dividerl 0bh r/w pll divider low - byte 0100 1000 46h phase 0ch r/w pll phase delay control 0000 0000 one - line auto - positioning registers hnumber 10h r/w horizontal line number for hde_st, 0000 0110 unit: 8 lines
AL875 preliminary version subject to change without notice january 25, 2001 25 hde_end det ection 6 * 8 = 48 data_th 11h r/w data threshold for 0001 0000 20h hde_sth 12h r only horizontal active data start (high - byte) hde_stl 13h r only horizontal active data start (low - byte) hde_endh 14h r only horizontal active data end (high - byte) hde_endl 15h r only horizontal active data end (low - byte) hcnt_toth 16h r only detected horizontal total value (high - byte) hcnt_totl 17h r only detected horizontal total value (low - byte) hs_width 18h r only detected horizo ntal sync width vcolumn 19h r/w vertical column number for vde_st, vde_end detection 0011 0111 unit: 8 lines 37h * 8=440 vde_sth 1ah r only vertical active data start (high - byte) vde_stl 1bh r only vertical active data start (low - byte) vde_endh 1 ch r only vertical active data end (high - byte) vde_endl 1dh r only vertical active data end (low - byte) whole - frame auto positioning registers whde_sth 21h r only detected horizontal active start pixel position (high - byte) whde_stl 22h r only dete cted horizontal active start pixel position (low - byte) whde_endh 23h r only detected horizontal active end pixel position (high - byte) whde_endl 23h r only detected horizontal active end pixel position (low - byte) wvde_sth 25h r only detected verti cal active start line (high byte) wvde_stl 26h r only detected vertical active start line (low - byte) wvde_endh 27h r only detected vertical active end line (high - byte) wvde_endl 28h r only detected vertical active end line (low - byte) note: u ? unused 8.2 register description 00h: company id (r) [companyid] companyid <7:0> company id (46h)
AL875 preliminary version subject to change without notice january 25, 2001 26 01h: revision (r) [revision] revision <7:0> revision number (00h) 02h: hardware/software configuration (r/w) [hwconfig] ckrefo_inv <4> invert the phase of ckrefo (reference clock output) inv <1> invert the phase of ckadco (adc sampling clock) pwrdn <0> power - down mode (active high) please refer to the clock distribution circuitry diagram in section 6.3 for additional reference. 03h: general (r/w) [ge neral] if softcinfig (0x03<4>) = 0, the values of hardware configuration pins are set/read. if softcinfig (0x03<4>) = 1, the values of software configuration registers are set/read. softconfig <4> enable configuration defined by software configuration registers 0x02. 04h: chip family (r) [family] family <7:0> 10000111, AL875 series 05h: status register (r) [status] vspol_det <7> detected input vsync polarity 1: positive, 0: negative. hspol_det <6> detected input hsync polarity 1: positive, 0: ne gative. vsync <4> input vsync signal (without any processing) hsync <3> input hsync signal (without any processing) hspeed <2> chips speed version; 1: high speed; 0: low speed. clock phase test (jitter test) 06h: clock phase test (r/w) [phitest] en v_th <7> enable vdata_th when env_th = 0, data_th (reg.#11h) applies for both horizontal and vertical threshold. when env_th = 1, data_th (reg.#11h) defines horizontal threshold only; vertical threshold is defined by vdata_th (reg.#0fh). adcdiff_th <6:5> bits 5 and 4 of adcdiff_th, threshold of data difference in clock phase test mode for auto phase detection phitest <4> clock phase test enable
AL875 preliminary version subject to change without notice january 25, 2001 27 adcdiff_th <3:0> bits 0~3 of adcdiff_th, threshold of data difference in clock phase test mode for auto p hase detection. any difference lower than the threshold is considered as noise and can be disregarded. 07h: delayed clock value select (r/w) [delta] delta <3:0> delayed clock phase - delay select this register defines the delay of the two adc sampling cl ocks in jitter detection mode 1. each delay is equivalent to 1.6ns. the detected value is stored in registers #08h and 09h. 08h: number of pixels with significant data difference in jitter detection mode (r) [diffh] diff (9:8) <1:0> 09h: number of p ixels with significant data difference in jitter detection mode (r) [diffl] diff (7:0) <7:0> in this jitter detection mode, all odd pixels in a designated line are sampled and digitized twice. the total number of data pairs with data value difference hi gher than the specified threshold value is stored in these two registers. the delay of the two sampling clocks can be programmed by register #07h. change of hsync and clock phase may result in different diff values. the lowest diff value usually in dicates the optimized hsync and clock phase setting. 0dh: difference of first and last pixel position (r) [diff2h] diff2 (10:8) <2:0> bits 11~8 of the difference of first and last pixel position 0eh: difference of first and last pixel position (r) [diff 2l] diff2 (7:0) <7:0> bits 7~0 of the difference of first and last pixel position in this jitter detection mode, position of the first active pixel of each line is compared with that of the previous line. when there is difference, this value is increment ed by 1. similarly, position of the last active pixel of each line is also compared with that of the previous line; when there is difference, this register values is incremented by 1. the total number is stored in diff2hand diff2l. pll - related regist ers 0ah: divider high - byte (r/w) [dividerh] dividerh(11:8) <3:0> bits 8~11 of the pll divider 0bh: divider low - byte (r/w) [dividerl] dividerl(7:0) <7:0> bits 7~0 of the pll divider this is the pll divider number when a non - programmable genlock pll suc h as ics9173 is used.
AL875 preliminary version subject to change without notice january 25, 2001 28 0ch: pll phase delay control (r/w) [phase] phasea <7:4> hsync phase delay adjustment phaseb <3:0> ckbo phase delay adjustment refer to the internal pll block diagram and AL875 clock distribution circuitry in section 6.3 for addi tional reference. one - line automatic positioning: 0fh: vertical data threshold (r/w) [vdata_th] vdata_th <7:0> luma (brightness) threshold value. this value is used to determine non - blanking pixel for vertical direction. any pixel luma value less than this value is considered as blanking. . hardware default value is 32 (20h). vertical column used to detect vertical active start and end is defined by register #19h. this register is enabled by register #06h<7>. 10h: horizontal line number for hde_st & hde_end detection (r/w) [hnumber] hnumber <7:0> horizontal line number for horizontal active start and end detection; refer to register #11h for additional reference. (unit: 8 lines) hardware default value is 06h, which means 6 x 8 = 48 lines 11h: d ata threshold (r/w) [data_th] data_th <7:0> luma (brightness) threshold value. this value is used to determine non - blanking pixel for horizontal direction. any pixel luma value less than this value is considered as blanking. . hardware default value is 32 (20h). horizontal line used to detect horizontal active start and end is defined by register #10h. this register is enabled by register #06h<7>. 12h: horizontal active start high (r only) [hde_sth] hde_sth <2:0> bits <10:8> of detected horizontal a ctive start pixel position. 13h: horizontal active start low (r only) [hde_stl] hde_stl <7:0> bits <7:0> of detected horizontal active start pixel position. (unit: 1 pixel) 14h: horizontal active end high (r only) [hde_endh] hde_endh <2:0> bits <10 :8> of detected horizontal active end - pixel position. 15h: horizontal active end low (r only) [hde_endl] hde_endl <7:0> bits <7:0> of detected horizontal active end - pixel position. (unit: 1 pixel) 16h: detected h total value (r only) [hcnt_toth] hcnt _toth <2:0> bits <10:8> of the detected horizontal total pixel number.
AL875 preliminary version subject to change without notice january 25, 2001 29 17h: detected h total value low (r only) [hcnt_totl] hcnt_totl <7:0> bits <7:0> of the detected horizontal total pixel number. 18h: detected hsync width (r only) [hs_width] hs_width <7:0> indicate the detected horizontal sync pulse width. 19h: vertical column for vdestart & vdeend detection (r/w) [vcolumn] vcolumn <7:0> vertical column number for vertical active start and end detection; refer to register #11h for additional referen ce. hardware default value: 37h = 55 x 8 = 440. (unit: 8 pixels) 1ah: vertical active start high (r only) [vde_sth] vde_sth <2:0> bits <10:8> of detected vertical active start line. 1bh: vertical active start low (r only) [vde_stl] vde_stl <7:0> bits <7:0> of detected vertical active start line. (unit: 1 line) 1ch: vertical active end high (r only) [vdeendh] vde_endh <2:0> bits <10:8> of detected vertical active end line. 1dh: vertical active end low (r only) [vde_endl] vde_endl <7:0> bits <7:0> of detected vertical active end line. (unit: 1 line) whole - frame automatic positioning: 21h: horizontal active start high (r only) [whde_sth] whde_sth <2:0> bits <10:8> of detected horizontal active start pixel position. 22h: horizontal active start low (r only) [whde_stl] whde_stl <7:0> bits <7:0> of detected horizontal active start pixel position. (unit: 1 pixel) 23h: horizontal active end high (r only) [whde_endh] whde_endh<2:0> bits <10:8> of detected horizontal active end pixel position. 24 h: horizontal active end low (r only) [whde_endl] whde_endl <7:0> bits <7:0> of detected horizontal active end pixel position (unit: 1 pixel) 25h: vertical active start high (r only) [wvde_sth] wvde_sth <2:0> bits <10:8> of detected vertical active start line 26h: vertical active start low (r only) [wvde_stl] wvde_stl <7:0> bits <7:0> of detected vertical active start line (unit: 1 line) 27h: vertical active end high (r only) [wvde_endh] wvde_endh<2:0> bits <10:8> of detected vertical active en d line
AL875 preliminary version subject to change without notice january 25, 2001 30 28h: vertical active end low (r only) [wvde_endl] wvde_endl <7:0> bits <7:0> of detected vertical active end line (unit: 1 line)
AL875 preliminary version subject to change without notice january 25, 2001 31 9.0 board design and layout considerations the AL875 contains both precision analog and high - speed digital circuitr y. noise coupling from digital circuits to analog circuits may result in poor video quality. the layout should be optimized for lowest noise on the power and ground planes by shielding the digital circuitry and providing good decoupling. 9.1 grounding a nalog and digital circuits are separated within the AL875 chip. to minimize system noise and prevent digital system noise from entering the analog portion, a common ground plane for all devices, including the AL875 is recommended. all the connections to th e ground plane should have very short leads. the ground plane should be solid, not cross - hatched. 9.2 power planes and power supply decoupling the analog portion of the AL875 and any associated analog circuitry should have their own power plane, referred t o as the analog power plane (avdd). the analog power plane should be connected to the digital power plane (dvdd) at a single point through a low resistance ferrite bead. additionally, in order to minimize cross interference, the analog power planes of r, g, b and pll should also be separated with low resistance ferrite beads. power supply connection pins should be individually decoupled. for best results, use 0.1 m f ceramic chip capacitors. lead lengths should be minimized. the power pins should be connec ted to the bypass capacitors before being connected to the power planes. 22 m f capacitors should also be used between the AL875 power planes and the ground planes to control low - frequency power ripple. 9.3 digital signal and clock interconnect digital sign als to the AL875 should be isolated as much as possible from the analog outputs and other analog circuitry. the high frequency clock reference or crystal should be handled carefully because jitters and noise on the clock will degrade the video performance . keep the clock paths to the decoder as short as possible to reduce noise pickup. 9.4 analog signal interconnect the AL875 should be located closely to the output connectors to minimize noise and reflections. keep the critical analog traces as short and wide as possible (20~30 mil). digital signals, especially pixel clocks and data signals should not overlap any of the analog signal circuitry and should be kept as far apart as possible. the AL875 and the decoder ic should have no inputs left floating.
AL875 preliminary version subject to change without notice january 25, 2001 32 10.0 mechanical drawing AL875: 14mm x 20mm 100 - pin 0.65 - pitch pqfp package
AL875 preliminary version subject to change without notice january 25, 2001 33 11.0 power consumption the AL875 works at single 3.3v power. the following table shows the current consumption of the AL875 at different operating frequencies. frequency cur rent AL875@3.3v 110mhz 135 ma (typ.) AL875@3.3v 90mhz 115 ma (typ.) AL875@3.3v 65mhz 95 ma (typ.) AL875@3.3v 40mhz 65 ma (typ.) for more information about the AL875 or other averlogic products, please contact your local authorized representatives, visit our website, or contact us directly.
contact information averlogic technologies, inc. 6840 via del oro suite 160 san jose, ca 95119 usa tel : 1 408 361 - 0400 fax : 1 408 361 - 0404 e - mail : sales@averlogic.com url : www .averlogic.com