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65com/132seg driver & controller for 4 g/s stn lcd KS0711 1 preliminary introduction the KS0711 is an lcd driver lsi for liquid crystal dot-matrix graphic display systems. it incorporates 198 driver circuits for 132 segments, 64 commons an icon-driving common, 65 132 2 bit-map ram, and 4-level gray scale controller for enhanced graphics. it is capable of interfacing the microprocessor, accepting serial or 8-bit parallel display data directly from the microprocessor, and storing data in an on-chip display data ram. in addition, the KS0711 can read and write display data ram with minimum current consumption, as it does not require any external operation clocks. it also has lcd driving voltage generation circuits, such as the voltage converter, voltage regulator and voltage follower to reduce power consumption. features ? 4-level (white, light gray, dark gray, black) gray scale display 9/12/15 pwm and 3/4 frc method ? driver outputs ? common outputs: 65 common ? segment outputs: 132 segment ? on-chip display data ram ? capacity: 65 132 2 = 17,160 bits ? multi-chip operation (master, slave) available ? applicable duty-ratio ? microprocessor interface ? 8-bit parallel bidirectional interface with 6800-series or 8080-series ? serial interface (only write operation) available ? on-chip oscillator circuit ? on-chip low power supply for lcd driving voltage generation ? voltage converter ( 2 / 3 / 4 / 5) ? voltage regulator (selective temperature coefficient) ? voltage follower ? on-chip electronic contrast control functions (64 steps) ddram data [2n: 2n+1] 00 01 10 11 gray scale white light gray dark gray dark (accessible column address, n = 0, 1, 2,......., 129, 130, 131) duty ratio applicable lcd bias maximum display area 1/65 1/9 or 1/7 65 132 1/49 1/8 or 1/6 49 132 1/33 1/7 or 1/5 33 132
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 2 preliminary ? operating voltage range ? supply voltage (v dd ): 2.4v to 5.5v ? lcd driving voltage (v lcd = v0 - v ss ): 4.0v to 15.0v ? low power consumption ? 150 m a max. (operation) ? 10 m a max. (standby mode) ? wide operating temperature range ? ta = - 40 c to 85 c ? cmos process ? package ? slim chip for cog, and tcp available
65com/132seg driver & controller for 4 g/s stn lcd KS0711 3 preliminary block diagram figure 1. block diagram status register bus holder page address circuit display data ram 65x132x2 = 17,160bits line address circuit i/o buffer column address circuit voltage converter & lcd voltage generator circuit vr intrs hpmb temp1 temp0 ref dcdc5b vext vout c1- c1+ c2- c2+ c3- c3+ command decoder mpu interface ( parallel & serial ) db0 db1 db2 db3 db4 db5 db6(sclk) db7(sid) c68 resetb ps rw_wr e_rd rs cs2 cs1b display timing generator circuit oscillator ms cl m frs disp duty0 duty1 v dd v0 v1 v2 v3 v4 v ss 132 channel segment driver common output control circuit display latch circuit coms com63 : com32 seg131 seg130 seg129 : : : seg66 seg65 seg64 seg63 : : : seg2 seg1 seg0 com31 : com1 com0 33 channel common driver 33 channel common driver frc/pwm function circuit test1 test2 test3 test4 test5 cls rext1 rext2 oscck
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 4 preliminary pad configuration figure 2. pad configuration item pad no. size unit x y chip size - 11690 3420 m m pad pitch 1 to 125 90 126 to 349 70 bumped pad size 1 to 125 56 114 126 to 162 108 50 163 to 312 50 108 313 to 349 108 50 bumped pad height all pad 17 (typ.) eeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeeeeeeeee 163 312 162 313 126 349 125 1 KS0711 (top view) (0,0) x eeeeeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeee eeee - - - - eeee eee - - - - eeee y
65com/132seg driver & controller for 4 g/s stn lcd KS0711 5 preliminary pad location (not fixed) table 1. pad location [unit: m m] pad no pad name coordinate pad no pad name coordinate pad no pad name coordinate x y x y x y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 dummy dummy dummy dummy frs m cl disp v ss cs1b cs2 v dd resetb rs v ss rw_wr e_rd v dd c68 ps v ss ref dummy dummy v dd db0 db1 db2 db3 db4 db5 db6 db7 v ss test1 test2 v dd duty0 duty1 v ss ms cls v dd vext v ss -5580 -5490 -5400 -5310 -5220 -5130 -5040 -4950 -4860 -4770 -4680 -4590 -4500 -4410 -4320 -4230 -4140 -4050 -3960 -3870 -3780 -3690 -3600 -3510 -3420 -3330 -3240 -3150 -3060 -2970 -2880 -2790 -2700 -2610 -2520 -2430 -2340 -2250 -2160 -2070 -1980 -1890 -1800 -1710 -1620 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 v ss v ss v ss v ss v ss v ss v ss v dd v dd v dd v dd v dd v dd v dd v dd vout vout vout vout c3+ c3+ c3+ c3+ c3- c3- c3- c3- c1+ c1+ c1+ c1+ c1- c1- c1- c1- c2+ c2+ c2+ c2+ c2- c2- c2- c2- v ss v ss -1530 -1440 -1350 -1260 -1170 -1080 -990 -900 -810 -720 -630 -540 -450 -360 -270 -180 -90 0 90 180 270 360 450 540 630 720 810 900 990 1080 1170 1260 1350 1440 1530 1620 1710 1800 1890 1980 2070 2160 2250 2340 2430 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 vr vr v0 v0 v0 v0 v1 v1 v2 v2 v3 v3 v4 v4 v ss v ss oscck dcdc5b v dd hpmb intrs v ss temp0 temp1 v dd rext1 rext2 vss test3 test4 test5 dummy dummy dummy dummy dummy dummy dummy coms com0 com1 com2 com3 com4 com5 2520 2610 2700 2790 2880 2970 3060 3150 3240 3330 3420 3510 3600 3690 3780 3870 3960 4050 4140 4230 4320 4410 4500 4590 4680 4770 4860 4950 5040 5130 5220 5310 5400 5490 5580 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1586 -1330 -1260 -1190 -1120 -1050 -980 -910 -840 -770 -700
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 6 preliminary 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5669 5215 5145 5075 5005 4935 4865 4795 4725 4655 4585 4515 4445 4375 4305 4235 4165 4095 4025 3955 3885 3815 3745 3675 -630 -560 -490 -420 -350 -280 -210 -140 -70 0 70 140 210 280 350 420 490 560 630 700 770 840 910 980 1050 1120 1190 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 3605 3535 3465 3395 3325 3255 3185 3115 3045 2975 2905 2835 2765 2695 2625 2555 2485 2415 2345 2275 2205 2135 2065 1995 1925 1855 1785 1715 1645 1575 1505 1435 1365 1295 1225 1155 1085 1015 945 875 805 735 665 595 525 455 385 315 245 175 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 seg64 seg65 seg66 seg67 seg68 seg69 seg70 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 seg81 seg82 seg83 seg84 seg85 seg86 seg87 seg88 seg89 seg90 seg91 seg92 seg93 seg94 seg95 seg96 seg97 seg98 seg99 seg100 seg101 seg102 seg103 seg104 seg105 seg106 seg107 seg108 seg109 seg110 seg111 seg112 seg113 105 35 -35 -105 -175 -245 -315 -385 -455 -525 -595 -665 -735 -805 -875 -945 -1015 -1085 -1155 -1225 -1295 -1365 -1435 -1505 -1575 -1645 -1715 -1785 -1855 -1925 -1995 -2065 -2135 -2205 -2275 -2345 -2415 -2485 -2555 -2625 -2695 -2765 -2835 -2905 -2975 -3045 -3115 -3185 -3255 -3325 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 table 1. pad location (continued) [unit: m m] pad no pad name coordinate pad no pad name coordinate pad no pad name coordinate x y x y x y
65com/132seg driver & controller for 4 g/s stn lcd KS0711 7 preliminary 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 seg114 seg115 seg116 seg117 seg118 seg119 seg120 seg121 seg122 seg123 seg124 seg125 seg126 seg127 seg128 seg129 seg130 seg131 dummy dummy dummy dummy -3395 -3465 -3535 -3605 -3675 -3745 -3815 -3885 -3955 -4025 -4095 -4165 -4235 -4305 -4375 -4445 -4515 -4585 -4655 -4725 -4795 -4865 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 1534 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 dummy dummy dummy dummy dummy dummy coms com63 com62 com61 com60 com59 com58 com57 com56 com55 com54 com53 com52 com51 com50 com49 -4935 -5005 -5075 -5145 -5215 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 1534 1534 1534 1534 1534 1190 1120 1050 980 910 840 770 700 630 560 490 420 350 280 210 140 70 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 com48 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 dummy dummy dummy -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 -5669 0 -70 -140 -210 -280 -350 -420 -490 -560 -630 -700 -770 -840 -910 -980 -1050 -1120 -1190 -1260 -1330 table 1. pad location (continued) [unit: m m] pad no pad name coordinate pad no pad name coordinate pad no pad name coordinate x y x y x y
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 8 preliminary pin descriptions table 2. pin description name i/o description power supply v dd supply power supply v ss supply ground v0 v1 v2 v3 v4 i/o lcd driver supply voltages. the voltage determined by lcd pixel is impedance- converted by an operational amplifier for application. voltages should have the following relationship: v0 3 v1 3 v2 3 v3 3 v4 3 v ss when the internal power circuit is active, these voltages are generated as shown in the following table, according to the state of lcd bias. lcd driver supply c1 - i capacitor 1 - negative connection pin for voltage converter c1+ i capacitor 1+ positive connection pin for voltage converter c2 - i capacitor 2 - negative connection pin for voltage converter c2+ i capacitor 2+ positive connection pin for voltage converter c3 - i capacitor 3 - negative connection pin for voltage converter c3+ i capacitor 3+ positive connection pin for voltage converter vout i/o voltage converter output vr i v0 voltage adjust pin which is valid only when on-chip registers are not used dcdc5b i 5-times boosting circuit enable input pin. when this pin is low in 4-times boosting circuit, the 5-times boosted voltage appears at vout rext1, rext2 i when using an internal clock oscillator, connect a register between rext1 and rext2. vext i external vref input terminal for the lcd power supply voltage regulator. lcd bias v1 v2 v3 v4 1/9 bias (8/9) v0 (7/9) v0 (2/9) v0 (1/9) v0 1/8 bias (7/8) v0 (6/8) v0 (2/8) v0 (1/8) v0 1/7 bias (6/7) v0 (5/7) v0 (2/7) v0 (1/7) v0 1/6 bias (5/6) v0 (4/6) v0 (2/6) v0 (1/6) v0 1/5 bias (4/5) v0 (3/5) v0 (2/5) v0 (1/5) v0
65com/132seg driver & controller for 4 g/s stn lcd KS0711 9 preliminary system control ms i master/slave mode select input. master makes some signals for display, and slave receives them. this is for display synchronization. ms = ? h ? : master mode ms = ? l ? : slave mode cls i built-in oscillator circuit enable / disable select pin. cls = ? h ? : enable cls = ? l ? : disable (external display clock input to cl pin) cl i/o display clock input/output. when KS0711 is used in master/slave mode (multi-chip), the cl pins must be connected to each other. ms = ? h ? : output ms = ? l ? : input m i/o lcd ac signal input / input. when KS0711 is used in master/slave mode (multi-chip), the m pins must be connected to each other. ms = ? h ? : output ms = ? l ? : input frs o static driver output. this pin is used together with the m pin. disp i/o lcd display blanking control input / output. when KS0711 is used in master/slave mode (multi-chip), the disp pins must be connected to each other. ms = ? h ? : output ms = ? l ? : input ref i selects the external vref voltage via the vext terminal. ref = ? h ? : using the internal vref ref = ? l ? : using the external vref intrs i internal resistor select. this pin selects the resistors for adjusting v0 voltage level and is available only in master mode. intrs = ? h ? : using built-in resistors, intrs = ? l ? : not using built-in resistors. v0 voltage is controlled by vr pin and external resistive divider. hpmb i power control pin of the power supply circuit for lcd driver. hpmb = ? l ? : high power mode hpmb = ? h ? : normal mode this pin is available only in master mode. table 2. pin description (continued) name i/o description ms osc circuit power supply cicuit cl m disp h enable enable output output output l disable disable input input input
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 10 preliminary temp1 temp0 i selects the temperature coefficient of the reference voltage. duty1 duty0 i the lcd driver duty ratio depends on the following table. oscck i/o oscillator clock input / output. table 2. pin description (continued) name i/o description temp1 temp0 temperature coefficient h h tbd h l tbd l h tbd l l tbd duty1 duty0 duty ratio l l 1/33 l h 1/49 h l 1/65 h h 1/65 ms cls oscck h h output l input l ? input
65com/132seg driver & controller for 4 g/s stn lcd KS0711 11 preliminary microprocessor interface resetb i reset input pin. when resetb is low, initialization is executed. ps i parallel/serial data input select input note: in serial mode, it is impossible to read data from the on-chip ram. db0 to db5 is high impedance and e_rd and rw_wr must be fixed on high or low. c68 i microprocessor interface select input in parallel mode. c68 = ? h ? : 6800-series mpu interface c68 = ? l ? : 8080-series mpu interface cs1b cs2 i chip select inputs. data input / output is enabled only when cs1b is low and cs2 is high. when chip select is non-active, db0 to db7 will be high impedance. rs i register select input. rs = ? h ? : then data on db0 to db7 is display data rs = ? l ? : then data on db0 to db7 is control data rw_wr i when interfacing to a 6800-series mpu, read/write is enable. rw_wr = ? h ? : read rw_wr = ? l ? : write when interfacing to a 8080-series mpu, rw_wr is enable at low. e_rd i when interfacing to a 6800-series mpu: active high. this is used as an enable clock input pin of the 6800-series mpu. when interfacing to an 8080-series mpu: active low. this input connects the rd signal of the 8080-series mpu. while this signal is low, KS0711 data bus output is enabled. db0 to db7 i/o 8-bit bidirectional data bus. it is connected to the standard 8-bit microprocessor data bus. when the serial interface selected (ps = ? l ? ): db7: serial input data (sid) db6: serial input clock (sclk) db0 to db5: high impedance. when chip select is not active, db0 to db7 will be high impedance. table 2. pin description (continued) name i/o description ps operating mode chip select data/ instruction data input/output read/ write serial clock h parallel cs1b, cs2 rs db0 to db7 e_rd, rw_wr - l serial cs1b, cs2 rs db7(sid) write only db6 (sclk)
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 12 preliminary lcd driver outputs seg0 to seg131 o lcd driver output for segment. the display data and the m signal control the output voltage of segment driver. com0 to com63 o lcd driver output for segment. the display data and the m signal control the output voltage of segment driver. coms o common output for the icons. the output signals of two pins are the same. when not used, these pins should be left open. in multi-chip (master / slave) mode, all coms pins on both master and slave units are the same signal. test pin test1 to test5 i ic test pins test1 to test2 pins: high test3 to test5 pins: open table 2. pin description (continued) name i/o description display data m segs output voltage normal display reverse display h h v0 v2 h l v ss v3 l h v2 v0 l l v3 v ss power save mode v ss display data m coms output voltage h h v ss h l v0 l h v1 l l v4 power save mode v ss
65com/132seg driver & controller for 4 g/s stn lcd KS0711 13 preliminary function description microprocessor interface chip select input there are cs1b and cs2 pins for chip selection. the KS0711 can interface with a microprocessor only when cs1b is low and cs2 is high. when these pins are set to any other combination, rs, e_rd, and rw_wr inputs are disabled and db0 to db7 are to be high impedance. also, in the case of serial interface, the internal shift register and the counter are reset. parallel / serial interface the KS0711 has three types of interface with mpu, one serial and two parallel. this parallel or serial interface is determined by ps pin as shown in table 3. note: don ? t care parallel interface (ps = ? h ? ) the 8-bit bidirectional data bus is used in parallel interface and the type of mpu is selected by c68 as shown in table 4. the type of data transfer is determined by signals at rs, e_rd and rw_wr as shown in table 5. table 3. parallel / serial interface mode ps type cs1b cs2 c68 interface mode h parallel cs1b cs2 h 6800-series mpu mode l 8080-series mpu mode l serial cs1b cs2 (note) serial-mode table 4. microprocessor selection for parallel interface c68 cs1b cs2 rs e_rd rw_wr db0 to db7 mpu bus h cs1b cs2 rs e rw db0 to db7 6800-series l cs1b cs2 rs rd wr db0 to db7 8080-series table 5. parallel data transfer common 6800-series 8080-series description rs e_rd (e) rw_wr (rw) e_rd (rd) rw_wr (wr) h h h l h display data read h h l h l display data write l h h l h register status read l h l h l writes to internal register (instruction)
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 14 preliminary serial interface (ps = ? l ? ) when KS0711 is active, serial data (db7) and serial clock (db6) inputs are enabled. when not active, the internal 8-bit shift register and the 3-bit counter are reset. serial data can be read on the rising edge of the serial clock going into db6 and is processed as 8-bit parallel data on the eighth serial clock. serial data input is display data when rs is high and control data when rs is low. since the clock signal (db6) is easily affected by the external noise caused by the line length, the operation check on the actual machine is recommended. busy flag the busy flag indicates whether the KS0711 is operating or not. when db7 is high in read status operation, this device is in busy status and will accept only read status instruction. if the cycle time is correct, the microprocessor does not need to check this flag before each instruction, which improves microprocessor performance. data transfer the KS0711 uses a bus holder and an internal data bus for data transfer with mpu. when writing data from the mpu to the on-chip ram, data is automatically transferred from the bus holder to the ram as shown in figure4. when reading data from the on-chip ram to mpu, the data for the initial read cycle is stored in the bus holder (dummy read) and mpu reads this stored data from the bus holder for the next data read cycle, as shown in figure 5. this means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. figure 3. serial interface timing cs1b cs2 sid sclk rs db5 db6 db7 db0 db1 db2 db3 db4 db5 db6 db7
65com/132seg driver & controller for 4 g/s stn lcd KS0711 15 preliminary figure 4. write timing figure 5. read timing mpu signals n preset rs wr rd db0 ~ db7 n d(n) d(n+1) d(n+2) d(n+3) d(n+4) d(n+5) n+5 wr rd bus holder column address n d(n) d(n+1) d(n+2) d(n+3) d(n+4) d(n+5) n+1 n+2 n+3 n+4 internal signals n+5 rs wr rd db0 ~ db7 dummy wr rd bus holder column address d(n+3) d(n+4) n+1 n+2 n+3 n+4 n preset n dummy d(n+2) d(n) d(n+1) n d(n+3) d(n+4) d(n+2) d(n) d(n+1) mpu signals internal signals
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 16 preliminary display data ram (ddram) the display data ram stores pixel data for the lcd. it is a 65-row ((8 page by 8 bits) + 1) by 264-column addressable array. each pixel can be selected when the page and column address is specified. the 65 rows are divided into 8 pages with 8 lines each, and a ninth page with a single line (db0 only). data is read from or written to the 8 lines of each page directly through db0 to db7. the display data of db0 to db7 from the microprocessor correspond to the lcd common lines. the microprocessor can read from and write to ram through the i/o buffer. since the lcd controller operates independently, data can be written into ram at the same time as when data is being displayed, without causing the lcd to flicker. page address circuit this circuit is for providing a page address to the display data ram shown in table 7. it incorporates a 4-bit page address register changed only by the set page instruction. page address 8 (db3 is high, but db2, db1 and db0 are low) is a special ram area for icons, and only display data db0 is valid. when page address is above 8, it is impossible to access the on-chip ram. line address circuit this circuit assigns ddram a line address corresponding to the first line (com1) of the display. therefore, by setting the line address repeatedly, it is possible to scroll the screen and switch the page without changing the contents of the on-chip ram (refer to table 7). it incorporates a 6-bit line address register which can only be changed by the initial display line instruction and a 6-bit counter circuit. at the beginning of each lcd frame, the contents of a register are copied to the line counter which is increased by the cl signal, and generates the line address for transferring the 264-bit ram data to the 100 display data latch circuit. however, display data of icons are not scrolled because the microprocessor cannot access the line address of icons.
65com/132seg driver & controller for 4 g/s stn lcd KS0711 17 preliminary column address circuit the column address circuit has a 9-bit preset counter that provides the column address to the display data ram (shown in table 7). when set column address msb / lsb instruction is issued, 8 bits [y8:y1] are set and lowest bit, y0 is set to ? 0 ? . since this address is increased by 1 at every read or write data instruction, the microprocessor can access the display data continuously. however, the counter is not increased and locked for a non-existing address above 108h. it is unlocked if a column address is set again by the set column address msb / lsb instruction. the column address counter is independent of the page address register. adc select instruction makes it possible to invert the relationship between the column address and the segment outputs. refer to table 6. table 6. segment output direction according to adc seg output seg 0 seg 1 seg 2 seg 3 ...... seg 128 seg 129 seg 130 seg 131 column address [y8:y1] 00h 01h 02h 03h ...... 80h 81h 82h 83h internal column address [y8:y1] 000 hex 001 hex 002 hex 003 hex 004 hex 005 hex 006 hex 007 hex ...... 100 hex 101 hex 102 hex 103 hex 104 hex 105 hex 106 hex 107 hex display data (adc=0) 1 1 1 0 0 0 0 1 ...... 1 0 1 1 0 0 0 1 lcd panel display ...... adc=1 0 1 0 0 1 1 1 0 ...... 0 1 0 0 1 0 1 1 lcd panel display
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 18 preliminary table 7. display data ram addressing page address p3, p2, p1, p0 data column address line address (hex) common output (1/65) common output (1/49) common output (1/33) 0 0 0 0 db0 db1 db2 db3 db4 db5 db6 db7 page0 00 01 02 03 04 05 06 07 com36 com37 com38 com39 com40 com41 com42 com43 com36 com37 com38 com39 com40 com41 com42 com43 - - - - - - - - 0 0 0 1 db0 db1 db2 db3 db4 db5 db6 db7 page1 08 09 0a 0b 0c 0d 0e 0f com44 com45 com46 com47 com48 com49 com50 com51 com44 com45 com46 com47 - - - - - - - - - - - - 0 0 1 0 db0 db1 db2 db3 db4 db5 db6 db7 page2 10 11 12 13 14 15 16 17 com52 com53 com54 com55 com56 com57 com58 com59 - - - - - - - - - - - - - - - - 0 0 1 1 db0 db1 db2 db3 db4 db5 db6 db7 page3 18 19 1a 1b 1c 1d 1e 1f com60 com61 com62 com63 com0 com1 com2 com3 - - - - com0 com1 com2 com3 - - - - com0 com1 com2 com3 0 1 0 0 db0 db1 db2 db3 db4 db5 db6 db7 page4 20 21 22 23 24 25 26 27 com4 com5 com6 com7 com8 com9 com10 com11 com4 com5 com6 com7 com8 com9 com10 com11 com4 com5 com6 com7 com8 com9 com10 com11 0 1 0 1 db0 db1 db2 db3 db4 db5 db6 db7 page5 28 29 2a 2b 2c 2d 2e 2f com12 com13 com14 com15 com16 com17 com18 com19 com12 com13 com14 com15 com16 com17 com18 com19 com12 com13 com14 com15 com16 com17 com18 com19
65com/132seg driver & controller for 4 g/s stn lcd KS0711 19 preliminary note: when the initial display line address is 1ch. 0 1 1 0 db0 db1 db2 db3 db4 db5 db6 db7 page6 30 31 32 33 34 35 36 37 com20 com21 com22 com23 com24 com25 com26 com27 com20 com21 com22 com23 com24 com25 com26 com27 com20 com21 com22 com23 com24 com25 com26 com27 0 1 1 1 db0 db1 db2 db3 db4 db5 db6 db7 page7 38 39 3a 3b 3c 3d 3e 3f com28 com29 com30 com31 com32 com33 com34 com35 com28 com29 com30 com31 com32 com33 com34 com35 com28 com29 com30 com31 - - - - 1 0 0 0 db0 page8 coms coms coms column address [hex] adc = 0 00 01 02 mpu accessible column address (y8~y1) 81 82 83 0 0 0 0 0 1 0 0 2 0 0 3 0 0 4 0 0 5 internal column address (y8~y0) 1 0 2 1 0 3 1 0 4 1 0 5 1 0 6 1 0 7 adc = 1 83 82 81 mpu accessible column address (y8~y1) 02 01 00 1 0 6 1 0 7 1 0 4 1 0 5 1 0 2 1 0 3 internal column address (y8~y1) 0 0 4 0 0 5 0 0 2 0 0 3 0 0 0 0 0 1 lcd output seg 0 seg 1 seg 2 - seg 129 seg 130 seg 131 table 7. display data ram addressing (continued) page address p3, p2, p1, p0 data column address line address (hex) common output (1/65) common output (1/49) common output (1/33)
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 20 preliminary lcd driving circuit oscillator this is a completely on-chip oscillator and its frequency is nearly independent of v dd . this oscillator signal is used in the voltage converter and display timing generation circuit. display timing generator circuit this circuit generates some signals to be used in the lcd. the display clock cl generates a clock to the line counter and a latch signal to the display data latch. the line address of the on-chip ram is generated in synchronization with the display clock (cl) and the 100-bit display data is latched by the display data latch circuit in synchronization with the display clock. the display data which is read to the lcd driver is completely independent of the access to the display data ram from the microprocessor. the display clock generates an lcd ac signal (m) which enables the lcd driver to make an ac drive waveform, and also generates an internal common timing signal and start signal to the common driver. 2-frame ac driver waveforms and the internal timing signal are shown in figure 6. when KS0711 is used in multi-chip mode, the slave chip needs to receive the m, cl, disp signals from the master. table 8 shows the m, cl, and disp status. display data latch circuit this latch circuit temporarily stores the output display data from the display data ram to the lcd driver in each instruction period. this latch circuit is controlled by the display on / off, reverse display on / off and entire display on / off instructions, and the data in the display data ram remains unchanged. frc (frame rate control) and pwm (pulse width modulation) function circuit the KS0711 incorporates an frc function and a pwm function circuit to display a four-level gray scale. the frc function and pwm utilize liquid crystal characteristics whose transmittance is changed by an effective value of applied voltage. the KS0711 provides 4 4-bit palette-registers to assign the desired gray level. these registers are set by the instructions and resetb. table 8. master and slave timing signal status operation mode oscillator on / off m cl disp master on (internal clock used) output output output off (external clock used) output input output slave - input input input
65com/132seg driver & controller for 4 g/s stn lcd KS0711 21 preliminary ? gray scale table of 4 frc (frame rate control) gray scale level msb (db7 to db4) lsb (db3 to db0) white 2nd fr (fr2) 1st fr (fr1) 4th fr (fr4) 3rd fr (fr3) light gray 2nd fr (fr2) 1st fr (fr1) 4th fr (fr4) 3rd fr (fr3) dark gray 2nd fr (fr2) 1st fr (fr1) 4th fr (fr4) 3rd fr (fr3) black 2nd fr (fr2) 1st fr (fr1) 4th fr (fr4) 3rd fr (fr3)
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 22 preliminary ? gray scale table of 3 frc (frame rate control) ? gray scale table of 15 pwm (pulse width modulation) ? gray scale table of 12 pwm (pulse width modulation) gray scale level msb (db7 to db4) lsb (db3 to db0) white 2nd fr (fr2) 1st fr (fr1) x x x x 3rd fr (fr3) light gray 2nd fr (fr2) 1st fr (fr1) x x x x 3rd fr (fr3) dark gray 2nd fr (fr2) 1st fr (fr1) x x x x 3rd fr (fr3) black 2nd fr (fr2) 1st fr (fr1) x x x x 3rd fr (fr3) hex 4-bits pwm (on width) note 0 00 0000 0 (0/15) 1 01 0001 1/15 2 02 0010 2/15 3 03 0011 3/15 4 04 0100 4/15 5 05 0101 5/15 6 06 0110 6/15 7 07 0111 7/15 8 08 1000 8/15 9 09 1001 9/15 10 0a 1010 10/15 11 0b 1011 11/15 12 0c 1100 12/15 13 0d 1101 13/15 14 0e 1110 14/15 15 0f 1111 1(15/15) hex 4-bits pwm (on width) note 0 00 0000 0 (0/12) 1 01 0001 1/12 2 02 0010 2/12 3 03 0011 3/12 4 04 0100 4/12 5 05 0101 5/12 6 06 0110 6/12 7 07 0111 7/12
65com/132seg driver & controller for 4 g/s stn lcd KS0711 23 preliminary note: this area is selected to off level (0/12 level). ? gray scale table of 9 pwm (pulse width modulation) note: this area is selected to off level (0/9 level). 8 08 1000 8/12 9 09 1001 9/12 10 0a 1010 10/12 11 0b 1011 11/12 12 0c 1100 1(12/12) 13 0d 1101 0/12 (note) 14 0e 1110 0/12 (note) 15 0f 1111 0/12 (note) hex 4-bits pwm (on width) note 0 00 0000 0 (0/9) 1 01 0001 1/9 2 02 0010 2/9 3 03 0011 3/9 4 04 0100 4/9 5 05 0101 5/9 6 06 0110 6/9 7 07 0111 7/9 8 08 1000 8/9 9 09 1001 1(9/9) 10 0a 1010 0/9 (note) 11 0b 1011 0/9 (note) 12 0c 1100 0/9 (note) 13 0d 1101 0/9 (note) 14 0e 1110 0/9 (note) 15 0f 1111 0/9 (note) hex 4-bits pwm (on width) note
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 24 preliminary duty ratio: 1/65 figure 6. 2-frame ac driving waveform v0 v1 v4 v ss v0 v1 v4 v ss v0 v1 v3 v ss cl m com0 com1 segn 64 65 1 2 3 4 5 64 65 1 2 3 4
65com/132seg driver & controller for 4 g/s stn lcd KS0711 25 preliminary common output control circuit this circuit controls the relationship between the number of common outputs and the specified duty ratio. shl select instruction specifies the scanning direction of the common output pins. table 9. the relationship between duty ration and common output duty shl common output pins com[0:15] com[16:23] com[24:31] com[32:39] com[40:47] com[48:63] coms 1/33 0 com[0:15] com[16:31] com[32] com[31:16] com[15:0] com[32] 1/49 0 com[0:23] com[24:47] com[48] 1 com[47:24] com[23:0] com[48] 1/65 0 com[0:63] com[64] 1 com[63:0] com[64]
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 26 preliminary lcd driver circuit this driver circuit is configured by a 65-channel common driver and a 132-channel segment driver. this lcd panel driver voltage depends on the combination of display data and m signal. figure 7. segment and common timing com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 s e g 4 s e g 3 s e g 2 s e g 1 s e g 0 |seg1-com0| |seg0-com0| seg2 seg1 seg0 com2 com0 com1 m |v0| |v1| |v2| |v3| |v4| |vss| |v0| |v1| |v2| |v3| |v4| |vss| v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss vdd vss
65com/132seg driver & controller for 4 g/s stn lcd KS0711 27 preliminary power supply circuits the power supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. there are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. they are valid only in master operation and are controlled by power control instruction. for details, refers to ? instruction description ? . table 10 shows the referenced combinations in using power supply circuits. table 10. recommended power supply combinations user setup power control register [vc, vr, vf] v/c circuits v/r circuits v/f circuits vout pin v0 pin v1?v4 pin only the internal power supply circuits are used 1 1 1 on on on open open open only the voltage regulator circuits and voltage follower circuits are used 0 1 1 off on on external input open open only the voltage follower circuits are used 0 0 1 off off on open external input open only the external power supply circuits are used 0 0 0 off off off open external input external input
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 28 preliminary voltage converter circuits these circuits multiply the electric potential between v dd and v ss to 4 or 5 times toward the positive side. boosted voltage is output from the vout pin. figure 8. two / three / four / five times boosting circuit ? two ? three ? four vout c3+ c3 - c2+ c2 - c1+ c1 - dcdc5b v dd v dd v ss v dd c1 c1 gnd vout=2 v dd v ss v dd vout=3 v dd vout c3+ c3 - c2+ c2 - c1+ c1 - dcdc5b v dd v ss v dd v dd c1 c1 c1 gnd v ss v dd - + - + + - + - + - vout c3+ c3 - c2+ c2 - c1+ c1 - dcdc5b v dd v dd vss vout c3+ c3 - c2+ c2 - c1+ c1 - dcdc5b v dd v dd v ss c1 c1 c1 c1 c1 c1 c1 c1 gnd gnd v ss v dd v ss v dd vout=5 v dd v dd vout=4 v dd - + - + + - + - + - + - + - + - gnd ? five
65com/132seg driver & controller for 4 g/s stn lcd KS0711 29 preliminary voltage regulator circuits the function of the internal voltage regulator circuits is to determine the liquid crystal operating voltage, v0, by adjusting the resistors ra and rb within the range of |v0| < |vout|. because vout is the operating voltage of the operational-amplifier circuits shown in figure 9, it is necessary to apply it either internally or externally. for equation 1, we determine v0 by ra, rb and v ev . the ra and rb are connected internally or externally by intrs pin. and v ev (voltage of electronic volume) is determined by equation 2, where the parameter is the value selected by the instruction, ? set reference voltage register ? , within the range 0 to 63. v ref voltage at ta = 25 c is shown in table 11. table 11. v ref voltage at ta = 25 c temp1 temp0 temp. coefficient v ref [v] h h tbd tbd h l tbd tbd l h tbd tbd l l tbd tbd figure 9. internal voltage regulator circuit v01 rb ra -------- + ? ?? v ev [v] = v ev 1 63 a ? () 162 --------------------- ? ? ?? v ref [v] = v ev gnd v ss ra vr rb v0 vout + _ + _ gnd
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 30 preliminary 1) in case of using internal resistors, ra and rb (intrs = ? h ? ) when intrs pin is high, resistor ra is connected internally between vr pin and vss, and rb is connected between v0 and vr. we determine v0 by two instructions, ? regulator resistor select ? and ? set reference voltage ? . figure 10. shows v0 voltage measured by adjusting the internal regulator resistor ratio (rb / ra) and 6-bit electronic volume registers for each temperature coefficient at ta = 25 c. table 12. internal rb/ra ratio depending on 3-bit data (r2 r1 r0) 3-bit data settings (r2 r1 r0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 + (rb/ra) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.4 figure 10. v0 voltage 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 0 8 16 24 32 40 48 63 56 ( 0 1 1 ) ( 0 1 0 ) ( 0 0 1 ) ( 0 0 0 ) ( 1 1 1 ) ( 1 1 0 ) ( 1 0 1 ) ( 1 0 0 ) rb/ra ratio electronic volume level (temperature coefficient = tbd / c) v0
65com/132seg driver & controller for 4 g/s stn lcd KS0711 31 preliminary 2) in case of using external resistors, ra and rb (intrs = ? l ? ) when intrs pin is low, it is necessary to connect external regulator resistor ra between vr and vss, and rb between v0 and vr. example: for the following requirements, 1. lcd driver voltage, v0 = 10v 2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. maximum current flowing ra, rb = 1 m a from equation 1 from equation 1 from requirement 3. from equations equation 3, 4 and 5: ra = 1.69 [ w ] rb = 8.31 [ w ] table 13. shows the range of v0 depending on the above requirements. voltage follower circuits v lcd voltage (v0) is resistively divided into four voltage levels (v1, v2, v3, v4), and those output impedances are converted by the voltage follower for increasing drive capability. table 13. the range of v0 depending electronic volume level 0 ....... 32 ....... 63 v0 7.59 ....... 10.00 ....... 12.43 101 rb ra -------- + ? ?? v ev [v] = v ev 1 6332 ? () 162 ------------------------ ? ? ?? 2.1 = 1.698 [v] = 10 ra + rb ----------------------- 1 m a [] =
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 32 preliminary referenced power supply circuit for driving lcd panel figure 11. when using all lcd power circuits (4-times, v/r: on, v/f: on) v dd ms intrs vout c3+ c3 - c2+ c2 - c1+ c1 - vr v0 v1 v2 v3 v4 vss c1 c1 c2 - + c2 - + c2 - + c2 - + c2 - + c1 c1 v dd ms intrs vout c3+ c3 - c2+ c2 - c1+ c1 - vr v0 v1 v2 v3 v4 vss c1 c1 c2 - + c2 - + c2 - + c2 - + c2 - + c1 c1 ra rb vss - when using internal regulator resistors - when not using internal regulator resistors
65com/132seg driver & controller for 4 g/s stn lcd KS0711 33 preliminary figure 12. when using some lcd power circuits (v/c: off, v/r: on, v/f: on) - when using internal regulator resistors - when not using internal regulator resistors external power supply v dd ms intrs vout c3+ c3 - c2+ c2 - c1+ c1 - vr v0 v1 v2 v3 v4 vss c2 - + c2 - + c2 - + c2 - + c2 - + ra rb vss v dd ms intrs vout c3+ c3 - c2+ c2 - c1+ c1 - vr v0 v1 v2 v3 v4 vss c2 - + c2 - + c2 - + c2 - + c2 - + external power supply
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 34 preliminary figure 13. when using some lcd power circuits (v/c: off, v/r: off, v/f: on) v dd ms intrs vout c3+ c3 - c2+ c2 - c1+ c1 - vr v0 v1 v2 v3 v4 vss c2 - + c2 - + c2 - + c2 - + c2 - + external power supply
65com/132seg driver & controller for 4 g/s stn lcd KS0711 35 preliminary figure 14. when not using any internal lcd power circuits (v/c: off, v/r: off, v/f: off) v dd ms intrs vout c3+ c3 - c2+ c2 - c1+ c1 - vr v0 v1 v2 v3 v4 vss external power supply table 14. value of external capacitance item value unit c1 1.0 to 4.7 m f c2 0.47 to 1.0
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 36 preliminary reset circuit internal function can be initialized by setting resetb to low or reset instruction. when resetb becomes low, following procedure occurs. ? display on / off:off ? entire display on / off: off (normal) ? adc select: off (normal) ? reverse display: off (normal) ? power control register (vc, vr, vf) = (0, 0, 0) ? lcd bias ratio: 1/9 (1/65 duty), 1/8 (1/49 duty), 1/7 (1/33 duty) ? modify-read: off ? shl select: 0 ? static indicator mode: off static indicator register: (s1, s0) = (0, 0) ? display start line: 0 (first) ? column address: 0 ? page address: 0 ? regulator resistor select register: (r2, r1, r0) = (1, 0, 0) ? reference voltage set: off, reference voltage control register: (sv5, sv4, sv3, sv2, sv1, sv0) = (1, 0, 0, 0, 0, 0) ? white mode set: off ? white palette register (wg4, wg3, wg2, wg1, wg0) = (0, 0, 0, 0, 0) ? light gray mode set: off ? light gray palette register (lg4, lg3, lg2, lg1, lg0) = (0, 1, 0, 1, 0) ? dark gray mode set: off ? dark gray palette register (dg4, dg3, dg2, dg1, dg0) = (1, 0, 1, 0, 1) ? black mode set: off ? black palette register (bg4, bg3, bg2, bg1, bg0) = (1, 1, 1, 1, 1)
65com/132seg driver & controller for 4 g/s stn lcd KS0711 37 preliminary when reset instruction is issued, following procedure is occurs. ? modify-read: off ? static indicator mode: off static indicator register: (s1, s0) = (0, 0) ? shl select: 0 (normal) ? display start line: 0 (first) ? column address: 0 ? page address: 0 ? regulator resistor select register: (r2, r1, r0) = (1, 0, 0) ? reference voltage set: off reference voltage control register (sv5, sv4, sv3, sv2, sv1, sv0) = (1, 0, 0, 0, 0, 0) ? white mode set: off ? white palette register (wg4, wg3, wg2, wg1, wg0) = (0, 0, 0, 0, 0) ? light gray mode set: off ? light gray palette register (lg4, lg3, lg2, lg1, lg0) = (0, 1, 0, 1, 0) ? dark gray mode set: off ? dark gray palette register (dg4, dg3, dg2, dg1, dg0) = (1, 0, 1, 0, 1) ? black mode set: off ? black palette register (bg4, bg3, bg2, bg1, bg0) = (1, 1, 1, 1, 1) no instruction except read status can be accepted, while resetb is low or reset instruction is being executed. reset status appears at db4. after db4 becomes low, any instruction can be accepted. resetb pin must be connected to the reset pin of mpu. initialize the mpu and this lsi at the same time. the initialization by resetb pin is essential before use.
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 38 preliminary instruction description table 15. instruction table instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description read display data 1 1 read data read data from ddram write display data 1 0 write data write data into ddram read status 0 1 busy adc on/ off resetb 0 0 0 0 read the internal status display on/off 0 0 1 0 1 0 1 1 1 don turn on/off lcd panel when don=0, display is off when don=1, display is on initial display line 0 0 0 1 st5 st4 st3 st2 st1 st0 specify ddram line for com0 set reference voltage mode 0 0 1 0 0 0 0 0 0 1 set reference voltage mode set reference voltage register 0 0 sv5 sv4 sv3 sv2 sv1 sv0 set reference voltage register set page address 0 0 1 0 1 1 p3 p2 p1 p0 set page address set column address msb 0 0 0 0 0 1 y8 y7 y6 y5 set column address msb set column address lsb 0 0 0 0 0 0 y4 y3 y2 y1 set column address lsb adc select 0 0 1 0 1 0 0 0 0 adc select seg output direction when adc=0 normal direction (seg0 ? seg131) when adc=1 reverse direction (seg131 ? seg0) normal / reverse display 0 0 1 0 1 0 0 1 1 rev select normal/reverse display when rev=0 normal when rev=1 reverse entire display on/off 0 0 1 0 1 0 0 1 0 eon select normal display / entire display on when eon=0, normal display when eon=1, entire display on lcd bias select 0 0 1 0 1 0 0 0 1 bias select lcd bias when bias=0, 1/7 when bias=1, 1/9 set modify-read 0 0 1 1 1 0 0 0 0 0 set modify-read mode reset modify-read 0 0 1 1 1 0 1 1 1 0 release modify-read mode reset 0 0 1 1 1 0 0 0 1 0 initialize internal functions shl select 0 0 1 1 0 0 shl select com output direction when shl=0 normal direction (com0 ? com63) when shl=1 reverse direction (com63 ? com0) power control 0 0 0 0 1 0 1 vc vr vf control power circuit operation regulator resistor select 0 0 0 0 1 0 0 r2 r1 r0 select resistance ratio of the regulator resistor
65com/132seg driver & controller for 4 g/s stn lcd KS0711 39 preliminary note : ? ? = don ? t care set static indicator mode 0 0 1 0 1 0 1 1 0 sm set static indicator mode when sm=0, off when sm=1, on set static indicator register 0 0 s1 s0 set static indicator register power save ? ? ? ? ? ? ? ? ? ? compound command of display off and entire display on set white mode and 1st/2nd frame, set pulse width 0 0 1 1 1 1 1 0 0 0 set white mode and 1st/2nd frame 0 0 wb3 wb2 wb1 wb0 wa3 wa2 wa1 wa0 set white 1st/2nd register set white mode and 3rd/4th frame, set pulse width 0 0 1 1 1 1 1 0 0 1 set white mode and 3rd/4th frame 0 0 wd3 wd2 wd1 wd0 wc3 wc2 wc1 wc0 set white 3rd/4th register set light gray mode and 1st/2nd frame, set pulse width 0 0 1 1 1 1 1 0 1 0 set light gray mode and 1st/ 2nd frame 0 0 lb3 lb2 lb1 lb0 la3 la2 la1 la0 set light gray 1st/2nd register set light gray mode and 3rd/4th frame, set pulse width 0 0 1 1 1 1 1 0 1 1 set light gray mode and 3rd/ 4th frame 0 0 ld3 ld2 ld1 ld0 lc3 lc2 lc1 lc0 set light gray 3rd/4th register set dark gray mode and 1st/2nd frame, set pulse width 0 0 1 1 1 1 1 1 0 0 set dark gray mode and 1st/ 2nd frame 0 0 db3 db2 db1 db0 da3 da2 da1 da0 set dark gray 1st/2nd register set dark gray mode and 3rd/4th frame, set pulse width 0 0 1 1 1 1 1 1 0 1 set dark gray mode and 3rd/ 4th frame 0 0 dd3 dd2 dd1 dd0 dc3 dc2 dc1 dc0 set dark gray 3rd/4th register set black mode and 1st/2nd frame, set pulse width 0 0 1 1 1 1 1 1 1 0 seg black mode 1st/2nd frame 0 0 bb3 bb2 bb1 bb0 ba3 ba2 ba1 ba0 seg black 1st/2nd register set black mode and 3rd/4th frame, set pulse width 0 0 1 1 1 1 1 1 1 1 set black mode and 3rd/4th frame 0 0 bd3 bd2 bd1 bd0 bc3 bc2 bc1 bc0 set black 3rd/4th register set frc and pwm mode 0 0 1 1 1 1 0 frc pwm 1 pwm 0 frc (1: 3frc, 0: 4frc) pwm1 pwm0 0 0 9pwm 0 1 9pwm 1 0 12pwm 1 1 15pwm table 15. instruction table (continued) instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 40 preliminary read display data you can read the 8-bit data from display data ram, specified by the column address and page address, using this instruction. as the column address is increased by 1 automatically after each instruction, the microprocessor can read data from the addressed page continuously. a dummy read is required after loading an address into the column address register. display data cannot be read through the serial interface. write display data you can write the 8-bit data of display data from the microprocessor to the ram location specified by the column address and page address. the column address is increased by 1 automatically so that the microprocessor can write data to the addressed page continuously. read status indicates the internal status conditions. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 1 busy adc on/off resetb 0 0 0 0 flag description busy the device is busy when in internal operation or reset. any instruction is rejected until busy goes low. 0 = chip is active. 1 = chip is busy. adc indicates the relationship between ram column address and segment driver. 0 = reverse direction (seg131 ? seg0), 1 = normal direction (seg0 ? seg131) on/off indicates display on/off status. 0 = display on 1 = display off resetb indicates the initialization is in progress by resetb signal. 0 = chip is active. 1 = chip is being reset.
65com/132seg driver & controller for 4 g/s stn lcd KS0711 41 preliminary display on/off turns the display on or off initial display line sets the line address of display ram to determine the initial display line. the ram display data is displayed at the top row (com0) of the lcd panel. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 1 don don 1 display on 0 display off rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 st5 st4 st3 st2 st1 st0 st5 st4 st3 st2 st1 st0 line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 42 preliminary reference voltage select set reference voltage mode set reference voltage register instruction consists of two bytes. the first byte sets the reference voltage mode, and the second one updates the contents of the reference voltage register. after the second instruction, the reference voltage mode is released. set page address sets the page address of display data ram from the microprocessor into the page address register. any ram data bit can be accessed when its page address and column address are specified. along with the column address, the page address defines the address of the display ram to write or read display data. changing the page address doesn't affect the display status. set column address set column address msb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 1 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 sv5 sv4 sv3 sv2 sv1 sv0 sv5 sv4 sv3 sv2 sv1 sv0 reference voltage ( a ) 0 0 0 0 0 0 0 : : : : : : : 1 1 1 1 1 1 63 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 p3 p2 p1 p0 p3 p2 p1 p0 page 0 0 0 0 0 0 0 0 1 1 : : : 0 1 1 1 7 1 0 0 0 8 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 y8 y7 y6 y5
65com/132seg driver & controller for 4 g/s stn lcd KS0711 43 preliminary set column address lsb sets the column address of display ram from the microprocessor into the column address register. along with the page address, the column address defines the address of the display ram to write or read display data. when the microprocessor reads or writes display data to or from display ram, column addresses are automatically increased, starting with the address stored in the column address register and continuously rotating right. adc select changes the relationship between the ram column address and segment driver. the direction of segment driver output pins can be reversed by software, making the ic layout flexible in an lcd module assembly. reverse display on / off reverses the display status on the lcd panel without rewriting the contents of the display data ram. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 y4 y3 y2 y1 y8 y7 y6 y5 y4 y3 y2 y1 column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 : : : : : : : : : 1 0 0 0 0 0 1 0 260 1 0 0 0 0 0 1 1 262 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 adc adc 0 normal direction (seg0 ? seg131) 1 reverse direction (seg131 ? seg0) rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 1 rev rev ram bit data = ? 1 ? ram bit data = ? 0 ? 0 (normal) lcd pixel is illuminated lcd pixel is not illuminated 1 (reverse) lcd pixel is not illuminated lcd pixel is illuminated
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 44 preliminary entire display on / off forces whole lcd points to be turned on regardless of the contents of the display data ram. at this time, the contents of the display data ram are held. this instruction has priority over the reverse display on / off instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 eon eon 0 normal display 1 entire display on
65com/132seg driver & controller for 4 g/s stn lcd KS0711 45 preliminary lcd bias select selects the lcd bias ratio of the voltage required for driving the lcd. set modify-read this instruction stops the automatic increment of the column address by read display data instruction, but the column address is still increased by the write display data. it also reduces the load of the microprocessor when the data of a specific area is repeatedly changed during cursor blinking or at other times. this mode is cancelled by the reset modify-read instruction. reset modify-read this instruction cancels the modify read mode, and makes the column address return to its initial value just before the set modify read instruction starts. reset this instruction resets the initial display line, column address, page address, and common output status select to their initial status, but does not affect the contents of the display data ram. this instruction cannot initialize the lcd power supply which is initialized by the resetb pin. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 bias duty ratio lcd bias bias = 1 bias = 0 1/65 1/9 1/7 1/49 1/8 1/6 1/33 1/6 1/5 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 0 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 0
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 46 preliminary shl select com output scanning direction is selected by this instruction which determines the lcd driver output status. power control selects one of eight power circuit functions by using a 3-bit register. an external power supply and part of internal power supply functions can be used simultaneously. regulator resistor select selects the resistance ratio of the resistor used in the voltage regulator. see the voltage regulator section in power supply circuit. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 shl shl 0 normal direction (com0 ? com63) 1 reverse direction (com63 ? com0) rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 1 vc vr vf vc, vr, vf indicates whether the voltage converter / regulator / follower turns on or not 0 off 1 on rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 1 r2 r1 r0 r2 - 0 [rb/ra] ratio 0 0 0 small 0 0 1 : : : : : 1 1 0 : 1 1 1 large
65com/132seg driver & controller for 4 g/s stn lcd KS0711 47 preliminary set static indicator state ? set static indicator mode (on/off) instruction consists of two bytes. the first byte instruction (set static indicator mode) enables the second byte instruction (set static indicator register) to be valid. the first byte sets the static indicator on/off. when it is on, the second byte updates the contents of the static indicator register without issuing any other instruction, and this static indicator state is released after setting the data of the indicator register. ? set static indicator register rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 0 sm sm 0 static indicator off 1 static indicator on rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 s1 s0 s1 s0 status of static indicator output 0 0 off 1 1 on (always on)
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 48 preliminary power save (compound instruction) if the entire display on / off instruction is issued during the display off state, KS0711 enters the power save status to reduce the power consumption to the static power consumption value. according to the status of static indicator mode, power save is entered to either sleep mode or. when static indicator mode is on, standby mode is issued. when off, sleep mode is issued. power save mode is released by the display on & entire display off instruction. figure 15. power save (compound instruction) release standby mode power save off ( compound instruction ) [ entire display off ] release sleep mode power save off ( compound instruction ) [ entire display off ] [ static indicator on ] standby mode [ oscillator circuit : on] [ lcd power supply circuit : off ] [ all com/seg outputs : vss ] [ consumption current : < 10 m a ] sleep mode [ oscillator circuit : off ] [ lcd power supply circuit : off ] [ all com/seg outputs : vss ] [ consumption current : < 2 m a ] power save ( compound instruction ) [ display off ] [ entire display on ] static indicator off static indicator on
65com/132seg driver & controller for 4 g/s stn lcd KS0711 49 preliminary set gray scale mode & register set gray scale mode instruction consists of two bytes. the first byte sets gray scale mode, and the second one updates the contents of the gray scale register without issuing any other instruction. gm2, gm1, gm0 set gray scale register note: 1. ga3=wa3, la3, da3, ba3, ga2=wa2, la2, da2, ba2, ga1=wa1, la1, da1, ba1, ga0=wa0, la0, da0, ba0 2. gb3=wb3, lb3, db3, bb3, gb2=wb2, lb2, db2, bb2, gb1=wb1, lb1, db1, bb1, gb0=wb0, lb0, db0, bb0 3. gc3=wc3, lc3, dc3, bc3, gc2=wc2, lc2, dc2, bc2, gc1=wc1, lc1, dc1, bc1, gc0=wc0, lc0, dc0, bc0 4. gd3=wd3, ld3, dd3, bd3, gd2=wd2, ld2, dd2, bd2, gd1=wd1, ld1, dd1, bd1, gd0=wd0, ld0, dd0, bd0 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1 1 gm2 gm1 gm0 0 0 0 in case of setting white mode and 1st/2nd frame 0 0 1 in case of setting white mode and 3rd/4th frame 0 1 0 in case of setting light gray mode and 1st/2nd frame 0 1 1 in case of setting light gray mode and 3rd/4th frame 1 0 0 in case of setting dark gray mode and 1st/2nd frame 1 0 1 in case of setting dark gray mode and 3rd/4th frame 1 1 0 in case of setting black mode and 1st/2nd frame 1 1 1 in case of setting black mode and 3rd/4th frame rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 gb3 gb2 gb1 gb0 ga3 ga2 ga1 ga0 0 0 gd3 gd2 gd1 gd0 gc3 gc2 gc1 gc0 ga3, gb3, gc3, gd3 ga2, gb2, gc2, gd2 ga1, gb1, gc1, gd1 ga0, gb0, gc0, gd0 degree of contrast 0 0 0 0 white 0 0 0 1 : : : : : : 1 1 1 0 : 1 1 1 1 black
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 50 preliminary set pwm & frc rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1 0 frc pwm1 pwm0 frc (1: 3fc, 0: 4frc), pwm1 pwm0 (00: 9pwm, 01: 9pwm, 10: 12pwm, 11: 15pwm)
65com/132seg driver & controller for 4 g/s stn lcd KS0711 51 preliminary referential instruction setup flow ? initializing with the built-in power supply circuits figure 16. initializing with the built-in power supply circuits end of initialization waiting for stabilizing the lcd power levels user lcd power setup by internal instructions [ power control ] [ regulator resistor select ] [reference voltage register set ] user application setup by internal instructions [ adc select ] [ shl select ] [lcd bias select ] start of initialization resetb pin = ? h ? user system setup by external pins waiting for stabilizing the power power on ( vdd - vss ) keeping the resetb pin = ? l ? user system setup by external pins
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 52 preliminary ? initializing without the built-in power supply circuits figure 17. initializing without the built-in power supply circuits end of initialization waiting for stabilizing the lcd power levels release power save user lcd power setup by internal instructions [ regulator resistor select ] [reference voltage register set ] user application setup by internal instructions [ adc select ] [ shl select ] [lcd bias select ] start of initialization resetb pin = ? h ? set power save waiting for stabilizing the power power on ( vdd - vss ) keeping the resetb pin = ? l ? user system setup by external pins
65com/132seg driver & controller for 4 g/s stn lcd KS0711 53 preliminary ? data displaying ? power off figure 18. data displaying figure 19. power off end of initialization write display on/off by instruction [ display on/off ] display data ram addressing by instruction [ initial display line ] [ set page address ] [ set column address ] end of data display turn display on/off by instruction [ display on/off ] power off ( vdd - vss ) set power save by instruction optional status
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 54 preliminary specifications absolute maximum ratings notes: 1. v dd and v lcd are based on v ss = 0 v . 2. voltages v0 3 v1 3 v2 3 v3 3 v4 3 v ss must always be satisfied ( v lcd = v0 - v ss ). 3. if supply voltage exceeds its absolute maximum range, this lsi may be damaged permanently. use this lsi under specified electrical characteristic conditions during general operation. otherwise, lsi malfunction or reduced lsi reliability may result. table 16. absolute maximum ratings parameter symbol rating unit supply voltage range v dd - 0.3 to + 7.0 v v lcd + 0.3 to + 17.0 input voltage range v in - 0.3 to v dd + 0.3 operating temperature range t opr - 40 to + 85 c storage temperature range t str - 55 to + 125
65com/132seg driver & controller for 4 g/s stn lcd KS0711 55 preliminary dc characteristics table 17. dc characteristics (v ss = 0v, v dd = 2.4v to 5.5v, ta = - 40 to 85 c) item symbol condition min. typ. max. unit pin used operating voltage (1) v dd - 2.4 - 5.5 v v dd (1) operating voltage (2) v 0 - 4.0 - 15.0 v 0 (2) input voltage high v ih - 0.8v dd - v dd (3) low v il - v ss - 0.2v dd output voltage high v oh i oh = - 0.5ma 0.8v dd - v dd (4) low v ol i ol = 0.5ma v ss - 0.2v dd input leakage current i il v in = v dd or v ss - 1.0 - + 1.0 m a (5) output leakage current i oz v in = v dd or v ss - 3.0 - + 3.0 (6) lcd driver on resistance r on ta = 25 c, v0 = 8v - 2.0 3.0 k w segn comn (7) operating frequency f osc ta = 25 c, rext = tbd tbd tbd tbd khz ossck voltage converter input voltage v dd 2 2.4 - 5.5 v v dd 3 2.4 - 5.0 4 2.4 - 3.75 5 2.4 - 3.0 voltage converter output voltage vout 2/ 3/ 4/ 5 voltage conversion (no-load) 95 99 - % vout voltage regulator operating voltage vout - 4.0 - 15.0 v vout voltage follower operating voltage v0 - 4.0 - 15.0 v0 (8) reference voltage v ref0 to v ref3 ta = 25 c tbd tbd tbd tbd v (9) tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd dynamic current consumption (1): when the built-in circuits are off (at operate mode). dynamic current consumption (1) i dd1 vdd = 3.0v, v0 - vss = 8.0v, built-in power circuit is off (operate mode) - - 50 m a (10) dynamic current consumption (2): when the built-in circuits are on (at operate mode). dynamic current consumption (2) i dd2 vdd = 3.0v, triple boosting, v0 - vss = 8.0v, built-in power circuit is on (operate mode), normal mode - - 150 m a (10)
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 56 preliminary notes: 1. though a wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from mpu. 2. when an external power supply is applied. 3. cs1b, cs2, rs, db0 to db7, e_rd, rw_wr, resetb, ms, c68, ps, intrs, hpmb, temp0, temp1, dcdc5b, cls, cl, m, disp pins 4. db0 - db7, m, frs, disp, cl pins 5. cs1b, cs2, rs, db0 to db7, e_rd, rw_wr, resetb, ms, c68, ps, intrs, hpmb, temp0, temp1, dcdc5b, cls, cl, m, disp pins 6. applies when the db0 to db7, m, disp, and cl pins are in high impedance. 7. resistance value when 0.1[ma] is applied during the on status of the output pin segn or comn. r on = d v / 0.1 [k w ] ( d v: voltage change when 0.1[ma] is applied in the on status.) 8. the voltage regulator circuit adjusts v0 within the voltage follower operating voltage range. 9. on-chip reference voltage source of the voltage regulator circuit to adjust v0. 10. applies to the case where the on-chip oscillation circuit is used and no access is made from the mpu. the current consumption does not include the current of the lcd panel capacity, wiring capacity, etc. dynamic current consumption (3): when the built-in power is off (at access mode). dynamic current consumption (3) i dd3 vdd = 3.0v, v0 - vss = 8.0v, f cyc = 1mhz, built-in power circuit is off (operate mode) - - 1 ma current consumption during power save mode during sleep i dds1 sleep mode - - 2.0 m a during standby i dds2 standby mode - - 10.0 m a table 17. dc characteristics (continued) (v ss = 0v, v dd = 2.4v to 5.5v, ta = - 40 to 85 c) item symbol condition min. typ. max. unit pin used
65com/132seg driver & controller for 4 g/s stn lcd KS0711 57 preliminary ac characteristics (v dd = 2.4v to 3.3v, ta = - 40 to + 85 c) (v dd = 4.5v to 5.5v, ta = - 40 to + 85 c) figure 20. read / write characteristics (8080-series microprocessor) item signal symbol min. typ. max. unit remark address setup time address hold time rs t as80 t ah80 13 17 - - ns - system cycle time rs t cy80 400 - - ns - pulse width (wr) rw_wr t pw80(w) 55 - - ns - pulse width (rd) e_rd t pw80(r) 125 - - ns - data setup time data hold time db0 to db7 t ds80 t dh80 35 13 - - ns - read access time output disable time t acc80 t od80 - 10 - - 125 90 ns ns c l = 100pf item signal symbol min. typ. max. unit remark address setup time address hold time rs t as80 t ah80 10 10 - - ns - system cycle time rs t cy80 150 - - ns - pulse width (wr) rw_wr t pw80(w) 25 - - ns - pulse width (rd) e_rd t pw80(r) 65 - - ns - data setup time data hold time db0 to db7 t ds80 t dh80 18 10 - - ns - read access time output disable time t acc80 t od80 - 10 - - 65 45 ns ns c l = 100pf t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pw80(r) , t pw80(w) t cy80 t ah80 t as80 db0-db7 ( write ) db0-db7 ( read) rd, wr cs1b (cs2=1) rs
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 58 preliminary (v dd = 2.4v to 3.3v, ta = - 40 to + 85 c) (v dd = 4.5v to 5.5v, ta = - 40 to + 85 c) figure 21. read/write characteristics (6800-series microprocessor) item signal symbol min. typ. max. unit remark address setup time address hold time rs t as68 t ah68 13 17 - - ns - system cycle time rs t cy68 400 - - ns - data setup time data hold time db0 to db7 t ds68 t dh68 35 13 - - ns - access time output disable time t acc68 t od68 - 10 - - 125 90 ns c l = 100pf enable pulse width read write e_rd t pw68(r) t pw68(w) 125 55 - - - - item signal symbol min. typ. max. unit remark address setup time address hold time rs t as68 t ah68 10 10 - - ns - system cycle time rs t cy68 150 - - ns - data setup time data hold time db0 to db7 t ds68 t dh68 18 10 - - ns - access time output disable time t acc68 t od68 - 10 - - 65 45 ns ns c l = 100pf enable pulse width read write e_rd t pw68( r ) t pw68( w) 65 25 - - - - t dh68 t od68 t ds68 t acc68 0.9v dd 0.1v dd t pw68(r) , t pw68(w) t cy68 t ah68 t as68 db0-db7 ( write ) db0-db7 ( read) e cs1b (cs2=1) rs
65com/132seg driver & controller for 4 g/s stn lcd KS0711 59 preliminary (v dd = 2.4v to 3.3v, ta = - 40 to + 85 c) (v dd = 4.5v to 5.5v, ta = - 40 to + 85 c) figure 22. serial interface characteristics item signal symbol min. typ. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) t cys t whs t wls 450 180 135 - - ns address setup time address hold time rs t ass t ahs 90 360 - - ns data setup time data hold time db7(sid) t dss t dhs 90 90 - - ns cs1b setup time cs1b hold time cs1b t css t chs 55 180 - - ns item signal symbol min. typ. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) t cys t whs t wls 225 90 70 - - ns address setup time address hold time rs t ass t ahs 45 180 - - ns data setup time data hold time db7 (sid) t dss t dhs 45 45 - - ns cs1b setup time cs1b hold time cs1b t css t chs 25 90 - - ns t dhs t dss t whs 0.9v dd 0.1v dd t wls t cys t ahs t ass t chs t css db7 ( sid ) db6 ( sclk ) rs cs1b (cs2 = 1 )
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 60 preliminary (v dd = 2.4v to 3.3v, ta = - 40 to + 85 c) (v dd = 4.5v to 5.5v, ta = - 40 to + 85 c) (v dd = 2.4v to 3.3v, ta = - 40 to + 85 c) (v dd = 4.5v to 5.5v, ta = - 40 to + 85 c) figure 23. reset input timing item signal symbol min. typ. max. unit reset low pulse width resetb t rw 900 - - ns item signal symbol min. typ. max. unit reset low pulse width resetb t rw 450 - - ns figure 24. display control output timing item signal symbol min. typ. max. unit m delay time m t dm - 13 70 ns item signal symbol min. typ. max. unit m delay time m t dm - 10 35 ns t rw resetb t dm cl m
65com/132seg driver & controller for 4 g/s stn lcd KS0711 61 preliminary reference applications microprocessor interface figure 25. in case of interfacing with the 6800_series (ps = ? h ? , c68 = ? h ? ) figure 26. in case of interfacing with the 8080-series (ps = ? h ? , c 68 = ? l ? ) figure 27. in case of serial interface (ps = ? l ? , c68 = ? h/l ? ) db0~db7 resetb v dd v dd rw e rs cs2 cs1b 6800-series microprocessor KS0711 cs1b cs2 rs e_rd rw_wr db0 ~ db7 resetb c68 ps db0~db7 resetb v dd v ss /wr /rd rs cs2 cs1b 8080-series microprocessor KS0711 cs1b cs2 rs e_rd rw_wr db0 ~ db7 resetb c68 ps db0~db5 resetb open v ss v ss or v dd sclk sid rs cs2 cs1b microprocessor KS0711 cs1b cs2 rs db7(sid) db6(sclk) resetb db0 ~ db5 c68 ps
KS0711 65com/132seg driver & controller for 4 g/s stn lcd 62 preliminary connections between ks0717 and lcd panel single-chip structure (1/55 duty configurations) shl = 1, adc = 1 ? d ? ? ggggggggggggggggggggg ggggggggggggggggggggg ggggggggggggggggggggg ggggggggggggggggggggg ggggggggggggggggggggg ? a ? * coms com0 : com31 com32 : com63 coms seg131 .............. seg0 KS0711 ( bottom view ) 65 132 pixels shl = 1, adc = 0 shl = 0, adc = 1 ? d ? ? ggggggggggggggggggggg ggggggggggggggggggggg ggggggggggggggggggggg ggggggggggggggggggggg ggggggggggggggggggggg ? a ? * 65 132 pixels coms com0 : com31 com32 : com63 coms seg0 ............ seg131 KS0711 ( top view ) ? d ? ? ggggggggggggggggggggg ggggggggggggggggggggg ggggggggggggggggggggg ggggggggggggggggggggg ggggggggggggggggggggg ? a ? * 65 132 pixels coms com63 : com32 com31 : com0 coms seg131 ............. seg0 KS0711 ( top view ) shl = 0, adc = 0 ? d ? ? ggggggggggggggggggggg ggggggggggggggggggggg ggggggggggggggggggggg ggggggggggggggggggggg ggggggggggggggggggggg ? a ? * com31 : com0 coms coms com63 : com32 seg0 .............. seg131 KS0711 ( bottom view ) 65 132 pixels

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