View 25759_804709.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

revision guide for amd athlon tm 64 and amd opteron tm processors 25759 publication # 3.09 revision: september 2003 issue date:
? 2003 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. (?amd?) products. amd makes no represen tations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descrip tions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. excep t as set forth in amd?s standard terms and conditions of sale, amd assu mes no liability whatsoever, an d disclaims any express or implied warranty, relating to its products including, but no t limited to, the implied warranty of merchantability, fitness for a particular purpos e, or infringement of any intellectual prop- erty right. amd?s products are not designed, intended, aut horized or warranted for use as components in systems intended for surgical implant into th e body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd?s product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice. trademarks amd, the amd arrow logo, amd athlon, amd opteron, and combinations thereof, and 3dnow!, are trademarks of advanced micro devices, inc. hypertransport is a licensed trademark of the hypertransport technology consortium. other product names used in this publicati on are for identification purposes only and ma y be trademarks of their respective com panies.
revision history 3 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 revision history date revision description september 2003 3.09 added amd athlon 64, mobile amd athlon 64, and amd athlon 64 fx information; revised erratum #91. corrected erratum #77. august 2003 3.07 added erratum #95, #97, and #98; modified description in erratum #94; added c0 silicon information. june 2003 3.05 added erratum #94. may 2003 3.03 added erratum #92. april 2003 3.01 initial public release.
4 revision history 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors
5 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 revision guide for amd athlon tm 64 and amd opteron tm processors the purpose of the revision guide for amd athlon? 64 and amd opteron? processors is to communicate updated pr oduct information to designers of computer systems and software developers. this revision guide includ es information on the following products: amd athlon? 64 processor mobile amd athlon? 64 processor ? in cludes desktop replacement (dtr) amd athlon? 64 fx processor amd opteron? processor this guide consists of three major sections: revision determination: this section, starting on page 6, desc ribes the mechanism by which the current revision of the part is identified. product errata: this section, starting on page 7, provides a detailed description of product errata, including potential effect s on system operation and suggested workarounds. an erratum is defined as a deviation from the product?s specification, and as such may cause the behavior of the processor to deviate from the published specifications. documentation support: this section, starting on page 49, pr ovides a listing of available technical support resources. revision guide policy occasionally, amd identifies product errata that cause the proce ssor to deviate from published specifications. descriptions of iden tified product errata are designed to assist system and software designers in using the processors described in this revision guide. this revision guide may be updated periodically.
6 revision determination 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors revision determination figure 1 shows the format of the value returned in eax by cpuid function 1. figure 1. format of cpuid va lue returned by function 1 table 1 shows the identification number returned by the cpuid instruction for each revision of the processor. table 1. cpuid values for revisions of the processors revision cpuid function 1 eax value amd opteron? processor amd athlon? 64 processor amd athlon? 64 fx processor mobile amd athlon? 64 processor sh7-b3 00000f51h n/a n/a n/a sh7-c0 00000f58h 00000f48h 00000f58h 00000f48h 31 28 27 20 19 16 15 12 11 8 7 4 3 0 reserved (zero) extended family extended model reserved (zero) family model stepping reserved 31?28 27?20 19?16 15?12 11?8 7?4 3?0 31 28 27 20 19 16 15 12 11 8 7 4 3 0 reserved (zero) extended family extended model reserved (zero) family model stepping reserved 31?28 27?20 19?16 15?12 11?8 7?4 3?0
product errata 7 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 product errata this section documents product errata for the pro cessors. a unique tracking number for each erratum has been assigned within this document for user convenience in tracking the errata within specific revision levels. table 2 cross-refere nces the revisions of the part to each erratum. an ?x? indicates that the erratum applies to the revision. the absen ce of an ?x? indicates that the erratum does not apply to the revision. an ? * ? indicates advance information that the erratum has been fixed but not yet verified. ?no fix planned? indicates that no fix is planned for current or future revisions of the processor. note: there may be missing errata numbe rs. errata that have been resolved from early revisions of the processor have been deleted, and errata that have been reconsidered may have been deleted or renumbered. table 2. cross-reference of pr oduct revision to errata no. errata description revision number sh7-b3 sh7-c0 1 inconsistent global page m appings can lead to machine check error no fix planned 51 arbitrated interrupt with illegal vector sets apic error bit in all processors x x 57 some data cache tag eviction errors are reported as snoop errors no fix planned 58 memory latency with processor power states x 60 single machine check error may report overflow no fix planned 61 real mode rdpmc with illegal ecx may cause unpredictable operation x 62 task gates with breakpoints enabled may cause unexpected faults x 63 tlb flush filter causes coherency problem in multiprocessor systems x 64 single step across i/o smi skips one debug trap x 65 uncorrectable nb machine check error may disrupt power management x 66 upstream read response delayed by downstream posted writes x 68 disable dqs hysteresis bit not readable x 69 multiprocessor coherency problem with hardware prefetch mechanism x 71 rsm from smm with paging enabled may deadlock x 74 registered dimm exit-self-refresh requirements not met x 75 apic timer accuracy across power management events no fix planned 76 apic timer undercounts in divide-by-8 low power mode x 77 long mode callf or jmpf may fail to signal gp when callgate descriptor is beyond gdt/ldt limit no fix planned
8 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 78 apic interrupt latency with c2 enabled x x 79 power management limitations above 1.50v x x 80 registered dimm initialization requirements not met x 81 cache coherency problem with hardware prefetching and streaming stores x 82 certain faults on far transfer instructions in 64-bit mode save incorrect rip x 83 dc machine check extended error code bit not writeable x x 85 insufficient delay between memclk startup and cke assertion during resume from s3 no fix planned 86 dram data masking feat ure can cause ecc failures x 88 swapgs may fail to read correct gs base x x 89 potential deadlock with locked transactions no fix planned 90 false ic machine check overflow error logged on reset x x 91 software prefetches may report a page fault x x 92 deadlock in multi-processor systems may occur when earlier operations prevent an older store from writing data xx 93 rsm auto-halt restart returns to incorrect rip x 94 sequential prefetch feature may cause incorrect processor operation x x 95 ret instruction may return to incorrect eip x x 96 increased memory latency during p-state changes x x 97 128-bit streaming stores may cause coherency failure x 98 ldtstop assertion may be missed x table 2. cross-reference of product revision to errata (continued) no. errata description revision number sh7-b3 sh7-c0
product errata 9 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 table 3 cross-references the errata to each processor segm ent. an empty cell si gnifies that the erratum does not apply to the processor segment. ?x? signi fies that the erratum a pplies to the processor segment. ?n/a? signifies that the erratum does not apply to the processor se gment due to the silicon revision. table 3. cross-reference of er rata to processor segments errata number amd opteron? processor amd athlon? 64 processor mobile amd athlon? 64 processor amd athlon? 64 fx processor 1xxxx 51 x 57xxxx 58 x n/a n/a n/a 60xxxx 61 x n/a n/a n/a 62 x n/a n/a n/a 63 x 64 x n/a n/a n/a 65 x n/a n/a n/a 66 x n/a n/a n/a 68 x n/a n/a n/a 69 x 71 x n/a n/a n/a 74 x n/a n/a n/a 75xxxx 76 x n/a n/a n/a 77xxxx 78xxxx 79xxxx 80 x n/a n/a 81 x n/a n/a n/a 82 x n/a n/a n/a 83xxxx 85xxxx 86xxxx 88xxxx 89xxxx 90xxxx 91xxxx
10 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 92 x 93xxxx 94xxxx 95xxxx 96 x x 97xxxx 98xxxx table 3. cross-reference of errata to processor segm ents (continued) errata number amd opteron? processor amd athlon? 64 processor mobile amd athlon? 64 processor amd athlon? 64 fx processor
product errata 11 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 1 inconsistent global page mappings can lead to machine check error description if the same linear to physical mapping exists in multiple cr3 contexts, and that mapping is marked global in one context and not global in another cont ext, then a machine check error may be reported by the tlb error detection logic (depending on th e specific access patter n and tlb replacements encountered). potential effect on system in the somewhat unlikely event that all required c onditions are present (incl uding the effects of the tlb replacement policy), then an unexpected mach ine check error may be reported. if the erratum occurs in the instruction cache tlb (l1 or l2), th e apparent error is logge d and corrected. if the erratum occurs in the data cache tlb (l1 or l2), the apparent error is logged and reported as an uncorrectable machine check error. suggested workaround if the described software scenario can be avoided, th is erratum will not occur (i.e., if software never maps the same linear page global in one context and not global in another context). if the software scenario cannot be avoided, two othe r potential workarounds are possible: 1. disable tlb error reporting in the machine ch eck architecture (or disable the machine check architecture entirely). refer to the bios and kernel developer's guide for amd athlon tm 64 and amd opteron tm processors, order# 26094, for information on ho w to program the machine check architecture. 2. disable the tlb flush filter by sett ing hwcr.ffdis (bit 6) in msr c001_015h. fix planned no
12 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 51 arbitrated interrupt with illegal vector sets apic error bit in all processors description if an arbitrated interrupt uses an illegal interrupt vector (0?15), th en the corresponding error bit is erroneously set in the apic error st atus register (esr) of all processors, not just the processor that accepted the arbitrated interrupt. the accepting proc essor has its error bit set twice?once during the arbitration phase (at the same time as all the other processors are e rroneously setting their error bits), and once during the acceptance phase. potential effect on system if an arbitrated interrupt uses an il legal vector, all processors report th at error in their apic esr. this is not expected to impact system operation. in the case of the accepting processor, the error may appear to be reported twice if software clears the esr in the short interval between the arbitration and acceptance phases. suggested workaround none required. fix planned ye s
product errata 13 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 57 some data cache tag eviction errors are reported as snoop errors description in some cases, the machine check error code on a da ta cache (dc) tag array parity error erroneously classifies an eviction er ror as a snoop error. the common cases of cache line replacements and exte rnal probes are classifie d correctly (as eviction and snoop respectively). the errone ous cases occur when a tag error is detected during a dc eviction that was generated by a hardware prefetch, a cache line state change operatio n, or a number of other internal microarchitectural events . in such cases, the error code logged in the dc machine check status register (mc0_status, msr 0x401) erroneously indicates a snoop error. potential effect on system internally detected dc tag errors may be reporte d to software as having been detected by snoops. depending upon machine check software architecture, the system response to such errors may be broader than necessary. suggested workaround none required. fix planned no
14 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 58 memory latency with processor power states description if cpu low power mode is enabled in the c1, c2, or throttling processor power states, then externally generated sequences of memory referen ces may experience unexpe ctedly large latencies through the memory controller. potential effect on system long memory latencies may lead to performance anomolies or f unctional failures, depending on the buffering capabilities of external devices. suggested workaround do not enable cpu low power mode in the c1, c2, or throttling processor po wer states. specifically, disable the cpulowpwren bits for system man agement action field (s maf) codes 000, 101, and 111 by clearing dev:3x80[0] for c2, dev:3x84[24] for c1, an d dev:3x84[8] for throttling. fix planned ye s
product errata 15 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 60 single machine check error may report overflow description a single parity error encountered in the data cach e tag array may incorrectly report the detection of multiple errors, as indicated by the overflow bit of the dc machine check status register (bit 62 of msr 0x401). potential effect on system system software may be informed of a machine check overflow when only a single error was actually encountered. suggested workaround do not rely on the state of the over bit in the dc machine check status register. fix planned no
16 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 61 real mode rdpmc with illega l ecx may cause unpredictable operation description illegal values of ecx (that is, ecx > 3) fo r the rdpmc (read performance monitor counter) instruction correctly cause the processo r to take a general protection exception. however, if the rdpmc instruction is executed in r eal mode with a specific illegal value of ecx = 9, then the processor may incorrectly enter the gp fault handler as if it were in 32-bit mode. potential effect on system incorrect instruction d ecode leading to unpredictable system failure. suggested workaround when in real mode, restrict use of the rdpmc instruction to the legal counter values (0?3). this circumstance is not expected to occur in normal operation and has onl y been detected in a simulation environment. fix planned ye s
product errata 17 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 62 task gates with breakpoints en abled may cause unexpected faults description when a task gate is used by a call or jmp inst ruction and any debug breakpoint is enabled through the dr7.le or ge bits, the processor may incorrect ly use the new tss base [15:0] contained in the new tss as a selector. this will most likely lead to a gp fault with an error code of the new tss base. potential effect on system unexpected faults leading to unpredictable system failure. suggested workaround when running software that uses task gates with call or jmp instructions, do not enable debug breakpoints. fix planned ye s
18 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 63 tlb flush filter causes coherency problem in multiprocessor systems description if the tlb flush filter is enabled in a multipro cessor configuration, coherency problems may arise between the page tables in memory a nd the translations stored in the on-chip tlbs. this can result in the possible use of stale translations even after software has performed a tlb flush. potential effect on system unpredictable system failure. suggested workaround in mp systems, disable the tlb flush filter by setting hwcr.ffdis (bit 6 of msr 0xc001_0015). fix planned ye s
product errata 19 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 64 single step across i/o smi skips one debug trap description when single stepping (with eflags.tf) accross an in or out instruct ion that detects an smi, the processor correcly defers taking the debug trap and instead enters smm. upon rsm (without i/o restart), the processor should immediat ely enter the debug trap handler. under this senario, the processor does not enter the debug trap handler but instead returns to the instruction following the i/o instruction. potential effect on system when using the single step debug mode, followi ng an i/o operation that detects an smi, one instruction may appear to be skipped. suggested workaround none required as this is a debug limitation only. if a workaround is desired, modify the smm handler to detect this case and enter the debug handler directly. fix planned ye s
20 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 65 uncorrectable nb machine ch eck error may disrupt power management description if an uncorrectable machine check error in the no rthbridge (nb) error repor ting bank is detected at approximately the same time as any of the follo wing events, then the intended power management activity may be disrupted a nd various failures may result: a hypertransport? link frequency change entry into the s3 state (suspend-to-ram) potential effect on system for hypertransport link frequency changes, undefine d operation results, le ading to unpredicatble system failure. for entry into the s3 power state, the dram is not put into self-refresh st ate, leading to likely corruption of dram contents. suggested workaround a workaround may not be required sinc e this erratum only occurs in the presence of a fatal machine check error, and even then only when it happens to coincide in a small window of time with one of the power management events described. if desired, the nb error reporting bank mcg_ctl, msr 0x17b, bit 4 (nbe), (or all of the machine check architecture) can be disabled by software around the time of these events. refer to the bios and kernel developer's guide for am d athlon? 64 and amd opteron? processors , order# 26094, for information on how to program the machine check architecture. fix planned ye s
product errata 21 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 66 upstream read response delayed by downstream posted writes description an upstream read to main memory can be delayed when the following sequence occurs: 1. the processor issues one or more posted writes downstream. 2. the processor evicts a line from its cache. 3. the chipset performs an upstrea m read to memory with the passp w bit set in the hypertransport packet. in this case, the read should pass the downstream pos ted writes but due to a resource conflict in the internal request queues, the read is delayed until the processor?s cache line is written and all previously enqueued posted writes have completed. potential effect on system unexpectedly large latencies may be experien ced during upstream memory reads, potentially resulting in performance anomolies or functional failures, depe nding on the buffering capabilities of external devices. suggested workaround limit the number of processor downstream poste d requests to one by programming the following register values: set dev:3x70[1:0] to 10b (sri-to-xbar buffer counts) set dev:3x7c[5:4] to 00b (free list buffer counts) note that a warm reset is required to allow these new values to take effect. fix planned ye s
22 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 68 disable dqs hysteresis bit not readable description the disdqshys bit of the dram config low regist er (dev:2x90[3]) is writeable and performs its intended function, but it incorrectly always reads as zero to software. potential effect on system none expected. this bit is configured by bios and readability is not required. suggested workaround perform writes to the disdqshys bi t as appropriate for the system, disregarding the value read back. fix planned ye s
product errata 23 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 69 multiprocessor coherency problem with hardware prefetch mechanism description if the on-chip hardware prefetch mechansim genera tes a prefetch with write intent for a cache line that is also found to be present in the instruction cache, then the eventual prefetch response from the system is incorrectly di scarded by the processor. in the event the prefetched line was transferred in the modified state from another processor?s cache, that processor?s modified data is lost. potential effect on system multiprocessor memory coherency issues le ading to unpredictable system failure. suggested workaround in mp systems, set bu_cfg.wbpfsmcchkd is (bit 45 of msr 0xc001_1023). no loss of performance results from this workaround. fix planned ye s
24 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 71 rsm from smm with paging enabled may deadlock description under a rare set of internal timi ng circumstances, a speculative tlb reload may incorrectly interact with the rsm instruction such that the processor becomes deadlocked. this can only occur if the smm handler configures and enables its own paging environment. potential effect on system the system hangs and recovers only after a system reset is performed. suggested workaround if paging is enabled in the smm handler, disable it (by clearing cr0.pg) before executing the rsm instruction. fix planned ye s
product errata 25 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 74 registered dimm exit-self-refresh requirements not met description when sequencing registered dimms out of self re fresh state at the completion of an s1, s3 or ldtstop_l initiated hypertransport link wi dth/frequency change, certain sequencing requirements of the regist ered dimms are not met. potential effect on system memory system failure leading to unpredictable system failure. suggested workaround do not use s1 s3 on a platform that employs registered dimms. hypertransport link width/frequency changes must be initiated using wa rm reset (as opposed to ldtstop_l). fix planned ye s
26 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 75 apic timer accuracy across power management events description the apic timer may be inaccurate by up to 1 s across each use of s1or ldtstop_l initiated hypertransport link width/frequency changes. potential effect on system no observable system impact expected. suggested workaround none. fix planned no
product errata 27 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 76 apic timer undercounts in divide-by-8 low power mode description if s1 or ldtstop_l initiated hypertransport link width/frequency changes are performed with the clock divisor select (clksel) set to divide-by-8, then the apic time r incorrectly counts at 1/8 its intended rate. this miscounting remains in effect fo r as long as the processor remains in the divide- by-8 mode. potential effect on system for s1, the divide-by-8 mode is not typically used, so no sytem implication is expected. ldtstop_l initiated hypertranspor t link width/frequency changes do typically use the divide-by-8 clksel setting (to minimize latency) and are therefore affected by th is erratum. however, for these operations the time spent in the divide-b y-8 mode is limited to approximately 1 s per use, implying the apic timer may lo se approximately 0.875 s each time one of these transitions is performed. this error would be in addition to any other ap ic timer accuracy errors that may exist. suggested workaround none required. the accuracy loss is small a nd no observable system impact is expected. fix planned ye s
28 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 77 long mode callf or jmpf may fa il to signal gp when callgate descriptor is beyond gdt/ldt limit description if the target selector of a far call or far jump (callf or jmpf) instruction references a 16-byte long mode system descriptor where any of the last 8 bytes are beyond the gdt or ldt limit, the processor fails to report a general protection fault. potential effect on system none expected, since the operating system typical ly aligns the gdt/ldt limit such that all descriptors are legal. however, in the case of er roneous operating system code, the above described gp fault will not be signalled, resu lting in unpredictable system failure. suggested workaround none required, it is anticipated that long mode ope rating system code will ensure the gdt and ldt limits are set high enough to cover the larg er (16-byte) long mode system descriptors. fix planned no
product errata 29 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 78 apic interrupt late ncy with c2 enabled description if an apic interrupt is delivered to the proc essor at a time when inte rrupts are masked (i.e., eflags.if=0), and just shortly before entering the c2 power state, then the interrupt may experience a long latency before being serviced. the interrupt is not lost, but it is not serviced until some other wakeup even t (for example, a timer tick) occurs to take the processor out of the c2 state. potential effect on system excessively long interrupt latencies may occur, resulting in unpredictable system failures. suggested workaround do not enable the c2 power state. fix planned ye s
30 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 79 power management limitations above 1.50v description processor versions with a core voltage greater than 1.50v do not support northbridge low power mode while in the s1 power state or ldtstop_l initiated hypertranspor t link width/frequency changes. potential effect on system unpredictable system failures may occur. suggested workaround for affected versions of the processor, do not enab le northbridge low power mode in the s1 power state. specifically, clear the nblowpwren bit in smaf code 011 of the po wer mangement control registers (i.e., clear dev:3x80[25]). also, use warm reset (rather than ldtstop_l) to initiate hypertranspor t link width/frequency changes. fix planned ye s
product errata 31 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 80 registered dimm initialization requirements not met description when initializing registered di mms after a powerup or warm r eset assertion, the time interval between the deassertion of memreset_l and the asse rtion of cke is not sufficient for some dimms. potential effect on system the memory system may fail to in itialize, leading to boot failure. suggested workaround a board level workaround is available for this problem, see methodologies for using registered dimms with amd athlon? 64 and amd opteron? processors, order #27510, for details. fix planned ye s
32 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 81 cache coherency problem with hardware prefetching and streaming stores description if the processor's hardware prefetch mechanism init iates a cache line prefet ch at approximately the same time as a streaming store (m ovnt* or maskmov*) is performed to that same address, then a stale copy of that line may be loaded into the cache. potential effect on system cache coherency failure leading to unpredictabl e system failure. this erratum affects both uniprocessor and multiprocessor configurations. it has only ever been observed in a randomized diagnostic environment. suggested workaround set dc_cfg.dis_smc_chk_buf (bit 10 of msr 0xc001_1022) to disable the smc check buffer for streaming stores. no loss of functionality occurs as a result of setting this bit. fix planned ye s
product errata 33 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 82 certain faults on far transfer instructions in 64-bit mode save incorrect rip description this erratum affects the far transf er instructions (callf, retf, iret , jmpf) in 64-bit mode. if a far transfer is executed in 64-bit mode and: the rip of the far transfer is 4 gb or greater (> 32 bits) the target is a 32-bit compatibility segment the far transfer en counters a fault _after_ loading the cs then the rip pushed onto the exception handler stack will be erroneously truncated to 32-bits. the following table lists the instructions and faults that are subject to this erratum. potential effect on system the fault handler will return to the incorrect addr ess if it attempts to iret back to the faulting instruction (the far transfer), leadi ng to unpredictable system failures. suggested workaround none required. this erratum can only affect 64-bit operating systems, bu t has never been seen in such systems. it has only been seen in random instruction testing. this erratum can only affect kernel operating system code, not applications since transfers from 64- bit mode to 32-bit compatibility can only be done by the kernel. furthermore, existing 64-bit operating systems provide e nough error checking and are constructed such that it is not possible to encounter one of the above faults at the point the kernel uses the far transfe rs to exit to a 32-bit compatibility application. fix planned ye s instruction fault callf (intersegment, no gate) target limit violation faults on stack pushes jmpf (intersegment, no gate) target limit violation retf/iret (no cpl change) target limit violation retf/iret (with cpl change ) target limit violation fault while loading new ss
34 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 83 dc machine check extended error code bit not writeable description the extended error code bit in the dc machine ch eck status register (i.e., bit 16 of msr 0x0401) cannot be predictably updated by software. when this register is written, bit 16 may be updated to either a zero or a one depending on internal processor conditions. the ability of this register to correctly log and cl assify machine check errors is not compromised by this erratum. when an error occurs, all status in formation (including the extended error code bit) is captured correctly and is readable by software. the erratum only aff ects the software writeability of this bit. potential effect on system none expected. as described, errors are captured a nd classified correctly and are software readable. since software only interprets the extended error co de bit in the context of a valid tlb error, the inability of software to clear that extende d error bit is of no functional consequence. suggested workaround none required. fix planned ye s
product errata 35 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 85 insufficient delay between memclk startup and cke assertion during resume from s3 description when sequencing the drams out of self refresh during a resume from the s3 (suspend-to-ram) state, the processor fails to insert sufficien t delay between memclk startup and cke assertion. potential effect on system memory system failure leading to unpredictable system failure. suggested workaround modify the resume from s3 bios sequence such that sufficient delay is inserted between the time memclk is enabled in the dram config high re gister (dev:2x94) and the time the esr and sr_s bits are written in the dram config low register (dev:2x90[13:12]) to exit self refresh. for registered dimms, 100 s of delay is required. for unbuffered dimms, 10 s of delay is required. fix planned no
36 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 86 dram data masking feature can cause ecc failures description under certain conditions, the memory controller fa ils to generate a dram read request when performing partial writes to an already allocated write combining buffer. because the dram is not read for these subsequent write requests, the generated ecc bits are incorrect. potential effect on system incorrect data can be read back from dram. suggested workaround bios should disable the data m asking feature when ecc dimms are used by setting the disdatmsk bit (northbridge configuration register - msr c001_001f, bit 36). fix planned ye s
product errata 37 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 88 swapgs may fail to read correct gs base description the swapgs instruction fails to cause an input dependency on the gs segment register. if the gs segment register has been recently changed vi a a mov or pop segment register instruction, swapgs may incorrectly save the old value of gs base into the kernelgsbase msr. potential effect on system the kernelgsbase msr may be corrupted. suggested workaround between a mov/pop into gs and any subseque nt swapgs there must be a synchronizing operation. that operation can be one of the following: any of the instructions that are require d by the x86 architecture to be serializing (see amd64 architecture programmer's manual volume 2: system programming , order# 24593). a trap, interrupt or exception. an sfence or mfence instruction. an instruction that flushes the pipeline: - callf, jmpf, retf, intn, iret, syscall, sysret. the mfence alternative is the lowest latency a nd the recommended alternative. the others are mentioned in case the code alrea dy satisfies them by construction. fix planned ye s
38 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 89 potential deadlock with locked transactions description downstream non-posted requests to devices that ar e dependent on the completion of an upstream non-posted request can cause a deadlock in the pr esence of transactions resulting in bus locks, as shown in the following two scenarios: 1. a downstream non-posted read to the lpc bus occu rs while an lpc bus dm a is in progress. the legacy lpc dma blocks downstream traffi c until it completes its upstream reads. 2. a downstream non-posted read is sent to a device that must first send an upstream non-posted read before it can comple te the downstream read. in both cases, a locked transacti on causes the upstream channel to be blocked, causing the deadlock condition. potential effect on system the system fails due to a bus deadlock. suggested workaround bios should set the disioreqlock bit (bit 3 in nb_cfg, msr c001_001f). fix planned no
product errata 39 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 90 false ic machine check overflow error logged on reset description if a processor cold or warm reset occurs during a precise window when the in struction cach e is being accessed due to a branch re-direct, a false ic machi ne check overflow error may be logged in the ic machine check status register. potential effect on system system operation is not compromised, but a false machine check overflow error (bit 62) may be reported in the ic machine check status register. suggested workaround after a cold or warm reset, bios should clear the ic machine check stat us register if the valid bit in that register is 0. fix planned ye s
40 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 91 software prefetches may report a page fault description software prefetch instructions ar e defined to ignore page faults. u nder highly specific and detailed internal circumstances, a prefetch instruction may report a page fault if both of the following conditions are true: the target address of the prefetch would cau se a page fault if the address was accessed by an actual memory load or store instru ction under the current privilege mode; the prefetch instruction is followed in executi on-order by an actual or speculative byte-sized memory access of the same modify -intent to the same address. prefetch and prefetchnta/0/1/2 have the sam e modify-intent as a memory load access. prefetchw has the same modify -intent as a memory store access. the page fault exception error code bits for the faulti ng prefetch will be identical to that for a byte- sized memory access of the same-modi fy intent to the same address. note that some misaligned accesses can be broken up by the processor into multiple accesses where at least one of the accesses is a byte-sized access. if the target address of the subsequent memory access of the same modify-i ntent is aligned and not byte-sized, this errata does not occur and no workaround is needed. potential effect on system an unexpected page fault may occur in frequently on a prefetch instruction. suggested workaround two workarounds are described for this erratum. kernel workaround the operating system kernel can work around the erratum by allowing the page fault handler to satisfy the page fault to an "accessi ble" page regardless of whether the fault was due to a load, store, or prefetch operation. if the faulti ng instruction is permitted access to the page, return to it as usual. (an "accessible" page is one fo r which memory accesses are allowed under the current privilege mode once the page is resident in memory). if the faulting instruction is tryi ng to access an "inaccessible" page, scan the instructi on stream bytes at the faulting instruction pointer to determine if the instruction is a prefetch. (an "inaccessi ble" page is one for which memory accesses are not allowed unde r the current privilege mode.) if the faulting instruction is a prefetch instruction, simply return back to it; the internal hardware conditions that caused the prefetch to fault shoul d be removed and operati on should continue normally. if it is not a prefetch instruction, generate th e appropriate memory access contro l violation as appropriate. the performance impact of doing the scan is small because the actual errata is infrequent and does not produce an excessive number of page faul ts that affect system performance. general workaround if the page-fault handler for a ke rnel can be patched as described in the preceding kernel workaround, no further action by software is required. th e following general workarounds should only be
product errata 41 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 considered for kernels where the page-fault handler can not be patched and a prefetch instruction could end up targeting an address in an "inaccessible" page. because the actual errata is infr equent, it does not produce an excess ive number of page faults that affect system performance. theref ore a page fault from a prefetch instruction for an address within an "accessible" page does not require any general workaround. software can minimize the occurrence of the erra ta by issuing only one prefetch instruction per cache-line (a naturally-alig ned 64-byte quantity) and ensuring one of the following: in many cases, if a partic ular target address of a prefetch is known to encounter this errata, simply change the prefetch to target the next byte. avoid prefetching inaccessible memory locations, when possible. in the general case, ensure that the address used by the prefetch is offset into the middle of an aligned quadword near the end of the cache-line . for example, if the address desired to be prefetched is "addr", use an offset of 0x33 to co mpute the address used by the actual prefetch instruction as: "(addr & ~0x3f) + 0x33". fix planned ye s
42 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 92 deadlock in multi-processor s ystems may occur when earlier operations prevent an older store from writing data description a system deadlock may occur in multi-proc essor systems under the following conditions: 1. interrupts are disabled. 2. a store operation occurs to a cacheable memory type. 3. the store is retired but no t yet written the data cache. 4. the store is followed by a persistent (infinit e) stream of loads while some of the loads are misaligned. 5. the misaligned loads are to the same cache i ndex as the store (i.e., bits 11:6 are the same). 6. the misaligned loads are continually pi cked in the cycle preceding the store. 7. the destination cache line of the store is in a st ate other than modified (i .e., a probe from another processor to the same address as the store has previ ously transitioned this line to a shared state). potential effect on system in the unlikely event that the above conditions occcur, the system hangs. suggested workaround none. this scenario was contrived in a highly randomized synthetic stre ss test and is not expected to occur in real systems. fix planned ye s
product errata 43 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 93 rsm auto-halt restart returns to incorrect rip description if an smi occurs on a halt instruction in 64-bit mode, and the subsequent rsm uses the auto-halt restart feature, the rip wi ll incorrectly truncate to 32 bits. potential effect on system unpredictable system operation. suggested workaround if the upper 32 bits of rip are not cleared to zero es, bios should clear the auto-halt restart byte before executing the rsm instruction in the smi ha ndler. the rip content can be verified and the auto-halt restart byte can be modified in the smm state-save area in sm mode. fix planned ye s
44 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 94 sequential prefetch feature may cause incorrect processor operation description on an instruction cache miss, the sequential prefetch mechanism may en able the early prefetch of the next sequential cache line. under a highly specific set of internal pi peline conditions this mechanism may cause the processor to hang or execute inco rrect code in 64-bit systems running 32-bit compatibility mode applications. potential effect on system processor may deadlock or execute incorrect code. suggested workaround bios should disable ic sequent ial prefetch by setting ic_c fg.dis_seq_prefetch (bit 11 of msr c001_1021). fix planned ye s
product errata 45 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 95 ret instruction may return to incorrect eip description in order to efficiently predict return addresses, the processor implements a 12-deep return address stack to pair rets with previous calls. under the following unusual and speci fic conditions, an overflowed hard ware return stack may cause a ret instruction to return to an incorrect eip in 64-b it systems running 32-bit compatibility mode applications: a call near is executed in 32-bit compatibility mode. prior to a return from the called procedure, the processor is switched to 64-bit mode. in 64-bit mode, subsequent calls are nested 12 levels deep or greater. the lower 32 bits of the 64-bit return address for the 12th-most deeply nested call in 64-bit mode matches exactly the 32-bit return address of the origin al 32-bit mode call. a series of rets is executed fr om the nested 64-bit procedures. the processor returns to 32-bit compatibility mode. a ret is executed from the originally called procedure. potential effect on system the processor returns to an incorrect ei p, causing unpredictable system operation. suggested workaround none. this has been observed in synthetic load stre ss-testing only, and not in any operating system or application. fix planned ye s
46 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 96 increased memory latency during p-state changes description the memory controller's idle counters are dynamic ally managed to help reduce page misses and conflicts. when ldtstop is asserted for a p-st ate (frequency) change, the memory controller incorrectly waits for the idle counters to expire before placing dram in self-refresh. this has the effect of increasing memory late ncy (up to 256 memory clocks in rare cases) during p-state changes. potential effect on system the slight increase in memory la tency may lead to performance anomalies depending on buffering capabilities of external devices. suggested workaround none. fix planned ye s
product errata 47 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 97 128-bit streaming stores may cause coherency failure description under a specific set of internal pi peline conditions, stale data may be left in the l1 cache when a 128- bit streaming store (movnt*) to a writeback (wb) memory type misses in the l1 data cache and both l1 and l2 tlbs. potential effect on system memory coherence failures lead ing to unpredictable operation. suggested workaround set dc_cfg.dis_cnv_wc_sso (bit 3 of msr 0xc001_1022). the perf ormance effects of setting this bit are limited to s treaming stores to the write-combining (w c) memory type, a case expected to rarely occur in actual usage. no loss of perfor mance occurs in the general case (wb memory type). this workaround must not be applied to processors prior to revision c0. fix planned ye s
48 product errata 25759 rev. 3.09 september 2003 revision guide for amd athlon? 64 and amd opteron? processors 98 ldtstop assertion may be missed description if ldtstop width is too short relative to the programmed value of clock ramp hysteresis, the ldtstop assertion may be missed. potential effect on system fid changes or hypertransport width/fre quency changes may not work correctly. suggested workaround program the clock ramp hysterisis value (dev: 3xd4 [10-8]) to be less than the ldtstop pulse width. fix planned ye s
documentation support 49 revision guide for amd athlon? 64 and amd opteron? processors 25759 rev. 3.09 september 2003 documentation support the following documents provide additional info rmation regarding the ope ration of the processor: amd athlon? 64 processor data sheet , order# 24659 amd opteron? proc essor data sheet , order# 23932 ? amd athlon? 64 fx processor data sheet, order# 30431 cpuid guide for amd athlon? 64 and amd opteron? processors: application note addendum , order# 25481 bios and kernel developer?s guide for amd athlon? 64 and amd opteron? processors , order# 26094 amd athlon? 64 processor motherboard design guide , order# 24665 amd64 architecture programmer's manual volume 1: application programming , order# 24592 amd64 architecture programmer's manual volume 2: system programming , order# 24593 amd64 architecture programmer's manual vo lume 3: instruction-set reference , order# 24594 amd64 architecture programmer's manual volume 4: 128-bit media instructions , order# 26568 amd64 architecture programmer's manual volu me 5: 64-bit media and x87 floating-point instructions , order# 26569 methodologies for using registered di mms with amd athlon? 64 and amd opteron? processors , order# 27510 see the amd web site at www.amd.com for the latest updates to documents. for documents subject to a non-disclosure agreement (nda), pleas e contact your local sales representative.

▲Up To Search▲

Price & Availability of 25759

	To Download 25759 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .