GM72V66441ET/elt 4,194,304 word x 4 bit x 4 bank synchronous dynamic ram description the GM72V66441ET/elt is a synchronous dynamic random access memory comprised of 67,108,864 memory cells and logic including input and output circuits operating synchronously by referring to the positive edge of the externally provided clock. the GM72V66441ET/elt provides four banks of 4,194,304 word by 4 bit to realize high bandwidth with the clock frequency up to 143 mhz . features * pc133/pc100/pc66 compatible -7(143mhz)/-75(133mhz)/-8(125mhz) -7k(pc100,2-2-2)/-7j(pc100,3-2-2) * 3.3v single power supply * lvttl interface * max clock frequency 143/133/125/100mhz * 4,096 refresh cycle per 64 ms * two kinds of refresh operation auto refresh / self refresh * programmable burst access capability ; - sequence:sequential / interleave - length :1/2/4/8/fp * programmable cas latency : 2/3 * 4 banks can operate independently or simultaneously * burst read/burst write or burst read/single write operation capability * input and output masking by dqm input * one clock of back to back read or write command interval * synchronous power down and clock suspend capability with one clock latency for both entry and exit * jedec standard 54pin 400mil tsop ii package pin configuration pin name clk cke cs ras cas we a0~a9,a11 a10 / ap ba0/a13 ~ba1/a12 dq0~dq7 dqm vccq vssq vcc vss nc clock clock enable chip select row address strobe column address strobe write enable address input address input or auto precharge bank select data input / data output data input / output mask v cc for dq v ss for dq power for internal circuit ground for internal circuit no connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 jedec standard 400 mil 54 pin tsop ii (top view) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 vcc nc vccq nc dq0 vssq nc nc vccq nc dq1 vssq nc vcc nc / we / cas / ras / cs ba0/a13 ba1/a12 a10,ap a0 a1 a2 a3 vcc vss nc vssq nc dq3 vccq nc nc vssq nc dq2 vccq nc vss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 vss -1- this document is a general product description and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 1.1/apr.01
GM72V66441ET/elt rev. 1.1/apr.01 block diagram a0 to a13 a0 to a9 a0 to a13 column address counter column address buffer row address counter refresh counter input buffer output buffer dq0 to dq3 control logic & timing generator clk cke dqm ras cas row decoder memory array bank 0 4096 row x 1024 column x 4 bit column decoder sense amplifier & i/o bus row decoder memory array bank 1 4096 row x 1024 column x 4 bit column decoder sense amplifier & i/o bus row decoder memory array bank 2 4096 row x 1024 column x 4 bit column decoder sense amplifier & i/o bus row decoder memory array bank 3 4096 row x 1024 column x 4 bit column decoder sense amplifier & i/o bus cs we -2-
GM72V66441ET/elt rev. 1.1/apr.01 absolute maximum ratings notes : 1. respect to v ss symbol value unit note parameter v t -0.5 to vcc +0.5 ( <= 4.6 (max)) v 1 voltage on any pin relative to v ss v cc -0.5 to +4.6 v 1 supply voltage relative to v ss i out 50 ma short circuit output current p t 1.0 w power dissipation topr 0 to +70 c operating temperature tstg -55 to +125 c storage temperature notes : 1. all voltage referred to v ss . 2. v ih (max) = 5.6v for pulse width <= 3ns 3. v il (min) = -2.0v for pulse width <= 3ns recommended dc operating conditions ( ta = 0 to + 70 c ) symbol min unit note v cc , v ccq v 1 v ss , v ssq v input high voltage v ih v 1, 2 input low voltage v il v 1,3 supply voltage parameter max 3.0 3.6 0 0 2.0 vcc +0.3 -0.3 0.8 -3-
GM72V66441ET/elt rev. 1.1/apr.01 dc characteristics ( ta = 0 to 70c, v cc , v ccq = 3.3 v +/- 0.3 v, v ss , v ssq = 0 v) parameter symbol unit test conditions notes operating current standby current in power down i cc2p self refresh current i cc6 ma v ih >=v cc - 0.2 v il <=0.2v 7 burst length= 1 t rc = min 1, 2, 3 cke = v il , t ck = 12 ns 5 i cc1 ma ma standby current in power down (input signal stable) i cc2ps cke=v il , t ck = infinity 6 ma standby current in non power down (cas latency=2) i cc2n cke,cs = v ih , t ck = 12ns 4 ma standby current in non power down (input signal stable) i cc2ns cke = v ih , t ck = infinity 4 ma active standby current in power down i cc3p cke = v il , t ck = 12 ns , dq = high-z 1,2,5 ma active standby current in power down (input signal stable) i cc3ps cke = v il , t ck = infinity 2,6 ma active standby current in non power down i cc3n cke,cs = v ih , t ck = 12 ns , dq = high-z 1,2,4 ma active standby current in non power down (input signal stable) i cc3ns cke = v ih , t ck = infinity 2,9 ma burst operating current i cc4 t ck = min bl = 4 1,2,3 ma ( cl= 2 ) i cc4 ma ( cl= 3 ) refresh current t rc = min 3 i cc5 ma 7,8 6,8 - 8 max 80 150 max -7 j 80 120 - 75 max 85 150 max -7 k 80 120 - 7 max 1 85 2 2 15 12 6 5 20 120 150 160 0.4 0.4 30 -4-
GM72V66441ET/elt rev. 1.1/apr.01 notes : 1. i cc depends on output load condition when the device is selected. i cc ( max) is specified at the output open condition. 2. one bank operation. 3. addresses are changed once per one cycle. 4. addresses are changed once per two cycles. 5. after power down mode, clk operating current. 6. after power down mode, no clk operating current. 7. after self refresh mode set, self refresh current. 8. l-version. 9. input signals are v ih or v il fixed. capacitance ( ta = 25 c , v cc , v ccq = 3.3 v +/- 0.3 v) input leakage current i li ua 0 <= vin <= v cc output leakage current i lo ua 0 <= vout <= v cc dq = disable output high voltage v oh v i oh = -2 ma output low voltage v ol v i ol =2 ma -1 1 -1.5 1.5 - 0.4 parameter symbol unit test conditions notes min max - 7, -75, - 8, - 7 k, - 7j 2.4 - notes : 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. dqm = v ih to disable dout . 3. this parameter is sampled and not 100% tested. 4. measured with 1.4 v bias and 200mv swing at the pin under measurement. parameter input capacitance (clk) input capacitance (signals) output capacitance (dq) symbol c i1 c i2 c o min. 2.5 2.5 4.0 max. 4 5 6.5 unit pf pf pf notes 1, 3, 4 1, 3, 4 1, 2, 3, 4 dc characteristics ( ta = 0 to 70c, v cc , v ccq = 3.3 v +/- 0.3 v, v ss , v ssq = 0 v) (continued) -5-
GM72V66441ET/elt rev. 1.1/apr.01 ac characteristics ( ta = 0 to 70 c , v cc , v ccq = 3.3 v +/- 0.3 v, v ss , v ssq = 0 v) symbol unit notes t ck t ck parameter system clock cycle time ( cl=2) ( cl=3) ns 1 t ckh ns 1 clk high pulse width t ckl ns 1 clk low pulse width t ac t ac access time from clk ( cl=2) ( cl=3) ns 1, 2 t oh ns 1, 2 data-out hold time t lz ns 1, 2, 3 clk to data-out low impedance t hz clk to data-out high impedance ( cl = 2,3 ) ns 1, 4 t ds ns 1 data-in setup time t dh ns 1 data-in hold time t as ns 1 address setup time t ah ns 1 address hold time t ces ns 1, 5 cke setup time t cesp ns 1 cke setup time for power down exit t ceh ns 1 cke hold time t cs ns 1 command (cs, ras, cas, we, dqm) setup time t rc ns 1 ref/active to ref/active command period t ch ns 1 command (cs, ras, cas, we, dqm) hold time t ras ns 1 active to precharge command period t rcd ns 1 active command to column command (same bank) t rp ns 1 precharge to active command period - 7 k min max 10 - 10 - 3 - 3 - - 6 - 6 3 - 2 - - 6 2 - 1 - 2 - 1 - 2 - 2 - 1 - 2 - 70 - 1 - 50 120000 20 - 20 - - 7 j min max 10 - 15 - 3 - 3 - - 6 - 8 3 - 2 - - 6 2 - 1 - 2 - 1 - 2 - 2 - 1 - 2 - 70 - 1 - 50 120000 20 - 20 - - 8 min max 8 - 10 - 3 - 3 - - 6 - 6 3 - 2 - - 6 2 - 1 - 2 - 1 - 2 - 2 - 1 - 2 - 68 - 1 - 48 120000 20 - 20 - - 75 min max 7.5 - 10 - 2.5 - 2.5 - - 5.4 - 6 2.7 - 1.5 - - 5.4 1.5 - 0.8 - 1.5 - 0.8 - 1.5 - 1.5 - 0.8 - 1.5 - 65 - 0.8 - 45 120000 20 - 20 - - 7 min max 7 - 10 - 2.5 - 2.5 - - 5.4 - 6 2.7 - 1.5 - - 5.4 1.5 - 0.8 - 1.5 - 0.8 - 1.5 - 1.5 - 0.8 - 1.5 - 62 - 0.8 - 42 120000 20 - 20 - -6-
GM72V66441ET/elt rev. 1.1/apr.01 ac characteristics ( ta = 0 to 70 c , v cc , v ccq = 3.3 v +/- 0.3 v, v ss , v ssq = 0 v) (continued) notes : 1. ac measurement assumes t t = 1ns. reference level for timing of input signals is 1.40v. if t t is longer than 1ns,transition time compensation should be considered. 2. access time is measured at 1.40v. load condition is c l = 50pf without termination. 3. t lz (min)defines the time at which the outputs achieves the low impedance state. 4. t hz (max)defines the time at which the outputs achieves the high impedance state. 5. t ces define cke setup time to cke rising edge except power down exit command. test condition ? input and output-timing reference levels: 1.4v ? input waveform and output load: see following figures 20% t t t t 0.4 v 2.4 v i/o 80% open input c l symbol notes parameter 1 t rrd 1 active (a) to active (b) command period t ref refresh period t rwl write recovery or data-in to precharge lead time unit ns ns ms - 8 min max 8 - 16 - - 64 - 7 k min max 10 - 20 - - 64 - 7 j min max 10 - 20 - - 64 - 75 min max 7.5 - 15 - - 64 - 7 min max 7 - 14 - - 64 -7-
GM72V66441ET/elt rev. 1.1/apr.01 relationship between frequency and minimum latency notes l rcd 1 active command to column command (same bank) l rc = [ l ras + l rp ], 1 active command to active command (same bank) l ras active command to precharge command (same bank) l rp 1 precharge command to active command (same bank) l rwl 1 write recovery or last data-in to precharge command (same bank) l rrd 1 active command to active command (different bank) l srex self refresh exit time l apw = [ l rwl + l rp ], 1 last data in to active command (auto precharge , same bank) l sec = [ l rc ] self refresh exit to command input l hzp precharge command to high impedance l hzp ( cl=2) ( cl=3) l apr last data out to active command (auto precharge ) (same bank) l ep last data out to precharge (early precharge ) l ep ( cl=2) ( cl=3) l ccd column command to column command l wcd write command to data in latency l did dqm to data in l dod dqm to data out l pec power down exit to command input l cle cke to clk disable l rsa register set to active command l cdd parameter t ck ( ns ) frequency(mhz) 1 cs to command disable symbol -7 j 100 2 7 5 10 2 1 2 1 3 7 - 3 1 - - 2 1 0 0 2 1 1 1 0 -75 133 3 9 6 7.5 3 1 2 1 4 9 - 3 1 - -2 1 0 0 2 1 1 1 0 -8 125 3 9 6 8 3 1 2 1 4 9 - 3 1 - -2 1 0 0 2 1 1 1 0 100 2 7 5 10 2 1 2 2 3 7 2 3 1 -1 -2 1 0 0 2 1 1 1 0 66 2 6 4 15 2 1 2 2 3 6 2 3 1 -1 - 2 1 0 0 2 1 1 1 0 -7 143 3 9 6 7 3 1 2 1 4 9 - 3 1 - -2 1 0 0 2 1 1 1 0 100 2 7 5 10 2 1 2 1 3 7 2 3 1 - 1 - 2 1 0 0 2 1 1 1 0 -7 k 100 2 7 5 10 2 1 2 1 3 7 2 3 1 -1 -2 1 0 0 2 1 1 1 0 100 2 7 5 10 2 1 2 1 3 7 2 3 1 -1 -2 1 0 0 2 1 1 1 0 100 2 7 5 10 2 1 2 1 3 7 2 3 1 - 1 - 2 1 0 0 2 1 1 1 0 -8-
GM72V66441ET/elt rev. 1.1/apr.01 relationship between frequency and minimum latency symbol notes l bsr burst stop to output valid data hold l bsr ( cl=2) ( cl=3) l bsh burst stop to output high impedance l bsh ( cl=2) ( cl=3) l bsw burst stop to write data ignore notes : 1. l rcd to l rrd are recommended value. parameter t ck ( ns ) frequency(mhz) - 7 k - 7 j -7 143 7 - 2 - 3 0 - 8 125 8 - 2 - 3 0 100 10 1 2 2 3 0 100 10 - 2 - 3 0 66 15 1 2 2 3 0 -75 133 7.5 - 2 - 3 0 100 10 1 2 2 3 0 100 10 1 2 2 3 0 100 10 1 2 2 3 0 100 10 1 2 2 3 0 -9-
GM72V66441ET/elt rev. 1.1/apr.01 package dimensions GM72V66441ET/elt series (ttp-54d) unit: (mm) 0.145 +/- 0.05 0.125 +/- 0.04 0.91 max 0.30 22.72 max 22.22 54 28 1 27 10.16 0.80 0.13 m +0.10 - 0.05 0.28 +/- 0.05 1.20 max 0.10 dimension including the plating thickness base material dimension 0.68 0.50 +/- 0.10 0.80 preliminary hitachi code eiaj code jedec code weight(reference value) ttp-54d - - 0.53 g 11.76 +/- 0.20 0.13 +/- 0.05 0 ~ 5 ? -10-
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