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s ynchronous e quipment t iming s ource for sonet or sdh network elements acs8510 rev2.1 sets description features block diagram the acs8510 is a highly integrated, single-chip solution for the synchronous equipment timing source (sets) function in a sonet or sdh net- work element. the device generates sonet or sdh equipment clocks (sec) and frame synchro- nization clocks. the acs8510 is fully compliant with the required specifications and standards. the device supports free-run, locked and holdover modes. it also supports all three types of reference clock source: recovered line clock, pdh network, and node synchronization. the acs8510 generates independent sec and bits clocks, an 8 khz frame synchronization clock and a 2 khz multi-frame synchronization clock. two acs8510 devices can be used together in a master/slave configuration mode allowing sys- tem protection against a single acs8510 failure. a microprocessor port is incorporated, providing access to the configuration and status registers for device setup and monitoring. the acs8510 supports ieee 1149.1 jtag boundary scan. rev2.1 adds choice of edge alignment for 8khz input, as well as a low jitter n x e1/ds1 output mode. other minor changes are made, with all described in appendix a. advanced communications final revision 1.06/october 2002 ? semtech corp. www.semtech.com ?suitable for stratum 3e*, 3, 4e and 4 sonet or sdh equipment clock (sec) applications ?meets at&t, itu-t, etsi and telcordia specifications ?accepts 14 individual input reference clocks ?generates 11 output clocks ?supports free-run, locked and holdover modes of operation ?robust input clock source quality monitoring on all inputs ?automatic ?hit-less? source switchover on loss of input ?phase build out for output clock phase continuity during input switchover and mode transitions ?microprocessor interface - intel, motorola, serial, multiplexed, eprom ?programmable wander and jitter tracking attenuation 0.1 hz to 20 hz ?support for master/slave device configuration alignment and hot/standby redundancy ?ieee 1149.1 jtag boundary scan ?single +3.3 v operation, +5 v i/o compatible ?operating temperature (ambient) -40c to +85c ?available in 100 pin lqfp package * meets holdover requirements, lowest bandwidth 0.1 hz. dpll/f req. synthesis t out0 selector t out4 selector chip c lock generator div ider pfd dpll/f req. s ynt hes is div ider monitors dig ital loop filter apll frequency dividers microprocessor port 2 x a mi 10 x ttl 2 x pecl/lvds programmable; 64/8khz 2khz 4khz n x 8khz 1.544/2.048mhz 6.48mhz 19.44mhz 25.92mhz 38.88mhz 51.84mhz 77.76mhz 155.52mhz dto dig ital lo op filter pfd 1 x ami 6 x ttl 2 x pecl/lv ds programmable: 64/8khz 1.544/2.048mhz 3.088/4.096mhz 6.176/8.182mhz 12.352/16.384mhz 6.48mhz 19.44mhz 25.92mhz 38.88mhz 51.84mhz 77.76mhz 155.52mhz 311.04mhz 2khz mfrsync 8khz frsync inp ut ports 14xsec mfrsync output ports tcxo (*ocxo) ieee 1149.1 jtag priority table register set priority table register set dto 9xsec frsync mfrsync tck td i tms trs t tdo figure 1. simple block diagram
www.semtech.com 2 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. table of contents list of sections description ................................................................................................................... ............................................................................. 1 block diagram ................................................................................................................. .......................................................................... 1 features ............................................................................................................................... ...................................................................... 1 table of contents ............................................................................................................. ......................................................................... 2 pin diagram ............................................................................................................................... ................................................................ 5 pin descriptions .............................................................................................................. .......................................................................... 6 functional description ........................................................................................................ ..................................................................... 9 local oscillator clock ......................................................................................................... .......................................................................... 10 itu and etsi specification ..................................................................................................... ........................................................ 10 telcordia gr-1244 core specification ........................................................................................... ............................................ 10 crystal frequency calibration ............................................................................................................................... ....................... 10 input interfaces ............................................................................................................................... .............................................................. 10 over-voltage protection ............................................................................................................................... ............................................... 10 input reference clock ports .................................................................................................... ................................................................... 11 input wander and jitter tolerance .............................................................................................. ................................................................ 9 output clock ports ............................................................................................................................... ......................................................... 12 low speed output clock (dpll2) ................................................................................................. ................................................ 12 high speed output clock (dpll1) ................................................................................................ ............................................... 12 frame sync and multi-frame sync clocks (part of dpll1) ......................................................................... .......................... 13 low jitter multiple e1/ds1 outputs ............................................................................................. .............................................. 13 output wander and jitter ....................................................................................................... ..................................................................... 13 phase variation ............................................................................................................................... .............................................................. 18 phase build out ................................................................................................................ ............................................................................. 21 microprocessor interface ............................................................................................................................... .............................................. 21 motorola mode ............................................................................................................................... ................................................. 21 intel mode ............................................................................................................................... ......................................................... 21 multiplexed mode ............................................................................................................................... ............................................ 21 serial mode ............................................................................................................................... ....................................................... 21 eprom mode ............................................................................................................................... .................................................... 21 register set ............................................................................................................................... ...................................................... 22 configuration registers ............................................................................................................................... .................................. 22 status registers ............................................................................................................................... ............................................... 22 register access ............................................................................................................................... ................................................ 22 interrupt enable and clear ..................................................................................................... .................................................................... 22 register map ............................................................................................................................... ................................................................... 23 register map description ............................................................................................................................... ............................................ 27 selection of input reference clock source ...................................................................................... ....................................................... 36 forced control selection ............................................................................................................................... ................................ 37 automatic control selection ............................................................................................................................... ......................... 37 ultra fast switching ............................................................................................................................... ........................................ 37 external protection switching ............................................................................................................................... ...................... 38 clock quality monitoring ............................................................................................................................... .............................................. 38 activity monitoring ............................................................................................................................... ........................................................ 39 frequency monitoring ............................................................................................................................... ................................................... 39 modes of operation ............................................................................................................................... ....................................................... 41 free-run mode ............................................................................................................................... .................................................. 41 pre-locked mode ............................................................................................................................... ............................................. 41 locked mode .................................................................................................................... ................................................................ 41 lost_phase mode ............................................................................................................................... ............................................ 41 holdover mode ............................................................................................................................... ................................................. 42 pre-locked(2) mode ............................................................................................................. ........................................................... 42 protection facility ............................................................................................................................... ......................................................... 43 alignment of priority tables in master and slave acs8510 ....................................................................... .......................... 44 alignment of the selection of reference sources for tout4 generation in the master and slave acs8510 ........... 45 alignment of the phases of the 8khz and 2khz clocks in both master and slave acs8510 ....................................... 45 jtag ........................................................................................................................... ....................................................................................... 45 porb ............................................................................................................................... ................................................................................. 45 electrical specification ...................................................................................................... .................................................................... 48
www.semtech.com 3 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. list of figures figure 1. simple block diagram ................................................................................................ ............................................................. 1 figure 2. acs8510 pin diagram ................................................................................................. ........................................................... 5 figure 3. minimum input jitter tolerance (oc-3/stm-1) ......................................................................... .......................................... 15 figure 4. minimum input jitter tolerance (ds1/e1) ............................................................................. ............................................. 16 figure 5. wander and jitter measured transfer characteristics ................................................................. ...................................... 18 figure 6. maximum time interval error of tout0 output port .................................................................... ....................................... 20 figure 7. time deviation of tout0 output port ................................................................................. .................................................. 20 figure 8. phase error accumulation of tout0 output port in holdover mode ....................................................... ........................... 20 figure 9. inactivity and irregularity monitoring .............................................................................. ..................................................... 38 figure 10. master-slave schematic ............................................................................................. ........................................................ 46 figure 11. automatic mode control state diagram ............................................................................... ............................................ 47 figure 12. recommended line termination for pecl input/output ports ........................................................... ........................... 51 figure 13. recommended line termination for lvds input/output ports ........................................................... ........................... 53 figure 14. signal structure of 64 khz/8khz central clock interface ............................................................ ................................ 55 figure 15. ami input and output signal levels ................................................................................. ................................................. 55 figure 16. recommended line termination for ami output/output ports ........................................................... .......................... 56 figure 17. jtag timing ........................................................................................................ .................................................................... 61 figure 18. input/output timing ................................................................................................ ............................................................ 62 figure 19. read access timing in motorola mode ................................................................................ ........................................ 63 figure 20. write access timing in motorola mode ............................................................................... ........................................ 64 figure 21. read access timing in intel mode ................................................................................... ................................................ 65 figure 22. write access timing in intel mode .................................................................................. ................................................ 66 figure 23. read access timing in multiplexed mode ............................................................................. ....................................... 67 figure 24. write access timing in multiplexed mode ............................................................................ ....................................... 68 figure 25. read access timing in serial mode .................................................................................. .............................................. 69 figure 26. write access timing in serial mode ................................................................................. .............................................. 70 figure 27. access timing in eprom mode ........................................................................................ ................................................. 71 figure 28. lqfp package ....................................................................................................... ............................................................... 72 figure 29. typical 100 pin lqfp footprint ...................................................................................................................... ................... 73 figure 30. simplified application schematic ................................................................................... ................................................... 74 dc characteristics: ami input/output port ..................................................................................... ...................................................... 54 microprocessor interface timing ............................................................................................... ........................................................... 63 motorola mode ............................................................................................................................... ............................................................... 63 intel mode ............................................................................................................................... ........................................................................ 65 multiplexed mode ............................................................................................................................... .......................................................... 67 serial mode ............................................................................................................................... ..................................................................... 69 eprom mode ............................................................................................................................... .................................................................. 71 package information ............................................................................................................................... ............................................... 72 thermal conditions ............................................................................................................................... ........................................................ 73 application information ............................................................................................................................... ........................................... 74 revision history .............................................................................................................. ........................................................................ 75 ordering information ............................................................................................................................... ............................................... 76 disclaimers ............................................................................................................................... ...................................................................... 76
www.semtech.com 4 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. list of tables table 1. power pins ............................................................................................................ ........................................................................ 6 table 2. no connections ........................................................................................................ .................................................................... 6 table 3. other pins ............................................................................................................ ......................................................................... 7 table 4. input reference source selection and priority table .................................................................. ........................................ 12 table 5. input referencesource jitter tolerance ................................................................................ ................................................. 14 table 6. amplitude and frequency values for jitter tolerance ............................................................................................................ 15 table 7. amplitude and frequency values for jitter tolerance ............................................................................................................ 16 table 8. output reference source selection table ............................................................................................................................. 17 table 9. multiple e1/ds1 output in relation to normal outputs .................................................................. ................................... 17 table 10. microprocessor interface mode selection ............................................................................. ............................................ 21 table 11. register map ........................................................................................................ .................................................................. 23 table 12. register map description ............................................................................................ ......................................................... 27 table 13. master-slave relationship ........................................................................................... ......................................................... 46 table 14. absolute maximum ratings ............................................................................................................................... ................... 48 table 15. operating conditions ................................................................................................ ............................................................. 48 table 16. dc characteristics: ttl input port .................................................................................. ..................................................... 48 table 17. dc characteristics: ttl input port with internal pull-up ............................................................ ........................................ 49 table 18. dc characteristics: ttl input port with internal pull-down .......................................................... ..................................... 49 table 18. dc characteristics: ttl output port ................................................................................. ................................................... 49 table 20. dc characteristics: pecl input/output port .......................................................................... ............................................ 50 table 21. dc characteristics: lvds input/output port .......................................................................... ............................................ 52 table 22. dc characteristics: ami input/output port ........................................................................... ............................................. 54 table 23. dc characteristics: ouput jitter generation (test definition g.813) ................................................. ............................ 57 table 24. dc characteristics: ouput jitter generation (test definition g.812) ................................................. ............................ 57 table 25. dc characteristics: ouput jitter generation (test definition ets-300-462-3) ......................................... ..................... 58 table 26. dc characteristics: ouput jitter generation (test definition gr-253-core) ........................................... .................... 58 table 27. dc characteristics: ouput jitter generation (test definition at&t 62411) ............................................ ....................... 59 table 28. dc characteristics: ouput jitter generation (test definition g.742) ................................................. ............................. 59 table 29. dc characteristics: ouput jitter generation (test definition tr-nwt-000499) ......................................... .................. 59 table 30. dc characteristics: ouput jitter generation (test definition gr-1244-core) .......................................... ................... 60 table 31. jtag timing (for use with figure 17) ................................................................................ ................................................... 61 table 32. read access timing in motorola mode (for use with figure 19) ......................................................... ........................ 63 table 33. write access timing in motorola mode (for use with figure 20) ........................................................ ........................ 64 table 34. read access timing in intel mode (for use with figure 21) ............................................................ ................................ 65 table 35. write access timing in intel mode (for use with figure 22) ........................................................... ................................ 66 table 36. read access timing in multiplexed mode (for use with figure 23) ...................................................... ....................... 67 table 37. write access timing in multiplexed mode (for use with figure 24) ..................................................... ........................ 68 table 38. read access timing in serial mode (for use with figure 25) ........................................................... .............................. 70 table 39. write access timing in serial mode (for use with figure 26) .......................................................... .............................. 70 table 40. access timing in eprom mode (for use with figure 27) ................................................................. ................................. 71 table 41. 100 pin lqfp package dimension data (for use with figure 28) ......................................................... .......................... 73
www.semtech.com 5 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. nc - not connected; leave to float. ic - internally connected; leave to float. 100 sonsdhb 99 mstslvb 98 ic 97 ic 96 ic 95 to9 94 to5 93 to4 92 dgnd 91 vdd 90 to3 89 to2 88 to1 87 dgnd 86 vdd 85 vdd 84 dgnd 83 ad0 82 ad1 81 ad2 80 ad3 79 ad4 78 ad5 77 ad6 76 ad7 75 rdy 74 porb 73 ale 72 rdb 71 wrb 70 csb 69 a0 68 a1 67 a2 66 a3 65 a4 64 a5 63 a6 62 dgnd 61 vdd 60 upsel0 59 upsel1 58 upsel2 57 i14 56 i13 55 i12 54 i11 53 i10 52 i9 51 i8 acs8510 sdh/sonet sets rev 2.1 1 1 agnd 2 trst 3ic 4nc 5 agnd 6 va1+ 7 tms 8 intreq 9 tck 10 refclk 11 dgnd 12 vd+ 13 vd+ 14 dgnd 15 dgnd 16 vd+ 17 nc 18 srcsw 19 va2+ 20 agnd 21 tdo 22 ic 23 tdi 24 i1 25 i2 26 vami+ 27 to8neg 28 to8pos 29 gnd_ami 30 frsync 31 mfrsync 32 gnd_diff 33 vdd_diff 34 to6pos 35 to6neg 36 to7pos 37 to7neg 38 gnd_diff 39 vdd_diff 40 i5pos 41 i5neg 42 i6pos 43 i6neg 44 vdd5 45 sync2k 46 i3 47 i4 48 i7 49 dgnd 50 vdd pin diagram figure 2. acs8510 pin diagram
www.semtech.com 6 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. n i pl o b m y so ie p y tn o i t p i r c s e d / e m a n 7 1 , 4c n-- d e t c e n n o c t o n t a o l f o t e v a e l : , 6 9 , 2 2 , 3 8 9 , 7 9 c i-- d e t c e n n o c y l l a n r e t n i t a o l f o t e v a e l : pin descriptions table 1. power pins table 2. no connections note: i = input, o = output, p = power, ttl u = ttl input with pull-up resistor, ttl d = ttl input with pull-down resistor n i pl o b m y so ie p y tn o i t p i r c s e d / e m a n 6 1 , 3 1 , 2 1+ d vp- : e g a t l o v y l p p u s 3 . 3 + , n o i t c e s g o l a n a n i s e t a g o t y l p p u s l a t i g i d % 0 1 - / + . s t l o v 6 2+ i m a vp- : e g a t l o v y l p p u s % 0 1 - / + . s t l o v 3 . 3 + , t u p t u o i m a o t y l p p u s l a t i g i d 9 3 , 3 3f f i d _ d d vp- : e g a t l o v y l p p u s . s t l o v 3 . 3 + , s t r o p l a i t n e r e f f i d r o f y l p p u s l a t i g i d % 0 1 - / + 4 45 d d vp- 5 d d v t c e n n o c . s n i p t u p n i o t e c n a r e l o t s t l o v 5 + r o f y l p p u s l a t i g i d : r o f d d v o t t c e n n o c . s t l o v 5 + o t g n i p m a l c r o f ) % 0 1 - / + ( s t l o v 5 + o t s n i p t u p n i , g n i p m a l c o n r o f g n i t a o l f e v a e l . s t l o v 3 . 3 + o t g n i p m a l c . s t l o v 5 . 5 + o t p u t n a r e l o t , 5 8 , 1 6 , 0 5 1 9 , 6 8 d d vp- : e g a t l o v y l p p u s % 0 1 - / + . s t l o v 3 . 3 + , c i g o l o t y l p p u s l a t i g i d 6+ 1 a vp- : e g a t l o v y l p p u s . s t l o v 3 . 3 + , l l p g n i y p i t l u m k c o l c o t y l p p u s g o l a n a % 0 1 - / + 9 1+ 2 a vp- e g a t l o v y l p p u s % 0 1 - / + . s t l o v 3 . 3 + , l l p t u p t u o o t y l p p u s g o l a n a : , 5 1 , 4 1 , 1 1 , 4 8 , 2 6 , 9 4 2 9 , 7 8 d n g dp- d n u o r g y l p p u s c i g o l r o f d n u o r g l a t i g i d : 9 2i m a _ d n gp - d n u o r g y l p p u s t u p t u o i m a r o f d n u o r g l a t i g i d : 8 3 , 2 3f f i d _ d n gp- d n u o r g y l p p u s s t r o p l a i t n e r e f f i d r o f d n u o r g l a t i g i d : 0 2 , 5 , 1d n g ap- d n u o r g y l p p u s d n u o r g g o l a n a :
www.semtech.com 7 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. table 3. other pins n i pl o b m y so ie p y tn o i t p i r c s e d / e m a n 2t s r til t t d t u p n i t e s e r l o r t n o c g a t j y r a d n u o b g a t j e l b a n e o t 1 = t s r t : c i g o l g a t j ( n o i t a r e p o e c i v e d l a m r o n r o f 0 = t s r t . e d o m n a c s . g n i t a o l f e v a e l r o d n g o t t c e n n o c d e s u t o n f i . ) t n e r a p s n a r t 7s m til t t u t c e l e s e d o m t s e t g a t j n o d e l p m a s . e l b a n e n a c s y r a d n u o b : . g n i t a o l f e v a e l r o d d v o t t c e n n o c d e s u t o n f i . k c t f o e g d e g n i s i r 8q e r t n io l t t s o m c t s e u q e r t p u r r e t n i t u p t u o t p u r r e t n i e r a w t f o s h g i h e v i t c a : 9k c til t t d k c o l c g a t j o t t c e n n o c d e s u t o n f i . t u p n i k c o l c n a c s y r a d n u o b : d e c a l p r o t i c a p a c a e r i u q e r y a m n i p s i h t . g n i t a o l f e v a e l r o d n g a . p u k c i p e s i o n e c u d e r o t , d n g t s e r a e n e h t d n a n i p e h t n e e w t e b n o t n e d n e p e d s i e u l a v e h t t u b , e t a u q e d a e b d l u o h s f p 0 1 f o e u l a v . t u o y a l b c p 0 1k l c f e ril t t k c o l c e c n e r e f e r l a c o l d e d a e h n o i t c e s o t r e f e r ( z h m 8 . 2 1 : ) k c o l c r o t a l l i c s o 8 1w s c r sil t t d g n i h c t i w s e c r u o s g n i h c t i w s e c r u o s t s a f e c r o f : 1 2o d to l t t s o m c t u p t u o g a t j f o e g d e g n i l l a f n o d e t a d p u . t u p t u o a t a d t s e t l a i r e s : . g n i t a o l f e v a e l d e s u t o n f i . k c t 3 2i d til t t u t u p n i g a t j . k c t f o e g d e g n i s i r n o d e l p m a s . t u p n i a t a d t s e t l a i r e s : . g n i t a o l f e v a e l r o d d v o t t c e n n o c d e s u t o n f i 4 21 iii m a 1 e c n e r e f e r t u p n i z h k 8 + z h k 4 6 k c o l c e t i s o p m o c : 5 22 iii m a 2 e c n e r e f e r t u p n i z h k 8 + z h k 4 6 k c o l c e t i s o p m o c : 7 2g e n 8 o toi m a 8 e c n e r e f e r t u p t u o e v i t a g e n z h k 8 + z h k 4 6 , k c o l c e t i s o p m o c : e s l u p 8 2s o p 8 o toi m a 8 e c n e r e f e r t u p t u o e v i t i s o p z h k 8 + z h k 4 6 , k c o l c e t i s o p m o c : e s l u p 0 3c n y s r fo l t t s o m c 0 1 e c n e r e f e r t u p t u o e r a u q s ( t u p t u o k c o l c c n y s e m a r f z h k 8 : ) e v a w 1 3c n y s r f mo l t t s o m c 1 1 e c n e r e f e r t u p t u o t u p t u o k c o l c c n y s e m a r f - i t l u m z h k 2 : ) e v a w e r a u q s ( 4 3 5 3 s o p 6 o t g e n 6 o t o s d v l l c e p 6 e c n e r e f e r t u p t u o 4 4 5 . 1 ( 1 g i d o s l a . z h m 8 8 . 8 3 t l u a f e d : 4 0 . 1 1 3 , z h m 2 5 . 5 5 1 , z h m 4 4 . 9 1 , ) x 8 , 4 , 2 d n a z h m 8 4 0 . 2 / z h m . s d v l e p y t t l u a f e d . z h m 6 3 7 3 s o p 7 o t g e n 7 o t o l c e p s d v l 7 e c n e r e f e r t u p t u o 6 7 . 7 7 , z h m 4 8 . 1 5 o s l a . z h m 4 4 . 9 1 t l u a f e d : . l c e p e p y t t l u a f e d . z h m 2 5 . 5 5 1 , z h m 0 4 1 4 s o p 5 i g e n 5 i i s d v l l c e p 5 e c n e r e f e r t u p n i s d v l e p y t t l u a f e d , z h m 4 4 . 9 1 t l u a f e d : 2 4 3 4 s o p 6 i g e n 6 i i l c e p s d v l 6 e c n e r e f e r t u p n i l c e p e p y t t l u a f e d , z h m 4 4 . 9 1 t l u a f e d :
www.semtech.com 8 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. table 3. other pins (continued) n i pl o b m y so ie p y tn o i t p i r c s e d / e m a n 5 4k 2 c n y sil t t d z h k 2 e s i n o r h c n y s f o t u p t u o c n y s e m a r f - i t l u m z h k 2 o t t c e n n o c : m e t s y s y c n a d n u d e r n i 0 1 5 8 s c a r e n t r a p 6 43 iil t t d 3 e c n e r e f e r t u p n i z h k 8 t l u a f e d , e l b a m m a r g o r p : 7 44 iil t t d 4 e c n e r e f e r t u p n i z h k 8 t l u a f e d , e l b a m m a r g o r p : 8 47 iil t t d 7 e c n e r e f e r t u p n i z h m 4 4 . 9 1 t l u a f e d , e l b a m m a r g o r p : 1 58 iil t t d 8 e c n e r e f e r t u p n i z h m 4 4 . 9 1 t l u a f e d , e l b a m m a r g o r p : 2 59 iil t t d 9 e c n e r e f e r t u p n i z h m 4 4 . 9 1 t l u a f e d , e l b a m m a r g o r p : 3 50 1 iil t t d 0 1 e c n e r e f e r t u p n i . z h m 4 4 . 9 1 t l u a f e d , e l b a m m a r g o r p : 4 51 1 iil t t d : 1 1 e c n e r e f e r t u p n i , e l b a m m a r g o r p , z h m 8 4 0 . 2 / 4 4 5 . 1 ) e d o m r e t s a m ( t l u a f e d z h m 8 4 . 6 ) e d o m e v a l s ( t l u a f e d 5 52 1 iil t t d 2 1 e c n e r e f e r t u p n i . z h m 8 4 0 . 2 / 4 4 5 . 1 t l u a f e d , e l b a m m a r g o r p : 6 53 1 iil t t d 3 1 e c n e r e f e r t u p n i . z h m 8 4 0 . 2 / 4 4 5 . 1 t l u a f e d , e l b a m m a r g o r p : 7 54 1 iil t t d 4 1 e c n e r e f e r t u p n i . z h m 8 4 0 . 2 / 4 4 5 . 1 t l u a f e d , e l b a m m a r g o r p : 0 6 - 8 5) 0 : 2 ( l e s p uil t t d t c e l e s r o s s e c o r p o r c i m r a l u c i t r a p a r o f e c a f r e t n i e h t s e r u g i f n o c : . e p y t r o s s e c o r p o r c i m 9 6 - 3 6) 0 : 6 ( ail t t d s s e r d d a e c a f r e t n i r o s s e c o r p o r c i m e h t r o f s u b s s e r d d a : . e d o m l a i r e s n i i d s s i ) 0 ( a . s r e t s i g e r e c a f r e t n i r o s s e c o r p o r c i m 0 7b s cil t t u ) w o l e v i t c a ( t c e l e s p i h c e h t y b w o l d e t r e s s a s i n i p s i h t : . e c a f r e t n i r o s s e c o r p o r c i m e h t e l b a n e o t r o s s e c o r p o r c i m 1 7b r wil t t u ) w o l e v i t c a ( e t i r w e h t y b w o l d e t r e s s a s i n i p s i h t : 1 = b r w , e d o m a l o r o t o m n i . e l c y c e t i r w a e t a i t i n i o t r o s s e c o r p o r c i m . d a e r r o f 2 7b d ril t t u ) w o l e v i t c a ( d a e r e h t y b w o l d e t r e s s a s i n i p s i h t : . e l c y c d a e r a e t a i t i n i o t r o s s e c o r p o r c i m 3 7e l ail t t d e l b a n e h c t a l s s e r d d a h c t a l s s e r d d a e h t s e m o c e b n i p s i h t : m o r f s n o i t i s n a r t n i p s i h t n e h w . r o s s e c o r p o r c i m e h t m o r f e l b a n e l a n r e t n i e h t o t n i d e h c t a l e r a s t u p n i s u b s s e r d d a e h t , h g i h o t w o l . e d o m l a i r e s n i k l c s = e l a . s r e t s i g e r 4 7b r o pil t t u t e s e r n o r e w o p l a n r e t n i l l a , w o l d e c r o f s i b r o p f i . t e s e r r e t s a m : . s e u l a v t l u a f e d o t k c a b t e s e r e r a s e t a t s 5 7y d ro l t t s o m c e g d e l w o n k c a a t a d / y d a e r e t a c i d n i o t h g i h d e t r e s s a s i n i p s i h t : . n o i t a r e p o e t i r w r o d a e r a d e t e l p m o c s a h e c i v e d e h t 3 8 - 6 7) 0 : 7 ( d ao il t t d a t a d / s s e r d d a e h t n o g n i d n e p e d s u b s s e r d d a / a t a d d e x e l p i t l u m : . e d o m l a i r e s n i o d s s i ) 0 ( d a . n o i t c e l e s e d o m r o s s e c o r p o r c i m
www.semtech.com 9 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. functional description the acs8510 is a highly integrated, single-chip solution for the sets function in a sonet/sdh network element, for the generation of sec and frame synchronization pulses. in free-run mode, the acs8510 generates a stable, low- noise clock signal from an internal oscillator. in locked mode, the acs8510 selects the most appropriate input reference source and generates a stable, low-noise clock signal locked to the selected reference. in holdover mode, the acs8510 generates a stable, low-noise clock signal from the internal oscillator, adjusted to match the last known good frequency of the last selected reference source. in all modes, the frequency accuracy, jitter and drift performance of the clock meet the requirements of itu g.812, g.813, g.823, and gr-1244-core. the acs8510 supports all three types of reference clock source: recovered line clock (t in1 ), pdh network synchronization timing (t in2 ) and node synchronization (t in3 ). the acs8510 generates independent t out0 and t out4 clocks, an 8 khz frame synchronization clock and a 2 khz multi-frame synchronization clock. the acs8510 has a high tolerance to input jitter and wander. the jitter/wander transfer is programmable (0.1 hz up to 20 hz cut-off points). the acs8510 supports protection. two acs8510 devices can be configured to provide protection against a single acs8510 failure. the protection maintains alignment of the two acs8510 devices (master and slave) and ensures that both acs8510 devices maintain the same priority table, choose the same table 3. other pins (continued) n i pl o b m y so ie p y tn o i t p i r c s e d / e m a n 8 81 o to l t t s o m c 1 e c n e r e f e r t u p t u o 4 4 5 . 1 ( 1 g i d o s l a . z h m 8 4 . 6 t l u a f e d : z h m 2 9 . 5 2 , z h m 4 4 . 9 1 , ) x 8 , 4 , 2 d n a z h m 8 4 0 . 2 / z h m 9 82 o to l t t s o m c 2 e c n e r e f e r t u p t u o 4 4 5 . 1 ( 2 g i d o s l a . z h m 8 8 . 8 3 t l u a f e d : z h m 4 8 . 1 5 , z h m 2 9 . 5 2 , ) x 8 , 4 , 2 d n a z h m 8 4 0 . 2 / z h m 0 93 o to l t t s o m c 3 e c n e r e f e r t u p t u o . d e x i f - z h m 4 4 . 9 1 : 3 94 o to l t t s o m c 4 e c n e r e f e r t u p t u o . d e x i f - z h m 8 8 . 8 3 : 4 95 o to l t t s o m c 5 e c n e r e f e r t u p t u o . d e x i f - z h m 6 7 . 7 7 : 5 99 o to l t t s o m c 9 e c n e r e f e r t u p t u o ) s t i b 4 t ( . z h m 8 4 0 . 2 / 4 4 5 . 1 : 9 9b v l s t s mil t t u b e v a l s r e t s a m p u r e w o p l a i t i n i e h t s t e s : t c e l e s e v a l s r e t s a m : , r e t s i g e r n o i t c e l e s e v a l s / r e t s a m e h t f o ) b r o p a r e t f a e t a t s r o ( e t a t s y b p u r e w o p r e t f a d e g n a h c e b n a c e t a t s r e t s i g e r e h t . 1 t i b , 4 3 r d d a . e r a w t f o s 0 0 1b h d s n o sil t t d b h d s t e n o s l a i t i n i e h t s t e s : t c e l e s y c n e u q e r f h d s r o t e n o s : h d s / t e n o s e h t f o ) b r o p a r e t f a e t a t s r o ( e t a t s p u r e w o p 5 s t i b , 8 3 r d d a d n a 2 t i b , h 4 3 r d d a , s r e t s i g e r n o i t c e l e s y c n e u q e r f y b p u r e w o p r e t f a d e g n a h c e b n a c s e t a t s r e t s i g e r e h t . 6 d n a . e r a w t f o s
www.semtech.com 10 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. reference input and generate the t out0 clock, the 8 khz frame synchronization clock and the 2 khz multi-frame synchronization clock with the same phase. the acs8510 includes a microprocessor port, providing access to the configuration and status registers for device setup and monitoring. local oscillator clock the master system clock on the acs8510 should be provided by an external clock oscillator of frequency 12.80 mhz. the clock specification is important for meeting the itu/etsi and telcordia performance requirements for holdover mode. itu and etsi specifications permit a combined drift characteristic, at constant temperature, of all non-temperature- related parameters, of up to 10 ppb per day. the same specifications allow a drift of 1 ppm over a temperature range of 0 to +70 c. telcordia specifications are somewhat tighter, requiring a non-temperature-related drift of less than 40 ppb per day and a drift of 280 ppb over the temperature range 0 to +50 c. itu and etsi specification tolerance: +/- 4.6 ppm over 20 year life time. drift*: +/- 0.05 ppm/15 seconds @ constant temp. +/- 0.01 ppm/day @ constant temp. +/- 1 ppm over temp. range 0 to +70 c *frequency drift over supply range of +2.7v to +3.3v. telcordia gr-1244 core specification tolerance: +/- 4.6 ppm over 20 year life time. drift*: +/- 0.05 ppm/15 seconds @ constant temp. +/- 0.04 ppm/day @ constant temp. +/- 0.28 ppm over temp. range 0 to +50 c *frequency drift over supply range of +2.7v to +3.3v. please contact semtech for information on crystal oscillator suppliers. crystal frequency calibration the absolute crystal frequency accuracy is less important than the stability since any frequency offset can be compensated by adjustment of register values in the ic. this allows for calibration and compensation of any crystal frequency variation away from its nominal value. +/- 50 ppm adjustment would be sufficient to cope with most crystals, in fact the range is an order of magnitude larger due to the use of two 8 bit register locations. the setting of the conf_nominal_frequency register allows for this adjustment. an increase in the register value increases the output frequencies by 0.02 ppm for each lsb step. the default value (in decimal) is 39321. the minimum being 0 and the maximum 65535, gives a -700 ppm to +500 ppm adjustment range of the output frequencies. for example, if the crystal was oscillating at 12.8 mhz + 5 ppm, then the calibration value in the register to give a -5 ppm adjustment in output frequencies to compensate for the crystal inaccuracy, would be : 39321 - (5 / 0.02) = 39071 (decimal) input interfaces the acs8510 supports up to fourteen input reference clock sources from input types t in1 , t in2 and t in3 using ttl, cmos, pecl, lvds and ami buffer i/o technologies. these interface technologies support +3.3 v and +5 v operation. over-voltage protection the acs8510 may require over-voltage protection on input reference clock ports according to itu recommendation k.41. semtech protection devices are recommended for this purpose (see separate semtech data book).
www.semtech.com 11 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. input reference clock ports table 4 gives details of the input reference ports, showing the input technologies and the range of frequencies supported on each port; the default spot frequencies and default priorities assigned to each port on power-up or by reset are also shown. note that sdh and sonet networks use different default frequencies; the network type is pin-selectable (using the sonsdhb pin). specific frequencies and priorities are set by configuration. although each input port is shown as belonging to one of the types, t in1 , t in2 or t in3 , they are fully interchangeable as long as the selected speed is within the maximum operating speed of the input port technology. sdh and sonet networks use different default frequencies; the network type is selectable using the config_mode register 34 hex, bit 2. for sonet, config_mode register 34 hex, bit 2 = 1, for sdh config_mode register 34 hex, bit 2 = 0. on power-up or by reset, the default will be set by the state of the sonsdhb pin (pin 100). specific frequencies and priorities are set by configuration. ttl ports (compatible also with cmos signals) support clock speeds up to 100 mhz, with the highest spot frequency being 77.76 mhz. the actual spot frequencies supported are: ? 2 khz ? 4 khz ? 8 khz (and n x 8 khz) ? 1.544 mhz (sonet)/2.048 mhz (sdh) ? 6.48 mhz, ? 19.44 mhz, ? 25.92 mhz, ? 38.88 mhz, ? 51.84 mhz, ? 77.76 mhz. the frequency selection is programmed via the cnfg_ref_source_frequency register. the internal dpll will normally lock to the selected input at the frequency of the input, eg. 19.44 mhz will lock the dpll phase comparisons at 19.44 mhz. it is, however, possible to utilise an internal pre-divider to the dpll to divide the input frequency before it is used for phase comparisons in the dpll. this pre-divider can be used in one of 2 ways: 1. any of the supported spot frequencies can be divided to 8 khz by setting the ?lock8k? bit (bit 6) in the appropriate cnfg_ref_source_frequency register location. for good jitter tolerance for all frequencies and for operation at 19.44 mhz and above, use lock8k. it is possible to choose which edge of the 8khz input to lock to, by setting the appropriate bit of the cnfg_control1 register. 2. any multiple of 8 khz between 1544 khz to 100 mhz can be supported by using the ?divn? feature (bit 7 of the cnfg_ref_source_frequency register). any reference input can be set to use divn independently of the frequencies and configurations of the other inputs. any reference input with the divn bit set in the cnfg_ref_source_frequency register will employ the internal pre-divider prior to the dpll locking. the cnfg_freq_divn register contains the divider ratio n where the reference input will get divided by (n+1) where 0 www.semtech.com 12 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. table 4. input reference source selection and priority table t r o p r e b m u n l e n n a h c r e b m u n t r o p e p y t t r o p t u p n i y g o l o n h c e t d e t r o p p u s s e i c n e u q e r f t l u a f e d y t i r o i r p 1 _ i1 0 0 0t n i3 i m a ) z h k 8 + z h k 4 6 , k c o l c e t i s o p m o c ( z h k 8 / 4 6 z h k 8 / 4 6 : ) t e n o s ( t l u a f e d z h k 8 / 4 6 : ) h d s ( t l u a f e d 2 2 _ i0 1 0 0t n i3 i m a ) z h k 8 + z h k 4 6 , k c o l c e t i s o p m o c ( z h k 8 / 4 6 z h k 8 / 4 6 : ) t e n o s ( t l u a f e d z h k 8 / 4 6 : ) h d s ( t l u a f e d 3 3 _ i1 1 0 0t n i3 s o m c / l t t z h m 0 0 1 o t p u) 1 e t o n e e s ( : ) t e n o s ( t l u a f e dh k 8z : ) h d s ( t l u a f e dh k 8z 4 4 _ i0 0 1 0t n i3 s o m c / l t t z h m 0 0 1 o t p u) 1 e t o n e e s ( : ) t e n o s ( t l u a f e dh k 8z : ) h d s ( t l u a f e dh k 8z 5 5 _ i1 0 1 0t n i1 l c e p / s d v l t l u a f e d s d v l z h m 2 5 . 5 5 1 o t p u) 2 e t o n e e s ( z h m 4 4 . 9 1 : ) t e n o s ( t l u a f e d z h m 4 4 . 9 1 : ) h d s ( t l u a f e d 6 6 _ i0 1 1 0t n i1 s d v l / l c e p t l u a f e d l c e p z h m 2 5 . 5 5 1 o t p u) 2 e t o n e e s ( z h m 4 4 . 9 1 : ) t e n o s ( t l u a f e d z h m 4 4 . 9 1 : ) h d s ( t l u a f e d 7 7 _ i1 1 1 0t n i1 s o m c / l t t z h m 0 0 1 o t p u) 1 e t o n e e s ( z h m 4 4 . 9 1 : ) t e n o s ( t l u a f e d z h m 4 4 . 9 1 : ) h d s ( t l u a f e d 8 8 _ i0 0 0 1t n i1 s o m c / l t t z h m 0 0 1 o t p u) 1 e t o n e e s ( z h m 4 4 . 9 1 : ) t e n o s ( t l u a f e d z h m 4 4 . 9 1 : ) h d s ( t l u a f e d 9 9 _ i1 0 0 1t n i1 s o m c / l t t z h m 0 0 1 o t p u) 1 e t o n e e s ( z h m 4 4 . 9 1 : ) t e n o s ( t l u a f e d z h m 4 4 . 9 1 : ) h d s ( t l u a f e d 0 1 0 1 _ i0 1 0 1t n i1 s o m c / l t t z h m 0 0 1 o t p u) 1 e t o n e e s ( : ) t e n o s ( t l u a f e dz h m 4 4 . 9 1 z h m 4 4 . 9 1 : ) h d s ( t l u a f e d 1 1 1 1 _ i1 1 0 1t n i2 s o m c / l t t ) 1 e t o n e e s ( z h m 0 0 1 o t p u z h m 4 4 5 . 1 : ) t e n o s ( ) r e t s a m ( t l u a f e d z h m 8 4 0 . 2 : ) h d s ( ) r e t s a m ( t l u a f e d ) e v a l s ( t l u a f e d6z h m 8 4 . 1 / 2 1 ) 3 e t o n ( 2 1 _ i0 0 1 1t n i2 s o m c / l t t z h m 0 0 1 o t p u) 1 e t o n e e s ( z h m 4 4 5 . 1 : ) t e n o s ( t l u a f e d z h m 8 4 0 . 2 : ) h d s ( t l u a f e d 3 1 3 1 _ i1 0 1 1t n i2 s o m c / l t t z h m 0 0 1 o t p u) 1 e t o n e e s ( z h m 4 4 5 . 1 : ) t e n o s ( t l u a f e d z h m 8 4 0 . 2 : ) h d s ( t l u a f e d 4 1 4 1 _ i0 1 1 1t n i2 s o m c / l t t z h m 0 0 1 o t p u) 1 e t o n e e s ( z h m 4 4 5 . 1 : ) t e n o s ( t l u a f e d z h m 8 4 0 . 2 : ) h d s ( t l u a f e d 5 1
www.semtech.com 13 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. notes for table 4. note 1: ttl ports (compatible also with cmos signals) support clock speeds up to 100 mhz, with the highest spot frequency being 77.76 mhz. the actual spot frequencies are: 2 khz, 4 khz, 8 khz (and n x 8 khz), 1.544 mhz (sonet)/2.048 mhz (sdh), 6.48 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz. sonet or sdh is selected using the sonsdhb pin. when the sonsdhb pin is high sonet is selected, when the sonsdhb pin is low sdh is selected. note 2: pecl and lvds ports support the spot clock frequencies listed above plus 155.52 mhz and 311.04 mhz. note 3: input port is set at 12 on the master sets ic and 1 on the slave sets ic, as default on power up (or porb). the default setup of master or slave priority is determined by the mstslvb pin. pecl and lvds ports support the spot clock frequencies listed plus 155.52 mhz and 311.04 mhz. the choice of pecl or lvds compatibility is programmed via the cnfg_differential_inputs register. unused pecl/ lvds differential inputs should be fixed with one input high (vdd) and the other input low (gnd), or set in lvds mode and left floating, in which case one input is internally pulled high and the other low. an ami port supports a composite clock, consisting of a 64 khz ami clock with 8 khz boundaries marked by deliberate violations of the ami coding rules, as specified in itu recommendation g.703. departures from the nominal pattern are detected within the acs8510, and may cause reference-switching if too frequent. see section dc characteristics: ami input/output port, for more details. if the ami port is unused, the pins (i1 and i2) should be tied to gnd and the vami+ supply pin (pin 26) disconnected. input wander and jitter tolerance the acs8510 is compliant to the requirements of all relevant standards, principally itu recommendation g.825, ansi ds1.101-1994 and ets 300 462-5 (1997). all reference clock inputs have a tight frequency tolerance but a generous jitter tolerance. pull- in, hold-in and pull-out ranges are specified for each input port in table 5. minimum jitter divn examples to lock to 2.000 mhz. (1) the cnfg_ref_source_frequency register is set to 11xx0001 (binary) to set the divn, lock8k bits, and the frequency to e1/ds1. (xx = ?leaky bucket? id for this input). (2) the cnfg_mode register (34hex) bit 2 needs to be set to 1 to select sonet frequencies (ds1). (3) the frequency monitors are disabled in cnfg_monitors register (48hex) by writing 00 to bits 0 and 1. (4) the divn register is set to f9 hex (249 decimal). to lock to 10.000 mhz. (1) the cnfg_ref_source_frequency register is set to 11xx0010 (binary) to set the divn, lock8k bits, and the frequency to 6.48 mhz. (xx = ?leaky bucket? id for this input). (2) the frequency monitors are disabled in cnfg_monitors register (48hex) by writing 00 to bits 0 and 1. (3) the divn register is set to 4e1 hex (1249 decimal).
www.semtech.com 14 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. tolerance masks are specified in figures 3 and 4, and tables 6 and 7, respectively. the acs8510 will tolerate wander and jitter components greater than those shown in figure 3 and figure 4, up to a limit determined by a combination of the apparent long-term frequency offset caused by wander and the eye-closure caused by jitter (the input source will be rejected if the offset pushes the frequency outside the hold-in range for long enough to be detected, whilst the signal will also be rejected if the eye closes sufficiently to affect the signal purity). the ?8klocking? mode should be engaged for high jitter tolerance according to these masks. all reference clock ports are monitored for quality, including frequency offset and general activity. single short-term interruptions in selected reference clocks may not cause rearrangements, whilst longer interruptions, or multiple, short-term interruptions, will cause rearrangements, as will frequency offsets which are sufficiently large or sufficiently long to cause loss-of-lock in the phase-locked loop. the failed reference source will be removed from the priority table and declared as unserviceable, until its perceived quality has been restored to an acceptable level. the registers sts_curr_inc_offset (address 0c, 0d, 07) report the frequency of the dpll with respect to the external tcxo frequency. this is a 19 bit signed number with one lsb representing 0.0003 ppm (range of +/- 80 ppm). reading this regularly can show how the currently locked source is varying in value e.g. due to wander on its input. the acs8510 performs automatic frequency monitoring with an acceptable input frequency offset range of +/- 16.6 ppm. the acs8510 dpll has a programmable frequency limit of +/- 80 ppm. if the range is programmed to be > 16.6 ppm, the frequency monitors should be disabled so the input reference source is not automatically rejected as out of frequency range. r e t t i j e c n a r e l o t r o t i n o m y c n e u q e r f e g n a r e c n a t p e c c a y c n e u q e r f e g n a r e c n a t p e c c a ) n i - l l u p ( y c n e u q e r f e c n a t p e c c a ) n i - d l o h ( e g n a r y c n e u q e r f e g n a r e c n a t p e c c a ) t u o - l l u p ( 3 0 7 . g m p p 6 . 6 1 - / + m p p 6 . 4 - / + ) 1 e t o n e e s ( m p p 2 . 9 - / + ) 2 e t o n e e s ( m p p 6 . 4 - / + ) 1 e t o n e e s ( m p p 2 . 9 - / + ) 2 e t o n e e s ( m p p 6 . 4 - / + ) 1 e t o n e e s ( m p p 2 . 9 - / + ) 2 e t o n e e s ( 3 8 7 . g 3 2 8 . g e r o c - 4 4 2 1 - r g table 5. input reference source jitter tolerance notes for table 5. note 1. the frequency acceptance and generation range will be +/-4.6 ppm around the required frequency when the external crystal frequency accuracy is within a tolerance of +/- 4.6 ppm. note 2. the fundamental acceptance range and generation range is +/- 9.2 ppm with an exact external crystal frequency of 12.8 mhz. this is the default dpll range, the range is also programmable from 0 to 80 ppm in 0.08 ppm steps.
www.semtech.com 15 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. i i i i i i i $ $ $ $ -lwwhudqgzdqghuiuhtxhqf\orjvfdoh i i $ i i i i i i i $ $ $ $ -lwwhudqgzdqghuiuhtxhqf\orjvfdoh i i $ (for inputs supporting g.783 compliant sources) table 6. amplitude and frequency values for jitter tolerance m t s l e v e l e d u t i l p m a k a e p o t k a e p ) l a v r e t n i t i n u ( ) z h ( y c n e u q e r f 0 a1 a2 a3 a4 a0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f 1 - m t s0 0 8 21 1 39 35 . 15 1 . 0u 2 1u 8 7 1m 6 . 1m 6 . 5 15 2 1 . 03 . 9 10 0 5k 5 . 6k 5 6m 3 . 1 output clock ports the device supports a set of main output clocks, t out0 and t out4 , and a pair of secondary output clocks, 'frame-sync' and 'multi-frame-sync'. the two main output clocks, t out0 and t out4 , are independent of each other and are individually selectable. the two secondary output clocks, 'frame-sync' and 'multi-frame-sync', are derived from t out0 . the frequencies of the output clocks are selectable from a range of pre-defined spot frequencies and a variety of output technologies are supported, as defined in table 8. low-speed output clock (t out4 ) the t out4 clock is supplied on two output ports, t o8 and t o9 . the former port will provide an ami signal carrying a composite clock of 64 khz and 8 khz, according to itu recommendation g.703. the latter port will provide a ttl/cmos signal at either 1.544 mhz or 2.048 mhz, depending on the setting of the sonsdhb pin. high-speed output clock (part of t out0 ) the t out0 port has multiple outputs. outputs t o1 and t o2 are ttl/cmos output with a choice of 11 different frequencies up to 51.84 mhz. outputs t o3 to t o5 are all ttl/cmos outputs with fixed frequencies of 19.44 mhz, 38.88 mhz and 77.76 mhz respectively. output t o6 is differential and can support clocks up to 155.52 mhz. output t o7 is also differential and can support clocks up to 155.52 mhz. each output is individually configured to operate at the frequencies shown in table 8 (configuration must be consistent between acs8510 devices for protection-switching to be effective - output clocks will be phase-aligned figure 3. minimum input jitter tolerance (oc-3/stm-1)
www.semtech.com 16 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. between devices). using the cnfg_differential_outputs register, outputs t o6 and t o7 can be made to be lvds or pecl compatible. frame sync and multi-frame sync clocks (part of t out0 ) frame sync (8 khz) and multi-frame sync (2 khz) clocks are provided on outputs t o10 (frsync) and t o11 (mfrsync). the frsync and mfrsync clocks have a 50:50 mark space ratio. these are driven from the t out0 clock. they are synchronized with their counterparts in a second acs8510 device (if used), using the technique described later. low jitter multiple e1/ds1 outputs this feature added to rev2.1 is activated using the cnfg_control1 register. this sends a fre- quency of twice the dig2 rate (see reg addr 39h, bits 7:6) to the apll instead of the normal 77.76mhz. for this feature to be used, the dig2 rate must only be set to 12352khz/16384khz using the cnfg_t0_output_frequencies register. the normal oc3 rate outputs are then replaced with e1/ds1 multiple rates. the e1(sonet)/ ds1(sdh) selection is made in the same way as for dig2 using the cnfg_t0_output_enable reg- ister. table 9 shows the relationship between primary output frequencies and the correspond- ing output in e1/ds1 mode, and which output they are available from. e p y t. c e p s e d u t i l p m a ) k p - k p i u ( y c n e u q e r f ) z h ( 1 a2 a1 f2 f3 f4 f 1 s de r o c - 4 4 2 1 - r g 51 . 00 10 0 5k 8k 0 4 1 e3 2 8 . g u t i 5 . 12 . 00 2k 4 . 2k 8 1k 0 0 1 i i i i $ $ 3hdnwrshdnmlwwhudqgzdqghudpsolwxghorj vfdoh -lwwhudqgzdqghuiuhtxhqf\orjvfdoh i i i i $ $ 3hdnwrshdnmlwwhudqgzdqghudpsolwxghorj vfdoh -lwwhudqgzdqghuiuhtxhqf\orjvfdoh (for inputs supporting g.783 compliant sources) figure 4. minimum input jitter tolerance (ds1/e1) table 7. amplitude and frequency values for jitter tolerance
www.semtech.com 17 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. output wander and jitter wander and jitter present on the output clocks are dependent on: 1. the magnitude of wander and jitter on the selected input reference clock (in locked mode) 2. the internal wander and jitter transfer characteristic (in locked mode) 3. the jitter on the local oscillator clock 4. the wander on the local oscillator clock (in holdover mode) wander and jitter are treated in different ways to reflect their differing impacts on network design. jitter is always strongly attenuated, whilst wander attenuation can be varied to suit the application and operating state. wander and jitter attenuation is performed using a digital phase locked loop (dpll) with a programmable bandwidth. this gives a transfer characteristic of a low pass filter, with a programmable pole. it is sometimes necessary to change the filter dynamics to suit particular circumstances - one example being when locking to a new source, note for table 8. where 1.544 mhz/2.048 mhz is shown, 1.544 mhz is sonet, and 2.048 mhz is sdh. pin sonsdhb controls the default frequency output. where the sonsdhb pin is high sonet is default, and when sonsdhb pin is low sdh is default. t r o p e m a n t r o p t u p t u o y g o l o n h c e t d e t r o p p u s s e i c n e u q e r f t 1 0 s o m c / l t t , z h m 2 9 1 . 8 / z h m 6 7 1 . 6 , z h m 6 9 0 . 4 / z h m 8 8 0 . 3 , z h m 8 4 0 . 2 / z h m 4 4 5 . 1 z h m 2 9 . 5 2 , z h m 4 4 . 9 1 , z h m 4 8 3 . 6 1 / z h m 2 5 3 . 2 1 , ) t l u a f e d ( z h m 8 4 . 6 t 2 0 s o m c / l t t , z h m 2 9 1 . 8 / z h m 6 7 1 . 6 , z h m 6 9 0 . 4 / z h m 8 8 0 . 3 , z h m 8 4 0 . 2 / z h m 4 4 5 . 1 z h m 4 8 . 1 5 , ) t l u a f e d ( z h m 8 8 . 8 3 , z h m 2 9 . 5 2 , z h m 4 8 3 . 6 1 / z h m 2 5 3 . 2 1 t 3 0 s o m c / l t td e x i f - z h m 4 4 . 9 1 t 4 0 s o m c / l t td e x i f - z h m 8 8 . 8 3 t 5 0 s o m c / l t td e x i f - z h m 6 7 . 7 7 t 6 0 ls d vl c e p / s d v l () t l u a f e d , z h m 2 9 1 . 8 / z h m 6 7 1 . 6 , z h m 6 9 0 . 4 / z h m 8 8 0 . 3 , z h m 8 4 0 . 2 / z h m 4 4 5 . 1 , z h m 2 5 . 5 5 1 , ) t l u a f e d ( z h m 8 8 . 8 3 , z h m 4 4 . 9 1 , z h m 4 8 3 . 6 1 / z h m 2 5 3 . 2 1 z h m 4 0 . 1 1 3 t 7 0 s d v l / l c e p l c e p () t l u a f e d z h m 2 5 . 5 5 1 , z h m 6 7 . 7 7 , z h m 4 8 . 1 5 , ) t l u a f e d ( z h m 4 4 . 9 1 t 8 0 i m a) z h k 8 + z h k 4 6 , k c o l c e t i s o p m o c ( z h k 8 / 4 6 t 9 0 s o m c / l t tz h m 8 4 0 . 2 / z h m 4 4 5 . 1 t 0 1 0 s o m c / l t tr s m 0 5 : 0 5 a h t i w - z h k 8 , c n y s r f t 1 1 0 s o m c / l t tr s m 0 5 : 0 5 a h t i w - z h k 2 , c n y s r f m table 8. output reference source selection table
www.semtech.com 18 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. the filter can be opened up to reduce locking time and can then be gradually tightened again to remove wander. since wander represents a relatively long-term deviation from the nominal operating frequency, it affects the rate of supply of data to the network element. strong wander attenuation limits the rate of consumption of data to within a smaller range, so a larger buffer store is required to prevent data loss. but, since any buffer store potentially increases latency, wander may often only need to be removed at specific points within a network where buffer stores are acceptable, such as at digital cross connects. otherwise, wander is sometimes not required to be attenuated and can be passed through transparently. the acs8510 has programmable wander transfer characteristics in a range from 0.1 hz to 20 hz. the wander and jitter transfer characteristic is shown in figure 5. wander on the local oscillator clock will not have significant effect on the output clock whilst in locked mode, so long as the dpll bandwidth is set high enough so that the dpll can compensate quickly enough for any frequency changes in the crystal. in free-run or holdover mode wander on the crystal is more significant. variation in crystal temperature or supply voltage both cause drifts in operating frequency, as does ageing. these effects must be limited by careful selection of a suitable component for the local oscillator, as specified in the section ?local oscillator clock?. phase variation there will be a phase shift across the acs8510 between the selected input reference source and the output clock. this phase shift may vary over time but will be constrained to lie within specified limits. the phase shift is characterised using two parameters, mtie (maximum time interval error), and tdev (time deviation), which, although being specified in all relevent specifications, differ in acceptable limits in each one. typical measurements for the acs8510 are shown in figures 6 and 7, for locked mode operation. figure 8 shows a typical measurement of phase error accumulation in holdover mode operation. the required performance for phase variation during holdover is specified in several ways depending upon the particular circumstances pertaining: e d o mo t q e r f l l p a l l p a r e i l p i t l u m l l p a q e r f t l i f _ k l c_ k l c 2 / t l i f _ k l c 4 / t l i f _ k l c 6 / t l i f _ k l c 8 / t l i f _ k l c 2 1 / t l i f _ k l c 6 1 / t l i f _ k l c 8 4 / t l i f l l p d q e r f t l u a f e d6 7 . 7 74 4 0 . 1 1 34 0 . 1 1 32 5 . 5 5 16 7 . 7 74 8 . 1 58 8 . 8 32 9 . 5 24 4 . 9 18 4 . 66 7 . 7 7 e u l a v n 6 184 1 e x n8 6 7 . 2 34 2 7 0 . 1 3 12 7 0 . 1 3 16 3 5 . 5 6 8 6 7 . 2 3 3 3 5 4 8 . 1 2 4 8 3 . 6 1 7 6 2 2 9 . 0 1 2 9 1 . 8 7 6 6 0 3 7 . 26 7 . 7 7 1 t x n4 0 7 . 4 246 1 8 . 8 96 1 8 . 8 98 0 4 . 9 4 4 0 7 . 4 2 3 3 9 6 4 . 6 1 2 5 3 . 2 1 7 6 6 4 3 2 . 8 6 7 1 . 6 7 6 6 8 5 0 . 26 7 . 7 7 t u p t u o y b e l b a l i a v a s e i c n e u q e r f 1 0 t 2 0 t 3 0 t 4 0 t 5 0 t 6 0 t 6 0 t 6 0 t 7 0 t 7 0 t table 9. multiple e1/ds1 ouputs in relation to standard outputs
www.semtech.com 19 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. 1. etsi 300 462-5, section 9.1, requires that the short- term phase error during switchover (i.e., locked to holdover to locked) be limited to an accumulation rate no greater than 0.05 ppm during a 15 second interval. 2. etsi 300 462-5, section 9.2, requires that the long- term phase error in the holdover mode should not exceed {(a1+a2)s+0.5bs 2 +c} where a1 = 50 ns/s (allowance for initial frequency offset) a2 = 2000 ns/s (allowance for temperature variation) b = 1.16x10 -4 ns/s 2 (allowance for ageing) c = 120 ns (allowance for entry into holdover mode). 3. ansi tin1.101-1994, section 8.2.2, requires that the phase variation be limited so that no more than 255 slips (of 125 s each) occur during the first day of holdover. this requires a frequency accuracy better than: ((24x60x60)+(255x125s))/(24x60x60) = 0.37 ppm temperature variation is not restricted, except to within the normal bounds of 0 to 50 c. 4. telcordia gr.1244.core, section 5.2., table 4, shows that an initial frequency offset of 50 ppb is permitted on entering holdover, whilst a drift over temperature of 280 ppb is allowed; an allowance of 40 ppb is permitted for all other effects. 5. itu g.822, section 2.6, requires that the slip rate during category(b) operation (interpreted as being applicable to holdover mode operation) be limited to less than 30 slips (of 125 s each) per hour ((((60 x 60)/30)+125s)/(60x60)) = 1.042 ppm * d l q g % )uhtxhqf\+] +] +] +] +] +] +] +] +] figure 5. wander and jitter measured transfer characteristics
www.semtech.com 20 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. 10 1 0.1 0.01 time (ns) 0.01 0.1 1 10 100 1000 10000 observation interval (s) g.813 option 1 constant temperature wander limit tdev measurement on 155 mhz output, 19.44 mhz i/p (8khz locking), vectron 6664 xtal 100 10 1 0.1 0.01 0.01 0.1 1 10 100 1000 10000 observation interval (s) time (ns) g.813 option 1, constant temperature wander limit mtie measurement on 155 mhz output, 19.44 mhz i/p (8khz locking), vectron 6664 xtal 10000000 1000000 100000 10000 1000 100 1000 10000 100000 observation interval (s) phase error (ns) permitted phase error limit typical measurement, 25c constant temperature figure 8. phase error accumulation of t out0 output port in holdover mode figure 6. maximum time interval error of t out0 output port figure 7. time deviation of t out0 output port
www.semtech.com 21 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. phase build out phase build out (pbo) is the function to minimise phase transients on the output sec clock during input reference switching. if the currently selected input reference clock source is lost (due to a short interruption, out of frequency detection, or complete loss of reference), the second, next highest priority reference source will be selected. during this transition, the lost_phase mode is entered. the typical phase disturbance on clock reference source switching will be less than 12 ns on the acs8510. for clock reference switching caused by the main input failing or being disconnected, then the phase disturbance on the output will still be less than the 120 ns allowed for in the g.813 spec. the actual value is dependent on the frequency being locked to. itu-t g.813 states that the max allowable short term phase transient response, resulting from a switch from one clock source to another, with holdover mode entered in between, should be a maximum of 1 s over a 15 second interval. the maximum phase transient or jump should be less than 120 ns at a rate of change of less than 7.5 ppm and the holdover performance should be better than 0.05 ppm. on the acs8510, pbo can be enabled, disabled or frozen using the p interface. by default, it is enabled. when pbo is enabled, it can also be frozen, which will disable the pbo operation on the next input reference switch, but will remain with the current offset. if pbo is disabled while the device is in the locked mode, there will be a phase jump on the output sec clocks as the dpll locks back to 0 degree phase error. microprocessor interface the acs8510 incorporates a microprocessor interface, which can be configured for the following modes via the bus interface mode control pins upsel(2:0) as defined in table 10. table 10. microprocessor interface mode selection motorola mode parallel data + address: this mode is suitable for use with motorola's 68x0 type bus. intel mode parallel data + address: this mode is suitable for use with intel's 80x86 type bus. multiplexed mode data/address: this mode is suitable for use with microprocessors which share bus signals between address and data (e.g., intel's 80x86 family). serial mode this mode is suitable for use with micro- processor which use a serial interface. eprom mode this mode is suitable for simple standalone applications where it is required to change the default loading of the register values to suit different applications. this can be done by loading values from an external rom. the data is read from the rom automatically after power up when the upsel(2:0) pins are set to ?001?. each register value is stored sequentially, with rom address 0 corresponding to register address 0 and so on. the value in the ?chip_id? location (address 00 & 01) is checked to see if it matches the id number of the acs8510 v2 (value 213e). upon a successful number match, the remaining data upsel(2:0) mode description 111 (7) off interface disabled 110 (6) off interface disabled 101 (5) serial serial up bus interface 100 (4) motorola motorola interface 011 (3) intel intel compatible bus interface 010 (2) multiplexed mu ltiplexed bus interface 001 (1) eprom eprom read mode 000 (0) off interface disabled
www.semtech.com 22 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. interrupt enable and clear interrupt requests are flagged on pin intreq (active high). bits in the interrupt status register are set (high) by the following conditions: 1. any reference source becoming valid or going invalid 2. a change in the operating state (eg. locked, holdover etc.) 3. a brief loss of the currently selected reference source 4. an ami input error all interrupt sources are maskable via the mask register, each one being enabled by writing a '1' to the appropriate bit. any unmasked bit set in the interrupt status register will cause the interrupt request pin to be asserted (high). all interrupts are cleared by writing a '1' to the bit(s) to be cleared in the status register. when all pending unmasked interrupts are cleared the interrupt pin will go inactive (low). the loss of the currently selected reference source will eventually cause the input to be considered invalid, triggering an interrupt. the time taken to raise this interrupt is dependant on the leaky bucket configuration of the activity monitors. the fastest leaky bucket setting will still take up to 128 ms to trigger the interrupt. the interrupt caused by the brief loss of the currently selected reference source is provided to facilitate very fast source failure detection if desired. it is triggered after missing just a couple of cycles of the reference source. some applications require the facility to switch downstream devices based on the status of the reference sources. in order to provide extra flexibility, it is possible to flag the ?main reference failed? interrupt (addr 06, bit 6) on the pin tdo. this is simply a copy of the status bit in the interrupt register and is independent of the mask register settings. the bit is reset by writing to the interrupt status register in the normal way. this feature can be enabled and disabled by writing to bit 6 of register 48hex. from the rom is used to set the internal register values. only 64 locations in the rom are required. register set all registers are 8-bits wide, organised with the most-significant bit positioned in the left-most bit, with bit significance decreasing towards the right most bit. some registers carry several individual data fields of various sizes, from single-bit values (e.g. flags) upwards. several data fields are spread across multiple registers; their organisation is shown in the register map, table 11. configuration registers each configuration register reverts to a default value on power-up or following a reset. most default values are fixed, but some will be pin- settable. all configuration registers can be read out over the microprocessor port. status registers the status registers contain readable registers. they may all be read from outside the chip but are not writeable from outside the chip (except for a clearing operation). all status registers are read via shadow registers to avoid data hits due to dynamic operation. each individual status register has a unique location. register access most registers are of one of two types, configuration registers or status registers, the exceptions being the chip_id and chip_revision registers. configuration registers may be written to or read from at any time (the complete 8-bit register must be written, even if only one bit is being modified). all status registers may be read at any time and, in some status registers (such as the sts_interrupts register), any individual data field may be cleared by writing a ?1? into each bit of the field (writing a ?0? value into a bit will not affect the value of the bit). a description of each register is given in the register map, and register map description.
www.semtech.com 23 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. . r d d a ) x e h ( e m a n r e t e m a r a pt i b a t a d ) b s m ( 7 654321 ) b s l ( 0 0 0d i _ p i h c ) y l n o d a e r ( ) 0 : 7 ( r e b m u n t r a p e c i v e d 1 0 ) 8 : 5 1 ( r e b m u n t r a p e c i v e d 2 0n o i s i v e r _ p i h c ) y l n o d a e r ( ) 0 : 7 ( r e b m u n n o i s i v e r p i h c 3 01 l o r t n o c _ g f n c ) e t i r w / d a e r ( e l p i t l u m p / o 1 t / 1 e g o l a n a c n y s v i d ' 0 ' o t t e s e g d e k 8 y t i r a l o p ' 0 ' o t t e s' 0 ' o t t e s 4 02 l o r t n o c _ g f n c ) e t i r w / d a e r ( t i m i l g a l f s s o l e s a h p' 0 ' o t t e s' 1 ' o t t e s' 0 ' o t t e s 5 0s t p u r r e t n i _ s t s ) e t i r w / d a e r ( d i l a v > 8 _ i < e g n a h c d i l a v > 7 _ i < e g n a h c d i l a v > 6 _ i < e g n a h c d i l a v > 5 _ i < e g n a h c d i l a v > 4 _ i < e g n a h c d i l a v > 3 _ i < e g n a h c d i l a v > 2 _ i < e g n a h c d i l a v > 1 _ i < e g n a h c 6 0g n i t a r e p o e d o m . f e r n i a m d e l i a f d i l a v > 4 1 _ i < e g n a h c d i l a v > 3 1 _ i < e g n a h c d i l a v > 2 1 _ i < e g n a h c d i l a v > 1 1 _ i < e g n a h c d i l a v > 0 1 _ i < e g n a h c d i l a v > 9 _ i < e g n a h c 8 0s t u p n i _ 4 t _ s t s ) e t i r w / d a e r ( d e l i a f f e r 4 t 2 i m a n o i t a l o i v 2 i m a . s . o . l 1 i m a n o i t a l o i v 1 i m a . s . o . l 9 0e d o m _ g n i t a r e p o _ s t s ) y l n o d a e r ( ) 0 : 2 ( e d o m g n i t a r e p o a 0e l b a t _ y t i r o i r p _ s t s ) y l n o d a e r ( e c r u o s d i l a v y t i r o i r p t s e h g i h e c r u o s e c n e r e f e r d e t c e l e s y l t n e r r u c b 0 3 d r e c r u o s d i l a v y t i r o i r p t s e h g i h2 d n e c r u o s d i l a v y t i r o i r p t s e h g i h c 0t e s f f o _ c n i _ r r u c _ s t s ) y l n o d a e r ( ) 0 : 7 ( t e s f f o t n e m e r c n i t n e r r u c d 0 ) 8 : 5 1 ( t e s f f o t n e m e r c n i t n e r r u c 7 0 ) 6 1 : 8 1 ( t e s f f o t n e m e r c n i t n e r r u c e 0d i l a v _ s e c r u o s _ s t s ) y l n o d a e r ( > 8 _ i <> 7 _ i <> 6 _ i <> 5 _ i <> 4 _ i <> 3 _ i <> 2 _ i <> 1 _ i < f 0 > 4 1 _ i <> 3 1 _ i <> 2 1 _ i <> 1 1 _ i <> 0 1 _ i <> 9 _ i < register map shaded areas in the map are ?don?t care? and writing either 0 or 1 will not affect any function of the device. bits labelled ?set to 0? or ?set to 1? must be set as stated during initialisation of the device, either following power up, or after a power on reset (por). failure to correctly set these bits may result in the device operating in an unexpected way. some registers do not appear in this list. these are either not used, or have test functionality. do not write to any undefined registers as this may cause the device to operate in a test mode. if an undefined register has been inadvertently addressed, the device should be reset to ensure the undefined registers are at default values. table 11. register map
www.semtech.com 24 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. . r d d a ) x e h ( e m a n r e t e m a r a pt i b a t a d ) b s m ( 7 654321 ) b s l ( 0 0 1s e c r u o s _ e c n e r e f e r _ s t s ) e t i r w / d a e r ( > 2 _ i < s u t a t s> 1 _ i < s u t a t s 1 1 > 4 _ i < s u t a t s> 3 _ i < s u t a t s 2 1 > 6 _ i < s u t a t s> 5 _ i < s u t a t s 3 1 > 8 _ i < s u t a t s> 7 _ i < s u t a t s 4 1 > 0 1 _ i < s u t a t s> 9 _ i < s u t a t s 5 1 > 2 1 _ i < s u t a t s> 1 1 _ i < s u t a t s 6 1 > 4 1 _ i < s u t a t s> 3 1 _ i < s u t a t s 8 1y t i r o i r p _ n o i t c e l e s _ f e r _ g f n c ) e t i r w / d a e r ( > 2 _ i < y t i r o i r p _ d e m m a r g o r p > 1 _ i < y t i r o i r p _ d e m m a r g o r p 9 1 > 4 _ i < y t i r o i r p _ d e m m a r g o r p > 3 _ i < y t i r o i r p _ d e m m a r g o r p a 1 > 6 _ i < y t i r o i r p _ d e m m a r g o r p > 5 _ i < y t i r o i r p _ d e m m a r g o r p b 1 > 8 _ i < y t i r o i r p _ d e m m a r g o r p > 7 _ i < y t i r o i r p _ d e m m a r g o r p c 1 > 0 1 _ i < y t i r o i r p _ d e m m a r g o r p > 9 _ i < y t i r o i r p _ d e m m a r g o r p d 1 > 2 1 _ i < y t i r o i r p _ d e m m a r g o r p > 1 1 _ i < y t i r o i r p _ d e m m a r g o r p e 1 > 4 1 _ i < y t i r o i r p _ d e m m a r g o r p > 3 1 _ i < y t i r o i r p _ d e m m a r g o r p 0 2y c n e u q e r f _ e c r u o s _ f e r _ g f n c ) e t i r w / d a e r ( n v i dk 8 k c o l) 0 : 1 ( > 1 _ i < d i _ t e k c u b) 0 : 3 ( > 1 _ i < y c n e u q e r f _ e c r u o s _ e c n e r e f e r 1 2 n v i dk 8 k c o l) 0 : 1 ( > 2 _ i < d i _ t e k c u b) 0 : 3 ( > 2 _ i < y c n e u q e r f _ e c r u o s _ e c n e r e f e r 2 2 n v i dk 8 k c o l) 0 : 1 ( > 3 _ i < d i _ t e k c u b) 0 : 3 ( > 3 _ i < y c n e u q e r f _ e c r u o s _ e c n e r e f e r 3 2 n v i dk 8 k c o l) 0 : 1 ( > 4 _ i < d i _ t e k c u b) 0 : 3 ( > 4 _ i < y c n e u q e r f _ e c r u o s _ e c n e r e f e r 4 2 n v i dk 8 k c o l) 0 : 1 ( > 5 _ i < d i _ t e k c u b) 0 : 3 ( > 5 _ i < y c n e u q e r f _ e c r u o s _ e c n e r e f e r 5 2 n v i dk 8 k c o l) 0 : 1 ( > 6 _ i < d i _ t e k c u b) 0 : 3 ( > 6 _ i < y c n e u q e r f _ e c r u o s _ e c n e r e f e r 6 2 n v i dk 8 k c o l) 0 : 1 ( > 7 _ i < d i _ t e k c u b) 0 : 3 ( > 7 _ i < y c n e u q e r f _ e c r u o s _ e c n e r e f e r 7 2 n v i dk 8 k c o l) 0 : 1 ( > 8 _ i < d i _ t e k c u b) 0 : 3 ( > 8 _ i < y c n e u q e r f _ e c r u o s _ e c n e r e f e r 8 2 n v i dk 8 k c o l) 0 : 1 ( > 9 _ i < d i _ t e k c u b) 0 : 3 ( > 9 _ i < y c n e u q e r f _ e c r u o s _ e c n e r e f e r 9 2 n v i dk 8 k c o l) 0 : 1 ( > 0 1 _ i < d i _ t e k c u b) 0 : 3 ( > 0 1 _ i < y c n e u q e r f _ e c r u o s _ e c n e r e f e r a 2 n v i dk 8 k c o l) 0 : 1 ( > 1 1 _ i < d i _ t e k c u b) 0 : 3 ( > 1 1 _ i < y c n e u q e r f _ e c r u o s _ e c n e r e f e r b 2 n v i dk 8 k c o l) 0 : 1 ( > 2 1 _ i < d i _ t e k c u b) 0 : 3 ( > 2 1 _ i < y c n e u q e r f _ e c r u o s _ e c n e r e f e r c 2 n v i dk 8 k c o l) 0 : 1 ( > 3 1 _ i < d i _ t e k c u b) 0 : 3 ( > 3 1 _ i < y c n e u q e r f _ e c r u o s _ e c n e r e f e r d 2 n v i dk 8 k c o l) 0 : 1 ( > 4 1 _ i < d i _ t e k c u b) 0 : 3 ( > 4 1 _ i < y c n e u q e r f _ e c r u o s _ e c n e r e f e r table 11. register map (continued).
www.semtech.com 25 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. . r d d a ) x e h ( e m a n r e t e m a r a pt i b a t a d ) b s m ( 7654321) b s l ( 0 0 3_ s e c r u o s _ e t o m e r _ s t s _ g f n c d i l a v ) e t i r w / d a e r ( > 1 : 8 < s l e n n a h c , s u t a t s e t o m e r 1 3 > 9 : 4 1 < s l e n n a h c , s u t a t s e t o m e r 2 3e d o m _ g n i t a r e p o _ g f n c ) e t i r w / d a e r ( e d o m g n i t a r e p o d e c r o f 3 3n o i t c e l e s _ f e r _ g f n c ) e t i r w / d a e r ( e c r u o s _ e c n e r e f e r _ t c e l e s _ e c r o f 4 3e d o m _ g f n c ) e t i r w / d a e r ( o t u a l a n r e t x e e l b a n e k 2 e s a h p m r a l a t u o e m i t e l b a n e e g d e k c o l c r e v o d l o h t e s f f o e l b a n e k 2 l a n r e t x e e l b a n e c n y s / t e n o s h d s p / i / r e t s a m e v a l s n o i s r e v e r e d o m 5 34 t _ g f n c ) e t i r w / d a e r ( h c l e u q s t c e l e s 1 t / 0 t n o i t c e l e s e c r u o s t u p n i 1 t e c r o f ) 0 1 _ i o t 5 _ i s t u p n i r o f d i l a v y l n o ( 6 3s t u p n i _ l a i t n e r e f f i d _ g f n c ) e t i r w / d a e r ( > 6 _ i < l c e p > 5 _ i < l c e p 7 3s n i p _ l e s p u _ g f n c ) y l n o d a e r ( e p y t r o s s e c o r p - o r c i m 8 3e l b a n e _ t u p t u o _ 0 t _ g f n c ) e t i r w / d a e r ( z h m 4 0 . 1 1 3 6 0 t n o t e n o s = 1 h d s = 0 2 g i d r o f t e n o s = 1 h d s = 0 1 g i d r o f 1 0 t2 0 t 3 0 t z h m 4 4 . 9 1 4 0 t z h m 8 8 . 8 3 5 0 t z h m 6 7 . 7 7 9 3s e i c n e u q e r f _ t u p t u o _ 0 t _ g f n c ) e t i r w / d a e r ( 2 l a t i g i d1 l a t i g i d2 0 t1 0 t a 3s t u p t u o _ l a i t n e r e f f i d _ g f n c ) e t i r w / d a e r ( y c n e u q e r f 7 0 t n o i t c e l e s y c n e u q e r f 6 0 t n o i t c e l e s s d v l 7 0 t e l b a n e l c e p 7 0 t e l b a n e s d v l 6 0 t e l b a n e l c e p 6 0 t e l b a n e b 3h t d i w d n a b _ g f n c ) e t i r w / d a e r ( w / b o t u a h c t i w s k c o l / q c a h t d i w d n a b n o i t i s i u q c a' 0 ' o t t e sh t d i w d n a b d e k c o l / l a m r o n c 3y c n e u q e r f _ l a n i m o n _ g f n c ) e t i r w / d a e r ( ) 0 : 7 ( y c n e u q e r f l a n i m o n d 3 ) 8 : 5 1 ( y c n e u q e r f l a n i m o n e 3t e s f f o _ r e v o d l o h _ g f n c ) e t i r w / d a e r ( ) 0 : 7 ( t e s f f o r e v o d l o h f 3 ) 8 : 5 1 ( t e s f f o r e v o d l o h 0 4o t u a r e v o d l o h g n i g a r e v a ) 6 1 : 8 1 ( t e s f f o r e v o d l o h 1 4t i m i l _ q e r f _ g f n c ) e t i r w / d a e r ( ) 0 : 7 ( t i m i l t e s f f o y c n e u q e r f l l p d 2 4 t e s f f o y c n e u q e r f l l p d ) 8 : 9 ( t i m i l 3 4k s a m _ t p u r r e t n i _ g f n c ) e t i r w / d a e r ( d i l a v > 8 _ i < e g n a h c d i l a v > 7 _ i < e g n a h c d i l a v > 6 _ i < e g n a h c d i l a v > 5 _ i < e g n a h c d i l a v > 4 _ i < e g n a h c d i l a v > 3 _ i < e g n a h c d i l a v > 2 _ i < e g n a h c d i l a v > 1 _ i < e g n a h c 4 4g n i t a r e p o e d o m . f e r n i a m d e l i a f d i l a v > 4 1 _ i < e g n a h c d i l a v > 3 1 _ i < e g n a h c d i l a v > 2 1 _ i < e g n a h c d i l a v > 1 1 _ i < e g n a h c d i l a v > 0 1 _ i < e g n a h c d i l a v > 9 _ i < e g n a h c 5 4 f e r 4 t 2 i m a n o i t a l o i v 2 i m a s . o . l 1 i m a n o i t a l o i v 1 i m a s . o . l 6 4n v i d _ q e r f _ g f n c ) e t i r w / d a e r ( ) 0 : 7 ( o i t a r n - y b - t u p n i - e d i v i d 7 4 ) 8 : 3 1 ( o i t a r n - y b - t u p n i - e d i v i d table 11. register map (continued).
www.semtech.com 26 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. . r d d a ) x e h ( e m a n r e t e m a r a pt i b a t a d ) b s m ( 7654321) b s l ( 0 8 4s r o t i n o m _ g f n c ) e t i r w / d a e r ( t s o l f e r g a l f o d t n o t s a f - a r t l u g n i h c t i w s l a n r e t x e e c r u o s h c t i w s e l b a n e e s a h p e z e e r f t u o d l i u b e s a h p t u o d l i u b e l b a n e s r o t i n o m y c n e u q e r f ) 0 : 1 ( n o i t a r u g i f n o c 0 50 d l o h s e r h t _ r e p p u _ v i t c a _ g f n c ) e t i r w / d a e r ( ) 0 : 7 ( d l o h s e r h t t e s m r a l a y t i v i t c a : 0 n o i t a r u g i f n o c 1 50 d l o h s e r h t _ r e w o l _ v i t c a _ g f n c ) e t i r w / d a e r ( ) 0 : 7 ( d l o h s e r h t t e s e r m r a l a y t i v i t c a : 0 n o i t a r u g i f n o c 2 50 e z i s _ t e k c u b _ g f n c ) e t i r w / d a e r ( ) 0 : 7 ( e z i s t e k c u b m r a l a y t i v i t c a : 0 n o i t a r u g i f n o c 3 50 e t a r _ y a c e d _ g f n c ) e t i r w / d a e r ( ) 0 : 1 ( e t a r _ y a c e d : 0 g f c 4 51 d l o h s e r h t _ r e p p u _ v i t c a _ g f n c ) e t i r w / d a e r ( ) 0 : 7 ( d l o h s e r h t t e s m r a l a y t i v i t c a : 1 n o i t a r u g i f n o c 5 51 d l o h s e r h t _ r e w o l _ v i t c a _ g f n c ) e t i r w / d a e r ( ) 0 : 7 ( d l o h s e r h t t e s e r m r a l a y t i v i t c a : 1 n o i t a r u g i f n o c 6 51 e z i s _ t e k c u b _ g f n c ) e t i r w / d a e r ( ) 0 : 7 ( e z i s t e k c u b m r a l a y t i v i t c a : 1 n o i t a r u g i f n o c 7 51 e t a r _ y a c e d _ g f n c ) e t i r w / d a e r ( ) 0 : 1 ( e t a r _ y a c e d : 1 g f c 8 52 d l o h s e r h t _ r e p p u _ v i t c a _ g f n c ) e t i r w / d a e r ( ) 0 : 7 ( d l o h s e r h t t e s m r a l a y t i v i t c a : 2 n o i t a r u g i f n o c 9 52 d l o h s e r h t _ r e w o l _ v i t c a _ g f n c ) e t i r w / d a e r ( ) 0 : 7 ( d l o h s e r h t t e s e r m r a l a y t i v i t c a : 2 n o i t a r u g i f n o c a 52 e z i s _ t e k c u b _ g f n c ) e t i r w / d a e r ( ) 0 : 7 ( e z i s t e k c u b m r a l a y t i v i t c a : 2 n o i t a r u g i f n o c b 52 e t a r _ y a c e d _ g f n c ) e t i r w / d a e r ( ) 0 : 1 ( e t a r _ y a c e d : 2 g f c c 53 d l o h s e r h t _ r e p p u _ v i t c a _ g f n c ) e t i r w / d a e r ( ) 0 : 7 ( d l o h s e r h t t e s m r a l a y t i v i t c a : 3 n o i t a r u g i f n o c d 53 d l o h s e r h t _ r e w o l _ v i t c a _ g f n c ) e t i r w / d a e r ( ) 0 : 7 ( d l o h s e r h t t e s e r m r a l a y t i v i t c a : 3 n o i t a r u g i f n o c e 53 e z i s _ t e k c u b _ g f n c ) e t i r w / d a e r ( ) 0 : 7 ( e z i s t e k c u b m r a l a y t i v i t c a : 3 n o i t a r u g i f n o c f 53 e t a r _ y a c e d _ g f n c ) e t i r w / d a e r ( ) 0 : 1 ( e t a r _ y a c e d : 3 g f c f 7l e s p u _ g f n c ) e t i r w / d a e r ( e p y t r o s s e c o r p - o r c i m table 11. register map (continued).
www.semtech.com 27 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. register map description table 12. register map description . r d d a ) x e h ( e m a n r e t e m a r a pn o i t p i r c s e dt l u a f e d ) n i b ( e u l a v d i _ p i h c ) l a m i c e d ( 0 1 5 8 = d i p i h c e h t s n i a t n o c r e t s i g e r s i h t 0 0) 0 : 7 ( s t i b d i p i h c ) 0 : 7 ( s t i b 0 1 1 1 1 1 0 0 1 0) 8 : 5 1 ( s t i b d i p i h c ) 0 : 7 ( s t i b 1 0 0 0 0 1 0 0 2 0 n o i s i v e r _ p i h c r e b m u n n o i s i v e r p i h c e h t s n i a t n o c r e t s i g e r y l n o d a e r s i h t 1 = n o i s i v e r s i h t 0 = ) s e l p m a s g n i r e e n i g n e ( n o i s i v e r t s a l 1 0 0 0 0 0 0 0 3 0 1 l o r t n o c _ g f n cd e s u n u ) 6 : 7 ( s t i b 5 t i b . z h m 6 7 . 7 7 l a m r o n e h t f o d a e t s n i l l p a e h t o t y c n e u q e r f 2 g i d x 2 s d e e f : l l p a o t z h m 4 2 / 2 3 1 = s t i b t e s 2 g i d : e t o n . s e t a r 1 t / 1 e e l p i t l u m h t i w d e c a l p e r e r a s t u p t u o 1 m t s / 3 c o l a m r o n e h t s u h t . e d o m s i h t r o f 1 1 o t t e s e b t s u m ) ) 6 : 7 ( s t i b h 9 3 . g e r ( l l p a o t z h m 6 7 . 7 7 0 = 4 t i b n o i t c e s l l p d e h t n i s r e d i v i d e h t o t n o i t c e s l l p a t u p t u o e h t n i s r e d i v i d e h t s e z i n o r h c n y s 1 = s t u p n i n e e w t e b t n e m n g i l a e s a h p e v a h o t r e d r o n i y r a s s e c e n s i s i h t . n g i l a s e s a h p r i e h t t a h t h c u s e b y a m h g i h t i b s i h t g n i p e e k . ) z h m 6 7 . 7 7 o t z h m 8 4 . 6 ( s e t a r d e v i r e d 3 c o t a s k c o l c t u p t u o d n a y c n e u q e r f n i s e g n a h c k c i u q n e h w n o i t a z i n o r h c n y s f o t u o g n i t t e g s r e d i v i d e h t d i o v a o t y r a s s e c e n . n u r - e e r f o t n i e c r o f a s a h c u s r u c c o e h t e d o m s i h t n i t u b , y c n e u q e r f n i s e g n a h c p e t s g n i w o l l o f e s a h p f o t u o t e g y a m s r e d i v i d e h t 0 = e h t . d o i r e p n o i t a z i n o r h c n y s y n a n i h t i w d e e t n e r a u g s i s e g d e y c n e u q e r f h g i h f o r e b m u n t c e r r o c . ) t l u a f e d ( k c o l y c n e u q e r f l l i w t u p t u o t l u a f e d e h t e r o f e b , t e s e r a m o r f s d n o c e s 2 n o i t a z i n o r h c n y s n i n i a m e r s y a w l a l l i w e c i v e d e h t . s e i l p p a g n i t t e s ' 0 ' o t t e s r o , d e g n a h c n u e v a e l - l o r t n o c t s e t 3 s t i b 2 t i b . e g d e k c o l c t u p n i g n i s i r e h t o t k c o l l l i w m e t s y s e h t e d o m g n i k c o l k 8 n i n e h w 1 = . e g d e k c o l c t u p n i g n i l l a f e h t o t k c o l l l i w m e t s y s e h t e d o m g n i k c o l k 8 n i n e h w 0 = ' 0 0 ' o t t e s r o , d e g n a h c n u e v a e l - s l o r t n o c t s e t ) 0 : 1 ( s t i b 0 0 0 0 0 0 x x 4 0 2 l o r t n o c _ g f n cd e s u n u ) 6 : 7 ( s t i b o t s d n o p s e r r o c h c i h w ) 0 0 1 ( 4 o t t e s t l u a f e d y b . t i m i l g a l f s s o l e s a h p e h t e n i f e d ) 3 : 5 ( s t i b t i m i l g a l f e h t . t i m i l e s a h p r e w o l g n i d n o p s e r r o c a s t e s e u l a v r e w o l a . 0 4 1 y l e t a m i x o r p p a e s a h p a , r e t t i j t u p n i f o t l u s e r a s a t s o l e s a h p s e t a c i d n i l l p d e h t h c i h w t a e u l a v e h t s e n i m r e t e d t u p n i e h t n o p m u j y c n e u q e r f a r o , p m u j ' 0 1 0 ' o t t e s r o , d e g n a h c n u e v a e l - s l o r t n o c t s e t ) 0 : 2 ( s t i b 0 1 0 0 0 1 x x s t p u r r e t n i _ s t s e h t e c n e r e f e r f o s s o l r o f e n o , d i l a v _ s e c r u o s _ s t s f o t i b h c a e r o f t i b e n o s n i a t n o c r e t s i g e r s i h t . h g i h e v i t c a e r a s t i b l l a . e d o m g n i t a r e p o e h t r o f r e h t o n a d n a , o t d e k c o l s a w e c i v e d t n e v e l e r e h t f o e t a t s e h t n i ' e g n a h c ' a n o t e s e r a ) 4 1 t i b ( t i b d e l i a f _ f e r _ n i a m e h t t p e c x e s t i b l l a e h t f i . t p u r r e t n i n a r e g g i r t l l i w t i d i l a v n i s e o g r o , d i l a v s e m o c e b e c r u o s a f i . e . i , t i b s u t a t s . d e t a r e n e g e b l l i w t p u r r e t n i e h t e t a t s s e g n a h c ) 9 r e t s i g e r ( e d o m g n i t a r e p o e c n e r e f e r e h t n o y t i v i t c a n i g a l f o t d e s u s i r e t s i g e r s u t a t s t p u r r e t n i e h t f o ) d e l i a f _ f e r _ n i a m ( 4 1 t i b e h t f o 6 t i b f i . t r o p p u s n a c s r o t i n o m y t i v i t c a e h t n a h t y l k c i u q e r o m o t d e k c o l s i e c i v e d e h t t a h t e h t o t n o n e v i r d s i t i b s i h t f o e t a t s e h t n e h t , t e s s i ) o d t n o s s o l f e r g a l f ( r e t s i g e r s r o t i n o m _ g f n c . e c i v e d e h t f o n i p o d t d e r a e l c e b y a m t i b h c a e . r e t s i g e r k s a m _ t p u r r e t n i _ g f n c e h t n i s t i b e h t y b e l b a k s a m e r a s t i b l l a e b n a c s t i b f o r e b m u n y n a . t p u r r e t n i e h t g n i t t e s e r s u h t , t i b t a h t o t ' 1 ' a g n i t i r w y b y l l a u d i v i d n i . t c e f f e o n e v a h l l i w s ' 0 ' g n i t i r w . n o i t a r e p o e t i r w e l g n i s a h t i w d e r a e l c 5 0> 1 _ i < o t > 8 _ i < ) 0 : 7 ( s t i b 0 0 0 0 0 0 0 0 6 0 > 9 _ i < o t > 4 1 _ i < , d e l i a f f e r n i a m , e d o m g n i t a r e p o ) 0 : 7 ( s t i b 0 0 0 0 0 0 0 0
www.semtech.com 28 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. table 12. register map description (continued). . r d d a ) x e h ( e m a n r e t e m a r a pn o i t p i r c s e dt l u a f e d ) n i b ( e u l a v 8 0 s t u p n i _ 4 t _ s t s e c n o s m r a l a e h t . e c n e r e f e r 4 t u o t e h t d n a s t u p n i i m a e h t f o s g a l f s u t a t s e h t s d l o h r e t s i g e r s i h t , t i b t a h t o t ' 1 ' a g n i t i r w y b y l l a u d i v i d n i d e r a e l c e b y a m t i b h c a e . t e s e r l i t n u e t a t s r i e h t d l o h l l i w t e s e t a r e n e g o s l a n a c s t i b e s e h t . t c e f f e o n e v a h l l i w s ' 0 ' g n i t i r w . t p u r r e t n i e h t g n i t t e s e r s u h t . s t p u r r e t n i . d e s u n u ) 5 : 7 ( s t i b 4 t i b t d i l a v o n - d e l i a f e c n e r e f e r 4 t 1 = 1 n i k c o l t o n n a c l l p d 4 t , ) > 5 _ i < : > 0 1 _ i < ( t u p n i ) t l u a f e d ( e c r u o s o t t d i l a v - d o o g e c n e r e f e r 4 t 0 = 1 n i . e l b a l i a v a t u p n i 3 t i b d e t c e t e d n o i t a l o i v 2 i m a 1 = ) t l u a f e d ( r a e l c 2 i m a 0 = 2 t i b l a n g i s f o s s o l 2 i m a 1 = ) t l u a f e d ( r a e l c 2 i m a 0 = 1 t i b d e t c e t e d n o i t a l o i v 1 i m a 1 = ) t l u a f e d ( r a e l c 1 i m a 0 = 0 t i b l a n g i s f o s s o l 1 i m a 1 = ) t l u a f e d ( r a e l c 1 i m a 0 = 0 0 0 0 1 x x x 9 0 e d o m _ g n i t a r e p o _ s t s 1 1 e r u g i f . e n i h c a m e t a t s n i a m e h t f o e t a t s g n i t a r e p o t n e r r u c e h t s d l o h r e t s i g e r y l n o - d a e r s i h t . s e t a t s l a u d i v i d n i e h t h t i w h c t a m e l b a i r a v ' e t a t s g n i t a r e p o ' e h t f o s e u l a v e h t w o h s w o h s . d e s u n u ) 3 : 7 ( s t i b e t a t s ) 0 : 2 ( s t i b ) t l u a f e d ( n u r - e e r f 1 0 0 r e v o d l o h 0 1 0 d e k c o l 0 0 1 d e k c o l - e r p 0 1 1 2 d e k c o l - e r p 1 0 1 t s o l e s a h p 1 1 1 1 0 0 x x x x x e l b a t _ y t i r o i r p _ s t s. r e t s i g e r y l n o - d a e r t i b - 6 1 a s i s i h t e c n e r e f e r t u p n i e h t f o r e b m u n l e n n a h c e h t s i s i h t : e c r u o s d i l a v y t i r o i r p t s e h g i h d r i h t ) 2 1 : 5 1 ( s t i b d i l a v y t i r o i r p - t s e h g i h - d n o c e s e h t o t y t i r o i r p t s e h g i h - t x e n e h t s a h d n a d i l a v s i h c i h w e c r u o s . e c r u o s t u p n i e h t f o r e b m u n l e n n a h c e h t s i s i h t : e c r u o s d i l a v y t i r o i r p t s e h g i h d n o c e s ) 8 : 1 1 ( s t i b d i l a v y t i r o i r p - t s e h g i h e h t o t y t i r o i r p t s e h g i h - t x e n e h t s a h d n a d i l a v s i h c i h w e c r u o s e c n e r e f e r . e c r u o s e c r u o s e c n e r e f e r t u p n i e h t f o r e b m u n l e n n a h c e h t s i s i h t : e c r u o s d i l a v y t i r o i r p t s e h g i h ) 4 : 7 ( s t i b d e t c e l e s y l t n e r r u c e h t s a e m a s e h t e b t o n y a m t i - y t i r o i r p t s e h g i h e h t s a h d n a d i l a v s i h c i h w . ) y t i r o i r p d e m m a r g o r p n i s e g n a h c r o y r o t s i h e r u l i a f o t e u d ( e c r u o s e c n e r e f e r e c n e r e f e r t u p n i e h t f o r e b m u n l e n n a h c e h t s i s i h t : e c r u o s e c n e r e f e r d e t c e l e s y l t n e r r u c ) 0 : 3 ( s t i b . l l p d o t t u p n i y l t n e r r u c s i h c i h w e c r u o s e h t f o s t n e t n o c e h t o t e s n o p s e r n i e n i h c a m e t a t s e h t y b d e t a d p u e r a s r e t s i g e r e s e h t t a h t e t o n l e n n a h c ; s l e n n a h c l a u d i v i d n i f o s u t a t s g n i o g n o e h t d n a r e t s i g e r y t i r o i r p _ n o i t c e l e s _ f e r _ g f n c r o f e l b a l i a v a s i l e n n a h c o n t a h t s e t a c i d n i , s r e t s i g e r e s e h t f o y n a n i g n i r a e p p a , ' 0 0 0 0 ' r e b m u n . y t i r o i r p t a h t a 0 ) ) 4 : 7 ( s t i b e l b a t _ y t i r o i r p _ s t s ( e c r u o s d i l a v y t i r o i r p t s e h g i h ) 4 : 7 ( s t i b ) ) 0 : 3 ( s t i b e l b a t _ y t i r o i r p _ s t s ( e c r u o s e c n e r e f e r d e t c e l e s y l t n e r r u c ) 0 : 3 ( s t i b 0 0 0 0 0 0 0 0 b 0 3 ) 4 : 7 ( s t i b d r ) ) 2 1 : 5 1 ( s t i b e l b a t _ y t i r o i r p _ s t s ( e c r u o s d i l a v y t i r o i r p t s e h g i h - 2 ) 0 : 3 ( s t i b d n ) ) 8 : 1 1 ( s t i b e l b a t _ y t i r o i r p _ s t s ( e c r u o s d i l a v y t i r o i r p t s e h g i h - 0 0 0 0 0 0 0 0
www.semtech.com 29 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. . r d d a ) x e h ( e m a n r e t e m a r a pn o i t p i r c s e dt l u a f e d ) n i b ( e u l a v t e s f f o _ c n i _ r r u c _ s t s f o s t i b t n a c i f i n g i s 9 1 e h t g n i t n e s e r p e r e u l a v r e g e t n i - d e n g i s a s n i a t n o c r e t s i g e r y l n o - d a e r s i h t d l i u b o t y l l a c i d o i r e p d a e r e b y a m r e t s i g e r e h t . l l p l a t i g i d e h t f o t e s f f o t n e m e r c n i t n e r r u c e h t f i y r a s s e c e n e b y l n o d l u o w s i h t ( s d o i r e p r e v o d l o h g n i r u d e s u r e t a l r o f e s a b a t a d l a c i r o t s i h a p u r o t a l l i c s o l a c o l n i d e b i r c s e d a i r e t i r c y t i l i b a t s e h t t e e m t o n d i d h c i h w r o t a l l i c s o l a n r e t x e n a . t e s e r r e t f a y l e t a i d e m m i 0 0 0 0 0 0 0 0 d a e r l l i w r e t s i g e r e h t . ) d e s u s i n o i t c e s k c o l c c 0 ) 0 : 7 ( s t i b t e s f f o _ c n i _ r r u c _ s t s ) 0 : 7 ( s t i b 0 0 0 0 0 0 0 0 d 0 ) 8 : 5 1 ( s t i b t e s f f o _ c n i _ r r u c _ s t s ) 0 : 7 ( s t i b 0 0 0 0 0 0 0 0 7 0 d e s u n u ) 3 : 7 ( s t i b ) 6 1 : 8 1 ( s t i b t e s f f o _ c n i _ r r u c _ s t s ) 0 : 2 ( s t i b 0 0 0 x x x x x d i l a v _ s e c r u o s _ s t s . e c r u o s e c n e r e f e r y r e v e r o f y t i d i l a v w o h s o t t i b a s n i a t n o c r e t s i g e r s i h t e c r u o s d i l a v 1 = ) t l u a f e d ( e c r u o s d i l a v n i 0 = e 0> 1 _ i < o t > 8 _ i < ) 0 : 7 ( s t i b 0 0 0 0 0 0 0 0 f 0 d e s u n u ) 6 : 7 ( s t i b > 9 _ i < o t > 4 1 _ i < ) 0 : 5 ( s t i b 0 0 0 0 0 0 x x s e c r u o s _ e c n e r e f e r _ s t s e h t . s e c r u o s e c n e r e f e r t u p n i 4 1 e h t f o h c a e f o s u t a t s e h t s d l o h h c i h w r e t s i g e r e t y b - 7 a s i s i h t s u t a t s d i a o t . h g i h e v i t c a s i t i b h c a e . d l e i f t i b - 4 a n i n w o h s s i e c r u o s e c n e r e f e r h c a e f o s u t a t s s u t a t s e h t . r e t s i g e r d i l a v _ s e c r u o s _ s t s e h t n i d e d i v o r p s i 3 t i b s u t a t s h c a e f o y p o c a , g n i k c e h c ) y l l a u d i v i d n i d e r a e l c e b y a m t i b h c a e ( : s w o l l o f s a d e t r o p e r s i ) 0 t l u a f e d ( ) ) 0 : 2 ( s t i b f o n o i t a n i b m o c s i 3 t i b ( ) s m r a l a o n ( d i l a v e c r u o s = 3 t i b s u t a t s ) 1 t l u a f e d ( m r a l a d n a b - f o - t u o = 2 t i b s u t a t s ) 1 t l u a f e d ( m r a l a y t i v i t c a o n = 1 t i b s u t a t s ) 0 t l u a f e d ( m r a l a k c o l e s a h p = 0 t i b s u t a t s 0 1 > 2 _ i < e c r u o s e c n e r e f e r t u p n i f o s u t a t s ) 4 : 7 ( s t i b > 1 _ i < e c r u o s e c n e r e f e r t u p n i f o s u t a t s ) 0 : 3 ( s t i b 0 1 1 0 0 1 1 0 1 1 > 4 _ i < e c r u o s e c n e r e f e r t u p n i f o s u t a t s ) 4 : 7 ( s t i b > 3 _ i < e c r u o s e c n e r e f e r t u p n i f o s u t a t s ) 0 : 3 ( s t i b 0 1 1 0 0 1 1 0 2 1 s e c r u o s _ e c n e r e f e r _ s t s ) d e u n i t n o c ( > 6 _ i < e c r u o s e c n e r e f e r t u p n i f o s u t a t s ) 4 : 7 ( s t i b > 5 _ i < e c r u o s e c n e r e f e r t u p n i f o s u t a t s ) 0 : 3 ( s t i b 0 1 1 0 0 1 1 0 3 1 > 8 _ i < e c r u o s e c n e r e f e r t u p n i f o s u t a t s ) 4 : 7 ( s t i b > 7 _ i < e c r u o s e c n e r e f e r t u p n i f o s u t a t s ) 0 : 3 ( s t i b 0 1 1 0 0 1 1 0 4 1 > 0 1 _ i < e c r u o s e c n e r e f e r t u p n i f o s u t a t s ) 4 : 7 ( s t i b > 9 _ i < e c r u o s e c n e r e f e r t u p n i f o s u t a t s ) 0 : 3 ( s t i b 0 1 1 0 0 1 1 0 5 1 > 2 1 _ i < e c r u o s e c n e r e f e r t u p n i f o s u t a t s ) 4 : 7 ( s t i b > 1 1 _ i < e c r u o s e c n e r e f e r t u p n i f o s u t a t s ) 0 : 3 ( s t i b 0 1 1 0 0 1 1 0 6 1 > 4 1 _ i < e c r u o s e c n e r e f e r t u p n i f o s u t a t s ) 4 : 7 ( s t i b > 3 1 _ i < e c r u o s e c n e r e f e r t u p n i f o s u t a t s ) 0 : 3 ( s t i b 0 1 1 0 0 1 1 0 y t i r o i r p _ n o i t c e l e s _ f e r _ g f n c e r a s e u l a v y t i r o i r p e h t . s e c r u o s e c n e r e f e r t u p n i 4 1 e h t f o h c a e f o y t i r o i r p e h t s d l o h r e t s i g e r s i h t ' 1 ' s e u l a v e h t y l n o . s e i t i r o i r p r e h g i h g n i k a t s r e b m u n d e u l a v - r e w o l h t i w , r e h t o h c a e o t e v i t a l e r l l a e b d l u o h s e c r u o s e c n e r e f e r h c a e . e c r u o s e c n e r e f e r e h t s e l b a s i d ' 0 ' - d i l a v e r a ) c e d ( ' 5 1 ' o t d e n g i s s a e b l l i w r e b m u n y t i r o i r p e m a s e h t n e v i g s e c r u o s o w t r e v e w o h , r e b m u n e u q i n u a n e v i g . s i s a b t u o t s r i f n i t s r i f a n o e c n e r e f e r g n i c r o f n e h w d e s u s i s i h t s a ' 1 ' e u l a v y t i r o i r p e h t e v r e s e r o t d e d n e m m o c e r s i t i e h t e s u o t d n e t n i t o n s e o d r e s u e h t f i . r e t s i g e r n o i t c e l e s _ f e r _ g f n c e h t a i v n o i t c e l e s . d e v r e s e r e b t o n d e e n ' 1 ' e u l a v y t i r o i r p e h t n e h t r e t s i g e r n o i t c e l e s _ f e r _ g f n c 8 1 > 2 _ i < e c r u o s e c n e r e f e r t u p n i f o y t i r o i r p d e m m a r g o r p ) 4 : 7 ( s t i b > 1 _ i < e c r u o s e c n e r e f e r t u p n i f o y t i r o i r p d e m m a r g o r p ) 0 : 3 ( s t i b 0 1 0 0 1 1 0 0 9 1 > 4 _ i < e c r u o s e c n e r e f e r t u p n i f o y t i r o i r p d e m m a r g o r p ) 4 : 7 ( s t i b > 3 _ i < e c r u o s e c n e r e f e r t u p n i f o y t i r o i r p d e m m a r g o r p ) 0 : 3 ( s t i b 0 0 1 0 1 0 1 0 a 1 > 6 _ i < e c r u o s e c n e r e f e r t u p n i f o y t i r o i r p d e m m a r g o r p ) 4 : 7 ( s t i b > 5 _ i < e c r u o s e c n e r e f e r t u p n i f o y t i r o i r p d e m m a r g o r p ) 0 : 3 ( s t i b 0 1 1 0 1 1 1 0 b 1 > 8 _ i < e c r u o s e c n e r e f e r t u p n i f o y t i r o i r p d e m m a r g o r p ) 4 : 7 ( s t i b > 7 _ i < e c r u o s e c n e r e f e r t u p n i f o y t i r o i r p d e m m a r g o r p ) 0 : 3 ( s t i b 0 0 0 1 1 0 0 1 table 12. register map description (continued).
www.semtech.com 30 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. . r d d a ) x e h ( e m a n r e t e m a r a pn o i t p i r c s e dt l u a f e d ) n i b ( e u l a v c 1 y t i r o i r p _ n o i t c e l e s _ f e r _ g f n c ) d e u n i t n o c ( > 0 1 _ i < e c r u o s e c n e r e f e r t u p n i f o y t i r o i r p d e m m a r g o r p ) 4 : 7 ( s t i b > 9 _ i < e c r u o s e c n e r e f e r t u p n i f o y t i r o i r p d e m m a r g o r p ) 0 : 3 ( s t i b 0 1 0 1 1 1 0 1 d 1 > 2 1 _ i < e c r u o s e c n e r e f e r t u p n i f o y t i r o i r p d e m m a r g o r p ) 4 : 7 ( s t i b > 1 1 _ i < e c r u o s e c n e r e f e r t u p n i f o y t i r o i r p d e m m a r g o r p ) 0 : 3 ( s t i b 1 0 0 0 1 0 1 1 ) 0 = b v l s t s m ( 0 0 1 1 1 0 1 1 ) 1 = b v l s t s m ( e 1 > 4 1 _ i < e c r u o s e c n e r e f e r t u p n i f o y t i r o i r p d e m m a r g o r p ) 4 : 7 ( s t i b > 3 1 _ i < e c r u o s e c n e r e f e r t u p n i f o y t i r o i r p d e m m a r g o r p ) 0 : 3 ( s t i b 0 1 1 1 1 1 1 1 y c n e u q e r f _ e c r u o s _ f e r _ g f n c . s e c r u o s e c n e r e f e r t u p n i 4 1 e h t f o h c a e p u t e s o t d e s u s i r e t s i g e r s i h t e c n a d r o c c a n i , y c n e u q e r f t u p n i e h t n o n e k a t r e d n u n o i t a r e p o e h t s e n i f e d e t y b h c a e f o ) 6 : 7 ( s t i b : y e k g n i w o l l o f e h t h t i w . ) t l u a f e d ( . l l p d e h t o t n i y l t c e r i d d e f s i y c n e u q e r f t u p n i e h t 0 0 e h t o t n i d e f g n i e b e r o f e b , z h k 8 o t n w o d d e d i v i d y l l a n r e t n i s i y c n e u q e r f t u p n i e h t 1 0 . ) e c n a r e l o t r e t t i j h g i h r o f ( . l l p d . e s u t o n o d - n o i t a r u g i f n o c d e t r o p p u s n u 0 1 o t ) n v i d _ q e r f _ g f n c ( 7 4 d n a 6 4 s r e t s i g e r n i d e r o t s t n e i c i f f e o c n o i s i v i d e h t s e s u 1 1 y c n e u q e r f e h t . l l p d e h t o t n i d e f g n i e b o t r o i r p e u l a v s i h t y b t u p n i e h t e d i v i d e h t . z h k 8 l a u q e d l u o h s y c n e u q e r f n w o d d e d i v i d e h t . d e l b a s i d e b t s u m s r o t i n o m l a u t c a e h t w o l e b t s u j y c n e u q e r f t o p s t s e r a e n e h t o t t e s e b d l u o h s ) 0 : 3 ( y c n e u q e r f z h m 4 4 5 . 1 n e e w t e b s e i c n e u q e r f t u p n i r o f s k r o w e r u t a e f n v i d e h t . y c n e u q e r f t u p n i . z h m 0 0 1 d n a . f 5 o t 0 5 s r e t s i g e r n i d e n i f e d s a , d e s u s i ) 3 - 0 ( p u o r g t e k c u b y k a e l h c i h w e n i f e d ) 4 : 5 ( s t i b . ) 0 0 t l u a f e d ( : g n i w o l l o f e h t h t i w e c n a d r o c c a n i e c r u o s e c n e r e f e r e h t f o y c n e u q e r f e h t s e n i f e d ) 0 : 3 ( s t i b ) > 4 _ i < , > 3 _ i < t l u a f e d , > 2 _ i < , > 1 _ i < d e x i f ( z h k 8 0 0 0 0 ) 2 t i b , 4 3 r e t s i g e r y b d e n i f e d s a ( ) h d s ( z h m 8 4 0 . 2 / ) t e n o s ( z h m 4 4 5 . 1 1 0 0 0 ) > 4 1 _ i < , > 3 1 _ i < , > 2 1 _ i < t l u a f e d ( ) 1 = b v l s t s m n e h w > 1 1 _ i < t l u a f e d ( z h m 8 4 . 6 0 1 0 0 , > 8 _ i < , > 7 _ i < , > 6 _ i < , > 5 _ i < d n a , 0 = b v l s t s m n e h w > 1 1 _ i < t l u a f e d ( z h m 4 4 . 9 1 1 1 0 0 ) > 0 1 _ i < , > 9 _ i < z h m 2 9 . 5 2 0 0 1 0 z h m 8 8 . 8 3 1 0 1 0 z h m 4 8 . 1 5 0 1 1 0 z h m 6 7 . 7 7 1 1 1 0 z h m 2 5 . 5 5 1 0 0 0 1 z h k 2 1 0 0 1 z h k 4 0 1 0 1 0 2 y l n o z h k 8 r o f 0 0 0 0 0 0 0 0 t a d e x i f - > 1 _ i < e c r u o s e c n e r e f e r f o y c n e u q e r f 0 0 0 0 0 0 0 0 1 2 y l n o z h k 8 r o f 0 0 0 0 0 0 0 0 t a d e x i f - > 2 _ i < e c r u o s e c n e r e f e r f o y c n e u q e r f 0 0 0 0 0 0 0 0 2 2> 3 _ i < e c r u o s e c n e r e f e r f o y c n e u q e r f 0 0 0 0 0 0 0 0 3 2> 4 _ i < e c r u o s e c n e r e f e r f o y c n e u q e r f 0 0 0 0 0 0 0 0 4 2> 5 _ i < e c r u o s e c n e r e f e r f o y c n e u q e r f 1 1 0 0 0 0 0 0 5 2> 6 _ i < e c r u o s e c n e r e f e r f o y c n e u q e r f 1 1 0 0 0 0 0 0 6 2> 7 _ i < e c r u o s e c n e r e f e r f o y c n e u q e r f 1 1 0 0 0 0 0 0 7 2> 8 _ i < e c r u o s e c n e r e f e r f o y c n e u q e r f 1 1 0 0 0 0 0 0 8 2> 9 _ i < e c r u o s e c n e r e f e r f o y c n e u q e r f 1 1 0 0 0 0 0 0 9 2> 0 1 _ i < e c r u o s e c n e r e f e r f o y c n e u q e r f 1 1 0 0 0 0 0 0 a 2> 1 1 _ i < e c r u o s e c n e r e f e r f o y c n e u q e r f 0 1 0 0 0 0 0 0 ) 0 = b v l s t s m ( 1 1 0 0 0 0 0 0 ) 1 = b v l s t s m ( table 12. register map description (continued).
www.semtech.com 31 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. . r d d a ) x e h ( e m a n r e t e m a r a pn o i t p i r c s e dt l u a f e d ) n i b ( e u l a v b 2 y c n e u q e r f _ e c r u o s _ f e r _ g f n c ) d e u n i t n o c ( > 2 1 _ i < e c r u o s e c n e r e f e r f o y c n e u q e r f 1 0 0 0 0 0 0 0 c 2 > 3 1 _ i < e c r u o s e c n e r e f e r f o y c n e u q e r f 1 0 0 0 0 0 0 0 d 2 > 4 1 _ i < e c r u o s e c n e r e f e r f o y c n e u q e r f 1 0 0 0 0 0 0 0 _ s e c r u o s _ e t o m e r _ s t s _ g f n c d i l a v a n i e c i v e d r e h t o e h t o t d e i l p p u s s e c r u o s e c n e r e f e r e h t f o s u t a t s e h t s d l o h r e t s i g e r s i h t e h t . r e t s i g e r d i l a v _ s e c r u o s _ s t s s ' e c i v e d r e h t o e h t f o y p o c a s i t i . n o i t a r u g i f n o c e v a l s / r e t s a m . m s i n a h c e m n o i t c e t o r p e h t f o t r a p s i r e t s i g e r 0 3 > 1 _ i < : > 8 _ i < s e c r u o s e c n e r e f e r ) 0 : 7 ( s t i b 1 1 1 1 1 1 1 1 1 3 d e s u n u ) 6 : 7 ( s t i b > 9 _ i < : > 4 1 _ i < s e c r u o s e c n e r e f e r ) 0 : 5 ( s t i b 1 1 1 1 1 1 x x 2 3 e d o m _ g n i t a r e p o _ g f n c e h t y b d e t n e s e r p e r , e t a t s g n i t a r e p o d e r i s e d a o t n i e c i v e d e h t e c r o f o t d e s u s i r e t s i g e r s i h t e t a r e p o o t e n i h c a m e t a t s l o r t n o c e h t s w o l l a ) x e h ( 0 e u l a v . 1 1 e r u g i f n i n w o h s s e u l a v y r a n i b . y l l a c i t a m o t u a d e s u n u ) 3 : 7 ( s t i b ) 1 1 e r u g i f r e p s a ( e t a t s g n i t a r e p o d e r i s e d ) 0 : 2 ( s t i b 0 0 0 x x x x x 3 3 n o i t c e l e s _ f e r _ g f n c , e c r u o s e c n e r e f e r t u p n i r a l u c i t r a p a t c e l e s o t e c i v e d e h t e c r o f o t d e s u s i r e t s i g e r s i h t o t t u p n i d e t c e l e s e h t s e s i a r y l i r a r o p m e t r e t s i g e r s i h t o t g n i t i r w . y t i r o i r p s t i f o e v i t c e p s e r r i e d o m e v i t r e v e r d n a , ' 1 ' y t i r o i r p h t i w d e m m a r g o r p y d a e r l a s i t u p n i r e h t o o n d e d i v o r p . ' 1 ' y t i r o i r p . d e t c e l e s e b l l i w e c r u o s s i h t , n o s i d e s u n u ) 4 : 7 ( s t i b d n a , n o i t c e l e s e c r o f e h t s e l b a s i d 1 1 1 1 d n a 0 0 0 0 ( e c r u o s e c n e r e f e r d e r i s e d ) 0 : 3 ( s t i b ) 1 1 1 1 s i t l u a f e d , s e c r u o s l l a f o n o i t c e l e s c i t a m o t u a s w o l l a 1 1 1 1 x x x x 4 3 e d o m _ g f n c : w o l e b d e l i a t e d s a , s d l e i f n o i t a r u g i f n o c l a u d i v i d n i l a r e v e s s n i a t n o c r e t s i g e r s i h t 7 t i b s i e c r u o s e h t n e h w y l n o d e l b a n e e b l l i w c n y s z h k 2 l a n r e t x e : e l b a n e c n y s z h k 2 o t u a 1 = ) t l u a f e d ( d e l b a s i d e b l l i w t i e s i w r e h t o . z h m 8 4 . 6 o t d e k c o l s a , r e t s i g e r s i h t f o 3 t i b g n i s u n o i t c n u f s i h t s l o r t n o c r e s u e h t : e l b a s i d c n y s z h k 2 o t u a 0 = w o l e b d e b i r c s e d 6 t i b ) t l u a f e d ( s d n o c e s 0 0 1 r e t f a t u o e m i t l l i w m r a l a e s a h p e h t : e l b a n e t u o e m i t m r a l a e s a h p 1 = y b t e s e r e b t s u m d n a t u o e m i t t o n l l i w m r a l a e s a h p e h t : e l b a s i d t u o e m i t m r a l a e s a h p 0 = e r a w t f o s 5 t i b l a n r e t x e e h t f o e g d e g n i s i r e h t o t e c n e r e f e r l l i w e c i v e d e h t : d e t c e l e s e g d e k c o l c g n i s i r 1 = l a n g i s r o t a l l i c s o l a t s y r c z h m 8 . 2 1 l a n r e t x e e h t f o e g d e g n i l l a f e h t o t e c n e r e f e r l l i w e c i v e d e h t : d e t c e l e s e g d e e g d e g n i l l a f 0 = ) t l u a f e d ( l a n g i s r o t a l l i c s o l a t s y r c z h m 8 . 2 1 4 t i b e h t n i d e r o t s e u l a v t e s f f o r e v o d l o h e h t t p o d a l l i w e c i v e d e h t : e l b a n e t e s f f o r e v o d l o h 1 = r e v o d l o h n i y c n e u q e r f e h t t e s o t r e d r o n i , r e t s i g e r t e s f f o _ r e v o d l o h _ g f n c e h t e z e e r f l l i w r e v o d l o h d n a e u l a v e h t e r o n g i l l i w e c i v e d e h t : e l b a s i d t e s f f o r e v o d l o h 0 = ) t l u a f e d ( e d o m r e v o d l o h g n i r e t n e n o l l p d e h t f o y c n e u q e r f 3 t i b d e t a r e n e g y l l a n r e t n i s t i f o e s a h p e h t n g i l a l l i w e c i v e d e h t : e l b a n e c n y s z h k 2 l a n r e t x e 1 = l a n g i s e h t f o t a h t h t i w ) z h k 2 ( l a n g i s c n y s e m a r f - i t l u m d n a ) z h k 8 ( l a n g i s c n y s e m a r f r e h t o n a m o r f t u p t u o z h m 8 4 . 6 a o t d e k c o l e b d l u o h s e c i v e d e h t . n i p k 2 c n y s e h t o t d e i l p p u s . 0 1 5 8 s c a . n i p k 2 c n y s e h t e r o n g i l l i w e c i v e d e h t : e l b a s i d c n y s z h k 2 l a n r e t x e 0 = 0 0 0 1 0 0 1 1 ) 0 = b v l s t s m ( ) 0 = b h d s n o s ( 0 0 1 1 0 0 1 1 ) 0 = b v l s t s m ( ) 1 = b h d s n o s ( 0 1 0 0 0 0 1 1 ) 1 = b v l s t s m ( ) 0 = b h d s n o s ( 0 1 1 0 0 0 1 1 ) 1 = b v l s t s m ( ) 1 = b h d s n o s ( table 12. register map description (continued).
www.semtech.com 32 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. . r d d a ) x e h ( e m a n r e t e m a r a pn o i t p i r c s e dt l u a f e d ) n i b ( e u l a v 4 3 e d o m _ g f n c ) d e u n i t n o c ( : w o l e b d e l i a t e d s a , s d l e i f n o i t a r u g i f n o c l a u d i v i d n i l a r e v e s s n i a t n o c r e t s i g e r s i h t 2 t i b e h t n e v i g l e n n a h c t u p n i y n a f o y c n e u q e r f t u p n i e h t s t c e p x e e c i v e d e h t : e d o m t e n o s 1 = z h k 4 4 5 1 e b o t r e t s i g e r y c n e u q e r f _ e c r u o s _ f e r _ g f n c e h t n i ' 1 0 0 0 ' e u l a v e u l a v e h t n e v i g l e n n a h c t u p n i y n a f o y c n e u q e r f t u p n i e h t s t c e p x e e c i v e d e h t : e d o m h d s 0 = . z h k 8 4 0 2 e b o t r e t s i g e r y c n e u q e r f _ e c r u o s _ f e r _ g f n c e h t n i ' 1 0 0 0 ' g n i t t e s s i h t . b h d s n o s n i p f o g n i t t e s e h t o t d e t l u a f e d e b l l i w e u l a v t i b e h t t e s e r r o p u t r a t s t a e u l a v t i b s i h t g n i g n a h c y b d e r e t l a e b y l t n e u q e s b u s n a c 1 t i b f o s n o i s i c e d e v i t c a e h t e k a m d n a e d o m r e t s a m e h t t p o d a l l i w e c i v e d e h t : e d o m r e t s a m 1 = , n i p e h t y b d e n i m r e t e d s i e u l a v t l u a f e d s t i t u b , e l b a e t i r w s i t i b s i h t . c t e , t c e l e s o t e c r u o s h c i h w b v l s t s m . e c i v e d r e t s a m e h t w o l l o f l l i w d n a e d o m e v a l s e h t t p o d a l l i w e c i v e d e h t : e d o m e v a l s 0 = g n i t t e s s i h t . b v l s t s m n i p f o g n i t t e s e h t o t d e t l u a f e d e b l l i w e u l a v t i b e h t t e s e r r o p u t r a t s t a e u l a v t i b s i h t g n i g n a h c y b d e r e t l a e b y l t n e u q e s b u s n a c 0 t i b n i n w o h s e l b a l i a v a e c r u o s y t i r o i r p t s e h g i h e h t o t h c t i w s l l i w e c i v e d e h t : e d o m e v i t r e v e r 1 = ) 4 : 7 ( s t i b , r e t s i g e r e l b a t _ y t i r o i r p _ s t s e h t ) t l u a f e d ( e c r u o s d e t c e l e s y l t n e s e r p e h t n i a t e r l l i w e c i v e d e h t : e d o m e v i t r e v e r n o n 0 = 0 0 0 1 0 0 1 1 ) 0 = b v l s t s m ( ) 0 = b h d s n o s ( 0 0 1 1 0 0 1 1 ) 0 = b v l s t s m ( ) 1 = b h d s n o s ( 0 1 0 0 0 0 1 1 ) 1 = b v l s t s m ( ) 0 = b h d s n o s ( 0 1 1 0 0 0 1 1 ) 1 = b v l s t s m ( ) 1 = b h d s n o s ( 5 3 4 t _ g f n c : n o i t c e l e s e c r u o s t u p n i d n a ) 9 o t / 8 o t n o t u p t u o ( 4 t _ l l p d s l o r t n o c s i h t d e s u n u ) 6 : 7 ( s t i b 5 t i b ) d e h c l e u q s ( f f o d e n r u t s i 4 t _ l l p d 1 = ) t l u a f e d ( n o s i 4 t _ l l p d 0 = : 9 o t / 8 o t s t u p t u o s d e e f e c r u o s ) 0 t r o 4 t ( l l p d h c i h w s t c e l e s 4 t i b 9 o t d n a 8 o t s t u p t u o o t d e f s i t u p t u o 0 t _ l l p d 1 = 9 o t d n a 8 o t s t u p t u o o t d e f s i t u p t u o 4 t _ l l p d 0 = r o f d l e i f s i h t n i n w o h s e c r u o s e h t o t h c t i w s l l i w e c i v e d e h t . n o i t c e l e s e c r u o s t u p n i ) 0 : 3 ( s t i b t e h t f o n o i t a r e n e g e h t 4 t u o t e v i t c a y t i r o i r p t s e h g i h e h t t c e l e s l l i w t i ' 0 ' f i . l a n g i s 1 n i . 0 0 0 0 0 0 x x 6 3 s t u p n i _ l a i t n e r e f f i d _ g f n c : s w o l l o f s a , s d l e i f n o i t a r u g i f n o c l a u d i v i d n i o w t s n i a t n o c r e t s i g e r s i h t d e s u n u ) 2 : 7 ( s t i b 1 t i b ) t l u a f e d ( e l b i t a p m o c - l c e p s i > 6 _ i < t u p n i 1 = e l b i t a p m o c - s d v l s i > 6 _ i < t u p n i 0 = 0 t i b e l b i t a p m o c - l c e p s i > 5 _ i < t u p n i 1 = ) t l u a f e d ( e l b i t a p m o c - s d v l s i > 5 _ i < t u p n i 0 = 0 1 x x x x x x 7 3 s n i p _ l e s p u _ g f n c r e w o p t a d e t c e l e s e p y t r o s s e c o r p o r c i m e h t g n i t a c i d n i e u l a v a s n r u t e r r e t s i g e r y l n o d a e r s i h t l e s p u e h t f i . ) 0 6 - 8 5 s n i p ( s n i p l e s p u e h t f o n o i t a r u g i f n o c e h t y b t e s s i s i h t . t e s e r r o p u s i h t t u b , e c a l p e k a t l l i w t c e f f e o n g n i t a r e p o s i e c i v e d e h t e l i h w d e g n a h c s i n o i t a r u g i f n o c n i p e h t t a d e t n e m e l p m i e b l l i w t a h t n o i t a r u g i f n o c e h t g n i t a c i d n i o s , e g n a h c t a h t t c e l f e r l l i w r e t s i g e r . t e s e r r o p u r e w o p t x e n . f 7 r e t s i g e r h g u o h t , l a n o i t a r e p o e c i v e d e h t h t i w d e g n a h c e b n a c e p y t r o s s e c o r p o r c i m e h t . d e s u n u ) 3 : 7 ( s t i b e p y t r o s s e c o r p o r c i m ) 0 : 2 ( t i b ) d e l b a s i d e c a f r e t n i ( f f o 0 0 0 m o r p e 1 0 0 d e x e l p i t l u m 0 1 0 l e t n i 1 1 0 a l o r o t o m 0 0 1 l a i r e s 1 0 1 ) d e l b a s i d e c a f r e t n i ( f f o 0 1 1 ) d e l b a s i d e c a f r e t n i ( f f o 1 1 1 = ) 3 : 7 ( s t i b x x x x x = ) 0 : 2 ( s t i b l e s p u n i p n o i t a r u g i f n o c table 12. register map description (continued).
www.semtech.com 33 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. . r d d a ) x e h ( e m a n r e t e m a r a pn o i t p i r c s e dt l u a f e d ) n i b ( e u l a v 8 3 e l b a n e _ t u p t u o _ 0 t _ g f n c : s w o l l o f s a , s d l e i f n o i t a r u g i f n o c l a u d i v i d n i l a r e v e s s n i a t n o c r e t s i g e r s i h t 7 t i b * z h m 4 0 . 1 1 3 o t t e s y c n e u q e r f t u p t u o 6 0 t 1 = ) t l u a f e d ( ) 4 : 5 ( a 3 s s e r d d a y b t e s y c n e u q e r f t u p t u o 6 0 t 0 = 6 t i b 2 g i d r o f d e t c e l e s e d o m t e n o s 1 = ) t l u a f e d ( 2 g i d r o f d e t c e l e s e d o m h d s 0 = s e i c n e u q e r f _ t u p t u o _ 0 t _ g f n c r e t s i g e r e e s - 5 t i b 1 g i d r o f d e t c e l e s e d o m t e n o s 1 = ) t l u a f e d ( 1 g i d r o f d e t c e l e s e d o m h d s 0 = s e i c n e u q e r f _ t u p t u o _ 0 t _ g f n c r e t s i g e r e e s - 4 t i b ) t l u a f e d ( d e l b a n e 1 0 t t r o p t u p t u o 1 = * * d e l b a s i d 1 0 t t r o p t u p t u o 0 = s e i c n e u q e r f _ t u p t u o _ 0 t _ g f n c r e t s i g e r e e s - 3 t i b ) t l u a f e d ( d e l b a n e 2 0 t t r o p t u p t u o 1 = * * d e l b a s i d 2 0 t t r o p t u p t u o 0 = s e i c n e u q e r f _ t u p t u o _ 0 t _ g f n c r e t s i g e r e e s - 2 t i b ) t l u a f e d ( ) * z h m 4 4 . 9 1 ( d e l b a n e 3 0 t t r o p t u p t u o 1 = * * d e l b a s i d 3 0 t t r o p t u p t u o 0 = 1 t i b ) t l u a f e d ( ) * z h m 8 8 . 8 3 ( d e l b a n e 4 0 t t r o p t u p t u o 1 = * * d e l b a s i d 4 0 t t r o p t u p t u o 0 = 0 t i b ) t l u a f e d ( ) * z h m 6 7 . 7 7 ( d e l b a n e 5 0 t t r o p t u p t u o 1 = * * d e l b a s i d 5 0 t t r o p t u p t u o 0 = : s e t o n e h t f o t i b e t a i r p o r p p a e h t f i 1 t / 1 e f o s e l p i t l u m o t d e g n a h c e r a s e i c n e u q e r f s t l u a f e d * 1 l o r t n o c _ g f n c . 8 e l b a t e e s , s l i a t e d r o f . 1 o t t e s s i r e t s i g e r . ) d e t a t s - i r t t o n s i t r o p e h t ( e u l a v c i g o l c i t a t s a s d l o h t r o p t u p t u o e h t t a h t s n a e m " d e l b a s i d " * * 1 1 1 1 1 0 0 0 9 3 s e i c n e u q e r f _ t u p t u o _ 0 t _ g f n c * . w o l e b d e l i a t e d s a , t r o p t u p t u o h c a e r o f s n o i t c e l e s y c n e u q e r f e h t s d l o h r e t s i g e r s i h t 1 g i d ) 4 : 5 ( s t i b 2 g i d ) 6 : 7 ( s t i b ) t l u a f e d ( z h k 8 4 0 2 / z h k 4 4 5 1 0 0 ) t l u a f e d ( z h k 8 4 0 2 / z h k 4 4 5 1 0 0 z h k 6 9 0 4 / z h k 8 8 0 3 1 0 z h k 6 9 0 4 / z h k 8 8 0 3 1 0 z h k 2 9 1 8 / z h k 6 7 1 6 0 1 z h k 2 9 1 8 / z h k 6 7 1 6 0 1 z h k 4 8 3 6 1 / z h k 2 5 3 2 1 1 1 z h k 4 8 3 6 1 / z h k 2 5 3 2 1 1 1 1 0 t ) 0 : 1 ( s t i b 2 0 t ) 2 : 3 ( s t i b ) t l u a f e d ( z h m 8 4 . 6 0 0 z h m 2 9 . 5 2 0 0 z h m 2 9 . 5 2 1 0 z h m 4 8 . 1 5 1 0 z h m 4 4 . 9 1 0 1 ) t l u a f e d ( z h m 8 8 . 8 3 0 1 1 g i d 1 1 2 g i d 1 1 e h t a i v d e t c e l e s e r a y e h t . h d s / t e n o s r o f n w o h s e r a s e u l a v y c n e u q e r f e h t 2 g i d / 1 g i d r o f . e l b a n e _ t u p t u o _ 0 t _ g f n c r e t s i g e r n i s t i b h d s / t e n o s : e t o n e h t f o t i b e t a i r p o r p p a e h t f i 1 t / 1 e f o s e l p i t l u m o t d e g n a h c e r a s e i c n e u q e r f e v o b a e h t * 1 l o r t n o c _ g f n c . 8 e l b a t e e s , s l i a t e d r o f . 1 o t t e s s i r e t s i g e r 0 0 0 1 0 0 0 0 table 12. register map description (continued).
www.semtech.com 34 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. . r d d a ) x e h ( e m a n r e t e m a r a pn o i t p i r c s e dt l u a f e d ) n i b ( e u l a v a 3 s t u p t u o _ l a i t n e r e f f i d _ g f n c l a i t n e r e f f i d e h t r o f e p y t y g o l o n h c e t - t r o p e h t d n a s n o i t c e l e s y c n e u q e r f e h t s d l o h r e t s i g e r s i h t . w o l e b d e l i a t e d s a , 7 0 t d n a 6 0 t , s t u p t u o 6 0 t ) 4 : 5 ( s t i b 7 0 t ) 6 : 7 ( s t i b ) t l u a f e d ( z h m 8 8 . 8 3 0 0 z h m 2 5 . 5 5 1 0 0 z h m 4 4 . 9 1 1 0 z h m 4 8 . 1 5 1 0 z h m 2 5 . 5 5 1 0 1 z h m 6 7 . 7 7 0 1 1 g i d 1 1 ) t l u a f e d ( z h m 4 4 . 9 1 1 1 6 0 t ) 0 : 1 ( 7 0 t ) 2 : 3 ( s t i b d e l b a s i d t r o p 0 0 d e l b a s i d t r o p 0 0 e l b i t a p m o c - l c e p 1 0 ) t l u a f e d ( e l b i t a p m o c - l c e p 1 0 ) t l u a f e d ( e l b i t a p m o c - s d v l 0 1 e l b i t a p m o c - s d v l 0 1 d e s u n u 1 1 d e s u n u 1 1 0 1 1 0 0 0 1 1 b 3 h t d i w d n a b _ g f n c n e h w . l l p l a t i g i d e h t f o n o i t a r e p o e h t l o r t n o c o t d e s u n o i t a m r o f n i s n i a t n o c r e t s i g e r s i h t g n i t t e s h t d i w d n a b n o i t i s i u q c a e h t e s u l l i w l l p d e h t , c i t a m o t u a o t t e s s i n o i t c e l e s h t d i w d n a b , l a u n a m o t t e s n e h w . k c o l n i n e h w g n i t t e s h t d i w d n a b d e k c o l / l a m r o n e h t d n a , k c o l f o t u o n e h w . g n i t t e s h t d i w d n a b d e k c o l / l a m r o n e h t e s u y a w l a l l i w l l p d e h t 7 t i b n o i t a r e p o c i t a m o t u a 1 = ) t l u a f e d ( n o i t a r e p o l a u n a m 0 = h t d i w d n a b p o o l ) 0 : 2 ( t i b h t d i w d n a b n o i t i s i u q c a ) 4 : 6 ( s t i b z h 1 . 0 0 0 0 z h 1 . 0 0 0 0 z h 3 . 0 1 0 0 z h 3 . 0 1 0 0 z h 5 . 0 0 1 0 z h 5 . 0 0 1 0 z h 0 . 1 1 1 0 z h 0 . 1 1 1 0 z h 0 . 2 0 0 1 z h 0 . 2 0 0 1 ) t l u a f e d ( z h 0 . 4 1 0 1 z h 0 . 4 1 0 1 z h 0 . 8 0 1 1 z h 0 . 8 0 1 1 z h 7 1 1 1 1 ) t l u a f e d ( z h 7 1 1 1 1 d e s u n u 3 t i b 1 0 1 x 1 1 1 0 y c n e u q e r f _ l a n i m o n _ g f n c l a t s y r c e h t f o t e s f f o r o f n o i t a s n e p m o c g n i w o l l a r e g e t n i d e n g i s n u t i b 6 1 a s d l o h r e t s i g e r s i h t t l u a f e d . n o i t a r b i l a c y c n e u q e r f l a t s y r c n o i t c e s e e s . z h m 8 . 2 1 l a n i m o n e h t m o r f r o t a l l i c s o . t n e m t s u j d a m p p 0 n i s t l u s e r c 3 ) 0 : 7 ( s t i b y c n e u q e r f _ l a n i m o n _ g f n c ) 0 : 7 ( s t i b 1 0 0 1 1 0 0 1 d 3 ) 8 : 5 1 ( s t i b y c n e u q e r f _ l a n i m o n _ g f n c ) 0 : 7 ( s t i b 1 0 0 1 1 0 0 1 t e s f f o _ r e v o d l o h _ g f n c n a c h c i h w , e u l a v t e s f f o r e v o d l o h e h t g n i t n e s e r p e r , r e g e t n i d e n g i s t i b 9 1 a s d l o h r e t s i g e r s i h t t i b d e l b a n e t e s f f o r e v o d l o h e h t a i v d e l b a n e n e h w y c n e u q e r f e d o m r e v o d l o h e h t t e s o t d e s u e b . r e t s i g e r e d o m _ g f n c e h t n i e 3 ) 0 : 7 ( s t i b t e s f f o _ r e v o d l o h _ g f n c ) 0 : 7 ( s t i b 0 0 0 0 0 0 0 0 f 3 ) 8 : 5 1 ( s t i b t e s f f o _ r e v o d l o h _ g f n c ) 0 : 7 ( s t i b 0 0 0 0 0 0 0 0 0 4 7 t i b 2 3 m o r f n e k a t e b o t e g a r e v a y c n e u q e r f e h t s e l b a n e s i h t . e l b a n e g n i g a r e v a r e v o d l o h o t u a 1 = e b o t d e m r i f n o c n e e b s a h y c n e u q e r f e h t r e t f a , s d n o c e s 2 3 y r e v e n e k a t e l p m a s e n o . s e l p m a s o t d e k c o l y l t n e r r u c e h t f o y r o t s i h e t u n i m 7 1 a s e v i g s i h t . s r o t i n o m y c n e u q e r f e h t y b d n a b - n i . ) t l u a f e d ( . r e v o d l o h n i e s u r o f e c r u o s e c n e r e f e r . d e l b a s i d g n i g a r e v a r e v o d l o h o t u a 0 = d e s u n u ) 3 : 6 ( s t i b ) 6 1 : 8 1 ( s t i b t e s f f o _ r e v o d l o h _ g f n c ) 0 : 2 ( s t i b 0 0 0 x x x x 1 t i m i l _ q e r f _ g f n c t i . l l p d e h t f o e g n a r n i - l l u p e h t g n i t n e s e r p e r r e g e t n i d e n g i s n u t i b 0 1 a s d l o h r e t s i g e r s i h t e h t g n i s u , n o i t a c i l p p a e h t n i d e t n e m e l p m i l a t s y r c f o y c a r u c c a e h t o t g n i d r o c c a t e s e b d l u o h s : a l u m r o f g n i w o l l o f r o 7 4 6 1 0 . 0 + ) 5 8 7 0 . 0 x t i m i l _ q e r f _ g f n c ( = ) m p p ( - / + e g n a r y c n e u q e r f 5 8 7 0 . 0 / ) 7 4 6 1 0 . 0 - ) m p p ( - / + e g n a r y c n e u q e r f ( = t i m i l _ q e r f _ g f n c n e h w e u l a v t l u a f e d . m p p 3 . 9 s i w o l d e i t r o d e t c e n n o c n u t f e l s i w s c r s n e h w e u l a v t l u a f e d . m p p 0 8 d n u o r a f o e g n a r l l u f e h t s i h g i h s i w s c r s table 12. register map description (continued).
www.semtech.com 35 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. . r d d a ) x e h ( e m a n r e t e m a r a pn o i t p i r c s e dt l u a f e d ) n i b ( e u l a v 1 4 t i m i l _ q e r f _ g f n c ) d e u n i t n o c ( ) 0 : 7 ( s t i b t i m i l _ q e r f _ g f n c ) 0 : 7 ( s t i b 1 0 1 0 1 1 1 0 ) w o l w s c r s ( 1 1 1 1 1 1 1 1 ) h g i h w s c r s ( 2 4 d e s u n u ) 2 : 7 ( s t i b ) 8 : 9 ( s t i b t i m i l _ q e r f _ g f n c ) 0 : 1 ( s t i b 0 0 x x x x x x ) w o l w s c r s ( 1 1 x x x x x x ) h g i h w s c r s ( k s a m - t p u r r e t n i _ g f n c s u t a t s t p u r r e t n i e h t r e h t i e n i e c r u o s t p u r r e t n i e t a i r p o r p p a e h t e l b a s i d l l i w ' 0 ' o t t e s f i , t i b h c a e . r e t s i g e r s t u p n i _ 4 t _ s t s e h t r o r e t s i g e r 3 4 ) 0 : 7 ( s t i b k s a m _ t p u r r e t n i _ g f n c ) 0 : 7 ( s t i b 1 1 1 1 1 1 1 1 4 4 ) 8 : 5 1 ( s t i b k s a m _ t p u r r e t n i _ g f n c ) 0 : 7 ( s t i b 1 1 1 1 1 1 1 1 5 4 d e s u n u ) 5 : 7 ( s t i b ) 6 1 : 0 2 ( s t i b k s a m _ t p u r r e t n i _ g f n c ) 0 : 4 ( s t i b 1 1 1 1 1 x x x n v i d _ q e r f _ g f n c e s a h p e h t t e g o t > 1 _ i < : > 4 1 _ i < o t d e i l p p a t u p n i y n a r o f r o s i v i d e h t s a d e s u s i r e g e t n i t i b 4 1 s i h t e s u a c l l i w s i h t . ? 1 ? o t t e s t i b n v i d e h t h t i w s t u p n i r o f e v i t c a y l n o . d e r i s e d y c n e u q e r f g n i k c o l : o t n m a r g o r p . g . e , n o s i r a p m o c e s a h p o t r o i r p ) 1 + n ( y b d e d i v i d e b o t y c n e u q e r f t u p n i e h t 1 - ) z h k 8 / ) q e r f t u p n i ( ( e h t o t y c n e u q e r f t o p s t s e s o l c e h t t c e l f e r o t t e s e b d l u o h s s t i b y c n e u q e r f _ e c r u o s _ e c n e r e f e r e h t . y c n e u q e r f t u p n i e h t n a h t r e w o l e b t s u m t u b , y c n e u q e r f t u p n i 6 4) 0 : 7 ( s t i b n v i d _ q e r f _ g f n c ) 0 : 7 ( s t i b 0 0 0 0 0 0 0 0 7 4 d e s u n u ) 6 : 7 ( s t i b ) 8 : 3 1 ( s t i b n v i d _ q e r f _ g f n c ) 0 : 5 ( s t i b 0 0 0 0 0 0 x x 8 4 s r o t i n o m _ g f n c . t u o d l i u b e s a h p f o l o r t n o c d n a s r o t i n o m f o n o i t a r u g i f n o c l a b o l g s w o l l a r e t s i g e r t i b 7 s i h t d e s u n u 7 t i b 6 t i b o d t n i p f o t u o n e v i r d e b o t t p u r r e t n i d e l i a f _ f e r _ n i a m e h t f o e u l a v s e l b a n e 1 = ) t l u a f e d ( o d t n i p f o t u o n e v i r d g n i e b m o r f t p u r r e t n i d e l i a f _ f e r _ n i a m e h t f o e u l a v s e l b a s i d 0 = 5 t i b y l t n e r r u c e h t n o m r a l a y t i v i t c a n i n a e s i a r o t l l p d e h t s w o l l a : g n i h c t i w s t s a f a r t l u s e l b a n e 1 = g n i h c t i w s t s a f a r t l u n o n o i t c e s e e s . s e l c y c w e f a y l n o g n i s s i m r e t f a e c r u o s d e t c e l e s ) t l u a f e d ( n o i t a r e p o l a m r o n 0 = 4 t i b w o l w s c r s f i > 4 _ i < r o , h g i h w s c r s n i p f i > 3 _ i < o t g n i k c o l s e c r o f 1 = d e l b a n e l o r t n o c c i t a m o t u a d n a , d e r o n g i w s c r s n i p 0 = 3 t i b t e s f f o e s a h p t u p t u o o t t u p n i t n e r r u c e h t h t i w p i h s n o i t a l e r e s a h p t u p t u o e h t e z e e r f l l i w 1 = ) t l u a f e d ( ) e d o m t u o d l i u b e s a h p l a m r o n ( t e s f f o e s a h p t u p t u o o t t u p n i n i s e g n a h c s w o l l a 0 = 2 t i b ) t l u a f e d ( t u o d l i u b e s a h p s e l b a n e 1 = 0 o t k c o l s y a w l a l l i w l l p d 0 = e r a s r e h t o , ) t l u a f e d ( m p p 5 1 = 1 0 , f f o = 0 0 - s r o t i n o m y c n e u q e r f g n i r u g i f n o c r o f e r a ) 0 : 1 ( s t i b . e s u e r u t u f r o f d e v r e s e r 1 0 1 0 0 0 0 x ) w o l w s c r s ( 1 0 1 0 1 0 0 x ) h g i h w s c r s ( 0 5 0 d l o h s e r h t _ r e p p u _ v i t c a _ g f n c d e s i a r e b o t m r a l a y t i v i t c a e h t s e s u a c t a h t t e k c u b y k a e l e h t n i e u l a v e h t t e s ) 0 : 7 ( s t i b 0 1 1 0 0 0 0 0 1 5 0 d l o h s e r h t _ r e w o l _ v i t c a _ g f n c d e r a e l c e b o t m r a l a y t i v i t c a e h t s e s u a c t a h t t e k c u b y k a e l e h t n i e u l a v e h t t e s ) 0 : 7 ( s t i b 0 0 1 0 0 0 0 0 2 5 0 e z i s _ t e k c u b _ g f n c t u p n i e v i t c a n i n a n e v i g h c a e r n a c t e k c u b y k a e l e h t t a h t e u l a v m u m i x a m e h t t e s ) 0 : 7 ( s t i b 0 0 0 1 0 0 0 0 3 5 0 e t a r _ y a c e d _ g f n cd e s u n u ) 2 : 7 ( s t i b y r e v e r o f 1 + s i t e k c u b e h t f o e t a r - l l i f e h t . t e k c u b y k a e l e h t f o e t a r k a e l e h t l o r t n o c ) 0 : 1 ( s t i b e l b a m m a r g o r p s i e t a r y a c e d e h t . y t i v i t c a n i f o l e v e l e m o s d e c n e i r e p x e s a h t a h t l a v r e t n i s m 8 2 1 , 0 1 , 1 0 , 0 0 f o s e u l a v g n i s u y b 1 : 8 , 1 : 4 , 1 : 2 , 1 : 1 o t t e s e b n a c o i t a r e h t . e t a r l l i f e h t f o s o i t a r n i t e k c u b e h t . e r u t a n n i s t e k c u b y k a e l ? e u r t ? t o n e r a s t e k c u b e s e h t , r e v e w o h . y l e v i t c e p s e r 1 1 e h t e b n a c s e t a r y a c e d d n a l l i f e h t t a h t s n a e m s i h t . d e l l i f g n i e b s i t i n e h w ? g n i k a e l ? s p o t s s a e t a r e m a s e h t t a d e s i n g o c e r e b n a c t u p n i e v i t c a n a t a h t t c e f f e t e n e h t h t i w ) 1 : 1 = 0 0 ( e m a s . e n o e v i t c a n i n a 1 0 x x x x x x table 12. register map description (continued).
www.semtech.com 36 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. selection of input reference clock source under normal operation, the input reference sources are selected automatically by an order of priority. but, for special circumstances, such as chip or board testing, the selection may be forced by configuration. automatic operation selects a reference source based on its pre-defined priority and its current availability. a table is maintained which lists all reference sources in the order of priority. this is initially downloaded into the acs8510 via the microprocessor interface by the network manager, and is subsequently modified by the results of the ongoing quality monitoring. in this way, when all the defined sources are active and valid, the source with the highest programmed priority is selected but, if this source fails, the next-highest source is selected, and so on. restoration of repaired reference sources is handled carefully to avoid inadvertent disturbance of the output clock. the acs8510 has two modes of operation; revertive and non-revertive. in revertive mode, if a re- validated (or newly validated) source has a higher priority than the reference source which is currently selected, a switch over will take place. many applications prefer to minimise the clock switching events and choose non- revertive mode. in non-revertive mode , when a re-validated (or newly validated) source has a higher priority then the selected source will be maintained. the re-validation of the reference source will be flagged in the sts_sources_valid register and, if not masked, will generate an interrupt. selection of the re-validated source can only take place under software control - the software should briefly enable revertive mode to affect a switch-over to the higher priority source. if the selected source fails under these conditions the device will still not select the higher priority source until instructed to do so by the software, by briefly setting the revertive mode bit. when there is a reference available with higher priority than the selected reference, there will be no change of reference source as long as the non-revertive mode remains on. this is the case even if there are lower priority references available or the . r d d a ) x e h ( e m a n r e t e m a r a pn o i t p i r c s e dt l u a f e d ) n i b ( e u l a v 4 51 d l o h s e r h t _ r e p p u _ v i t c a _ g f n c1 t e k c u b r o f t u b 0 5 r e t s i g e r r o f s a 0 1 1 0 0 0 0 0 5 51 d l o h s e r h t _ r e w o l _ v i t c a _ g f n c1 t e k c u b r o f t u b 1 5 r e t s i g e r r o f s a 0 0 1 0 0 0 0 0 6 51 e z i s _ t e k c u b _ g f n c1 t e k c u b r o f t u b 2 5 r e t s i g e r r o f s a 0 0 0 1 0 0 0 0 7 51 e t a r _ y a c e d _ g f n c1 t e k c u b r o f t u b 3 5 r e t s i g e r r o f s a 1 0 x x x x x x 8 52 d l o h s e r h t _ r e p p u _ v i t c a _ g f n c2 t e k c u b r o f t u b 0 5 r e t s i g e r r o f s a 0 1 1 0 0 0 0 0 9 52 d l o h s e r h t _ r e w o l _ v i t c a _ g f n c2 t e k c u b r o f t u b 1 5 r e t s i g e r r o f s a 0 0 1 0 0 0 0 0 a 52 e z i s _ t e k c u b _ g f n c2 t e k c u b r o f t u b 2 5 r e t s i g e r r o f s a 0 0 0 1 0 0 0 0 b 52 e t a r _ y a c e d _ g f n c2 t e k c u b r o f t u b 3 5 r e t s i g e r r o f s a 1 0 x x x x x x c 53 d l o h s e r h t _ r e p p u _ v i t c a _ g f n c3 t e k c u b r o f t u b 0 5 r e t s i g e r r o f s a 0 1 1 0 0 0 0 0 d 53 d l o h s e r h t _ r e w o l _ v i t c a _ g f n c3 t e k c u b r o f t u b 1 5 r e t s i g e r r o f s a 0 0 1 0 0 0 0 0 e 53 e z i s _ t e k c u b _ g f n c3 t e k c u b r o f t u b 2 5 r e t s i g e r r o f s a 0 0 0 1 0 0 0 0 f 53 e t a r _ y a c e d _ g f n c3 t e k c u b r o f t u b 3 5 r e t s i g e r r o f s a 1 0 x x x x x x f 7 l e s p u _ g f n cd e s u n u ) 3 : 7 ( s t i b l l i w e c a f r e t n i e h t . e c a f r e t n i r o s s e c o r p o r c i m e h t f o e d o m e h t e g n a h c o t d e s u e b n a c ) 0 : 2 ( s t i b 7 3 r e t s i g e r a i v d a e r e b n a c p u t e s n i p e h t - ) 0 6 - 8 5 s n i p ( l e s p u s n i p e h t s a t e s e b y l l a i t i n i . g n i t t e s s i h t o t t l u a f e d l l i w e c i v e d e h t t e s e r r o p u r e w o p t a . ) s n i p _ l e s p u _ g f n c ( g n i t r o p p u s , p u t r a t s r e t f a e d o m r o s s e c o r p o r c i m e h t e g n a h c o t d e s u e b n a c r e t s i g e r s i h t e h t p u t r a t s t a . e d o m r e h t o n a a i v g n i t a c i n u m m o c y l t n e u q e s b u s d n a m o r p e m o r f g n i t o o b t s a l e h t s a d n a , s r e t s i g e r e h t l l a r o f s g n i t t e s d e m m a r g o r p - e r p e h t d a o l n w o d l l i w m o r p e s i h t t a h t d e d n e m m o c e r s i t i . r e t s i g e r t s a l s i h t h t i w e c a f r e t n i f o e g n a h c e h t n o i t c a , n o i t a r e p o e c i v e d s i h t f o s n o i s r e v t n e u q e s b u s s a , s n o i t a c i l p p a p u t r a t s m o r p e r o f d e s u y l n o s i n o i t c n u f 7 3 r e t s i g e r n i n e v i g s a r o 9 e l b a t n i d e n i f e d e r a s t i b e h t . y a w s i h t n i n o i t a r e p o w o l l a y l n o y a m . n o i t p i r c s e d p a m r e t s i g e r e h t f o = ) 3 : 7 ( s t i b x x x x x = ) 0 : 2 ( s t i b t n e d n e p e d n i p table 12. register map description (continued).
www.semtech.com 37 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. currently selected reference fails. when the only valid reference sources that are available have a lower priority than the selected reference, a failure of the selected reference will always trigger a switch-over regardless of whether revertive or non-revertive mode has been chosen. also, in a master/slave redundancy-protection scheme, the slave device(s) must follow the master device. the alignment of the master and slave devices is part of the protection mechanism. the availability of each source is determined by a combination of local and remote monitoring of each source. each input reference source supplied to each acs8510 device is monitored locally and the results are made available to other devices. forced control selection a configuration register, cnfg_ref_selection , controls both the choice of automatic or forced selection and the selection itself (when forced selection is required). the forced selection of an input reference source occurs when the cnfg_ref_selection variable contains a non-zero value, the value then representing the input port required to be selected. this is not the normal mode of operation, and the cnfg_ref_selection variable is defaulted to the all-one value on reset, thereby adopting the automatic selection of the reference source. automatic control selection when an automatic selection is required, the cnfg_ref_selection register must be set to all zero or all one. the configuration registers, cnfg_ref_selection_priority , held in the p port block, consists of seven, 8 bit registers organised as one 4 bit register per input reference port. each register holds a 4-bit value which represents the desired priority of that particular port. unused ports should be given the value, '0000' or '1111', in the relevant register to indicate they are not to be included in the priority table. on power-up, or following a reset, the whole of the configuration file will be defaulted to the values defined by table 4. the selection priority values are all relative to each other, with lower-valued numbers taking higher priorities. each reference source should be given a unique number, the valid values are 1 to 15 (dec). a value of 0 disables the reference source. however if two or more inputs are given the same priority number those inputs will be selected on a first in, first out basis. if the first of two same priority number sources goes invalid the second will be switched in. if the first then becomes valid again, it becomes the second source on the first in, first out basis, and there will not be a switch. if a third source with the same priority number as the other two becomes valid, it joins the priority list on the same first in, first out basis. there is no implied priority based on the channel numbers. the input port is for the connection of the synchronous clock of the t out0 output of the master device (or the active-slave device), to be used to align the t out0 output with the master (or active-slave) device if this device is acting in a subordinate-slave or subordinate- master role. ultra fast switching a reference source is normally disqualified after the leaky bucket monitor thresholds have been crossed. an option for a faster disqualification has been implemented, whereby if register 48h, bit 5 (ultra fast switching), is set then a loss of activity of just a few reference clock cycles will set the ?no activity alarm? and cause a reference switch. this can be chosen to cause an interrupt to occur instead of or as well as causing the reference switch. the sts_interrupts register 05 hex bit 14 (main_ref_failed) of the interrupt status register is used to flag inactivity on the reference that the device is locked to much faster than the activity monitors can support. if bit 6 of the cnfg_monitors register (flag ref loss on tdo) is set, then the state of this bit is driven onto the tdo pin of the device.
www.semtech.com 38 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. the flagging of the loss of the main reference failure on tdo is simply allowing the status of the sts_interrupt bit 14 to be reflected in the state of the tdo output pin. the pin will, therefore remain high until the interrupt is cleared. this functionality is not enabled by default so the usual jtag functions can be used. when jtag is normally used straight out of power-up, then this feature will have no bearing on the functionality. the tdo flagging feature will need to be disabled if jtag is not enabled on power-up and the feature has since been enabled. when the tdo output from the acs8510 is connected to the tdi pin of the next device in the jtag scan chain, the implementation should be such that a logic change caused by the action of the interrupt on the tdi input should not effect the operation when jtag is not active. external protection switching fast external switching between inputs and can also be triggered directly from a dedicated pin (srcsw). this mode can be activated either by holding this pin high during reset, or by writing to bit 4 of register address 48hex. once external protection switching is enabled, then the value of this pin directly selects either (srcsw high) or (srcsw low). if this mode is activated at reset by pulling the srcsw pin high, then it configures the default frequency tolerance of and to +/- 80 ppm (register address 41hex and 42hex). any of these registers can be subsequently set by external software if required. when external protection switching is enabled, the device will operate as a simple switch. all clock monitoring is disabled and the dpll will simply be forced to try to lock on to the indicated reference source. clock quality monitoring clock quality is monitored and used to modify the priority tables of the local and remote acs8510 devices. the following parameters are monitored: 1. activity (toggling) 2. frequency (this monitoring is only performed when there is no irregular operation of the clock or loss of clock condition) in addition, input ports and carry ami-encoded composite clocks which are reference leaky bucket source response alarm bucket_size upper_threshold lower_threshold (all programmable) programmable fall slopes inactivities/irregularities figure 9. inactivity and irregularity monitoring
www.semtech.com 39 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. monitored by the ami-decoder blocks. loss of signal is declared by the decoders when either the signal amplitude falls below +0.3 v or there is no activity for 1 ms. any reference source which suffers a loss-of- signal, loss-of-activity, loss-of-regularity or clock- out-of-band condition will be declared as unavailable. clock quality monitoring is a continuous process which is used to identify clock problems. there is a difference in dynamics between the selected clock and the other reference clocks. anomalies occurring on non-selected reference sources affect only that source's suitability for selection, whereas anomalies occurring on the selected clock could have a detrimental impact on the accuracy of the output clock. anomalies, whether affecting signal purity or signal frequency, could induce jitter or frequency offsets in the output clock, leading to anomalous behaviour. anomalies on the selected clock, therefore, have to be detected as they occur and the phase locked loop must be temporarily isolated until the clock is once again pure. the clock monitoring process cannot be used for this because the high degree of accuracy required dictates that the process be slow. to achieve the immediacy required by the phase locked loop requires an alternative mechanism. the phase locked loop itself contains appropriate circuitry, based around the phase detector, and isolates itself from the selected reference source as soon as a signal impurity is detected. it can likewise respond to frequency offsets outside the permitted range since these result in saturation of the phase detector. when the phase locked loop is isolated from the reference source, it is essentially operating in a holdover state; this is preferable to feeding the loop with a standby source, either temporarily or permanently, since excessive phase excursions on the output clock are avoided. anomalies detected by the phase detector are integrated in a leaky bucket accumulator. the time taken to raise an inactivity alarm on a reference source that has previously been fully active (leaky bucket empty) will be: ( cnfg_activ_upper_threshold n) 8 where n is the number of the relevent leaky bucket configuration. if an input is intermittently inactive then this time can be longer. the default setting of cnfg_activ_upper_threshold is 6, therefore the default time is 0.75 s. the time taken to cancel the activity alarm on a previously completely inactive reference source is calculated as: 2 x (( cnfg_bucket_size n) - ( cnfg_activ_lower_thrshold n)) 8 where n is the number of the relevent leaky bucket configuration in each case. the default setting are shown in the following: 2 x (8-4) = 1.0 s 8 secs secs ( cnfg_decay_rate n) leaky bucket timing 1
www.semtech.com 40 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. occasional anomalies do not cause the accumulator to cross the alarm setting threshold, so the selected reference source is retained. persistent anomalies cause the alarm setting threshold to be crossed and result in the selected reference source being rejected. activity monitoring the acs8510 has a combined inactivity and irregularity monitor. the acs8510 uses a ?leaky bucket? accumulator, which is a digital circuit which mimics the operation of an analog integrator, in which input pulses increase the output amplitude but die away over time. such integrators are used when alarms have to be triggered either by fairly regular defect events, which occur sufficiently close together, or by defect events which occur in bursts. events which are sufficiently spread out should not trigger the alarm. by adjusting the alarm setting threshold, the point at which the alarm is triggered can be controlled. the point at which the alarm is cleared depends upon the decay rate and the alarm clearing threshold. on the alarm setting side, if several events occur close together, each event adds to the amplitude and the alarm will be triggered quickly; if events occur a little more spread out, but still sufficiently close together to overcome the decay, the alarm will be triggered eventually. if events occur at a rate which is not sufficient to overcome the decay, the alarm will not be triggered. on the alarm clearing side, if no defect events occur for a sufficient time, the amplitude will decay gradually and the alarm will be cleared when the amplitude falls below the alarm clearing threshold. the ability to decay the amplitude over time allows the importance of defect events to be reduced as time passes by. this means that, in the case of isolated events, the alarm will not be set, whereas, once the alarm becomes set, it will be held on until normal operation has persisted for a suitable time (but if the operation is still erratic, the alarm will remain set). see figure 9. the ?leaky bucket? accumulators are programmable for size, alarm set & reset thresholds and decay rate. each source is monitored over a 128 ms period. if, within a 128 ms period, an irregularity occurs that is not deemed to be due to allowable jitter/wander, then the accumulator is incremented. the accumulator will continue to increment up to the point that it reaches the programmed bucket size. the ?fill rate? of the leaky bucket is, therefore, 8 units/second. the ?leak rate? of the leaky bucket is programmable to be in multiples of the fill rate (x1, x0.5, x0.25 and x0.125) to give a programmable leak rate from 8 units/sec down to 1 unit/sec. a conflict between trying to ?leak? at the same time as a ?fill? is avoided by preventing a ?leak? when a ?fill? event occurs. disqualification of a non-selected reference source is based on inactivity, or on an out of band result from the frequency monitors. the currently selected reference source can be disqualified for phase, frequency, inactivity or if the source is outside the dpll lock range. if the currently selected reference source is disqualified, the next highest priority, active reference source is selected. frequency monitoring the acs8510 performs frequency monitoring to identify reference sources which have drifted outside the acceptable frequency range of +/- 16.6 ppm (measured with respect to the output clock). the sts_reference_sources out- of-band alarm for a particular reference source is raised when the reference source is outside the acceptable frequency range. the acs8510 dpll has a programmable frequency limit of +/- 80 ppm. if the range is programmed to be > 16.6 ppm, the frequency monitors should be disabled so the input reference source is not automatically rejected as out of frequency range.
www.semtech.com 41 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. modes of operation the acs8510 has three primary modes of operation (free-run, locked and holdover) supported by three secondary, temporary modes (pre-locked, lost_phase and pre- locked2). these are shown in the state transition diagram, figure 11. the acs8510 can operate in forced or automatic control. on reset, the acs8510 reverts to automatic control, where transitions between states are controlled completely automatically. forced control can be invoked by configuration, allowing transitions to be performed under external control. this is not the normal mode of operation, but is provided for special occasions such as testing, or where a high degree of hands-on control is required. free-run mode the free-run mode is typically used following a power-on-reset or a device reset before network synchronization has been achieved. in the free-run mode, the timing and synchronization signals generated from the acs8510 are based on the master clock frequency provided from the external oscillator and are not synchronized to an input reference source. the frequency of the output clock is a fixed multiple of the frequency of the external oscillator, and the accuracy of the output clock is equal to the accuracy of the master clock. the transition from free-run to pre-locked occurs when the acs8510 selects a reference source. pre-locked mode the acs8510 will enter the locked state in a maximum of 100 seconds, as defined by gr- 1244-core specification, if the selected reference source is of good quality. if the device cannot achieve lock within 100 seconds, it reverts to free-run mode and another reference source is selected. locked mode the locked mode is used when an input reference source has been selected and the pll has had time to lock. when the locked mode is achieved, the output signal is in phase and locked to the selected input reference source. the selected input reference source is determined by the priority table. when the acs8510 is in locked mode, the output frequency and phase follows that of the selected input reference source. variations of the external crystal frequency have a minimal effect on the output frequency. only the minimum to maximum frequency range is affected. note that the term, 'in phase', is not applied in the conventional sense when the acs8510 is used as a frequency translator (e.g., when the input frequency is 2.048 mhz and the output frequency is 19.44 mhz) as the input and output cycles will be constantly moving past each other; however, this variation will itself be cyclical over time unless the input and output are not locked. lost_phase mode lost-phase mode is entered when the current phase error, as measured within the dpll, is larger than a preset limit (see register 04, bits 5:3), as a result of a frequency or phase transient on the selected reference source. this mode is similar in behavior to the pre-locked or pre-locked(2) modes, although in this mode the dpll is attempting to regain lock to the same reference rather than attempt lock to a new reference. if the dpll cannot regain lock within 100 s, the source is disqualified, and one of the following transitions takes place: 1. go to pre-locked(2); - if a known-good standby source is available. 2. go to holdover; - if no standby sources are available.
www.semtech.com 42 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. holdover mode the holdover mode is used when the acs8510 has been in locked mode for long enough to acquire stable frequency data, but the final selected reference source has become unavailable and a replacement has not yet been qualified for selection. in holdover mode, the acs8510 provides the timing and synchronisation signals to maintain the network element (ne), but they are not phase locked to any input reference source. the timing is based on a stored value of the frequency ratio obtained during the last locked mode period. to allow for further development of the way the internal algorithm operates, and to allow for customised switching behaviour, the switch to and from holdover state may be controlled by external software. the device must be set in either ?manual? mode or ?automatic? mode: 1. register cnfg_mode bit ?holdover offset en? set high (manual mode). the holdover frequency is determined by the value in register cnfg_holdover_offset . this is a 19 bit signed number, with a lsb resolution of 0.0003 ppm, which gives an adjustment range of 80 ppm. this value can be derived from a reading of the register sts_curr_inc_offset (addr 0d, 0c and 07) which gives, in the same format, an indication of the current output frequency deviation, which would be read when the device is locked. if required, this value could be read by an external microcontroller and averaged over the time required. the averaged value could then be fed to the cnfg_holdover_offset register ready for setting of the averaged frequency value when the device enters holdover mode. the sts_curr_inc_offset value is internally derived from the digital phase locked loop (dpll) integral path value, which already represents a well averaged measure of the current frequency, depending on the loop bandwidth selected. 2. register cnfg_mode bit ?holdover offset en? set low (automatic mode). in automatic control, the device can be run in one of two ways: 2.1 register cnfg_holdover_offset register 40 bit 7 ?auto holdover averaging? is set high. the value is averaged internally over 32 samples at 32 seconds apart, giving the average frequency over approximatley the last 20 minutes. the proportional dpll path is ignored so that recent signal disturbances do not affect the holdover frequency value. if the device has been previously correctly locked, missing pulses in the input clock stream fed to the sets ic are ignored, hence also avoiding any frequency disturbances to the output frequency value when an input clock source fails. 2.2 register cnfg_holdover_offset register 40 bit 7 ?auto holdover averaging? is set low. this simply freezes the dpll at the current frequency (as reported by the sts_curr_inc_offset register). the proportional dpll path is ignored so that recent signal disturbances do not affect the holdover frequency value. automatic control with internal averaging (option 2.1) is the default condition. if the tcxo frequency is varying due to temperature fluctuations in the room, then the instantaneous value can be different from the average value, and then it may be possible to exceed the 0.05 ppm limit (depending on how extreme the temperature flucuations are). it is advantageous to shield the tcxo to slow down frequency changes due to drift and external temperature fluctuations. the frequency accuracy of holdover mode has to meet the itu-t, etsi and telcordia performance requirements. the performance of the external oscillator clock is critical in this mode, although only the frequency stability is important - the stability of the output clock in holdover is directly related to the stability of the external oscillator. pre-locked(2) mode this state is very similar to the pre-locked state. it is entered from the holdover state when a reference source has been selected and applied to the phase locked loop. it is also entered if the device is operating in revertive mode and a higher-priority reference source is restored. upon applying a reference source to the phase locked loop, the acs8510 will enter the locked state in a maximum of 100 seconds, as defined
www.semtech.com 43 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. by gr-1244-core specification, if the selected reference source is of good quality. if the device cannot achieve lock within 100 seconds, it reverts to holdover mode and another reference source is selected. protection facility the acs8510 supports redundancy protection. the primary functions of this include: - alignment of the priority tables of both master and slave acs8510 devices so as to align the selection of reference sources of both master and slave acs8510 devices. - alignment of the phases of the 8 khz and 2 khz clocks in both master and slave acs8510 devices to within one cycle of the 77.76 mhz internal clock. when two acs8510 devices are to be used in a redundancy-protection scheme within an ne, one will be designated as the master and the other as the slave. it is expected that an ne will use the t out0 output for its internal operations because the t out4 output is intended to feed an ssu/bits system. an ssu/bits will not be bothered by phase differences between signals arriving from different sources because it typically incorporates line build-out functions to absorb phase differences on reference inputs. this means that the phasing of the composite clocks between two acs8510 devices do not have to be mutually-aligned. the same is not true, however, of the t out0 output signals (t 01 - t 07 , frame clock and multi-frame clock). it is usually important to align the phases of all equivalent t out0 signals generated by different sources so that switch-over from one device to another does not affect the internal operations of the ne. both acs8510 devices will produce the same signals, which will be routed around the ne to the various consumers (clock sinks). with the possible exception of a through-timing mode, the signals from the master device will be used by all consumers, unless the master device fails, when each consumer will switch over to the signals generated by the slave device. switchover to a new t out0 clock should be as hitless as possible. this requires the signals of both acs8510 devices to be phase aligned at each consumer. phase alignment requires frequency alignment. to ensure that both devices can generate output clocks locked to the same source, both devices are supplied with the same reference sources on the same input ports and will have identical priority tables. failures of selected reference sources will result in both acs8510 devices making the same updates to their priority tables as availability information will be updated in both devices. although, in principle, the priority tables will be the same if the same reference sources are used on the same input port on each device, in practice, this is only true if the reference sources actually arrive at each device - failures of a source seen only by one device and not by the other, such as could be caused, for example, by a backplane connector failure, would result in the priority tables becoming misaligned. it is thus necessary to force the priority tables to be aligned under normal operating conditions so that the devices can make the same decisions - this can be achieved by loading the availability seen by one device (via the sts_reference_sources register) into the cnfg_sts_remote_sources_valid register of the other device. another factor which could affect hit-less switching is the frequency of the local oscillator clock used by each acs8510 device: these clocks are not mutually aligned and, whilst this has no impact on the frequency of the output clocks during locked mode, it could cause the output frequencies to diverge during holdover mode if no action were taken to avoid it. in order to maintain alignment of the output frequencies of each acs8510 device even
www.semtech.com 44 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. during holdover, the master device's 6.48 mhz output is fed into the slave device on its pin, whilst the multi-frame sync (2 khz) output is fed to the sync2k input of the slave. in this way, the slave locks to the master's output and remains locked whilst the master moves between operating states. only when the master fails does the slave use its own reference inputs - should the master have been in the holdover state, the slave device will see the same lack of reference sources and also enter the holdover state. this scheme also provides a convenient way to phase-align all t out0 output clocks in master and slave devices, and also to detect the failure of the master device. if a master device fails, the slave has to take over responsibility for the generation of the output clocks, including the 8 khz and 2 khz frame and multi-frame clocks. the slave device is also given responsibility for building the priority table and performing the reference switching operations. the slave device, therefore, adopts a more active role when the master has failed. the cnfg_mode register 34 (hex) bit 1 contains the ?master/slave? control bit to determine the designation of the device. to restore redundancy protection, the master has to be repaired and replaced. when this occurs, the new master cannot immediately adopt its normal role because it must not cause phase hits on the output clocks. it has, therefore, to adopt a subordinate role to the active slave device, at least until such time as it has acquired alignment to the 8 khz and 2 khz frame and multi-frame clocks and the priority table of the slave device; then, when a switch-back (restoration) is ordered, the master can take over responsibility. these activities, in master or slave operation, are summarized in table 12 and described in detail in application note an-sets-2. alignment of priority tables in master and slave acs8510 correct protection will only be achieved by connecting individual reference sources to the same input ports on each device and priority tables in each device must be aligned to each other. the master device must take account of the availability of each reference source seen by another device and a slave device must adopt the same order of priority as the master device (except that the slave's highest-priority input is ). both devices monitor the reference sources and decide the availability of each source; if the failure of a reference source is seen by both devices, they will both update their priority tables - however, if the reference source failure is only seen by one device and not by both, the priority tables could get out of step: this could be catastrophic if it resulted in two devices choosing different reference sources since any slight differences in frequency variation over time (e.g. wander) would mis-align the phase of the 8 khz frame and 2 khz multi- frame clocks produced by the individual devices, resulting in phase hits on switch-over. it is therefore important that the same priority table be built by each device, using the reference source availability seen by each device. the monitoring of the reference sources performed by a master acs8510 results in a list of available sources being placed in a sts_valid_sources register. this information is used within the device as one of the masks used to build the device's priority table. the information is passed to the slave device and used to configure the cnfg_sts_remote_ sources_valid register so that it can use it as a mask in building its own priority tables. the information is passed between devices using the microprocessor port.
www.semtech.com 45 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. alignment of the selection of reference sources for t out4 generation in the master and slave acs8510 as stated previously, there is no need to align the phases of the t out4 outputs in master and slave devices. there is a need, however, to ensure that all devices select the same reference source. but, since there is no holdover mode required for the generation of the t out4 clock, and every reference source is continuously monitored within each device, it is permissible to rely on external intelligence to command a switch-over to an alternative source should the selected one fail. the time delay involved in detecting the failure, indicating it to the outside and selecting a new source, will result only in the ssu/bits entering its holdover mode for a short time. alignment of the phases of the 8khz and 2khz clocks in both master and slave acs8510 in addition to aligning the edges of the t out0 outputs of master and slave devices, it is necessary to align the edges of the frame and multi-frame clocks. if this is not performed, frame alignment may be lost in distant equipment on switch-over to an alternative device, resulting in anomalous network operation of a very serious nature. in accordance with the alignment mechanism used with the main t out0 clock (described in the opening paragraphs of this section), whereby the 6.48 mhz output of the master device is supplied to the slave device, the alignment of both the 8 khz and 2 khz clocks is accomplished (they are already synchronous to the t out0 clocks) by feeding the 2 khz clock of the master device into the slave device. the multi-frame sync clock output of the slave device is also fed to the sync2k input of the master device. alignment of the multi-frame sync input occurs only when cnfg_mode register, bit 3, address 34hex external 2 khz sync enable is set to 1. jtag the jtag connections on the acs8510 allow a full boundary scan to be made. the jtag implementation is fully compliant to ieee 1149.1, with the following minor exceptions, and the user should refer to the standard for further information. 1. the output boundary scan cells do not capture data from the core, and so do not support extest. however this does not affect board testing. 2. in common with some other manufacturers, pin trst is internally pulled low to disable jtag by default. the standard is to pull high. the polarity of trst is as the standard: trst high to enable jtag boundary scan mode, trst low for normal operation. 3. the device does not support the optional tri-state capability (highz). this will be supported on the next revision of the device. the jtag timing diagram is shown in figure 17. porb the power on reset (porb) pin resets the device if forced low for a power on reset to be initiated. the reset is asynchronous, the minimum low pulse width is 5 ns. reset is needed to initialize all of the register values to their defaults. asserting reset is required at power on, and may be re-asserted at any time to restore defaults. this is implemented most simplistically by an external capacitor to gnd along with the internal pull-up resistor. the acs8510 is held in a reset state for 250 ms after the porb pin has been pulled high. in normal operation porb should be held high.
www.semtech.com 46 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. o t s e c r u o s _ f e r 0 1 5 8 s c a r e t s a m o t s e c r u o s _ f e r 0 1 5 8 s c a e v a l s 0 1 5 8 s c a r e t s a m s u t a t s 0 1 5 8 s c a e v a l s s u t a t s 0 1 5 8 s c a r e t s a m 0 1 5 8 s c a e v a l s t u p t u o s t n e m m o c d o o g l l ad o o g l l ad o o gd o o g) x _ f e r ( d e k c o lr e t s a m o t d e k c o l1 e t o n d e l i a f e m o sd e l i a f s r e h t o e m o sd o o gd o o g) y _ f e r ( d e k c o lr e t s a m o t d e k c o l1 e t o n d o o gd o o gd o o gd e l i a f) x _ f e r ( d e k c o ld a e d d o o gd o o gd e l i a fd o o gd a e d) x _ f e r ( d e k c o l2 e t o n d o o gd o o gd e l i a fd e l i a fd a e dd a e d d e l i a fd e l i a fd e l i a fd o o gr e v o d l o hr e t s a m o t d e k c o l3 e t o n d e l i a fd e l i a fd o o gd e l i a fr e v o d l o hd a e d d e l i a fd e l i a fd e l i a fd o o gd a e dr e v o d l o h d e l i a fd e l i a fd e l i a fd e l i a fd a e dd a e d master mstslvb i_1 i_2 i_3 i_11 i_14 sync2k . . . t v 01 02 03 04 011 07 dd t t t t t r mf s ync . . . t i_11 sync2k i_14 . . . mf t 011 ync s r . . . 07 mstslvb i_3 i_2 i_1 tcxo 04 t 03 t 02 t slave t 01 tcxo sec1 sec2 sec3 sec13 sec14 sec1 sec2 sec3 gnd 6.48 mhz 6.48 mhz sync2k_en=1 34bit3 . . . . . . . . . . . . notes to table 13 note 1: both acs8510 must build a common priority table so that the slave acs8510 can select the same input reference source as the master acs8510 if the master fails (when the master is ok, the slave locks to the master's output). note 2: slave acs8510 uses common priority table, built before master acs8510 failed - priority table can be modified as status of the input reference sources changes note 3: slave acs8510 outputs must remain in phase with those of master acs8510 figure 10. master-slave schematic table 13. master-slave relationship
www.semtech.com 47 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. pre-locked w ait f or up to 100s (state 110) locked keep ref (state 100) holdover select ref (state 010) (2) all refs evaluated & at least one r ef valid (5) selected ref phase l ocked (3) no valid standby ref & (main ref invalid or out of lock > 100s) (14) all refs evaluated & at least one r ef valid pre-locked2 w ait f or up to 100s (state 101) ( 10) selected sour ce phase locked (6) no valid standby ref & main ref invalid free-run select ref (state 001) (1)reset reference sources are flagged as 'valid' when active, 'in-band' and have no phase alarm set. all sources are continuously checked for activity and frequency. only the main source is checked for phase. a phase lock alarm is only raised on a reference when that reference has lost phase whilst being used as the main reference. the micro-processor can reset the phase lock alarm. a source is considered to have phase locked when it has b een continuously in phase lock for between 1 and 2 seconds lost phase w ait for up to 100s (state 111) ( 7) phase lost on main ref (8) phase regained within 100s ( 12) valid standby r ef & ( mai n r ef invali d or out of lock > 100s) (13) no vali d standby r ef & (main ref invalid or out of lock > 100s) (11) no valid standby r ef & (main ref invalid or out of lock >100s) ( 9) valid standby r ef & [ main ref invalid or (higher-priority ref valid & in revertive mode) ] ( 15) valid standby r ef & [ main ref invalid or (higher-priority ref valid & in r evertive mode) or out of lock >100s] ( 4) valid standby r ef & [ main ref invalid or (higher-priority ref valid & in r ever tive m ode) or out of lock > 100s] figure 11. automatic mode control state diagram
www.semtech.com 48 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. electrical specification important note : the ?absolute maximum ratings? are stress ratings only, and functional operation of the device at conditions other than those indicated in the ?operating conditions? sections of this specification are not implied. exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product. table 14. absolute maximum ratings table 15. operating conditions pr e t e m a r a sl o b m y mn i mx a us t i n p p u se g a t l o v y l v d d v , d v , + a , + 1v a + 2 v d d 5 . 0 -6 . 3v e g a t l o v t u p n i ) s n i p y l p p u s - n o n ( n i v- 5 . 5v e g a t l o v t u p t u o ) s n i p y l p p u s - n o n ( t u o v- 5 . 5v e r u t a r e p m e t g n i t a r e p o t n e i b m a e g n a r t a 0 4 -+5 8c e r u t a r e p m e t e g a r o t st r o t s 0 5 -+0 5 1c table 16. dc characteristics: ttl input port r e t e m a r a p l o b m y s n i m p y t x a m s t i n u v n i h g i hv h i 0 . 2--v v n i w o lv l i -- 8 . 0v t n e r r u c t u p n ii n i -- 0 1a across all operating conditions, unless otherwise stated pr e t e m a r a sl o b m y n i m p y t x a m s t i n u ) e g a t l o v c d ( y l p p u s r e w o p vd d+ 2 a v , + 1 a v , + d v ,, + i m a v , f f i d _ d d v d d v0 . 33 . 36 . 3v ) e g a t l o v c d ( y l p p u s r e w o p 5 d d v 5 d d v0 . 30 . 5 / 3 . 35 . 5v e g n a r e r u t a r e p m e t t n e i b m at a 0 4 --+5 8c t n e r r u c y l p p u s ) t u p t u o z h m 9 1 e n o - l a c i p y t ( d d i-0 1 10 0 2a m n o i t a p i s s i d r e w o p l a t o tp t o t -0 6 30 2 7w m
www.semtech.com 49 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. table 17. dc characteristics: ttl input port with internal pull-up table 18. dc characteristics: ttl input port with internal pull-down table 19. dc characteristics: ttl output port r e t e m a r a p l o b m y s n i m p y t x a m s t i n u w o l t u o v a m 4 = l o i l o v0- 4 . 0v h g i h t u o v a m 4 = h o i h o v4 . 2- v t n e r r u c e v i r dd i--4a m r e t e m a r a p l o b m y s n i m p y t x a m s t i n u v n i h g i hv h i 0 . 2--v v n i w o lv l i -- 8 . 0v r o t s i s e r p u - l l u pu p0 3-0 8k w t n e r r u c t u p n ii n i -- 0 2 1a r e t e m a r a p l o b m y s n i m p y t x a m s t i n u v n i h g i hv h i 0 . 2--v v n i w o lv l i -- 8 . 0v r o t s i s e r n w o d - l l u pd p0 3-0 8k w t n e r r u c t u p n ii n i -- 0 2 1a across all operating conditions, unless otherwise stated across all operating conditions, unless otherwise stated across all operating conditions, unless otherwise stated
www.semtech.com 50 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. table 20. dc characteristics: pecl input/output port notes to table 20 unused differential input ports should be left floating and set in lvds mode, or the positive and negative inputs tied to vdd and gnd respectively. note 1. assuming a differential input voltage of at least 100 mv. note 2. unused differential input terminated to vdd-1.4 v. note 3. with 50 w load on each pin to vdd-2 v. i.e. 82 w to gnd and 130 w to vdd. r e t e m a r a p l o b m y s n i m p y t x a m s t i n u e g a t l o v w o l t u p n i l c e p s t u p n i l a i t n e r e f f i d) 1 e t o n ( v l c e p l i - d d v5 . 2- 5 . 0 - d d vv e g a t l o v h g i h t u p n i l c e p s t u p n i l a i t n e r e f f i d) 1 e t o n ( v l c e p h i - d d v4 . 2- 4 . 0 - d d vv e g a t l o v l a i t n e r e f f i d t u p n iv l c e p d i 1 . 0-4 . 1v e g a t l o v w o l t u p n i l c e p t u p n i d e d n e e l g n i s) 2 e t o n ( v s _ l c e p l i - d d v4 . 2- 5 . 1 - d d vv e g a t l o v h g i h t u p n i l c e p t u p n i d e d n e e l g n i s) 2 e t o n ( v s _ l c e p h i 1 - d d v3 .- 5 . 0 - d d vv t n e r r u c h g i h t u p n i e g a t l o v l a i t n e r e f f i d t u p n i v d i v 4 . 1 = i l c e p h i 0 1 --0 1 +a t n e r r u c w o l t u p n i e g a t l o v l a i t n e r e f f i d t u p n i v d i v 4 . 1 = i l c e p l i 0 1 --0 1 +a e g a t l o v w o l t u p t u o l c e p ) 3 e t o n ( v l c e p l o - d d v0 1 . 2- 2 6 . 1 - d d vv e g a t l o v h g i h t u p t u o l c e p ) 3 e t o n ( v l c e p h o 5 2 . 1 - d d v-8 8 . 0 - d d vv e g a t l o v l a i t n e r e f f i d t u p t u o l c e p ) 1 e t o n ( v l c e p d o 0 8 5-0 0 9v m across all operating conditions, unless otherwise stated
www.semtech.com 51 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. 130r i6pos i6neg i5neg i5pos t06pos t06neg t07pos t07neg z o =50 w z o =50 w z o =50 w z o =50 w z o =50 w z o =50 w 82r dd v 82r 130r z o =50 w z o =50 w 130r 82r 82r 130r dd v dd 82r 130r v 82r 130r 130r 82r 82r 130r dd v gnd gnd gnd gnd 8khz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 mhz 51.84, 77.76 or 155.52 mhz 8khz, 1.544/2.048, 6.48, 19.44, 38.88, 19.44, 38.88, 155.52, 311.04 mhz & dig1 19.44, 51.84, 77.76, 155.52 mhz vdd = +3.3 v figure 12. recommended line termination for pecl input/output ports
www.semtech.com 52 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. table 21. dc characteristics: lvds input/output port note to table 21 note 1. with 100 w load between the differential outputs. r e t e m a r a p l o b m y s n i m p y t x a m s t i n u ls d ve g n a r e g a t l o v t u p n i v m 0 0 1 = e g a t l o v t u p n i l a i t n e r e f f i d v s d v l r v 0- 0 4 . 2v d l o h s e r h t t u p n i l a i t n e r e f f i d s d v lv h t i d 0 0 1 --0 0 1 +mv e g a t l o v l a i t n e r e f f i d t u p n i s d v lv s d v l d i 1 . 0-4 . 1v e c n a t s i s e r n o i t a n i m r e t t u p n i s d v l e h t s s o r c a y l l a n r e t x e d e c a l p e b t s u m . 0 1 5 8 s c a f o s n i p t u p n i - / + s d v l 0 0 1 e b d l u o h s r o t s i s e r w % 5 h t i w e c n a r e l o t r m r e t 5 90 0 15 0 1 w e g a t l o v h g i h t u p t u o s d v l ) 1 e t o n ( v s d v l h o -- 5 8 5 . 1v e g a t l o v w o l t u p t u o s d v l ) 1 e t o n ( v s d v l l o 5 8 8 . 0--v e g a t l o v t u p t u o l a i t n e r e f f i d s d v l ) 1 e t o n ( v s d v l d o 0 5 2-0 5 4v m ls d vf o e d u t i n g a m n i e g n a h c r o f e g a t l o v t u p t u o l a i t n e r e f f i d s e t a t s y r a t n e m i l p m o c ) 1 e t o n ( v s d v l s o d -- 5 2v m ls d ve g a t l o v t e s f f o t u p t u o c 5 2 = e r u t a r e p m e t ) 1 e t o n ( v s d v l s o 5 2 1 . 1-5 7 2 . 1v across all operating conditions, unless otherwise stated
www.semtech.com 53 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. i6pos i6neg i5neg i5pos t06pos t06neg t07pos t07neg z o =50 w z o =50 w z o =50 w z o =50 w z o =50 w z o =50 w 100r z o =50 w z o =50 w 8khz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 mhz 51.84, 77.76 or 155.52 mhz 8khz, 1.544/2.048, 6.48, 19.44, 38.88, 19.44, 38.88, 155.52, 311.04 mhz & dig1 19.44, 51.84, 77.76, 155.52 mhz 100r 100r 100r figure 13. recommended line termination for lvds input/output ports
www.semtech.com 54 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. the alternate mark inversion (ami) signal is dc balanced and consists of positive and negative pulses with a peak to peak voltage of 2.0 +/- 0.2 v. the electrical specifications are taken from option a) of table 2/g.703 - digital 64 kbit/s centralized clock interface, from itu g.703. the electrical characteristics of 64 kbits/s interface are as follows; nominal bit rate: 64 kbit/s. the tolerance is determined by the network clock stability. there should be a symmetrical pair carrying the composite timing signal (64 khz and 8 khz). the use of transformers is recommended. over-voltage protection requirement; refer to recommendation k.41. code conversion rules; the data signals are coded in ami code with 100% duty cycle. the composite clock timing signals convey the 64 khz bit-timing information using ami coding with a 50% to 70% duty ratio and the 8 khz octet phase information by introducing violations in the code rule. the structure of the signals and voltage levels are shown in figures 14 and 15. table 22. dc characteristics: ami input/output port dc characteristics: ami input/output port across all operating conditions, unless otherwise stated r e t e m a r a p l o b m y s n i m p y t x a m s t i n u h t d i w e s l u p t u p n it w p 6 5 . 18 . 74 0 . 4 1s u e m i t l l a f / e s i r e s l u p t u p n it f / r --5s u i m ah g i h e g a t l o v t u p n iv i m a h i 5 . 2-v d d 3 . 0 +v i m ae g a t l o v t u p n ie l d d i mv i m a m i v 5 . 15 6 . 18 . 1v i m ae g a t l o v t u p n iw o lv i m a l i v 0- 4 . 1v e v i r d t n e r r u c t u p t u o i m ai t u o i m a -- 0 2a m e g a t l o v h g i h t u p t u o i m a a m 0 2 = t n e r r u c t u p t u o v i m a h o v d d 6 1 . 0 ---v i m ae g a t l o v w o l t u p t u o a m 0 2 = t n e r r u c t u p t u o v i m a l o -- 6 1 . 0v e c n e d e p m i d a o l t s e t l a n i m o nr t s e t -0 1 1- w r e t f a e d u t i l p m a " k r a m " r e m r o f s n a r t v k r a m 9 . 00 . 11 . 1v r e t f a e d u t i l p m a " e c a p s " r e m r o f s n a r t v e c a p s 1 . 0 -01 . 0v
www.semtech.com 55 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. after suitable input/output transformer (also see figure 6/g.703) 15.6us 7.8us 2vp-p 1v +1.0v ih -1.0v il 0v im 1v 15.6us 7.8us 2vp-p 1v +1.0v ih -1.0v il 0v im 1v 15.6us 7.8us 2vp-p 1v +1.0v ih -1.0v il 0v im 1v 15.6us 7.8us 2vp-p 1v +1.0v ih -1.0v il 0v im 1v c1 c1 c2 to8pos to8neg i_1 i_2 15.6us 7.8us +vdd 0v 15.6us 7.8us +vdd 0v signal structure of 64 khz/ 8 khz central clock interface after suitable transformer. 15.6us 7.8us 0v +vdd 15.6us 7.8us 0v +vdd figure 14. signal structure of 64 khz/8khz central clock interface figure 15. ami input and output signal levels
www.semtech.com 56 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. figure 16. recommended line termination for ami output/output ports notes the ami inputs and should be connected to the external ami clock source by 470 nf coupling capacitor c1. the ami differential output to8pos/to8neg should be coupled to a line transformer with a turns ration of 3:1. components c2 = 470 pf and c3 = 2 nf. if a transformer with a turns ratio of 1:1 is used, a 3:1 ratio potential divider r load must be used to achieve the required 1 v pp voltage level for the positive and negative pulses. c1 c1 c2 c3 r to8pos to8neg ami input gnd ami output signal to external devices turns ratio 1:1 signal ami input signal load
www.semtech.com 57 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. output jitter generation measured over 60 seconds interval, ui pp max measured using vectron 6664 12.8 mhz tcxo on ict flexacom + 10 mhz reference from wavetek 905. across all operating conditions, unless otherwise stated table 23. dc characteristics: output jitter generation (test definition g.813) table 24. dc characteristics: output jitter generation (test definition g.812) across all operating conditions, unless otherwise stated output jitter generation measured over 60 seconds interval, ui pp max measured using vectron 6664 12.8 mhz tcxo on ict flexacom + 10 mhz reference from wavetek 905. n o i t i n i f e d t s e td e s u r e t l i fc e p s i u 0 1 5 8 s c a n o t n e m e r u s a e m i u 2 v e r 1 n o i t p o z h m 2 5 . 5 5 1 r o f 3 1 8 . gz h m 3 . 1 o t z h 0 0 5i u p p 5 . 0 =) 2 e t o n ( 8 5 0 . 0 1 n o i t p o z h m 2 5 . 5 5 1 r o f 3 1 8 . gz h m 3 . 1 o t z h k 5 6i u p p 1 . 0 = ) 3 e t o n ( 8 4 0 . 0 ) 2 e t o n ( 8 4 0 . 0 2 n o i t p o z h m 2 5 . 5 5 1 r o f 3 1 8 . gz h m 3 . 1 o t z h k 2 1i u p p 1 . 0 = ) 4 e t o n ( 3 5 0 . 0 ) 5 e t o n ( 3 5 0 . 0 ) 6 e t o n ( 8 5 0 . 0 ) 7 e t o n ( 3 5 0 . 0 ) 2 e t o n ( 3 5 0 . 0 ) 3 e t o n ( 8 5 0 . 0 ) 8 e t o n ( 7 5 0 . 0 ) 9 e t o n ( 5 5 0 . 0 ) 0 1 e t o n ( 7 5 0 . 0 ) 1 1 e t o n ( 7 5 0 . 0 ) 2 1 e t o n ( 7 5 0 . 0 ) 3 1 e t o n ( 3 5 0 . 0 z h m 8 4 0 . 2 r o f 2 1 8 . g & 3 1 8 . g 1 n o i t p o z h k 0 0 1 o t z h 0 2i u p p 5 0 . 0 =) 4 1 e t o n ( 6 4 0 . 0 n o i t i n i f e d t s e td e s u r e t l i fc e p s i u 0 1 5 8 s c a n o t n e m e r u s a e m i u 2 v e r z h m 4 4 5 . 1 r o f 2 1 8 . gz h k 0 4 o t z h 0 1i u p p 5 0 . 0 =) 4 1 e t o n ( 6 3 0 . 0 l a c i r t c e l e z h m 2 5 . 5 5 1 r o f 2 1 8 . gz h m 3 . 1 o t z h 0 0 5i u p p 5 . 0 =) 5 1 e t o n ( 8 5 0 . 0 l a c i r t c e l e z h m 8 4 0 . 2 r o f 2 1 8 . gz h m 3 . 1 o t z h k 5 6 i u p p = 5 7 0 . 0 ) 5 1 e t o n ( 8 4 0 . 0
www.semtech.com 58 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. n o i t i n i f e d t s e td e s u r e t l i fc e p s i u 0 1 5 8 s c a n o t n e m e r u s a e m i u 2 v e r z h m 8 4 0 . 2 r o f 3 - 2 6 4 - 0 0 3 - s t e c e s z h k 0 0 1 o t z h 0 2i u p p 5 . 0 =) 4 1 e t o n ( 6 4 0 . 0 z h m 8 4 0 . 2 r o f 3 - 2 6 4 - 0 0 3 - s t e c e s ) z h k 0 0 1 o t z h 9 4 c e p s r e t l i f ( z h k 0 0 1 o t z h 0 2i u p p 2 . 0 =) 4 1 e t o n ( 6 4 0 . 0 z h m 8 4 0 . 2 r o f 3 - 2 6 4 - 0 0 3 - s t e u s s z h k 0 0 1 o t z h 0 2i u p p 5 0 . 0 =) 4 1 e t o n ( 6 4 0 . 0 z h m 2 5 . 5 5 1 r o f 3 - 2 6 4 - 0 0 3 - s t ez h m 3 . 1 o t z h 0 0 5i u p p 5 . 0 =) 5 1 e t o n ( 8 5 0 . 0 z h m 2 5 . 5 5 1 r o f 3 - 2 6 4 - 0 0 3 - s t ez h m 3 . 1 o t z h k 5 6i u p p 1 . 0 =) 5 1 e t o n ( 8 4 0 . 0 n o i t i n i f e d t s e td e s u r e t l i fc e p s i u 0 1 5 8 s c a n o t n e m e r u s a e m i u 2 v e r 4 8 . 1 5 , f / i t e n e r o c - 3 5 2 - r g z h m z h k 0 0 4 o t z h 0 0 1i u p p 5 . 1 =) 5 1 e t o n ( 2 2 0 . 0 4 8 . 1 5 , f / i t e n e r o c - 3 5 2 - r g z h m ) z h k 0 0 4 o t z h k 0 2 c e p s r e t l i f ( z h k 0 0 4 o t z h k 8 1i u p p 5 1 . 0 =) 5 1 e t o n ( 9 1 0 . 0 2 5 . 5 5 1 , f / i t e n e r o c - 3 5 2 - r g z h m z h m 3 . 1 o t z h 0 0 5i u p p 5 . 1 =) 5 1 e t o n ( 8 5 0 . 0 2 5 . 5 5 1 , f / i t e n e r o c - 3 5 2 - r g z h m z h m 3 . 1 o t z h k 5 6i u p p 5 1 . 0 =) 5 1 e t o n ( 8 4 0 . 0 , f / i t c e l e i i t a c e r o c - 3 5 2 - r g z h m 2 5 . 5 5 1 z h k 0 0 4 o t z h k 2 1 i u p p 1 . 0 =) 5 1 e t o n ( 7 5 0 . 0 i u s m r 1 0 . 0 =) 5 1 e t o n ( 6 0 0 . 0 , f / i t c e l e i i t a c e r o c - 3 5 2 - r g z h m 4 8 . 1 5 z h m 3 . 1 o t z h k 2 1 i u p p 1 . 0 =) 5 1 e t o n ( 7 1 0 . 0 i u s m r 1 0 . 0 =) 5 1 e t o n ( 3 0 0 . 0 4 4 5 . 1 , f / i 1 s d e r o c - 3 5 2 - r g z h m z h k 0 4 o t z h 0 1 i u p p 1 . 0 =) 4 1 e t o n ( 6 3 0 . 0 i u s m r 1 0 . 0 =) 4 1 e t o n ( 5 5 0 0 . 0 table 25. dc characteristics: output jitter generation (test definition ets-300-462-3) across all operating conditions, unless otherwise stated output jitter generation measured over 60 seconds interval, ui pp max measured using vectron 6664 12.8 mhz tcxo on ict flexacom + 10 mhz reference from wavetek 905. table 26. dc characteristics: output jitter generation (test definition gr-253-core) across all operating conditions, unless otherwise stated output jitter generation measured over 60 seconds interval, ui pp max measured using vectron 6664 12.8 mhz tcxo on ict flexacom + 10 mhz reference from wavetek 905.
www.semtech.com 59 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. n o i t i n i f e d t s e td e s u r e t l i fc e p s i u 0 1 5 8 s c a n o t n e m e r u s a e m i u 2 v e r z h m 4 4 5 . 1 r o f 1 1 4 2 6 t & t a ) z h k 8 o t z h 0 1 c e p s r e t l i f ( z h k 0 4 o t z h 0 1i u s m r 2 0 . 0 =) 4 1 e t o n ( 5 5 0 0 . 0 z h m 4 4 5 . 1 r o f 1 1 4 2 6 t & t az h k 0 4 o t z h 0 1 i u s m r = 5 2 0 . 0 ) 4 1 e t o n ( 5 5 0 0 . 0 z h m 4 4 5 . 1 r o f 1 1 4 2 6 t & t az h k 0 4 o t z h 0 1 i u s m r = 5 2 0 . 0 ) 4 1 e t o n ( 5 5 0 0 . 0 z h m 4 4 5 . 1 r o f 1 1 4 2 6 t & t ad n a b d a o r bi u s m r 5 0 . 0 =) 4 1 e t o n ( 5 5 0 0 . 0 n o i t i n i f e d t s e td e s u r e t l i fc e p s i u 0 1 5 8 s c a n o t n e m e r u s a e m i u 2 v e r r o f 4 2 8 g & 9 9 4 0 0 0 - t w n - r t z h m 4 4 5 . 1 z h k 0 4 o t z h 0 1i u p p 0 . 5 =) 4 1 e t o n ( 6 3 0 . 0 r o f 4 2 8 g & 9 9 4 0 0 0 - t w n - r t z h m 4 4 5 . 1 ) z h k 0 4 o t z h k 8 c e p s r e t l i f ( z h k 0 4 o t z h 0 1i u p p 1 . 0 =) 4 1 e t o n ( 6 3 0 . 0 table 27. dc characteristics: output jitter generation (test definition at&t 62411) across all operating conditions, unless otherwise stated output jitter generation measured over 60 seconds interval, ui pp max measured using vectron 6664 12.8 mhz tcxo on ict flexacom + 10 mhz reference from wavetek 905. table 28. dc characteristics: output jitter generation (test definition g.742) across all operating conditions, unless otherwise stated output jitter generation measured over 60 seconds interval, ui pp max measured using vectron 6664 12.8 mhz tcxo on ict flexacom + 10 mhz reference from wavetek 905. table 29. dc characteristics: output jitter generation (test definition tr-nwt-000499) across all operating conditions, unless otherwise stated output jitter generation measured over 60 seconds interval, ui pp max measured using vectron 6664 12.8 mhz tcxo on ict flexacom + 10 mhz reference from wavetek 905. n o i t i n i f e d t s e td e s u r e t l i fc e p s i u 0 1 5 8 s c a n o t n e m e r u s a e m i u 2 v e r z h m 8 4 0 . 2 r o f 2 4 7 . gz h k 0 0 1 o t c di u p p 5 2 . 0 =) 4 1 e t o n ( 7 4 0 . 0 z h m 8 4 0 . 2 r o f 2 4 7 . g ) z h k 0 0 1 o t z h k 8 1 c e p s r e t l i f ( z h k 0 0 1 o t z h 0 2i u p p 5 0 . 0 =) 4 1 e t o n ( 6 4 0 . 0 z h m 8 4 0 . 2 r o f 2 4 7 . gz h k 0 0 1 o t z h 0 2i u p p 5 0 . 0 =) 4 1 e t o n ( 6 4 0 . 0
www.semtech.com 60 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. notes for tables 23 - 30 note 1. filter used is that defined by test definition unless otherwise stated note 2. 5 hz bandwidth, 19.44 mhz direct lock note 3. 5 hz bandwidth, 8 khz lock note 4. 20 hz bandwidth, 19.44 mhz direct lock note 5. 20 hz bandwidth, 8 khz lock note 6. 10 hz bandwidth, 19.44 mhz direct lock note 7. 10 hz bandwidth, 8 khz lock note 8. 2.5 hz bandwidth, 19.44 mhz direct lock note 9. 2.5 hz bandwidth, 8 khz lock note 10. 1.2 hz bandwidth, 19.44 mhz direct lock note 11. 1.2 hz bandwidth, 8 khz lock note 12. 0.6 hz bandwidth, 19.44 mhz direct lock note 13. 0.6 hz bandwidth, 8 khz lock note 14. 5 hz bandwidth, 8 khz lock, 2.048 mhz input note 15. 5 hz bandwidth, 8 khz lock, 19.44 mhz input n o i t i n i f e d t s e td e s u r e t l i fc e p s i u 0 1 5 8 s c a n o t n e m e r u s a e m i u 2 v e r z h m 4 4 5 . 1 r o f e r o c - 4 4 2 1 - r gz h 0 1 >i u p p 5 0 . 0 =) 4 1 e t o n ( 6 3 0 . 0 output jitter generation measured over 60 seconds interval, ui pp max measured using vectron 6664 12.8 mhz tcxo on ict flexacom + 10 mhz reference from wavetek 905. table 30. dc characteristics: output jitter generation (test definition gr-1244-core) across all operating conditions, unless otherwise stated
www.semtech.com 61 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. t sur t ht t dod t cyc tck tms tdo tdi r e t e m a r a p l o b m y s n i m p y t x a m s t i n u e m i t e l c y ct c y c 0 5--s n e g d e g n i s i r k c t o t i d t / s m t e m i t t r u s 3- -s n d l o h i d t / s m t o t g n i s i r k c t e m i t t t h 3 2--s n d i l a v o d t o t g n i l l a f k c tt d o d --5s n table 31. jtag timing (for use with figure 17) figure 17. jtag timing
www.semtech.com 62 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. 0xowlsohvkdyhwkh ( ?qv 0+] ?qv wrqv wrqv wrqv wrqv wrqv wrqv 0+] 0+] 0+] 0+] 0+] 0+] 0+] iruwklvrxwsxw $gglwlrqdoghod\ vdphriivhw wrqv wrqv ?qv $oljqphqw 3kdvh 7 n+] n+] 2xwsxw vdphriivhw 0xowlsohvkdyhwkh n+]lqsxw n+]rxwsxw 0+]lqsxw 0+]rxwsxw 0+]lqsxw 0+]rxwsxw 0+]lqsxw 0+]rxwsxw 0+]lqsxw 0+]rxwsxw 0+]lqsxw 0+]rxwsxw 0+]lqsxw 0+]rxwsxw ,qsxw2xwsxw 'hod\ ?qv wrqv wrqv wrqv wrqv wrqv wrqv 7\slfdo 7\slfdo figure 18. input/output timing
www.semtech.com 63 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. motorola mode in motorola mode, the device is configured to interface with a microprocessor using a 680x0 type bus. the following figures show the timing diagrams of write and read accesses for this mode. address data z z z z x x x x t d1 t d2 t pw2 t h3 t d4 t d3 t su1 t h1 t su2 t h2 t pw1 csb wrb a ad rdy (dtack) note 1: timing with rdy. if rdy not used, t pw1 becomes 178 ns. microprocessor interface timing l o b m y s r e t e m a r a p n i m p y t x a m t 1 u s b s c o t d i l a v a p u t e s e g d e g n i l l a f 0s n- - t 2 u s b s c o t d i l a v b r w p u t e s e g d e g n i l l a f s n 0-- t 1 d b s c y a l e d e g d e g n i l l a f d i l a v d a o t--s n 7 7 1 t 2 d b s c y a l e d e g d e g n i l l a f k c a t d o t e g d e g n i s i r -- s n 3 1 t 3 d b s c y a l e d e g d e g n i s i r z - h g i h d a o t--s n 0 t 4 d b s c y a l e d e g d e g n i s i r z - h g i h y d r o t--s n 7 t 1 w p e m i t w o l b s c s n 5 8 4 ) 1 ( -- t 2 w p e m i t h g i h y d r s n 0 1 3- s n 2 7 4 t 1 h b s c r e t f a d i l a v a d l o h e g d e g n i s i r s n 0-- t 2 h b s c r e t f a h g i h b r w d l o h e g d e g n i s i r s n 0-- t 3 h y d r r e t f a w o l b s c d l o h e g d e g n i l l a f s n 0-- t p b s c ( s e s s e c c a e v i t u c e s n o c n e e w t e b e m i t e g d e g n i s i r b s c o t e g d e g n i l l a f )s n 0 2 3-- figure 19. read access timing in motorola mode table 32. read access timing in motorola mode (for use with figure 19)
www.semtech.com 64 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. note 1: timing with rdy. if rdy not used, t pw1 becomes 178 ns. address data z x x z x x x x t su3 t d2 t pw2 t h3 t d4 t h4 t su1 t h1 t su2 t h2 t pw1 csb wrb a ad rdy (dtack) l o b m y s r e t e m a r a p n i m p y t x a m t 1 u s b s c o t d i l a v a p u t e s e g d e g n i l l a f 0s n- - t 2 u s b s c o t d i l a v b r w p u t e s e g d e g n i l l a f s n 0-- t 3 u s b s c e r o f e b d i l a v d a p u t e s e g d e g n i s i r s n 3-- t 2 d b s c y a l e d e g d e g n i l l a f y d r o t e g d e g n i s i r -- s n 3 1 t 4 d b s c y a l e d e g d e g n i s i r z - h g i h y d r o t--s n 7 t 1 w p e m i t w o l b s c s n 5 8 4 ) 1 ( -- t 2 w p e m i t h g i h y d r s n 0 1 3- s n 2 7 4 t 1 h b s c r e t f a d i l a v a d l o h e g d e g n i s i r s n 3-- t 2 h b s c r e t f a w o l b r w d l o h e g d e g n i s i r s n 0-- t 3 h y d r r e t f a w o l b s c d l o h e g d e g n i l l a f s n 0-- t 4 h b s c r e t f a d i l a v d a d l o h e g d e g n i s i r s n 4 t p b s c ( s e s s e c c a e v i t u c e s n o c n e e w t e b e m i t e g d e g n i s i r b s c o t e g d e g n i l l a f )s n 0 2 3-- figure 20. write access timing in motorola mode table 33. write access timing in motorola mode (for use with figure 20)
www.semtech.com 65 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. intel mode in intel mode, the device is configured to interface with a microprocessor using a 80x86 type bus. the following figures show the timing diagrams of write and read accesses for this mode. note 1: timing with rdy. if rdy not used, t pw1 becomes 180 ns. address data z z z z t d1 t d2 t pw2 t h3 t d3 t d4 t su1 t h1 t su2 t h2 t pw1 csb wrb a ad rdy rdb t d5 l o b m y s r e t e m a r a p n i m p y t x a m t 1 u s b s c o t d i l a v a p u t e s e g d e g n i l l a f 0s n- - t 2 u s b s c p u t e s e g d e g n i l l a f b d r o t e g d e g n i l l a f s n 0-- t 1 d b d r y a l e d e g d e g n i l l a f d i l a v d a o t--s n 7 7 1 t 2 d b s c y a l e d e g d e g n i l l a f e v i t c a y d r o t--s n 3 1 t 3 d b d r y a l e d e g d e g n i l l a f y d r o t e g d e g n i l l a f -- s n 4 1 t 4 d b d r y a l e d e g d e g n i s i r z - h g i h d a o t--s n 0 1 t 5 d b s c y a l e d e g d e g n i s i r z - h g i h y d r o t s n 9 t 1 w p e m i t w o l b d r s n 6 8 4 ) 1 ( -- t 2 w p e m i t w o l y d r s n 0 1 3- s n 2 7 4 t 1 h b d r r e t f a d i l a v a d l o h e g d e g n i s i r s n 0-- t 2 h b d r r e t f a w o l b s c d l o h e g d e g n i s i r s n 0-- t 3 h y d r r e t f a w o l b d r d l o h e g d e g n i s i r s n 0-- t p b d r ( s e s s e c c a e v i t u c e s n o c n e e w t e b e m i t e g d e g n i s i r b d r o t e g d e g n i l l a f r o , b d r e g d e g n i s i r b r w o t e g d e g n i l l a f ) s n 0 2 3-- figure 21. read access timing in intel mode table 34. read access timing in intel mode (for use with figure 21)
www.semtech.com 66 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. note 1: timing with rdy. if rdy not used, t pw1 becomes 180 ns. note 2: timing if t h2 is greater than 170 ns, otherwise 5 ns after csb rising edge. address data z z t d2 t pw2 t h3 t d3 t h4 t su1 t h1 t su2 t h2 t pw1 csb wrb a ad rdy rdb t d5 su3 t l o b m y s r e t e m a r a p n i m p y t x a m t 1 u s b s c o t d i l a v a p u t e s e g d e g n i l l a f 0s n- - t 2 u s b s c p u t e s e g d e g n i l l a f b r w o t e g d e g n i l l a f s n 0-- t 3 u s b r w o t d i l a v d a p u t e s e g d e g n i s i r s n 3-- t 2 d b s c y a l e d e g d e g n i l l a f e v i t c a y d r o t--s n 3 1 t 3 d b r w y a l e d e g d e g n i l l a f y d r o t e g d e g n i l l a f -- s n 4 1 t 5 d b s c y a l e d e g d e g n i s i r z - h g i h y d r o t s n 9 t 1 w p e m i t w o l b r w s n 6 8 4 ) 1 ( -- t 2 w p e m i t w o l y d r s n 0 1 3- s n 2 7 4 t 1 h b r w r e t f a d i l a v a d l o h e g d e g n i s i r s n 0 7 1 ) 2 ( -- t 2 h b r w r e t f a w o l b s c d l o h e g d e g n i s i r s n 0-- t 3 h y d r r e t f a w o l b r w d l o h e g d e g n i s i r s n 0-- t 4 h b r w r e t f a d i l a v d a d l o h e g d e g n i s i r s n 4 t p b r w ( s e s s e c c a e v i t u c e s n o c n e e w t e b e m i t e g d e g n i s i r b r w o t e g d e g n i l l a f r o , b r w e g d e g n i s i r b d r o t e g d e g n i l l a f ) s n 0 2 3-- figure 22. write access timing in intel mode table 35. write access timing in intel mode (for use with figure 22)
www.semtech.com 67 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. multiplexed mode in multiplexed mode, the device is configured to interface with a microprocessor using a multiplexed address/ data bus. the following figures show the timing diagrams of write and read accesses for this mode. note 1: timing with rdy. if rdy not used, t pw1 becomes 180 ns. address data z z t d1 t d2 t pw2 t h3 t d3 t d4 t h1 t h2 t pw1 csb wrb ad rdy rdb t d5 ale pw3 t su1 t x x t p1 su2 t l o b m y s r e t e m a r a p n i m p y t x a m t 1 u s e l a o t d i l a v s s e r d d a d a p u t e s e g d e g n i l l a f s n 2-- t 2 u s b s c p u t e s e g d e g n i l l a f b d r o t e g d e g n i l l a f s n 0-- t 1 d b d r y a l e d e g d e g n i l l a f d i l a v a t a d d a o t--s n 7 7 1 t 2 d b s c y a l e d e g d e g n i l l a f e v i t c a y d r o t--s n 3 1 t 3 d b d r y a l e d e g d e g n i l l a f y d r o t e g d e g n i l l a f -- s n 5 1 t 4 d b d r y a l e d e g d e g n i s i r z - h g i h a t a d d a o t--s n 9 t 5 d b s c y a l e d e g d e g n i s i r z - h g i h y d r o t--s n 0 1 t 1 w p e m i t w o l b d r s n 7 8 4 ) 1 ( -- t 2 w p e m i t w o l y d r s n 0 1 3- s n 2 7 4 t 3 w p e m i t h g i h e l a s n 2 t 1 h e l a r e t f a d i l a v s s e r d d a d a d l o h e g d e g n i l l a f s n 3-- t 2 h b d r r e t f a w o l b s c d l o h e g d e g n i s i r s n 0-- t 3 h y d r r e t f a w o l b d r d l o h e g d e g n i s i r s n 0-- t 1 p e l a n e e w t e b e m i t e g d e g n i l l a f b d r d n a e g d e g n i l l a f s n 0-- t 2 p b d r ( s e s s e c c a e v i t u c e s n o c n e e w t e b e m i t e g d e g n i s i r e l a o t e g d e g n i s i r )s n 0 2 3-- table 36. read access timing in multiplexed mode (for use with figure 23) figure 23. read access timing in multiplexed mode
www.semtech.com 68 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. note 1: timing with rdy. if rdy not used, t pw1 becomes 180 ns. address data z z t su3 t d2 t pw 2 t h3 t d3 t h4 t h1 t h2 t pw1 csb wrb ad rdy rdb t d5 ale pw3 t su1 t x x t p1 su2 t l o b m y s r e t e m a r a p n i m p y t x a m t 1 u s e l a o t d i l a v s s e r d d a d a p u t e s e g d e g n i l l a f s n 2-- t 2 u s b s c p u t e s e g d e g n i l l a f b r w o t e g d e g n i l l a f s n 0-- t 3 u s b r w o t d i l a v a t a d d a p u t e s e g d e g n i s i r s n 3-- t 2 d b s c y a l e d e g d e g n i l l a f e v i t c a y d r o t--s n 3 1 t 3 d b r w y a l e d e g d e g n i l l a f y d r o t e g d e g n i l l a f -- s n 5 1 t 5 d b s c y a l e d e g d e g n i s i r z - h g i h y d r o t s n 9 t 1 w p e m i t w o l b r w s n 7 8 4 ) 1 ( -- t 2 w p e m i t w o l y d r s n 0 1 3- s n 2 7 4 t 3 w p e m i t h g i h e l a s n 2-- t 1 h e l a r e t f a d i l a v s s e r d d a d a d l o h e g d e g n i l l a f s n 3-- t 2 h b r w r e t f a w o l b s c d l o h e g d e g n i s i r s n 0-- t 3 h y d r r e t f a w o l b r w d l o h e g d e g n i s i r s n 0-- t 4 h b r w r e t f a d i l a v d l o h a t a d d a e g d e g n i s i r s n 4 t 1 p e l a n e e w t e b e m i t e g d e g n i l l a f b r w d n a e g d e g n i l l a f s n 0-- t 2 p b r w ( s e s s e c c a e v i t u c e s n o c n e e w t e b e m i t e g d e g n i s i r e l a o t e g d e g n i s i r )s n 0 2 3-- figure 24. write access timing in multiplexed mode table 37. write access timing in multiplexed mode (for use with figure 24)
www.semtech.com 69 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. serial mode in serial mode, the device is configured to interface with a serial microprocessor bus.the combined minimum high and low times for sclk define the maximum clock rate. for write access this is 2.77 mhz (360 ns). for read access the maximum sclk rate is slightly slower and is affected by the setting of clke, being either 2.0 mhz (500 ns) or 1 mhz (1 us). this mismatch in rates is caused by the sampling technique used to detect the end of the address field in read mode. it takes up to 3 cycles of an internal 6.40 mhz clock to start the read process following receipt of the final address bit. this is 468 ns. the read data is then decoded and clocked out onto sdo directly using sclk. with clke=1, the falling edge of sclk is used to clock out the sdo. with clke=0, the rising edge of sclk is used to clock out the sdo. a minimum period of 500 ns (468 capture plus 32 decode) is required between the final address bit and clocking it out onto sdo. this means that to guarantee the correct operation of the serial interface, with clke=0, sclk has a maximum clock rate of 2 mhz. with clke=1, sclk has a maximum clock rate of 1 mhz. sclk is not required to run between accesses (i.e., when csb = 1). the following figures show the timing diagrams for write and read access for this mode. figure 25. read access timing in serial mode f8525d_013readaccserial_01 s clk c s b clk e = 0 ; sd o da t a i s cl o c k ed out on th e ri s i ng ed g e of s clk clk e = 1 ; sd o da t a i s cl o c k ed out on th e f alli ng ed g e of s clk r /w out p ut not dri v e n , p u lled l o w by i nt er n al re s i sto r sd i sd o t su 2 t su 1 t h 1 t pw 1 t pw 2 _ a0 a1 a2 a3 a 4 a5 a 6 d0 d1 d2 d3 d 4 d5 d 6 d 7 t h 2 t d2 t d1 s clk c s b r /w out p ut not dri v e n , p u lled l o w by i nt er n al re s i sto r sd i sd o _ a0 a1 a2 a3 a 4 a5 a 6 d0 d1 d2 d3 d 4 d5 d 6 d 7 t h 2 t d2 t d1
www.semtech.com 70 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. l o b m y s r e t e m a r a p n i m p y t x a m t 1 u s k l c s o t d i l a v i d s p u t e s e g d e g n i s i r 0s n- - t 2 u s b s c p u t e s e g d e g n i l l a f k l c s o t e g d e g n i s i r s n 0 6 1-- t 1 d k l c s y a l e d e g d e g n i s i r k l c s ( e g d e g n i l l a f d i l a v o d s o t ) 1 = e k l c r o f--s n 7 1 t 2 d b s c y a l e d e g d e g n i s i r z - h g i h o d s o t--s n 0 1 t 1 w p e m i t w o l k l c s 0 = e k l c 1 = e k l c s n 0 5 2 s n 0 0 5 -- t 2 w p e m i t h g i h k l c s 0 = e k l c 1 = e k l c s n 0 5 2 s n 0 0 5 -- t 1 h k l c s r e t f a d i l a v i d s d l o h e g d e g n i s i r s n 0 7 1-- t 2 h k l c s r e t f a w o l b s c d l o h e g d e g n i s i r 0 = e k l c r o f , k l c s r e t f a w o l b s c d l o h e g d e g n i l l a f 1 = e k l c r o f , s n 5-- t p b s c ( s e s s e c c a e v i t u c e s n o c n e e w t e b e m i t e g d e g n i s i r b s c o t e g d e g n i l l a f )s n 0 6 1-- l o b m y s r e t e m a r a p n i m p y t x a m t 1 u s k l c s o t d i l a v i d s p u t e s e g d e g n i s i r 0s n- - t 2 u s b s c p u t e s e g d e g n i l l a f k l c s o t e g d e g n i s i r s n 0 6 1-- t 1 w p e m i t w o l k l c s s n 0 8 1-- t 2 w p e m i t h g i h k l c s s n 0 8 1-- t 1 h k l c s r e t f a d i l a v i d s d l o h e g d e g n i s i r s n 0 7 1-- t 2 h k l c s r e t f a w o l b s c d l o h e g d e g n i s i r s n 5-- t p b s c ( s e s s e c c a e v i t u c e s n o c n e e w t e b e m i t e g d e g n i s i r b s c o t e g d e g n i l l a f )s n 0 6 1-- table 38. read access timing in serial mode (for use with figure 25) figure 26. write access timing in serial mode table 39. write access timing in serial mode (for use with figure 26) ale=sclk cs b r/w output not driven, pulled low by internal resistor a (0) =s di a d(0) =s d o t su 2 t su 1 t h 1 t pw 1 t pw 2 _ a 0 a 1 a 2 a 3 a 4 a 5 a 6 t h 2 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 f8 11 0d _ 0 1 4 w rite a cc s erial _ 0 2
www.semtech.com 71 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. eprom mode in eprom mode, the acs8510 takes control of the bus as master, and reads the device set-up from an amd am27c64 type eprom at lowest speed (250ns), after device start-up (system reset). the eprom access state machine in the up interface sequences the accesses. further details can be found in the amd am27c64 data sheet. address data z z t acc csb (=oeb) a ad l o b m y s r e t e m a r a p n i m p y t x a m t c c a b s c y a l e d e g d e g n i l l a f d i l a v d a o t e g n a h c a r o--s n 0 2 9 figure 27. access timing in eprom mode table 40. access timing in eprom mode (for use with figure 27)
www.semtech.com 72 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. package information e d a a2 a1 b e b1 b c c1 l l1 an4 an3 an2 s an1 r2 section a-a section b-b aa seating plane 1 2 3 4 5 6 d1 e1 1 1 2 3 7 7 7 7 8 notes 1 2 3 4 5 6 7 8 r1 b b the top package body may be smaller than the bottom package body by as much as 0.15 mm. to be determined at seating plane. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. details of pin 1 identifier are optional but will be located within the zone indicated. exact shape of corners can vary. a1 is defined as the distance from the seating plane to the lowest point of the package body. these dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. shows plating. 1 2 3 figure 28. lqfp package
www.semtech.com 73 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. thermal conditions the device is rated for full temperature range when this package is used with a 4 layer or more pcb. copper coverage must exceed 50%. all pins must be soldered to the pcb. maximum operating temperature must be reduced when the device is used with a pcb with less than these requirements. p f q l 0 0 1 e g a k c a p s n o i s n e m i d m m n i e / d1 e / 1 da1 a2 ae 1 n a2 n a3 n a4 n a1 r2 rl 1 lsb1 bc1 c n i m0 4 . 15 0 . 05 3 . 1 1 1 1 1 0 08 0 . 08 0 . 05 4 . 00 2 . 07 1 . 07 1 . 09 0 . 09 0 . 0 m o n0 0 . 6 10 0 . 4 10 5 . 10 1 . 00 4 . 10 5 . 0 2 1 2 1- 5 . 3-- 0 6 . 0 0 0 . 1 ) f e r ( -2 2 . 00 2 . 0-- x a m0 6 . 15 1 . 05 4 . 1 3 1 3 1- 7- 0 2 . 05 7 . 0-7 2 . 03 2 . 00 2 . 06 1 . 0 width 0.3 mm pitch 0.5 mm 14.6 mm 17.0 mm (1) 18.3 mm 1.85 mm notes (1) solderable to this limit. square package - dimensions apply in both x and y directions. typical example. the user is reponsible for ensuring compatibility with pcb manufacturing process, etc. figure 29. typical 100 pin lqfp footprint table 41. 100 pin lqfp package dimension data (for use with figure 28)
www.semtech.com 74 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. application information figure 30. simplified application schematic
www.semtech.com 75 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. revision history table 42. changes from revision 1.05 to 1.06 october 2002 m e t in o i t c e se g a pn o i t p i r c s e d 1e d o m l a i r e s9 6k l c s f o n o i t p i r c s e d d e t a d p u
www.semtech.com 76 acs8510 rev2.1 sets advanced communications final revision 1.06/october 2002 ? semtech corp. ordering information iso9001 certified r e b m u n t r a p n o i t p i r c s e d 1 . 2 v e r 0 1 5 8 s c a p f q l n i p 0 0 1 , n o i t a s i n o r h c n y s h d s / t e n o s for additional information, contact the following: semtech corporation advanced communications products e-mail: sales@semtech.com acsupport@semtech.com internet: http://www.semtech.com usa: mailing address: p.o. box 6097, camarillo, ca 93011-6097 street address: 200 flynn road, camarillo, ca 93012-8790 tel: +1 805 498 2111, fax: +1 805 498 3804 far east: 11f, no. 46, lane 11, kuang fu north road, taipei, taiwan, r.o.c. tel: +886 2 2748 3380, fax: +886 2 2748 3390 europe: units 2 & 3 park court, premier way, abbey park industrial estate, romsey, hampshire, so51 9dn, uk tel: +44 1794 527 600, fax: +44 1794 527 601 disclaimers life support - this product is not designed or intended for use in life suport equipment, devices or systems, or other critical applications. this product is not authorized or warranted by semtech corporation for such use. right to change - semtech corporation reserves the right to make changes, without notice, to this product. customers are advised to obtain the latest version of the relevant information before placing orders. compliance to relevant standards - operation of this device is subject to the user?s implementation, and design practices. the user is responsible to ensure equipment using this device is compliant to any relevant standards.

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