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1/20 march 2002 AN1428 application note interfacing the psd813f5 with the ti tms320c203 dsp contents n purpose n psd813f1 architecture n development systems n programming the psd813f in-circuit using the jtag interface n interfacing the psd813f5 with thetms320c203 C psd813f5 bus interface C tms320c203 bus inter- face timing calculation C tms320c203 memory map C interfacing to thetms320c203 exter- nal memory bus C define the tms320c203 interface in psdsoft ex- press define psd and mcu utility C define the psd813f1 dpld functions in psd- soft express edit/add logic statements C accessing the psd813f5 internal reg- isters C external boot flash memory format n in-application re- programming (iap) using the psd813f5 n tms320c203 boot loader n summary n appendix the digital signal processing marketplace is typically divided into two specific areas: function and algorithm specific ics.are non-programmable dsps integrated with other peripherals. they consist of modem chips, dvds, mpeg and video decoders, etc. general purpose programmable dsps .are flexible dsps that are used in a broad spectrum of products. they typically use a microcontroller for control, as well as additional i/o and programmable logic. most general purpose dsps have internal 8-bit boot load rou- tines imbedded in rom which take advantage of slower, less expensive external flash memory and eproms to store non- volatile program code to upload to fast internal sram at reset. purpose although the flash psd8xx family has become an ideal pe- ripheral for 8-bit microcontrollers, many companies using the psd in dsp-based products have shown that it makes an ex- cellent peripheral for dsps. the psd8xx provides program- mable logic and the required bus interfacing to implement a clean two-chip solution. the psd jtag port allows in-system programming (isp) of a completely blank psd8xx device soldered to the board with no involvement of the dsp, which is ideal for first time program- ming during manufacturing. the psd8xx also offers in appli- cation re-programming (iap), in which the dsp participates by executing uart download code from the small flash memory in the psd while writing new code into the large flash memory in the psd. this unique concurrent operation of psd memories offers many iap options. after iap is complete, the dsp can copy the contents of the psd main flash memory into the fast dsp sram for full speed operation. this application note addresses the ease of interfacing the psd8xxf with the tms320c203 dsp. familiarity with the psd8xxf is assumed. please reference psd813f data sheet for a detailed description of the device. the c203 dsp is optimized for telemetry and consumer applications, including pos terminals, pbx systems and smart card readers. the psd8xxf family of zero power parts meets these criteria and enables the core dsp design to be done with two chips.
AN1428 - application note 2/20 psd813f1 architecture the psd8xx family is complemented by a lower-cost psd9xx family. figure 1 is a block diagram of the psd8xx and psd9xxf. table 1 shows a comparison of the functional differences in the memory and cpld options. on-chip features supply the key elements to implement a two-chip dsp system. some de- vices have 32k bytes of byte-erasable eeprom that may be used in place of external sram in some designs. flash psd features include: n programmable bus interface to dsps that are capable of accessing external 8-bit boot code and/or program code. n programmable bus interface to dsps with external 8-bit boot code and/or program code. n 128-256 kbytes of main flash memory, divided into eight equal individually protected sectors. n separate 32 kbytes eeprom or flash boot memory divided into four equal blocks. n concurrent programming of the flash or eeprom/boot flash memories allows execution from one memory while reprogramming the other. n 2 kbytes or 8 kbytes scratch-pad sram. n two flash-based plds with 16 output micro ? cells and 24 input micro ? cells. n 27 individually configurable i/o port pins. each may be defined as dsp i/os, pld i/os, latched dsp address outputs or special function i/os. n 8-bit page register to expand the address space by a factor of 256. n jtag compliant serial port for true in-system programming (isp) of blank devices and reprogramming of devices in the factory or field. table 1. psd8xxf and psd9xx product matrix the c203 has a basic on-chip boot loader, but only 544 words on-chip daram. program code is down- loaded from external flash memory to fast external sram for execution after system reset. the low-cost psd813f5 (no secondary boot memory) is selected for this design to take advantage of the tms320c203 resident boot loader. the following design parameters are assumed for using the psd813f5 without the flash boot memory: 1. the initial firmware is programmed into the psd flash memory through the jtag interface on port c of the psd during manufacturing. device flash main memory kbit (8 sectors) additional memory for boot and/or data (4 sectors) sram kbit pld psd813f1 1024 256 kbit eeprom 16 sequential psd813f2 1024 256 kbit flash 16 sequential psd813f3 1024 none 16 sequential psd813f4 1024 256 kbit flash none sequential psd813f5 1024 none none sequential psd833f2 1024 256 kbit flash 64 sequential psd834f2 2048 256 kbit flash 64 sequential psd913f2 1024 256 kbit flash 16 combinatorial psd934f2 2048 256 kbit flash 64 combinatorial
3/20 AN1428 - application note 2. the firmware, containing the c203 serial port control code to download future code updates into the psd813f5 flash memory, is downloaded to the dsp daram during the boot operation after power on reset is over. 3. the psd813f5 page register is used to expand external local memory beyond 64 k words. development systems the psd family is supported by psdsoft express, a software development tool that runs on windows 95 and 98 and windows nt. this tool has point and click features for dsp bus interface configuration, and uses an hdl (psdabel) to define general programmable logic within the pld. dsp firmware is imported and merged to create a single object file to program into the psd. psdsoft express supports two device programmers directly (st psdpro, st flashlink). the generated object file is also compatible with third- party programmers. see web site for list (www.st.com/psm). st offers two low-cost device programmers: psdpro .plugs into a pc/laptop parallel port and replaces the st magicpro iii. flashlink .is a low cost cable that plugs into a pc/laptop parallel port to support jtag-isp program- ming. flashlink is controlled by psdsoft and supports device chaining of multiple psds and devices from other manufacturers. programming the psd813f in-circuit using the jtag interface the ability to initially program a new system board with a blank flash memory soldered directly to it has solved many manufacturing logistics problems C no sockets or individual labels are required; inventory of non-volatile program memory chips is reduced to one package; the pld is programmed at the same time as the memory chip. one system board can be built and inventoried. any options can be programmed into the flash memory at board level testing. port c i/o lines are used to interface to the standard jtag signals C tms, tck, tdi and tdo. tstat and terr are optional jtag-isp extensions that can be monitored to speed up decrease the program- ming time of the psd813f. the psd configuration, pld logic, flash memory and optional flash boot/ eeprom can be programmed simultaneously through this interface. port c also gives the option to multiplex its jtag pins with the psd813f general i/o lines. this option, if used, frees up the jtag pins for i/o functions after jtag programming is completed. this option is en- abled by the following three lines of code in psdabel, and its hardware implementation is illustrated in ap- plication note 054 jtag information C psd813f: jen pin 11; port c pin pc7 is used as external jtag multiplex enable jtagsel node; selects jtag port active using internal product term jtagsel = !jen; switches port c between jtag and i/o
AN1428 - application note 4/20 figure 1. psd8xx/psd9xx block diagrams mcu addr/data mcu control page reg decode pld gpld 19 combinatorial logic outputs 128k byte main flash 8 segments 32k byte secondary flash 4 segments 2k byte sram i/o port a i/o port b i/o port c i/o port d power mngt device security jtag-isc controller mcu addr/data/cntl bus pld bus i/o bus psd913f2 mcu addr/data mcu control page reg decode pld cpld 16 macro cells 3 combinatorial 128k byte main flash 8 segments eeprom 2k byte sram i/o port a i/o port b i/o port c i/o port d power mngt device security jtag-isc controller mcu addr/data/cntl bus pld bus i/o bus psd813f1 ai06502
5/20 AN1428 - application note interfacing the psd813f5 with thetms320c203 figure 2 is a block diagram that shows the implementation of a three-chip system, including external sram to execute program code, using the psd813f5 and the c203. all glue logic, flash memory, bus interface logic, i/o, chip selects and plds are contained in one chip. figure 2. block diagram C minimized dsp system tms320c203 sram 128k x 16 a0-a15 d0-d15 d0-d7 d0 - d15 psd813f port a port b port c port d i/o port a0 - a15 /mstrb r/ w r/ w /ds /ds /iostrb sram 64k x 16 -1 - port a port b port c port d jtag /mstrb r/ w /ds /iostrb & control lines d15-d0 a15-a0 control ad15-ad0 cntl[2..0] & pb7-pb6 ai06503
AN1428 - application note 6/20 psd813f5 bus interface the psd813f5 has a user-friendly programmable bus interface that is quickly configured to interface di- rectly to most general purpose dsps with no glue logic. table 2 lists the bus interface signals from the c203 used to access the flash memory, pld logic and i/o inside the psd813f5. these bus signals are also used to access the eeprom/flash boot memory and sram inside the psd813f, if these options are desired. table 2. tms320c203 bus interface pin functions tms320c203 bus interface timing calculation the tms320c203 has a programmable wait-state generator that generates between 0 and 7 separate wait states for program, data and i/o accesses. to enable the tms320c203 to interface to slow memory after reset, all wait state generators are reset to 7 wait-states. figure 3 shows the read/write timing differ- ences between the tms320c203-40 mhz and psd813f5-90ns. three wait states would have to be pro- grammed to access the flash memory in the psd813f5 during normal program execution. tms320c203 pin functions psd813f5 pin functions pin description a15 C a0 ad15 C ad0 external address bus addresses up to 64 kwords of external memory or i/o space d15 C d8 d7 C d0 nc porta pa7 C pa0 16 bi-directional external data bus lines d7 C d0 connect to porta (used as 8-bit data bus in non-multiplexed applications) /br cntl2 bus request pin. when active, /br accesses global boot flash memory resident in the psd813f5 /ds portb pb7 data memory select. when active, /ds access external data memory C local or global /ps nc program memory select. when active /ps accesses external program memory in sram /is portb pb6 i/o space select. when active, /is accesses external i/o space /rd cntl1 active low read select requests a read from external program, data or i/o space /we cntl0 active low write select requests a write to external program, data or i/o space
7/20 AN1428 - application note figure 3. tms320c203 read / write memory timing clkout1 a0-a15 /br, /ds /is, /ps /we do0-do15 /rd do0-do15 t c(co) = 50 t d(co-a) = 8 1 5 t w(nsn) t slw 18 20 t su(a) t avw l t w(wl) = 35-50 t wlwh = 35 t su(d)w = 48 t dvwh = 35 t h(d) = 21-32 t whdh = 5 t rlrh = 32 t w(rdh) = 21 1 58 t su(a)rd t a(rd) = 31 t avqv = 90 t h(d)rd = -2 t rhqx = 0 note: the timing values are referenced as: tms320c203-40 mhz psd813f5-90 ns ai06504
AN1428 - application note 8/20 tms320c203 memory map the tms320c203 has four separate address spaces which can access a maximum of 224k x 16-bit ex- ternal memory space C 64k program, 64k data, 64k i/o and 32k global. in addition, there are 544 words of internal daram divided into three blocks C 256 words in data or program memory (b0), 256 words in data memory (b1), and 32 words in data memory (b2). the memory map is illustrated in figure 4. their respective select signals are also shown. at reset, the on-chip boot loader boots software from an 8-bit external eprom/flash, located in external global data memory, to 16-bit external fast sram located in program memory space. figure 4. tms320c203 memory map external local memory i/o memory program memory ffff ffff ffff /br ff00 and/or feff /ds 8000 7fff /is /ps /ds 0800 07ff daram 0000 0000 0000 boot = 0 cnf = 0 microprocess or mode off-chip memory access local and/or global memory local data memory daram & res. reserved for internal functions external i/o and peripherals external fast sram ai06505
9/20 AN1428 - application note interfacing to thetms320c203 external memory bus the block diagram of figure 5 shows the bus interface between the tms320c203 and the psd813f5. the tms320c5203 has 16 address lines and 16 data lines. the psd813f5 internal page register is used to configure the flash memory into multiple pages. paging will increase the program space that is normally accessible to the c203, if system requirements necessitate this. figure 5. block diagram C adsp-21061 system block diagram tms320c203 sram 128k x 16 a0-a15 d0-d15 d0-d7 d0-d15 psd813f port a port b port c port d i/o port a0 - a15 /mstrb r/ w r/ w /ds /ds /iostrb d0-d15 d0-d7 d0-d15 port a port b port c port d jtag /mstrb r/ w /ds /iostrb & sram 64k x 16 /rd /we /br /we /cs /ps /ds /is d15-d0 a15-a0 ad15-ad0 cntl1 - /rd cntl0 - /wr cntl2 - /br ai06506
AN1428 - application note 10/20 define the tms320c203 interface in psdsoft express define psd and mcu utility figure 6 is the mcu and psd selection screen from the psdsoft express development software. for more information on the psdsoft express, see the on-line user manual on the st website listed on the back page. selecting the following appropriate signals in this screen quickly configures the bus configura- tion between the tms320c203 and psd813f5. /ds and /is are connected to the psd813f5 dpld through port b (pins pd6 and pd7) and included in the internal chip select equations generated in the chip select equations screen. n type: other n data bus width: 8-bit n address / data mode: non-mux n control setting: /rd, /we figure 6. psdsoft express define psd and mcu figure 7 is the schematic diagram of the tms320c203 / psd813f5 bus interface. the 128k bytes of psd813f5 flash program memory reside in external global memory space and are divided into four pag- es. it is downloaded to external sram for program execution during booting. executing the program code from sram allows updated program code to be uploaded to the flash program memory through the dsp serial port for future download to the daram for program execution.
11/20 AN1428 - application note figure 7. schematic diagram C tms320c203 to psd813f5 bus interface d6 d2 d4 d5 d1 d5 d1 d0 d3 d7 d6 d7 d2 d0 d3 d4 d10 d15 d14 d12 d11 d9 d13 tms320c203_pz 22 23 24 26 27 28 29 31 32 33 34 36 38 39 40 41 55 56 57 58 60 61 62 64 66 67 68 69 71 72 73 74 53 51 52 49 47 45 44 46 43 6 98 99 96 97 8 9 100 1 2 17 18 19 20 92 15 12 13 3 5 10 87 84 85 89 86 90 93 95 79 78 81 80 82 76 77 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 ps ds is ready r/w rd we strb br holda xf bio io0 io1 io2 io3 rs test boot nmi hold/int1 int2 int3 tout clkout1 clkin/x2 x1 div1 div2 pll5v clkx clkr fsr fsx dr dx tx rx trst tck tms tdi tdo emu0 emu1/off u3 k6r1008c1b 1 2 3 4 13 14 15 16 17 18 19 21 20 29 30 31 32 5 28 12 6 7 10 11 22 23 26 27 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a12 a11 a13 a14 a15 a16 cs oe we i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 1 2 3 4 u4 k6r1008c1b 1 2 3 4 13 14 15 16 17 18 19 21 20 29 30 31 32 5 28 12 6 7 10 11 22 23 26 27 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a12 a11 a13 a14 a15 a16 cs oe we i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 u2 psd813f5 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 46 20 19 18 17 14 13 12 11 47 50 49 10 9 8 48 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 adio15 pco/tms pc1/tck vstby pc3/tstat pc4/terr pc5/tdi pc6/tdo pc7/bhe cntl0-r/w,wr cntl1-e,rd,ds cntl2-psen pd0-as-ale pd1-clkin pd2-csi reset /reset pco/tms pc1/tck pc5/tdi pc6/tdo dsp interrupt u1 jtag port c pins rdy / bsy signal (optional) ai06508
AN1428 - application note 12/20 define the psd813f1 dpld functions in psdsoft express edit/add logic statements figure 8 is the system memory map created for this a/n. the data, i/o and program addresses are defined in the psdsoft express edit/add logic statements screen and implemented in the internal psd813f5 de- coding pld (dpld). three bits of the psd813f5 page register are used to extend the external data ad- dress range beyond the 64k limitation of the tms320c203. the 128k bytes in the psd813f5 are divided into four pages and reside in global memory space. extending the dsp address range for program mem- ory increases the value of the psd813f5 for this application. since paging is used, an area in data mem- ory containing routines common to all data memory pages C memory-mapped registers, daram, i/o and external peripheral C must be accessible independent of which page the dsp is addressing. the following dsp control bits are set to implement the system memory map in figure 8: 1. cnf (bit 12 of status register 1) = 0.daram b0 is mapped to data space and is accessible at data addresses 0200h-02ffh. this increases the addressable external program memory by 512 words. 2. greg (global memory allocation register) = xx80h.this value in the greg sets the address range of the external local data memory to 0000h-7ffffh and the address range of the external global memory to 800h-ffffh. important: when the boot loader accesses global memory, both /br and /ds are driven low. the system memory interface must be designed to prevent /ds from initiating erroneous accesses to data memory during boot loading. disabling /ds from accessing external global memory during boot loading is easily accomplished in the dpld of the psd813f5. internal dpld flash memory chip selects fs0Cfs7 are used to select the 128k bytes of flash memory in global memory space (4 pages C 32k bytes per page). the following typical dpld chip select equation illustrates how this is done: fs0 = ((address >= ^h8000) & (address <= ^hbfff) & (page == 0) & /br # ((address >= ^h8000) & (address <= ^hbfff) & (page == 0) & /ds & br; address locations h8000-hbfff are accessible as both global and local memory. when /br is access- ing global memory for boot loading, the inverse of /br disables /ds from accessing the shared memory space. when /ds is accessing global memory, /br is inactive. accessing the psd813f5 internal registers the bank of internal control registers in the psd813f5 (csiop + hxx) are 8-bits wide. the dsp data bus is 16-bits wide and accesses external memory locations on a word boundary. when an internal register in the psd813f5 is accessed, the dsp reads or writes a 16-bit word; only the lower 8 lines of the data bus are used to transfer data between the dsp and psd. when data is read from the internal registers, 16-bit data is read into the dsp accumulator. the high byte in the dsp accumulator is either ignored or masked out. when data is written to the internal registers, valid data must be located in the lower byte of the accumulator. the high byte is ignored by the psd813f5.
13/20 AN1428 - application note figure 8. tms320c203 system memory map in-application re-programming (iap) using the psd813f5 the psd813f5 (without secondary memory) was selected to reduce the system cost and take advantage of the dsp daram that can contain the program code for iap of psd flash memory through the dsp serial port. the asynchronous serial port on the tms320c203 is used for field updates to the program code that re- sides in one or more sectors of the psd813f5 flash memory; these sector s are located in bank 0 C bank 3 in external global data memory space. the three product terms of each of the eight internal flash mem- ory sector chip selects C fs0-fs7 C enable the control of the flash boot memory to switch between /br for downloading boot code, and /ds to field upgrade the flash program memory as though it were data mem- ory the tms320c203 transmit and receive data buffers of the asynchronous serial port are 16-bit buffers. an 8-bit word is stored in the lower eight bits of the 16-bit receive and transmit buffers. when a boot program update is received by the serial port, the 8-bit data in the receive data buffer is written to the accumulator to store either in an assigned section of the dsp daram allocated as a buffer for the uploaded program code, or write to the flash memory on a byte-by-byte basis. the byte-by byte write sequence to the flash memory can be speeded up dramatically by configuring the rdy/busy polling bit to port c (pin pc3) and using it as an interrupt input to the dsp. once a byte write command is issued, the time required to program the byte can now be executed in background mode. the dsp can be performing other tasks until the rdy/busy pin signals that the byte has been successfully programmed and generates an interrupt. the rdy/busy bit is hardware configured as an output interrupt pin as shown in figure 9 with the config- uration sequence as follows: 1. select pc3 from the psdsoft express pin definition screen. 2. select rdy/bsy output under other block. exter. interrupts page 0 fs0 & fs1 page1 fs2 & fs3 externa l program space page 2 fs4 & fs5 page 3 fs6 & fs7 external program sram 0000 003f 0400 ffff externa l data memory space i/o memo ry sp ace 0000 reserved psd813f5 csiop ffff ff00 feff fe00 fdff reserved & on-chip daram 0000 0f77 0800 7fff 8000 ffff local data memory note: if the eeprom/boot flash feature of the psd813f1 is required, it can be configured as page 4 at address h8000-hffff. 1000 psd813f5 sram (optional) ai06509
AN1428 - application note 14/20 figure 9. psdsoft express C pin definition screen
15/20 AN1428 - application note tms320c203 boot loader the tms320c203 has an on-chip boot loader that downloads program code from external 8-bit flash/ rom to external fast sram at reset. figure 10 shows how the 16-bit program code is programmed in ex- ternal flash. figure 10. flash memory boot loader store external boot flash memory format the boot code is stored in external global flash memory space in the following format: n destination.stores the 16-bit destination address of the external sram where the boot memory is to be downloaded. n length.stores the length of the boot program code to be downloaded to external sram. n word.stores the number of 16-bit program words, high byte first, indicated by the program length value. note: 1. the first four bytes are not included in the calculation of the length. the program downloaded from flash memory starts with the fifth byte. 2. the first four words of the program memory in the flash boot memory must contain code for the reset and interrupt vectors and must be stored in external sram first, at program memory addresses 000h-0003h. boot loader sequence the boot loader is enabled when the /boot pin is tied low and sampled only at reset. the wait state reg- ister defaults to seven wait states to access program and data spaces. the tms320c203 then branches to the location of the on-chip boot loader program and starts the following sequence of events: the boot loader loads the first two bytes from flash memory and uses this word as the destination address for the program code. 1. the boot loader loads the next two bytes to establish the code length. 8000 8001 8002 8003 8004 8005 8006 8007 nnne nnnf destination - high byte destination - low byte length n - high byte length n - low byte word1 - high byte word1 - low byte word2 - high byte word2 - low byte wordn - high byte wordn - low byte ai06511
AN1428 - application note 16/20 2. the boot loader transfers the next two bytes, combines the two bytes into one word, and stores the new program word in external sram at the address location pointed to by the destination address in flash boot memory. 3. the source and destination addresses are incremented, and the boot loader process checks and re- peats itself until the entire program has been downloaded to sram. 4. the boot loader disables the entire global memory and forces a branch to the reset vector at address 0000h in program memory. when boot loading is finished, tms320c203 switches the on-chip boot loader out of the memory map. summary as dsps continue to rapidly proliferate into markets such as communications, industrial, medical, signal conditioning, and hand held test equipment, the psd813f and dsp form an ideal 2-chip core with on-chip pld and 27 i/o lines that can be individually configured to perform any function required by the system design. using the psd813f as an 8-bit boot loader in both high speed and low speed systems is an ideal and rapid design alternative to a discrete solution. inexpensive slower memory and plds integrated in the psd813f now become both cost and performance effective. several features internal to the psd813f5 were used to expand the limitations of the tms320c203, and dsps in general: 1. flash memory allows iap update of the program code in the field through the serial port of the dsp while the dsp is running program code in the internal daram. 2. jtag-isp simplifies manufacturing. 3. expanded i/o was added to the system. 4. the internal flash pld allows design changes, in logic, i/o and memory mapping, to be made by soft- ware modifications instead of board level hardware changes. these changes have added to both the versatility and performance of the tms320c203; future changes most likely will not require a hardware change to the 2-chip core. appendix the appendix contains the psdsoft express design assistant summary listing all logic equations and showing how the psd813f5 is configured to implement the example in this application note. application note an1356 presents a step-by-step illustration of how to configure the flash psd family. although an1356 uses the 16-bit flash psd4235g2 in the example, the software and procedure is the same for the 8-bit psd813f5. *********************************************************************** psdsoft express version 6.02 summary of design assistant *********************************************************************** project : ti_c203 date : 09/22/2000 device : psd813f5 time : 10:33:19 mcu : *********************************************************************** pin definitions: ================ pin signal pin name name type
17/20 AN1428 - application note ------------ ------------ ------------ adio0 a0 address line adio1 a1 address line adio2 a2 address line adio3 a3 address line adio4 a4 address line adio5 a5 address line adio6 a6 address line adio7 a7 address line adio8 a8 address line adio9 a9 address line adio10 a10 address line adio11 a11 address line adio12 a12 address line adio13 a13 address line adio14 a14 address line adio15 a15 address line cntl0 _wr mcu bus control signal cntl2 _br logic or address cntl1 _rd mcu bus control signal reset _reset reset input pa0 d0 data line pa1 d1 data line pa2 d2 data line pa3 d3 data line pa4 d4 data line pa5 d5 data line pa6 d6 data line pa7 d7 data line pb6 _is logic or address pb7 _ds logic or address pc0 tms dedicated jtag - tms pc1 tck dedicated jtag - tck pc3 rdy_bsy_pin rdy/bsy output pc5 tdi dedicated jtag - tdi pc6 tdo dedicated jtag - tdo user defined nodes: =================== none defined page register settings: ======================= pgr0 is used for paging pgr1 is used for paging pgr2 is used for paging pgr3 is not used pgr4 is not used pgr5 is not used pgr6 is not used pgr7 is not used equations: ========== csiop = ((address >= ^hfe00) & (address <= ^hfeff) & (!_is)); fs0 = ((page == 0) & (address >= ^h8000) & (address <= ^hbf00) & (!_br))
AN1428 - application note 18/20 # ((page == 0) & (address >= ^h8000) & (address <= ^hbf00) & (!_ds & _br)); fs1 = ((page == 0) & (address >= ^hc000) & (address <= ^hff00) & (!_br)) # ((page == 0) & (address >= ^hc000) & (address <= ^hffff) & (!_ds & _br)); fs2 = ((page == 1) & (address >= ^h8000) & (address <= ^hbfff) & (!_br)) # ((page == 1) & (address >= ^h8000) & (address <= ^hbfff) & (!_ds & _br)); fs3 = ((page == 1) & (address >= ^hc000) & (address <= ^hffff) & (!_br)) # ((page == 1) & (address >= ^hc000) & (address <= ^hffff) & (!_ds & _br)); fs4 = ((page == 2) & (address >= ^h8000) & (address <= ^hbfff) & (!_br)) # ((page == 2) & (address >= ^h8000) & (address <= ^hbfff) & (!_ds & _br)); fs5 = ((page == 2) & (address >= ^hc000) & (address <= ^hffff) & (!_br)) # ((page == 2) & (address >= ^hc000) & (address <= ^hffff) & (!_ds & _br)); fs6 = ((page == 3) & (address >= ^h8000) & (address <= ^hbfff) & (!_br)) # ((page == 3) & (address >= ^h8000) & (address <= ^hbfff) & (!_ds & _br)); fs7 = ((page == 3) & (address >= ^hc000) & (address <= ^hffff) & (!_br)) # ((page == 3) & (address >= ^hc000) & (address <= ^hffff) & (!_ds & _br));
19/20 AN1428 - application note table 3. document revision history date rev. description of revision oct-2000 1.0 document written in the wsi format (an072) 01-mar-2002 2.0 document converted to the st format (AN1428)
AN1428 - application note 20/20 for current information on psd products, please consult our pages on the world wide web: www.st.com/psm if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses: apps.psd@st.com (for application support) ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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