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| software implementation of asynchronous serial i/o 3 ds00555b-page 1 ? 1994 microchip technology inc. AN555 software implementation of asynchronous serial i/o introduction the pic16cxx microcontrollers from microchip tech- nology, inc., are mid-range, high performance eprom based 8-bit microcontrollers. some of the members of this series (like pic16c71 and pic16c84) do not have an on-chip hardware asynchronous serial port. this application note describes the interrupt driven software implementation of asynchronous serial i/o (half duplex rs-232 communications) using pic16cxx microcontrollers. these microcontrollers can operate at very high speeds with a minimum of 250 ns cycle time (with input clock frequency of 16 mhz). to test the rs- 232 routines, a simple digital volt meter (dvm)/analog data acquisition systems has been implemented using pic16c71 in which upon reception of a command from host (ibm ? pc), an 8-bit value of the selected a/d channel is transmitted back to host. implementation a half duplex interrupt driven software implementation of rs-232 communications using pic16c71 is described in detail below. the transmit pin used in the example code is rb7 and receive pin is connected to rtcc/ra4 pin (see figure 2). of course these pins are connected with appropriate voltage translation to/from rs-232/ cmos levels. the voltage translation is given described with schematics in the hardware section of this applica- tion note. transmit mode the transmit mode in software is quite straight forward to implement using interrupts. once the input clock frequency and baud rate is known, the number of clock cycles per bit can be computed. the on-chip real time clock counter (rtcc) along with the prescaler can be used to generate interrupt on rtcc overflow. this rtcc overflow interrupt can be used as timing to send each bit. the input clock frequency (_clkin) and the baud rate (_baudrate) are programmable by the user and the rtcc time-out value (the period for each bit) is computed at assembly time. whether the prescaler must be assigned to rtcc or not is also determined at assembly time. this computation is done in the header file rs232.h. note that very high speed transmissions can be obtained if transmission is done with software delays instead of every interrupt driven, however, the processor will be totally dedicated to this job. transmission of a byte is performed by calling putchar function and the data byte in the txreg is transmitted out. before calling this function (putchar), the data must be loaded into txreg and also made sure that serial port is free. the serial port is free when both _txmtprogress and _rcvover bits are cleared (see de- scription of these bits in the serial status/control reg table given later ). summary of putchar function : 1) make sure _txmtprogress & _rcvover bits are cleared 2) load txreg with data to be transmitted 3) call putchar function receive mode the reception mode implementation is slightly different from the transmit mode. unlike the transmit pin (tx pin in the example code is rb7, but could be any i/o pin), the receive pin (rx pin) must be connected to rtcc/ra4 pin. this is because in reception, the start bit which is asynchronous in nature, must be detected. to detect the start bit, when put in reception mode, the rtcc module is configured to counter mode . the option register is configured so that rtcc module is put in counter mode (increment on external clock on rtcc/ra4 pin) and set to increment on falling edge on rtcc/ra4 pin with no prescaler assigned. after this configuration setup, rtcc (file reg 1) is loaded with 0xff. a falling edge on rtcc pin will make rtcc roll over from 0xff to 0x00, thus generating an interrupt indicating a start bit. the rtcc/ ra4 pin is sampled again to make sure the transition on rtcc is not a glitch. once the start bit has been detected, the rtcc module is reconfigured to increment on internal clock and the prescaler is as- signed to it depending on input master clock frequency and the baud rate (configured same way as the trans- mission mode). the software serial port is put in reception mode when a call is made to function getchar. before calling this function make sure serial port is free (i.e. _txmtprogress and _rcvover status bits must be 0). on completion of reception of a byte, the data is stored in rxreg and _rcvover bit is set to 0. summary of getchar function: 1) make sure _txmtprogress & _rcvover bits are cleared 2) call getchar function 3) the received byte is in txreg after _rcvover bit is cleared 3-181
software implementation of asynchronous serial i/o ? 1994 microchip technology inc. ds00555b-page 2 parity generation parity can be enabled at assembly time by setting _parity_enable flag to true. if enabled, the parity can be set to either even or odd parity. in transmission mode, if parity is enabled, the parity bit is computed and transmitted as the ninth bit. on reception, the parity is computed on the received byte and com- pared to the ninth bit received. if a match does not occur the parity error bit is set in the rs-232 status/control assembly time options the firmware is written as a general purpose routines and the user must specify the following parameters before assembling the program. the status/control register is also described below: _clkin input clock frequency of the processor. _baudrate desired baud rate. any valid value can be used. the highest baud rate achievable depends on input clock freq. 600 to 4800 baud was tested using 4 mhz input clock. 600 to 19200 baud was tested using 10 mhz input clock. higher rates can be obtained using higher input clock frequencies. once the _baudrate & _clkin are specified, the program automatically selects all the appropriate timings. _databits can specify 1 to 8 data bits. _stopbits limited to 1 stop bit. must be set to 1. _parity_enable parity enable flag. set it to true or false. if parity is used, then set it to true, else false. see _odd_parity flag description below. _odd_parity set it to true or false. if true, then odd parity is used, else meven parity scheme is used. this flag is ignored if _parity_enable is set to false. _use_rtscts rts & cts hardware handshaking signals. if set to false, no hardware handshaking is used. if set to true, rts & cts use up 2 i/o pins of portb. table 1 - list of assembly time options register ( _parityerr bit of serialstatus reg). the parity bit is computed using the algorithm shown in figure 1. this algorithm is highly efficient using pic16cxxs swapf and xorwf instructions (with ability to have the destination as either file register itself or w register) and the sub-routine (called genparity ) is in file txmtr.asm. figure 1 - an efficient parity generation scheme in software data byte bits <7:4> bits <3:0> xor <3,2> <1,0> 0 1 xor xor parity bit 3-182 software implementation of asynchronous serial i/o 3 ds00555b-page 3 ? 1994 microchip technology inc. table 2 - bit assignments of serial status/control register ("serialstatus" reg) bit # name description 0 _txmtprogress 1 = transmission in progress. 0 = transmission line free. 1 _txmtenable set this bit to 1 on initialization to enable transmission. this bit may be used to abort a transmission. the transmission is aborted if in the middle of a transmission (i.e. when _txmtprogress bit is 1) _txmtenable bit is set to 0. this bit gets automatically set when putchar function is called. 2 _rcvprogress 1 = middle of a byte reception. 0 = reception of a byte (in rxreg) is complete and is set to 1 when a valid start bit is detected in reception mode. 3 _rcvover 0 = completion of reception of a byte. the users code can poll this bit after calling getchar function and check to see if it is set. when set, the received byte is in rxreg. other status bits should also be checked for any reception errors. 4 _parityerr 1 = parity error on reception (irrespective of even or odd parity chosen). not applicable if no parity is used. 5 _frameerr 1 = framing error on reception. 6 unused 7 _paritybit the 9th bit of transmission or reception. in transmission mode, the parity bit of the byte to be transmitted is set in this bit. in receive mode, the 9th bit (or parity bit) received is stored in this bit. not applicable if no parity is used. 3-183 software implementation of asynchronous serial i/o ? 1994 microchip technology inc. ds00555b-page 4 hardware the hardware is primarily concerned with voltage trans- lation from rs-232 to cmos levels and vice versa. three circuits are given below and the user may choose which ever best suits his application. the primary difference between each solution is cost versus number of components. circuits in figure 3 and 4 are very low cost but have more components than the circuit in figure 2. the circuit in figure 2 interfaces to rs-232 line using a single chip (max-232) and single +5v supply. the circuit in figure 3 is a low cost rs-232 interface but requires two chips and a single +5v supply source. figure 2 - single chip for rs-232 interface (single +5v supply) figure 4 shows a very low cost rs-232 interface to an ibm pc ? with no external power requirements. the circuit draws power from rs-232 line (dtr) and meets the spec of drawing power less than 5ma. this requires that the host to communicate must assert dtr high and rts low. the power is drawn from dtr line and this requires that dtr to be asserted high and must be at least 7v. the negative -5 to -10 v required by lm339 is drawn from rts line and thus the host must assert rts low. this circuit is possible because of the low current consumption of pic16c71 (typical 2 ma). 16 12 11 9 10 1 3 6 5 v cc rs-232 signals 2 13 14 8 7 6 15 max-232a rts cts 0.1? rx tx rts cts rtcc rb7 +5v v dd v ss 10?, 6.3v pic16c71 0.1? 0.1? 0.1? figure 3 - low cost rs-232 interface (two chips, single +5v supply) b 1 b 2 a v- tx (rs-232) rts (rs-232) tx +5v mc14c88 rts dtr* (*assert dtr low) v+ outb outa gnd ina inb rx (rs-232) cts (rx-232) rx cts +5v v+ outa outb gnd 3-184 software implementation of asynchronous serial i/o 3 ds00555b-page 5 ? 1994 microchip technology inc. figure 4 - low cost, low power rs-232 interface (power supplied by rs-232 lines) test program to test the transmission and reception modules, a main program is written in which the pic16c71 waits to receive a command from a host through the rs-232. on reception of a byte (valid commands are 0x00, 0x01, 0x02 & 0x03), the received byte is treated as the pic16c71s a/d channel number and the requested channel is selected, an a/d conversion is started and when the conversion is complete (in about 20 us) the digital data (8 bits) are transmitted back to the host. a microsoft ? windows ? program running on an ibm pc/ at ? was written to act as a host and collect the a/d data from pic16c71 via an rs-232 port. the windows program (dvm.exe) runs as a background job and displays the a/d data in a small window (similar to the clock program that comes with ms windows). the windows program and the pic16c71 together act like a data acquisition system or a digital volt meter (dvm). the block diagram of the system is shown in figure 2. the input clock frequency is fixed at 4 mhz and rs-232 parameters are set to 1200 baud, 8-bits, 1 stop bit and no parity. the program during development stage was also tested at 1200, 2400, 4800 baud rates @ 4 mhz input clock and up to 19200 baud @ 10 mhz input clock frequency ( all tests were performed with no parity, even parity and odd parity at 8 and 7 data bits). figure 5 - ms windows program fetching a/d data from pic16c71 via rs-232 pic16c71 : dvm chan#0 ? 2.52 volts 3-185 10k lm301 +5v rx (pin 3 of db9) 0.1? rtcc ra0 ain lm2936 db9 rs-232 dtr 100? +5v 10? 1k 10k - + +5v -10v tx (pin 2 of db9) rts (pin 7 of db9) bat 42 1 6 rb7 zvn104 in4148 10k 10k in4148 pic16cxx software implementation of asynchronous serial i/o ? 1994 microchip technology inc. ds00555b-page 6 source code the pic16cxx source code along with the microsoft ? windows? dvm program (executable running on an ibm pc/at under ms windows 3.1 or higher) is avail- able on microchip's bbs. the assembly code for pic16cxx must be assembled using microchips uni- versal assembler, mpasm. the code cannot be as- sembled using the older assemblers without significant modifications. it is suggested that users who do not have the new assembler mpasm, must change to the new version. the ms windows program (dvm.exe) runs under ms windows 3.1 or higher. the program does not have any menus and shows up as a small window displaying a/d data and runs as a background job. there are a few command line options and are described below : -px : x is the comm port number (e.g. - p2 selects com2). default is com1 -cy : y is the number of a/d channels to display. default is one channel (channel #1) -sz : z is a floating point number that represents the scaling factor (for example - s5.5 would display the data as 5.5*<8bit a/d>/256). the default value is 5.0 volts. -s0 will display the data in raw format without any scaling. author: amar palacherla logic products division code update: scott fink - sr. applications engineer logic products division 3-186 ? 1994 microchip technology inc. ds00555b-page 7 software implementation of asynchronous serial i/o 3 nolist ;***************************************************************************************** ; rs-232 header file ; pic16c6x/7x/8x ;***************************************************************************************** _clkout equ (_clkin >> 2) ; instruction cycle freq = clkin/4 ; _cyclesperbit set (_clkout/_baudrate) _tempcompute set (_cyclesperbit >> 8) ; ;***************************************************************************************** ; auto generation of prescaler & rtcc values ; computed during assembly time ;***************************************************************************************** ; at first set default values for rtccprescale & rtccpreload ; rtccprescale set 0 rtccpreload set _cyclesperbit useprescale set false if (_tempcompute >= 1) rtccprescale set 0 rtccpreload set (_cyclesperbit >> 1) useprescale set true endif if (_tempcompute >= 2) rtccprescale set 1 rtccpreload set (_cyclesperbit >> 2) endif if (_tempcompute >= 4) rtccprescale set 2 rtccpreload set (_cyclesperbit >> 3) endif if (_tempcompute >= 8) rtccprescale set 3 rtccpreload set (_cyclesperbit >> 4) endif appendix a - rs232.h 3-187 ds00555b-page 8 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o if (_tempcompute >= 16) rtccprescale set 4 rtccpreload set (_cyclesperbit >> 5) endif if (_tempcompute >= 32) rtccprescale set 5 rtccpreload set (_cyclesperbit >> 6) endif if (_tempcompute >= 64) rtccprescale set 6 rtccpreload set (_cyclesperbit >> 7) endif if (_tempcompute >= 128) rtccprescale set 7 rtccpreload set (_cyclesperbit >> 8) endif ; if( (rtccprescale == 0) && (rtccpreload < 60)) messg warning : baud rate may be too high for this input clock endif ; ; compute rtcc & presclaer values for 1.5 times the baud rate for start bit detection ; _sbitcycles set (_clkout/_baudrate) + ((_clkout/4)/_baudrate) _tempcompute set (_sbitcycles >> 8) _bit1_init set 08 sbitprescale set 0 sbitrtccload set _sbitcycles if (_tempcompute >= 1) sbitprescale set 0 sbitrtccload set (_sbitcycles >> 1) _bit1_init set 0 endif if (_tempcompute >= 2) 3-188 ? 1994 microchip technology inc. ds00555b-page 9 software implementation of asynchronous serial i/o 3 sbitprescale set 1 sbitrtccload set (_sbitcycles >> 2) endif if (_tempcompute >= 4) sbitprescale set 2 sbitrtccload set (_sbitcycles >> 3) endif if (_tempcompute >= 8) sbitprescale set 3 sbitrtccload set (_sbitcycles >> 4) endif if (_tempcompute >= 16) sbitprescale set 4 sbitrtccload set (_sbitcycles >> 5) endif if (_tempcompute >= 32) sbitprescale set 5 sbitrtccload set (_sbitcycles >> 6) endif if (_tempcompute >= 64) sbitprescale set 6 sbitrtccload set (_sbitcycles >> 7) endif if (_tempcompute >= 128) sbitprescale set 7 sbitrtccload set (_sbitcycles >> 8) endif ; ;***************************************************************************************** ; #define _cycle_offset1 24 ;account for interrupt latency, call time load_rtcc macro mode, k, prescale if(useprescale == 0 && mode == 0) 3-189 ds00555b-page 10 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o movlw -k + _cycle_offset1 else movlw -k + (_cycle_offset1 >> (prescale+1)) ; re load rtcc init value + int latency offset endif movwf _rtcc ; note that prescaler is cleared when rtcc is written endm ;***************************************************************************************** load_bitcount macro movlw _databits+1 movwf bitcount movlw 1 movwf extrabitcount if _parity_enable movlw 2 movwf extrabitcount endif endm ; ;************************************************************************************************** ; pin assignements ;************************************************************************************************** #define rx_mask 0x10 ; rx pin is connected to ra4, ie. bit 4 #define rx_pin _porta,4 ; rx pin : ra4 #define rx rxtemp,4 #define tx _portb,7 ; tx pin , rb7 #define _rts _portb,5 ; rts pin, rb5, output signal #define _cts _portb,6 ; cts pin, rb6, input signal #define _txmtprogress serialstatus,0 #define _txmtenable serialstatus,1 #define _rcvprogress serialstatus,2 #define _rcvover serialstatus,3 #define _parityerr serialstatus,4 #define _frameerr serialstatus,5 #define _paritybit serialstatus,7 ;*************************************************************************************************** 3-190 ? 1994 microchip technology inc. ds00555b-page 11 software implementation of asynchronous serial i/o 3 _option_sbit set 0x38 ; increment on ext clock (falling edge), for start bit detect if useprescale _option_init set 0x00 ; prescaler is used depending on input clock & baud rate else _option_init set 0x0f endif cblock 0x0c txreg ; transmit data holding/shift reg rxreg ; rcv data holding reg rxtemp serialstatus ; txmt & rev status/control reg bitcount extrabitcount ; parity & stop bit count savewreg ; temp hold reg of wreg on int savestatus ; temp hold reg of status reg on int temp1, temp2 endc ;*************************************************************************************************** list 3-191 ds00555b-page 12 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o 3-192 appendix b - rs232.asm title rs232 communications : half duplex : pic16c6x/7x/8x subtitle software implementation : interrupt driven ;********************************************************************************************************* ; software implementation of rs232 communications using pic16cxx ; half-duplex ; ; these routines are intended to be used with pic16c6x/7x family. these routines can be ; used with processors in the 16c6x/7x family which do not have on board hardware async ; serial port. ; mx.. ; ; description : ; half duplex rs-232 mode is implemented in software. ; both reception & transmission are interrupt driven ; only 1 peripheral (rtcc) used for both transmission & reception ; rtcc is used for both timing generation (for bit transmission & bit polling) ; and start bit detection in reception mode. ; this is explained in more detail in the interrupt subroutine. ; programmable baud rate (speed depnding on input clock freq.), programmable ; #of bits, parity enable/disable, odd/even parity is implemented. ; parity & framing errors are detected on reception ; ; rs-232 parameters ; ;the rs-232 parameters are defined as shown below: ; ; _clkin : input clock frequency of the processor ; (note : rc clock mode is not suggested due to wide variations) ; _baudrate : desired baud rate. any valid value can be used. ; the highest baud rate achievable depends on input clock freq. ; 300 to 4800 baud was tested using 4 mhz input clock ; 300 to 19200 baud was tested using 10 mhz input clock ; higher rates can be obtained using higher input clock frequencies. ; once the _baudrate & _clkin are specified the program ; automatically selectes all the appropiate timings ; _databits : can specify 1 to 8 bits. ; _stopbits : limited to 1 stop bit. must set it to 1. ; _parity_enable : parity enable flag. set it to true or false. if parity ; is used, then set it to true, else false. see _odd_parity flag ; description below ; _odd_parity : set it to true or false. if true, then odd parity is used, else ; even parity scheme is used. ; this flag is ignored if _parity_enable is set to false. ; ; ? 1994 microchip technology inc. ds00555b-page 13 software implementation of asynchronous serial i/o 3 3-193 ; usage : ; an example is given in the main program on how to receive & transmit data ; in the example, the processor waits until a command is received. the command is interpreted ; as the a/d channel number of pic16c71. upon reception of a command, the desired a/d channel ; is selected and after a/d conversion, the 8 bit a/d data is transmitted back to the host. ; ; the rs-232 control/status regs bits are explained below : ; ; serialstatus : rs-232 status/control register ; ; bit 0 : _txmtprogress (1 if transmission in progress, 0 if transmission is complete) ; after a byte is transmitted by calling putchar function, the ; users code can poll this bit to check if transmission is complete. ; this bit is reset after the stop bit has been transmitted ; bit 1 : _txmtenable set this bit to 1 on initialization to enable transmission. ; this bit can be used to abort a transmission while the transmitter ; is in progress (i.e when _txmtprogress = 1) ; bit 2 : _rcvprogress indicates that the receiver is in middle of reception.it is reset when ; a byte is received. ; bit 3 : _rcvover this bit indicates the completion of reception of a byte. the users ; code can poll this bit after calling getchar function. once getchar ; function is called, this bit is 1 and is set to 0 after reception of ; a complete byte (parity bit if enabled & stop bit) ; bit 4 : _parityerr a 1 indicates parity error on reception (for both even & odd parity) ; bit 5 : _frameerr a 1 indicates framing error on reception ; ; bit 6 : _unused_ unimplemented bit ; ; bit 7 : _paritybit the 9 th bit of transmission or reception (status of parity bit ; if parity is enabled) ; ; to transmit a byte of data : ; 1) make sure _txmtprogress & _rcvover bits are cleared ; 2) load txreg with data to be transmitted ; 3) call putchar function ; ; to receive a byte of data : ; 1) make sure _txmtprogress & _rcvover bits are cleared ; 2) call getchar function ; 3) the received byte is in txreg after _rcvover bit is cleared ; ; ; rev 2, may 17,1994 scott fink ; corrected 7 bit and parity operation, corrected stop bit generation, corrected ; receive prescaler settings. protected against inadvertant wdt reset. ;********************************************************************************************************* processor 16c71 ds00555b-page 14 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o 3-194 radix dec expand include 16cxx.h ;********************************************************************************************************* ; setup rs-232 parameters ;********************************************************************************************************* _clkin equ 4000000 ; input clock frequency is 4 mhz _baudrate set 1200 ; baud rate (bits per second) is 1200 _databits set 8 ; 8 bit data, can be 1 to 8 _stopbits set 1 ; 1 stop bit, 2 stop bits is not implemented #define _parity_enable false ; no parity #define _odd_parity false ; even parity, if parity enabled #define _use_rtscts false ; no hardware handshaking is used include rs232.h ;********************************************************************************************************* ; org _resetvector goto start ; org _intvector goto interrupt ; ;********************************************************************************************************* ; table of adcon0 reg ; inputs : wreg (valid values are 0 thru 3) ; returns in wreg, adcon0 value, selecting the desired channel ; ; program memory : 6 locations ; cycles : 5 ; ;********************************************************************************************************* getadcon0: andlw 0x03 ; mask off all bits except 2 lsbs (for channel # 0, 1, 2, 3) addwf _pcl retlw (0xc1 | (0 << 3)) ; channel 0 retlw (0xc1 | (1 << 3)) ; channel 1 retlw (0xc1 | (2 << 3)) ; channel 2 getadcon0_end: retlw (0xc1 | (3 << 3)) ; channel 3 ? 1994 microchip technology inc. ds00555b-page 15 software implementation of asynchronous serial i/o 3 3-195 if( (getadcon0 & 0xff) >= (getadcon0_end & 0xff)) messg warning : crossing page boundary in computed jump, make sure pclath is loaded correctly endif ; ;********************************************************************************************************* ; initialize a/d converter ; ds00555b-page 16 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o 3-196 movf rxreg,w ; wreg = commanded channel # (0 thru 3) call getadcon0 ; get adcon0 reg constant from table lookup movwf _adcon0 ; load adcon0 reg, selecting the desired channel nop ; bsf _go ; start conversion btfsc _done goto $-1 ; loop until a/d conversion done movf _adres,w movwf txreg if _use_rtscts bsf _rts ; half duplex mode, transmission mode, ask host not to send data btfsc _cts ; check cts signal if host ready to accept data goto $-1 endif call putchar btfsc _txmtprogress goto $-1 ; loop until transmission over, user can perform other jobs ; goto waitfornextsel ; wait for next selection (command from serial port) ; ;********************************************************************************************************* ; rs-232 routines ;;********************************************************************************************************* ; interrupt service routine ; ; only rtcc inturrupt is used. rtcc inturrupt is used as timing for serial port receive & transmit ; since rs-232 is implemented only as a half duplex system, the rtcc is shared by both receive & ; transmit modules. ; transmission : ; rtcc is setup for internal clock increments and interrupt is generated when ; rtcc overflows. prescaler is assigned, depending on the input clock & the ; desired baud rate. ; reception : ; when put in receive mode, rtcc is setup for external clock mode (falling edge) ; and preloaded with 0xff. when a falling edge is detected on rtcc pin, rtcc ; rolls over and an interrupt is generated (thus start bit detect). once the start ; bit is detected, rtcc is changed to internal clock mode and rtcc is preloaded ; with a certain value for regular timing interrupts to poll rtcc pin (i.e rx pin). ; ;********************************************************************************************************* interrupt: btfss _rtif retfie ; other interrupt, simply return & enable gie ? 1994 microchip technology inc. ds00555b-page 17 software implementation of asynchronous serial i/o 3 3-197 ; ; save status on int : wreg & status regs ; movwf savewreg swapf _status,w ; affects no status bits : only way out to save status reg ????? movwf savestatus ; btfsc _txmtprogress goto _txmtnextbit ; txmt next bit btfsc _rcvprogress goto _rcvnextbit ; receive next bit goto _sbitdetected ; must be start bit ; restoreintstatus: swapf savestatus,w movwf _status ; restore status reg swapf savewreg ; save wreg swapf savewreg,w ; restore wreg bcf _rtif retfie ; ;********************************************************************************************************* ; ; ; ; configure tx pin as output, make sure tx pin comes up in high state on reset ; configure, rx_pin (rtcc pin) as input, which is used to poll data on reception ; ; program memory : 9 locations ; cycles : 10 ;********************************************************************************************************* initserialport: clrf serialstatus ; bcf _rp0 ; select page 0 for port access bsf tx ; make sure tx pin is high on powerup, use rb port pullup bsf _rp0 ; select page 1 for trisb access bcf tx ; set tx pin as output pin, by modifying tris if _use_rtscts bcf _rts ; rts is output signal, controlled by pic16cxx bsf _cts ; cts is input signal, controlled by the host endif bsf rx_pin ; set rx pin as input for reception return ; ;********************************************************************************************************* ds00555b-page 18 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o 3-198 include txmtr.asm ; the transmit routines are in file txmtr.asm include rcvr.asm ; the receiver routines are in file rcvr.asm ;********************************************************************************************************* end ? 1994 microchip technology inc. ds00555b-page 19 software implementation of asynchronous serial i/o 3 3-199 appendix c - rcvr.asm ;***************************************************************************************** ; getchar function ; receives a byte of data ; when reception is complete, _rcvover bit is cleared ; the received data is in rxreg ; ; program memory : 15 locations (17 locations if parity is used) ; cycles : 16 (18 if parity is used) ; ;***************************************************************************************** getchar: bcf _rp0 bsf _rcvover ; enable reception, this bit gets reset on byte rcv complete load_bitcount clrf rxreg bcf _frameerr bcf _parityerr ; init parity & framing errors clrf _rtcc clrwdt bsf _rp0 movlw 07h movwf _option bcf _rp0 clrf _rtcc bsf _rp0 movlw 0fh movwf _option clrwdt movlw _option_sbit ; inc on ext clk falling edge movwf _option ; set option reg located in page 1 bcf _rp0 ; make sure to select page 0 movlw 0xff movwf _rtcc ; a start bit will roll over rtcc & gen int bcf _rtif bsf _rtie ; enable rtcc interrupt retfie ; enable global interrupt ; ;***************************************************************************************** ; internal subroutine ; entered from interrupt service routine when start bit is detected. ; ; program memory : 14 locations ; cycles : 12 (worst case) ; ;***************************************************************************************** _sbitdetected: ds00555b-page 20 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o 3-200 bcf _rp0 btfsc rx_pin ; make sure start bit interrupt is not a glitch goto _falsestartbit ; false start bit bsf _rcvprogress clrf _rtcc clrwdt bsf _rp0 movlw 07h movwf _option bcf _rp0 clrf _rtcc bsf _rp0 movlw 0fh movwf _option clrwdt movlw (_bit1_init | sbitprescale) ; switch back to int clock movwf _option ; set option reg located in page 1 bcf _rp0 ; make sure to select page 0 load_rtcc 1,(sbitrtccload), sbitprescale goto restoreintstatus ; _falsestartbit: movlw 0xff movwf _rtcc ; reload rtcc with 0xff for start bit detection goto restoreintstatus ; ;***************************************************************************************** ; internal subroutine ; entered from interrupt service routine when start bit is detected. ; ; program memory : 28 locations ( 43 locations with parity enabled) ; cycles : 24 worst case ; ;***************************************************************************************** _rcvnextbit: clrwdt bsf _rp0 movlw 07h movwf _option bcf _rp0 clrf _rtcc clrwdt bsf _rp0 movlw 07h movwf _option bcf _rp0 clrf _rtcc bsf _rp0 ? 1994 microchip technology inc. ds00555b-page 21 software implementation of asynchronous serial i/o 3 3-201 movlw 0fh movwf _option clrwdt movlw (_option_init | rtccprescale) ; switch back to int clock movwf _option ; set option reg located in page 1 ; bcf _rp0 movf _porta,w ; read rx pin immediately into wreg movwf rxtemp load_rtcc 0,rtccpreload, rtccprescale ; macro to reload rtcc movf _porta,w xorwf rxtemp,w andlw rx_mask ; mask for only rx pin (ra4) btfsc _z goto _pinsampled ; both samples are same state _sampleagain: movf _porta,w movwf rxtemp ; 2 out of 3 majority sampling done _pinsampled: movf bitcount,1 btfsc _z goto _rcvp_or_s ; decfsz bitcount goto _nextrcvbit ; _rcvp_or_s: if _parity_enable decfsz extrabitcount goto _rcvparity endif ; _rcvstopbit: btfss rx bsf _frameerr ; may be framing error or glitch bcf _rtie ; disable further interrupts bcf _rcvprogress bcf _rcvover ; byte received, can rcv/txmt an other byte if _parity_enable movf rxreg,w call genparity ; generate parity, for parity check movlw 0 btfsc _paritybit movlw 0x10 ; to mask off received parity bit in _parityerr xorwf serialstatus ; _parityerr bit is set accordingly endif if _databits == 7 rrf rxreg,1 ds00555b-page 22 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o 3-202 bcf rxreg,7 endif goto restoreintstatus ; _nextrcvbit: bcf _carry btfsc rx ; prepare bit for shift bsf _carry rrf rxreg ; shift in received data goto restoreintstatus ; if _parity_enable _rcvparity: bcf _parityerr ; temporarily store parity bit in _parityerr btfsc rx ; sample again to avoid any glitches bsf _parityerr goto restoreintstatus endif ; ;***************************************************************************************** ? 1994 microchip technology inc. ds00555b-page 23 software implementation of asynchronous serial i/o 3 3-203 appendix d - txmtr.asm ;********************************************************************************************************* ; putchar function ; ; function to transmit a byte of data ; before calling this routine, load the byte to be transmitted into txreg ; make sure _txmtprogress & _rcvover bits (in status reg) are cleared before ; calling this routine ; ; program memory : 6 locations (10 locations if parity is used) ; cycles : 8 (13 if parity is used) ; ;********************************************************************************************************* putchar: bsf _txmtenable ; enable transmission bsf _txmtprogress load_bitcount ; macro to load bit count decf bitcount,1 if _databits == 7 bsf txreg,7 endif ; if _parity_enable movf txreg,w call genparity ; if parity is used, then generate parity bit endif ; call _txmtstartbit bsf _rtie ; enable rtcc overflow int retfie ; return with _gie bit set ; ;********************************************************************************************************* ; internal subroutine ; entered from interrupt service routine when start bit is detected. ; ; program memory : 30 locations (38 locations if parity is used) ; cycles : 15 worst case ; ;********************************************************************************************************* _txmtnextbit: bcf _rp0 load_rtcc 0,rtccpreload, rtccprescale ; macro to reload rtcc ; movf bitcount ;done with data xmission? btfsc _z goto _parityorstop ;yes, do parity or stop bit ds00555b-page 24 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o 3-204 ; decf bitcount goto _nexttxmtbit ;no, send another ; _parityorstop: if _parity_enable btfsc extrabitcount,1 ;ready for parity bit? goto _sendparity endif movf extrabitcount,1 ;check if sending stop bit btfsc _z goto donetxmt decf extrabitcount,1 ; _stopbit: bsf tx ; stop bit is high goto restoreintstatus goto donetxmt ; _nexttxmtbit: bsf _carry rrf txreg btfss _carry bcf tx btfsc _carry bsf tx ; btfss _txmtenable bsf _rtie ; disable further interrupts, transmission aborted ; goto restoreintstatus ; if _parity_enable _sendparity: decf extrabitcount,1 ;subtract parity from count btfss _paritybit bcf tx btfsc _paritybit bsf tx goto restoreintstatus endif donetxmt bsf tx ;stop bit is high bcf _rtie ;disable further interrupts bcf _txmtprogress ;indicates end of xmission goto restoreintstatus ; ? 1994 microchip technology inc. ds00555b-page 25 software implementation of asynchronous serial i/o 3 ;********************************************************************************************************* ; internal subroutine ; entered from interrupt service routine when start bit is detected. ; ; program memory : 9 locations ; cycles : 10 ; ;********************************************************************************************************* _txmtstartbit: bcf _rp0 clrf _rtcc clrwdt bsf _rp0 movlw 07h movwf _option bcf _rp0 clrf _rtcc bsf _rp0 movlw 0fh movwf _option clrwdt movlw (_option_init | rtccprescale) movwf _option ; set option reg located in page 1 bcf _rp0 ; make sure to select page 0 bcf tx ; send start bit movlw -rtccpreload ; prepare for timing interrupt movwf _rtcc bcf _rtif return ;********************************************************************************************************* ; generate parity for the value in wreg ; ; the parity bit is set in _paritybit (serialstatus,7) ; common routine for both transmission & reception ; ; program memory : 16 locations ; cycles : 72 ; ;********************************************************************************************************* if _parity_enable genparity: movwf temp2 ;save data movf bitcount,w ;save bitcount movwf temp1 parityloop rrf temp2 3-205 ds00555b-page 26 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o btfss _carry ;put data in carry bit goto notone xorlw 00h ;parity calculated by xoring all data bits goto onedone notone xorlw 01h onedone decfsz temp1 goto parityloop ;decrement count movwf temp1 ; parity bit is in bit 0 of temp1 ; if _odd_parity bsf _paritybit btfsc temp1,0 bcf _paritybit else bcf _paritybit btfsc temp1,0 bsf _paritybit endif return endif ;********************************************************************************************************* 3-206 ? 1994 microchip technology inc. ds00555b-page 27 software implementation of asynchronous serial i/o 3 3-207 mpasm 01.00.02 alpha \picmastr\cu 5-20-1994 9:13:56 page 1 rs232 communications : half duplex : pic16c6x/7x/8x software implementation : interrupt driven loc object code line source text 0001 title rs232 communications : half duplex : pic16c6x/7x/8x 0002 subtitle software implementation : interrupt driven 0003 0004 ;********************************************************************************************************* 0005 ; software implementation of rs232 communications using pic16cxx 0006 ; half-duplex 0007 ; 0008 ; these routines are intended to be used with pic16c6x/7x family. these routines can be 0009 ; used with processors in the 16c6x/7x family which do not have on board hardware async 0010 ; serial port. 0011 ; mx.. 0012 ; 0013 ; description : 0014 ; half duplex rs-232 mode is implemented in software. 0015 ; both reception & transmission are interrupt driven 0016 ; only 1 peripheral (rtcc) used for both transmission & reception 0017 ; rtcc is used for both timing generation (for bit transmission & bit polling) 0018 ; and start bit detection in reception mode. 0019 ; this is explained in more detail in the interrupt subroutine. 0020 ; programmable baud rate (speed depnding on input clock freq.), programmable 0021 ; #of bits, parity enable/disable, odd/even parity is implemented. 0022 ; parity & framing errors are detected on reception 0023 ; 0024 ; rs-232 parameters 0025 ; 0026 ;the rs-232 parameters are defined as shown below: 0027 ; 0028 ; _clkin : input clock frequency of the processor 0029 ; (note : rc clock mode is not suggested due to wide variations) 0030 ; _baudrate : desired baud rate. any valid value can be used. 0031 ; the highest baud rate achievable depends on input clock freq. 0032 ; 300 to 4800 baud was tested using 4 mhz input clock 0033 ; 300 to 19200 baud was tested using 10 mhz input clock 0034 ; higher rates can be obtained using higher input clock frequencies. 0035 ; once the _baudrate & _clkin are specified the program 0036 ; automatically selectes all the appropiate timings 0037 ; _databits : can specify 1 to 8 bits. 0038 ; _stopbits : limited to 1 stop bit. must set it to 1. 0039 ; _parity_enable : parity enable flag. set it to true or false. if parity appendix e - rs232.lst ds00555b-page 28 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o 3-208 0040 ; is used, then set it to true, else false. see _odd_parity flag 0041 ; description below 0042 ; _odd_parity : set it to true or false. if true, then odd parity is used, else 0043 ; even parity scheme is used. 0044 ; this flag is ignored if _parity_enable is set to false. 0045 ; 0046 ; 0047 ; usage : 0048 ; an example is given in the main program on how to receive & transmit data 0049 ; in the example, the processor waits until a command is received. the command is interpreted 0050 ; as the a/d channel number of pic16c71. upon reception of a command, the desired a/d channel 0051 ; is selected and after a/d conversion, the 8 bit a/d data is transmitted back to the host. 0052 ; 0053 ; the rs-232 control/status regs bits are explained below : 0054 ; 0055 ; serialstatus : rs-232 status/control register 0056 ; 0057 ; bit 0 : _txmtprogress (1 if transmission in progress, 0 if transmission is complete) 0058 ; after a byte is transmitted by calling putchar function, the 0059 ; users code can poll this bit to check if transmission is complete. 0060 ; this bit is reset after the stop bit has been transmitted 0061 ; bit 1 : _txmtenable set this bit to 1 on initialization to enable transmission. 0062 ; this bit can be used to abort a transmission while the transmitter 0063 ; is in progress (i.e when _txmtprogress = 1) 0064 ; bit 2 : _rcvprogress indicates that the receiver is in middle of reception.it is reset when 0065 ; a byte is received. 0066 ; bit 3 : _rcvover this bit indicates the completion of reception of a byte. the users 0067 ; code can poll this bit after calling getchar function. once getchar 0068 ; function is called, this bit is 1 and is set to 0 after reception of 0069 ; a complete byte (parity bit if enabled & stop bit) 0070 ; bit 4 : _parityerr a 1 indicates parity error on reception (for both even & odd parity) 0071 ; bit 5 : _frameerr a 1 indicates framing error on reception 0072 ; 0073 ; bit 6 : _unused_ unimplemented bit 0074 ; 0075 ; bit 7 : _paritybit the 9 th bit of transmission or reception (status of parity bit 0076 ; if parity is enabled) 0077 ; 0078 ; to transmit a byte of data : 0079 ; 1) make sure _txmtprogress & _rcvover bits are cleared 0080 ; 2) load txreg with data to be transmitted 0081 ; 3) call putchar function 0082 ; 0083 ; to receive a byte of data : 0084 ; 1) make sure _txmtprogress & _rcvover bits are cleared 0085 ; 2) call getchar function 0086 ; 3) the received byte is in txreg after _rcvover bit is cleared 0087 ; ? 1994 microchip technology inc. ds00555b-page 29 software implementation of asynchronous serial i/o 3 3-209 0088 ; 0089 ; rev 2, may 17,1994 scott fink 0090 ; corrected 7 bit and parity operation, corrected stop bit generation, corrected 0091 ; receive prescaler settings. protected against inadvertant wdt reset. 0092 ;********************************************************************************************************* 0093 0094 processor 16c71 0095 radix dec 0096 expand 0097 0098 include 16cxx.h 0179 0180 0181 0098 0099 0100 ;********************************************************************************************************* 0101 ; setup rs-232 parameters 0102 ;********************************************************************************************************* 0103 003d 0900 0104 _clkin equ 4000000 ; input clock frequency is 4 mhz 04b0 0105 _baudrate set 1200 ; baud rate (bits per second) is 1200 0008 0106 _databits set 8 ; 8 bit data, can be 1 to 8 0001 0107 _stopbits set 1 ; 1 stop bit, 2 stop bits is not implemented 0108 0046 0109 #define _parity_enable false ; no parity 0047 0110 #define _odd_parity false ; even parity, if parity enabled 0048 0111 #define _use_rtscts false ; no hardware handshaking is used 0112 0113 include rs232.h 0001 0113 0114 0115 ;********************************************************************************************************* 0116 ; 0117 0118 org _resetvector 0000 2811 0119 goto start 0120 ; 0121 0122 org _intvector 0004 2823 0123 goto interrupt 0124 ; 0125 ;********************************************************************************************************* 0126 ; table of adcon0 reg 0127 ; inputs : wreg (valid values are 0 thru 3) 0128 ; returns in wreg, adcon0 value, selecting the desired channel 0129 ; ds00555b-page 30 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o 3-210 0130 ; program memory : 6 locations 0131 ; cycles : 5 0132 ; 0133 ;********************************************************************************************************* 0134 0135 getadcon0: 0005 3903 0136 andlw 0x03 ; mask off all bits except 2 lsbs (for channel # 0, 1, 2, 3) 0006 0782 0137 addwf _pcl 0007 34c1 0138 retlw (0xc1 | (0 << 3)) ; channel 0 0008 34c9 0139 retlw (0xc1 | (1 << 3)) ; channel 1 0009 34d1 0140 retlw (0xc1 | (2 << 3)) ; channel 2 0141 getadcon0_end: 000a 34d9 0142 retlw (0xc1 | (3 << 3)) ; channel 3 0143 0144 if( (getadcon0 & 0xff) >= (getadcon0_end & 0xff)) 0145 messg warning : crossing page boundary in computed jump, make sure pclath is loaded correctly 0146 endif 0147 ; 0148 ;********************************************************************************************************* 0149 ; initialize a/d converter 0150 ; ? 1994 microchip technology inc. ds00555b-page 31 software implementation of asynchronous serial i/o 3 3-211 0178 ; 0179 waitfornextsel: 0180 if _use_rtscts 0181 bcf _rp0 0182 bcf _rts ; ready to accept data from host 0183 endif 0012 2074 0184 call getchar ; wait for a byte reception 0013 198f 0185 btfsc _rcvover ; _rcvover gets cleared when a byte is received (in rxreg) 0014 2813 0186 goto $-1 ; user can perform other jobs here, can poll _rcvover bit 0187 ; 0188 ; a byte is received, select the desired channel & tmxt the desired a/d channel data 0189 ; 0015 1283 0190 bcf _rp0 ; make sure to select page 0 0016 080d 0191 movf rxreg,w ; wreg = commanded channel # (0 thru 3) 0017 2005 0192 call getadcon0 ; get adcon0 reg constant from table lookup 0018 0088 0193 movwf _adcon0 ; load adcon0 reg, selecting the desired channel 0019 0000 0194 nop 0195 ; 001a 1508 0196 bsf _go ; start conversion 001b 1908 0197 btfsc _done 001c 281b 0198 goto $-1 ; loop until a/d conversion done 0199 001d 0809 0200 movf _adres,w 001e 008c 0201 movwf txreg 0202 if _use_rtscts 0203 bsf _rts ; half duplex mode, transmission mode, ask host not to send data 0204 btfsc _cts ; check cts signal if host ready to accept data 0205 goto $-1 0206 endif ww001f 203a 0207 call putchar 0020 180f 0208 btfsc _txmtprogress 0021 2820 0209 goto $-1 ; loop until transmission over, user can perform other jobs 0210 0211 0212 ; 0022 2812 0213 goto waitfornextsel ; wait for next selection (command from serial port) 0214 ; 0215 ;********************************************************************************************************* 0216 ; rs-232 routines 0217 ;;********************************************************************************************************* 0218 ; interrupt service routine 0219 ; 0220 ; only rtcc inturrupt is used. rtcc inturrupt is used as timing for serial port receive & transmit 0221 ; since rs-232 is implemented only as a half duplex system, the rtcc is shared by both receive & 0222 ; transmit modules. 0223 ; transmission : 0224 ; rtcc is setup for internal clock increments and interrupt is generated when ds00555b-page 32 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o 3-212 0225 ; rtcc overflows. prescaler is assigned, depending on the input clock & the 0226 ; desired baud rate. 0227 ; reception : 0228 ; when put in receive mode, rtcc is setup for external clock mode (falling edge) 0229 ; and preloaded with 0xff. when a falling edge is detected on rtcc pin, rtcc 0230 ; rolls over and an interrupt is generated (thus start bit detect). once the start 0231 ; bit is detected, rtcc is changed to internal clock mode and rtcc is preloaded 0232 ; with a certain value for regular timing interrupts to poll rtcc pin (i.e rx pin). 0233 ; 0234 ;********************************************************************************************************* 0235 0236 interrupt: 0023 1d0b 0237 btfss _rtif 0024 0009 0238 retfie ; other interrupt, simply return & enable gie 0239 ; 0240 ; save status on int : wreg & status regs 0241 ; 0025 0092 0242 movwf savewreg 0026 0e03 0243 swapf _status,w ; affects no status bits : only way out to save status reg ????? 0027 0093 0244 movwf savestatus 0245 ; 0028 180f 0246 btfsc _txmtprogress 0029 2844 0247 goto _txmtnextbit ; txmt next bit 002a 190f 0248 btfsc _rcvprogress 002b 28a8 0249 goto _rcvnextbit ; receive next bit 002c 2890 0250 goto _sbitdetected ; must be start bit 0251 ; 0252 restoreintstatus: 002d 0e13 0253 swapf savestatus,w 002e 0083 0254 movwf _status ; restore status reg 002f 0e92 0255 swapf savewreg ; save wreg 0030 0e12 0256 swapf savewreg,w ; restore wreg 0031 110b 0257 bcf _rtif 0032 0009 0258 retfie 0259 ; 0260 ;********************************************************************************************************* 0261 ; 0262 ; 0263 ; 0264 ; configure tx pin as output, make sure tx pin comes up in high state on reset 0265 ; configure, rx_pin (rtcc pin) as input, which is used to poll data on reception 0266 ; 0267 ; program memory : 9 locations 0268 ; cycles : 10 0269 ;********************************************************************************************************* 0270 0271 initserialport: ? 1994 microchip technology inc. ds00555b-page 33 software implementation of asynchronous serial i/o 3 3-213 0033 018f 0272 clrf serialstatus 0273 ; 0034 1283 0274 bcf _rp0 ; select page 0 for port access 0035 1786 0275 bsf tx ; make sure tx pin is high on powerup, use rb port pullup 0036 1683 0276 bsf _rp0 ; select page 1 for trisb access 0037 1386 0277 bcf tx ; set tx pin as output pin, by modifying tris 0278 if _use_rtscts 0279 bcf _rts ; rts is output signal, controlled by pic16cxx 0280 bsf _cts ; cts is input signal, controlled by the host 0281 endif 0038 1605 0282 bsf rx_pin ; set rx pin as input for reception 0039 0008 0283 return 0284 ; 0285 ;********************************************************************************************************* 0286 0287 include txmtr.asm ; the transmit routines are in file txmtr.asm 0001 ;********************************************************************************************************* 0002 ; putchar function 0003 ; 0004 ; function to transmit a byte of data 0005 ; before calling this routine, load the byte to be transmitted into txreg 0006 ; make sure _txmtprogress & _rcvover bits (in status reg) are cleared before 0007 ; calling this routine 0008 ; 0009 ; program memory : 6 locations (10 locations if parity is used) 0010 ; cycles : 8 (13 if parity is used) 0011 ; 0012 ;********************************************************************************************************* 0013 putchar: 003a 148f 0014 bsf _txmtenable ; enable transmission 003b 140f 0015 bsf _txmtprogress 0016 load_bitcount ; macro to load bit count 003c 3009 m movlw _databits+1 003d 0090 m movwf bitcount 003e 3001 m movlw 1 003f 0091 m movwf extrabitcount m if _parity_enable m movlw 2 m movwf extrabitcount m endif 0040 0390 0017 decf bitcount,1 0018 if _databits == 7 0019 bsf txreg,7 0020 endif 0021 ; 0022 if _parity_enable 0023 movf txreg,w 0024 call genparity ; if parity is used, then generate parity bit ds00555b-page 34 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o 3-214 0025 endif 0026 ; 0041 2060 0027 call _txmtstartbit 0042 168b 0028 bsf _rtie ; enable rtcc overflow int 0043 0009 0029 retfie ; return with _gie bit set 0030 ; 0031 ;********************************************************************************************************* 0032 ; internal subroutine 0033 ; entered from interrupt service routine when start bit is detected. 0034 ; 0035 ; program memory : 30 locations (38 locations if parity is used) 0036 ; cycles : 15 worst case 0037 ; 0038 ;********************************************************************************************************* 0039 0040 _txmtnextbit: 0044 1283 0041 bcf _rp0 0042 load_rtcc 0,rtccpreload, rtccprescale ; macro to reload rtcc m if(useprescale == 0 && 0 == 0) m movlw -rtccpreload + _cycle_offset1 m else 0045 3036 m movlw -rtccpreload + (_cycle_offset1 >> (rtccprescale+1)) ; re load rtcc init value + int la m endif 0046 0081 m movwf _rtcc ; note that prescaler is cleared when rtcc is written 0043 ; 0047 0890 0044 movf bitcount ;done with data xmission? 0048 1903 0045 btfsc _z 0049 284c 0046 goto _parityorstop ;yes, do parity or stop bit 0047 ; 004a 0390 0048 decf bitcount 004b 2853 0049 goto _nexttxmtbit ;no, send another 0050 ; 0051 _parityorstop: 0052 if _parity_enable 0053 btfsc extrabitcount,1 ;ready for parity bit? 0054 goto _sendparity 0055 endif 004c 0891 0056 movf extrabitcount,1 ;check if sending stop bit 004d 1903 0057 btfsc _z 004e 285c 0058 goto donetxmt 004f 0391 0059 decf extrabitcount,1 0060 ; 0061 _stopbit: 0050 1786 0062 bsf tx ; stop bit is high 0051 282d 0063 goto restoreintstatus 0052 285c 0064 goto donetxmt 0065 ; ? 1994 microchip technology inc. ds00555b-page 35 software implementation of asynchronous serial i/o 3 3-215 0066 _nexttxmtbit: 0053 1403 0067 bsf _carry 0054 0c8c 0068 rrf txreg 0055 1c03 0069 btfss _carry 0056 1386 0070 bcf tx 0057 1803 0071 btfsc _carry 0058 1786 0072 bsf tx 0073 ; 0059 1c8f 0074 btfss _txmtenable 005a 168b 0075 bsf _rtie ; disable further interrupts, transmission aborted 0076 ; 005b 282d 0077 goto restoreintstatus 0078 ; 0079 if _parity_enable 0080 _sendparity: 0081 decf extrabitcount,1 ;subtract parity from count 0082 btfss _paritybit 0083 bcf tx 0084 btfsc _paritybit 0085 bsf tx 0086 goto restoreintstatus 0087 endif 0088 0089 donetxmt 005c 1786 0090 bsf tx ;stop bit is high 005d 128b 0091 bcf _rtie ;disable further interrupts 005e 100f 0092 bcf _txmtprogress ;indicates end of xmission 005f 282d 0093 goto restoreintstatus 0094 ; 0095 ;********************************************************************************************************* 0096 ; internal subroutine 0097 ; entered from interrupt service routine when start bit is detected. 0098 ; 0099 ; program memory : 9 locations 0100 ; cycles : 10 0101 ; 0102 ;********************************************************************************************************* 0103 _txmtstartbit: 0060 1283 0104 bcf _rp0 0061 0181 0105 clrf _rtcc 0062 0064 0106 clrwdt 0063 1683 0107 bsf _rp0 0064 3007 0108 movlw 07h 0065 0081 0109 movwf _option 0066 1283 0110 bcf _rp0 0067 0181 0111 clrf _rtcc 0068 1683 0112 bsf _rp0 0069 300f 0113 movlw 0fh ds00555b-page 36 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o 3-216 006a 0081 0114 movwf _option 006b 0064 0115 clrwdt 006c 3001 0116 movlw (_option_init | rtccprescale) 006d 0081 0117 movwf _option ; set option reg located in page 1 006e 1283 0118 bcf _rp0 ; make sure to select page 0 006f 1386 0119 bcf tx ; send start bit 0070 3030 0120 movlw -rtccpreload ; prepare for timing interrupt 0071 0081 0121 movwf _rtcc 0072 110b 0122 bcf _rtif 0073 0008 0123 return 0124 0125 ;********************************************************************************************************* 0126 ; generate parity for the value in wreg 0127 ; 0128 ; the parity bit is set in _paritybit (serialstatus,7) 0129 ; common routine for both transmission & reception 0130 ; 0131 ; program memory : 16 locations 0132 ; cycles : 72 0133 ; 0134 ;********************************************************************************************************* 0135 if _parity_enable 0136 0137 genparity: 0138 movwf temp2 ;save data 0139 movf bitcount,w ;save bitcount 0140 movwf temp1 0141 parityloop 0142 rrf temp2 0143 btfss _carry ;put data in carry bit 0144 goto notone 0145 xorlw 00h ;parity calculated by xoring all data bits 0146 goto onedone 0147 notone 0148 xorlw 01h 0149 onedone 0150 decfsz temp1 0151 goto parityloop ;decrement count 0152 movwf temp1 0153 ; parity bit is in bit 0 of temp1 0154 ; 0155 if _odd_parity 0156 bsf _paritybit 0157 btfsc temp1,0 0158 bcf _paritybit 0159 else 0160 bcf _paritybit 0161 btfsc temp1,0 ? 1994 microchip technology inc. ds00555b-page 37 software implementation of asynchronous serial i/o 3 3-217 0162 bsf _paritybit 0163 endif 0164 0165 return 0166 endif 0167 ;********************************************************************************************************* 0287 0288 include rcvr.asm ; the receiver routines are in file rcvr.asm 0001 ;***************************************************************************************** 0002 ; getchar function 0003 ; receives a byte of data 0004 ; when reception is complete, _rcvover bit is cleared 0005 ; the received data is in rxreg 0006 ; 0007 ; program memory : 15 locations (17 locations if parity is used) 0008 ; cycles : 16 (18 if parity is used) 0009 ; 0010 ;***************************************************************************************** 0011 getchar: 0074 1283 0012 bcf _rp0 0075 158f 0013 bsf _rcvover ; enable reception, this bit gets reset on byte rcv complete 0014 load_bitcount 0076 3009 m movlw _databits+1 0077 0090 m movwf bitcount 0078 3001 m movlw 1 0079 0091 m movwf extrabitcount m if _parity_enable m movlw 2 m movwf extrabitcount m endif 007a 018d 0015 clrf rxreg 007b 128f 0016 bcf _frameerr 007c 120f 0017 bcf _parityerr ; init parity & framing errors 007d 0181 0018 clrf _rtcc 007e 0064 0019 clrwdt 007f 1683 0020 bsf _rp0 0080 3007 0021 movlw 07h 0081 0081 0022 movwf _option 0082 1283 0023 bcf _rp0 0083 0181 0024 clrf _rtcc 0084 1683 0025 bsf _rp0 0085 300f 0026 movlw 0fh 0086 0081 0027 movwf _option 0087 0064 0028 clrwdt 0088 3038 0029 movlw _option_sbit ; inc on ext clk falling edge 0089 0081 0030 movwf _option ; set option reg located in page 1 008a 1283 0031 bcf _rp0 ; make sure to select page 0 008b 30ff 0032 movlw 0xff ds00555b-page 38 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o 3-218 008c 0081 0033 movwf _rtcc ; a start bit will roll over rtcc & gen int 008d 110b 0034 bcf _rtif 008e 168b 0035 bsf _rtie ; enable rtcc interrupt 008f 0009 0036 retfie ; enable global interrupt 0037 ; 0038 ;***************************************************************************************** 0039 ; internal subroutine 0040 ; entered from interrupt service routine when start bit is detected. 0041 ; 0042 ; program memory : 14 locations 0043 ; cycles : 12 (worst case) 0044 ; 0045 ;***************************************************************************************** 0046 _sbitdetected: 0090 1283 0047 bcf _rp0 0091 1a05 0048 btfsc rx_pin ; make sure start bit interrupt is not a glitch 0092 28a5 0049 goto _falsestartbit ; false start bit 0093 150f 0050 bsf _rcvprogress 0094 0181 0051 clrf _rtcc 0095 0064 0052 clrwdt 0096 1683 0053 bsf _rp0 0097 3007 0054 movlw 07h 0098 0081 0055 movwf _option 0099 1283 0056 bcf _rp0 009a 0181 0057 clrf _rtcc 009b 1683 0058 bsf _rp0 009c 300f 0059 movlw 0fh 009d 0081 0060 movwf _option 009e 0064 0061 clrwdt 009f 3002 0062 movlw (_bit1_init | sbitprescale) ; switch back to int clock 00a0 0081 0063 movwf _option ; set option reg located in page 1 00a1 1283 0064 bcf _rp0 ; make sure to select page 0 0065 load_rtcc 1,(sbitrtccload), sbitprescale m if(useprescale == 0 && 1 == 0) m movlw -(sbitrtccload) + _cycle_offset1 m else 00a2 3081 m movlw -(sbitrtccload) + (_cycle_offset1 >> (sbitprescale+1)) ; re load rtcc init value + int la m endif 00a3 0081 m movwf _rtcc ; note that prescaler is cleared when rtcc is written 00a4 282d 0066 goto restoreintstatus 0067 ; 0068 _falsestartbit: 00a5 30ff 0069 movlw 0xff 00a6 0081 0070 movwf _rtcc ; reload rtcc with 0xff for start bit detection 00a7 282d 0071 goto restoreintstatus 0072 ; 0073 ;***************************************************************************************** 0074 ; internal subroutine ? 1994 microchip technology inc. ds00555b-page 39 software implementation of asynchronous serial i/o 3 3-219 0075 ; entered from interrupt service routine when start bit is detected. 0076 ; 0077 ; program memory : 28 locations ( 43 locations with parity enabled) 0078 ; cycles : 24 worst case 0079 ; 0080 ;***************************************************************************************** 0081 _rcvnextbit: 00a8 0064 0082 clrwdt 00a9 1683 0083 bsf _rp0 00aa 3007 0084 movlw 07h 00ab 0081 0085 movwf _option 00ac 1283 0086 bcf _rp0 00ad 0181 0087 clrf _rtcc 00ae 0064 0088 clrwdt 00af 1683 0089 bsf _rp0 00b0 3007 0090 movlw 07h 00b1 0081 0091 movwf _option 00b2 1283 0092 bcf _rp0 00b3 0181 0093 clrf _rtcc 00b4 1683 0094 bsf _rp0 00b5 300f 0095 movlw 0fh 00b6 0081 0096 movwf _option 00b7 0064 0097 clrwdt 00b8 3001 0098 movlw (_option_init | rtccprescale) ; switch back to int clock 00b9 0081 0099 movwf _option ; set option reg located in page 1 0100 ; 00ba 1283 0101 bcf _rp0 00bb 0805 0102 movf _porta,w ; read rx pin immediately into wreg 00bc 008e 0103 movwf rxtemp 0104 load_rtcc 0,rtccpreload, rtccprescale ; macro to reload rtcc m if(useprescale == 0 && 0 == 0) m movlw -rtccpreload + _cycle_offset1 m else 00bd 3036 m movlw -rtccpreload + (_cycle_offset1 >> (rtccprescale+1)) ; re load rtcc init value + int la m endif 00be 0081 m movwf _rtcc ; note that prescaler is cleared when rtcc is written 00bf 0805 0105 movf _porta,w 00c0 060e 0106 xorwf rxtemp,w 00c1 3910 0107 andlw rx_mask ; mask for only rx pin (ra4) 00c2 1903 0108 btfsc _z 00c3 28c6 0109 goto _pinsampled ; both samples are same state 0110 _sampleagain: 00c4 0805 0111 movf _porta,w 00c5 008e 0112 movwf rxtemp ; 2 out of 3 majority sampling done 0113 _pinsampled: 00c6 0890 0114 movf bitcount,1 00c7 1903 0115 btfsc _z ds00555b-page 40 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o 3-220 00c8 28cb 0116 goto _rcvp_or_s 0117 ; 00c9 0b90 0118 decfsz bitcount 00ca 28d1 0119 goto _nextrcvbit 0120 ; 0121 _rcvp_or_s: 0122 if _parity_enable 0123 decfsz extrabitcount 0124 goto _rcvparity 0125 endif 0126 ; 0127 _rcvstopbit: 00cb 1e0e 0128 btfss rx 00cc 168f 0129 bsf _frameerr ; may be framing error or glitch 00cd 128b 0130 bcf _rtie ; disable further interrupts 00ce 110f 0131 bcf _rcvprogress 00cf 118f 0132 bcf _rcvover ; byte received, can rcv/txmt an other byte 0133 if _parity_enable 0134 movf rxreg,w 0135 call genparity ; generate parity, for parity check 0136 movlw 0 0137 btfsc _paritybit 0138 movlw 0x10 ; to mask off received parity bit in _parityerr 0139 xorwf serialstatus ; _parityerr bit is set accordingly 0140 endif 0141 if _databits == 7 0142 rrf rxreg,1 0143 bcf rxreg,7 0144 endif 00d0 282d 0145 goto restoreintstatus 0146 ; 0147 _nextrcvbit: 00d1 1003 0148 bcf _carry 00d2 1a0e 0149 btfsc rx ; prepare bit for shift 00d3 1403 0150 bsf _carry 00d4 0c8d 0151 rrf rxreg ; shift in received data 00d5 282d 0152 goto restoreintstatus 0153 ; 0154 if _parity_enable 0155 _rcvparity: 0156 bcf _parityerr ; temporarily store parity bit in _parityerr 0157 btfsc rx ; sample again to avoid any glitches 0158 bsf _parityerr 0159 goto restoreintstatus 0160 endif 0161 ; 0162 ;***************************************************************************************** 0288 ? 1994 microchip technology inc. ds00555b-page 41 software implementation of asynchronous serial i/o 3 3-221 0289 0290 ;********************************************************************************************************* 0291 0292 end 0293 0294 0295 0296 memory usage map (x = used, - = unused) 0000 : xxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 0040 : xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 0080 : xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 00c0 : xxxxxxxxxxxxxxxx xxxxxx all other memory blocks unused. errors : 0 warnings : 0 ds00555b-page 42 ? 1994 microchip technology inc. software implementation of asynchronous serial i/o notes: 3-222 w orldwide s ales & s ervice americas (continued) san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408 436-7950 fax: 408 436-7955 asia/pacific hong kong microchip technology unit no. 3002-3004, tower 1 metroplaza 223 hing fong road kwai fong, n.t. hong kong tel: 852 2 401 1200 fax: 852 2 401 3431 korea microchip technology 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku, seoul, korea tel: 82 2 554 7200 fax: 82 2 558 5934 singapore microchip technology 200 middle road #10-03 prime centre singapore 188980 tel: 65 334 8870 fax: 65 334 8850 taiwan microchip technology 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886 2 717 7175 fax: 886 2 545 0139 europe united kingdom arizona microchip technology ltd. unit 6, the courtyard meadow bank, furlong road bourne end, buckinghamshire sl8 5aj tel: 44 0 1628 851077 fax: 44 0 1628 850259 france arizona microchip technology sarl 2 rue du buisson aux fraises 91300 massy - france tel: 33 1 69 53 63 20 fax: 33 1 69 30 90 79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 muenchen, germany tel: 49 89 627 144 0 fax: 49 89 627 144 44 italy arizona microchip technology srl centro direzionale colleoni palazzo pegaso ingresso no. 2 via paracelso 23, 20041 agrate brianza (mi) italy tel: 39 039 689 9939 fax: 39 039 689 9883 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shin yokohama kohoku-ku, yokohama kanagawa 222 japan tel: 81 45 471 6166 fax: 81 45 471 6122 9/22/95 americas corporate of ce microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602 786-7200 fax: 602 786-7277 technical support: 602 786-7627 web: http://www.mchip.com/microhip atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770 640-0034 fax: 770 640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508 480-9990 fax: 508 480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 708 285-0071 fax: 708 285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 214 991-7177 fax: 214 991-8588 dayton microchip technology inc. 35 rockridge road englewood, oh 45322 tel: 513 832-2543 fax: 513 832-2841 los angeles microchip technology inc. 18201 von karman, suite 455 irvine, ca 92715 tel: 714 263-1888 fax: 714 263-1338 new york microchip technology inc. 150 motor parkway, suite 416 hauppauge, ny 11788 tel: 516 273-5305 fax: 516 273-5335 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip? products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. all rights reserved. 1995, microchip technology incorporated, usa. |
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